Run-time antenna matching for wireless power transmission via short-range wireless communication

Abstract

To provide a system and a method for run-time antenna matching of a wireless power device.SOLUTION: An integrated circuit can include a controller. The integrated circuit can further include a circuit configured to detect a voltage at a switching converter. Further, the circuit may be configured to determine whether a negative voltage spike is present in the detected voltage. The controller may be configured to adjust the capacitance of an antenna interface circuit between the switching converter and the antenna to perform impedance matching based on whether a negative voltage spike is present in the detected voltage.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure generally relates to apparatuses and methods for antenna matching in wireless power devices. In particular, runtime antenna matching executable in a wireless charging device by near field communication (NFC) will be described.

Background Art

[0002] Wireless power transfer using the near field communication (NFC) protocol (e.g., an NFC wireless power system) can occur between two devices including a near field communication (NFC) interface. Such an NFC wireless power system can include a polarizer having a transmitting coil and a listener having a receiving coil. In one aspect, the polarizer may be connected to a structure including a wireless charging area. In response to a device including the listener being placed near a device including the polarizer, the transmitting coil and the receiving coil can be inductively coupled to each other to establish an NFC communication link between the polarizer and the listener, and inductive transfer of alternating current (AC) power occurs using the established NFC communication link. Transfer of AC power from the polarizer to the listener can facilitate charging of the battery of the device including the listener.

Summary of the Invention

[0003] In one embodiment, an integrated circuit for runtime antenna matching for a wireless power device is provided. The integrated circuit can include a controller. The integrated circuit can further include a circuit configured to sense a voltage in a switching converter. Further, the circuit can be configured to determine whether a negative voltage spike exists in the sensed voltage. The controller can be configured to adjust the capacitance of an antenna interface circuit between the switching converter and the antenna to perform impedance matching based on whether a negative voltage spike exists in the sensed voltage.

[0004] In one embodiment, an apparatus for runtime antenna matching for a wireless power device is provided. The apparatus can include an antenna. Further, the apparatus can include an antenna interface circuit. Further, the apparatus can include a transmitter. The transmitter is configured to sense a voltage in a switching converter of the transmitter. Further, the transmitter can be configured to determine whether a negative voltage spike exists in the sensed voltage. Further, the transmitter can be configured to adjust the capacitance of the antenna interface circuit between the switching converter and the antenna to perform impedance matching based on whether a negative voltage spike exists in the sensed voltage.

[0005] In one embodiment, generally, a method for operating a wireless power device for runtime antenna matching is provided. The method can include a step of sensing a voltage in a switching converter. Further, the method can include a step of determining whether a negative voltage spike exists in the sensed voltage. Further, the method can include a step of adjusting the capacitance of the antenna interface circuit between the switching converter and the antenna to perform impedance matching based on whether a negative voltage spike exists in the sensed voltage.

Brief Description of the Drawings

[0006] Hereinafter, with reference to the accompanying drawings, further features, structures, and operations of various embodiments of the present invention will be described in detail. In these drawings, like reference numerals indicate the same or functionally similar elements.

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DETAILED DESCRIPTION OF THE INVENTION

[0007] In the following description, for the purpose of facilitating the understanding of various embodiments of the present application, a number of specific details including specific structures, components, materials, dimensions, processing steps, and technologies are described. However, those skilled in the art will understand that various embodiments of the present application can be realized without these specific details. In some cases, the description of details of known structures or processing steps is omitted to avoid obscuring the present application.

[0008] The NFC wireless power system can provide charging under static mode or negotiation mode. The static mode uses a standard radio frequency (RF) electric field strength to provide a consistent power level. The negotiation mode can use a relatively high RF electric field corresponding to different power transfer classes such as 250, 500, 750, 1000 milliwatts (mW). In the NFC wireless power system, the polarizer and the listener can communicate with each other using the NFC communication protocol. In one aspect, the NFC wireless power system can use a specific fundamental frequency (e.g., 13.56 megahertz (MHz)) and utilize the NFC communication link between two devices to control power transfer. To perform NFC communication, one device can apply or transfer a modulation signal, such as an amplitude shift keying (ASK) signal, to the other device, and the other device can demodulate the modulation signal.

[0009] FIG. 1 is a diagram showing an exemplary system that can implement NFC current mode demodulation in one embodiment. System 100 can include an antenna interface circuit 102 and power devices such as a transmitter 110 and a receiver 120 configured to wirelessly transfer power and data therebetween via inductive coupling. Although described herein as transmitter 110 and receiver 120, each of transmitter 110 and receiver 120 may be configured to transmit and receive power or data therebetween via inductive coupling. Transmitter 110 is also referred to as a wireless power transmitter, and receiver 120 is also referred to as a wireless power receiver. In an embodiment where system 100 is configured as an NFC wireless power system, transmitter 110 may be configured as a polarizer and receiver 120 may be configured as a listener.

[0010] The transmitter 110 may be configured to receive power from one or more power sources and wirelessly transmit AC power to the receiver 120. For example, the transmitter 110 may be configured to connect to a power source 122 such as an adapter or a direct current (DC) power source. The transmitter 110 may be a semiconductor device including a controller 104, a switching converter 106, a circuit 107, and a circuit 108. The transmitter 110 may be connected to an antenna 124. The switching converter 106 may be an integrated circuit (IC) that forms part of a power driver and is configured to convert a particular type of current into another type of current. For example, the switching converter 106 may be configured as an inverter that converts a DC signal into an AC signal. As will be described in more detail below, the circuit 107 may be configured to detect a voltage signal in the switching converter 106 and transmit that voltage signal to the circuit 108. The circuit 108 may be configured to detect negative voltage spikes in two low-side MOSFETs (metal-oxide-semiconductor field-effect transistors) LS1, LS2. In one embodiment, the circuit 107 and the circuit 108 may be implemented as one circuit on the same circuit board.

[0011] The controller 104 can be configured to control and operate the switching converter 106, the circuit 107, and other components of the transmitter 110. The controller 104 can include, for example, a processor, a CPU (Central Processing Unit), an FPGA (Field Programmable Gate Array), or any other circuit configured to control and operate the switching converter 106. Although described as a CPU in an exemplary embodiment, the controller 104 is not limited to a CPU in these embodiments and may include any other circuit configured to control and operate the switching converter 106. In an exemplary embodiment, the controller 104 can be configured to control the switching converter 106 using a drive signal for switching devices such as transistors within the switching converter 106. The switching of the devices within the switching converter 106 can drive the antenna 124 within a range of frequencies and configurations defined by a wireless power standard such as the Wireless Charging (WLC) specification of the NFC Forum. The antenna 124 can include a resonant circuit including one or more capacitors, inductors, and resistors that can form a circuit for outputting a communication signal 132 and transmitting AC power 134 to the receiver 120. The antenna interface circuit 102 can be connected to the transmitter 110 and can include one or more capacitors, inductors, and resistors that form a filter, a matching network, or other circuit for interfacing the transmitter 110 and the antenna 124.

[0012] The receiver 120 is configured to receive the AC power 134 transmitted from the transmitter 110 and supply power to one or more loads 118 or other components of the destination device including the receiver 120. The load 118 may include, for example, a battery charger configured to charge the battery of the destination device 140, a DC-DC converter configured to supply DC power 136 to a processor, a display, or other electronic components of the destination device 140, or any other load of the destination device 140. The destination device can include an antenna interface circuit 112 and the receiver 120. The destination device 140 can be, for example, a computing device, a smart device, a wearable device, or any other electronic device configured to receive power wirelessly. In other embodiments, the receiver 120 may be separated from the destination device and connected to the destination device via a wire or other component configured to supply power to the destination device 140.

[0013] The receiver 120 can be a semiconductor device including a controller 114 and a switching converter 116. The receiver 120 can be connected to an antenna 126. The controller 114 can be an integrated circuit including, for example, a digital controller such as a microcontroller, a processor, a CPU, an FPGA, or any other circuit configured to control and operate the switching converter 116. The antenna 126 can be connected to an antenna interface circuit 112 including one or more capacitors, inductors, and resistors that can form a circuit for outputting a communication signal 132 received from the transmitter 110 by the antenna 126 and transmitting AC power 134. The antenna interface circuit 112 can include one or more capacitors, inductors, and resistors that can form a filter, a matching network, or other circuits for interfacing the receiver 120 with the antenna 126. The switching converter 116 can be an IC configured to convert a specific type of current to another type of current. For example, the switching converter 116 can be configured as a power rectifier that converts an AC signal to a DC signal. When configured as a power rectifier, the switching converter 116 can include a rectifier circuit such as a half-bridge rectifier, a full-bridge rectifier, or other types of rectifier circuits configured to rectify the power received via the antenna 126 to the power type required by the load 118. The controller 114 can be configured to execute application-specific programs and / or firmware to control and operate various components such as the antenna interface circuit 112 and the switching converter 116 of the receiver 120.

[0014] For example, when the receiver 120 is disposed close to the transmitter 110, the magnetic field generated by the antenna 124 can induce a current in the antenna 126. The induced current inductively transmits the AC power 134 through the antenna 126 to the switching converter 116. The switching converter 116 can receive the AC power 134 and convert the AC power 134 into DC power 136. The DC power 136 is then supplied to the load 118.

[0015] Also, the transmitter 110 and the receiver 120 are configured to exchange data such as information or messages via the inductive coupling of the antenna 124 and the antenna 126. For example, before the transmitter 110 starts power transfer to the receiver 120, a power contract may be agreed upon and created between the receiver 120 and the transmitter 110. For example, the receiver 120 may transmit a communication signal 132 or other data indicating power transfer information such as the amount of power transferred to the receiver 120, a command to increase, decrease, or maintain the power level of the AC power 134, a command to stop power transfer, or other power transfer information to the transmitter 110. In another embodiment, in response to the receiver 120 being disposed close to the transmitter 110, for example, in response to being sufficiently close so that a transformer can be formed by the antenna 124 and the antenna 126 to enable power transfer, the receiver 120 may be configured to start communication by transmitting a signal requesting power transfer to the transmitter 110. In such a case, the transmitter 110 may respond to the request by the receiver 120 by establishing a power contract, or may start power transfer to the receiver 120, for example, when a power contract has already been established. The transmitter 110 and the receiver 120 may transmit and receive the communication signal 132, data, or other information via the inductive coupling of the antenna 124 and the antenna 126.

[0016] NFC is a short-range wireless communication technology that enables standardized communication between two devices such as smartphones and smart tags. Conventionally, NFC can be used for data exchange, and NFC can also be extended to enable wireless power transfer from a power source to a listener at power levels in the range of approximately 1 watt (W) to 5 W. An important issue in an NFC system is antenna design and impedance matching for obtaining optimal power transfer efficiency. This is particularly prominent in wireless power applications where the equivalent impedance seen by the receiver can vary significantly.

[0017] As will be described in more detail below, the transmitter 110 of system 100 can execute runtime antenna matching techniques by reducing the number of external components to continuously optimize the impedance of the antenna in response to changes in operating conditions. To perform runtime antenna matching without adding external components, the circuit 107 of the transmitter 110 can be configured to sense the voltage of the switching converter 106 and transmit a voltage signal to the circuit 108. The circuit 108 can be configured to detect negative voltage spikes. The controller 104 can be configured to use the detected voltage spikes to determine a method for continuously matching the impedance of the antenna to the output impedance of the transmitter 110.

[0018] FIG. 2 is a diagram showing an exemplary circuit that can be implemented on a polar to perform runtime antenna matching for wireless power transmission by short-range wireless communication. The description of FIG. 2 may refer to the components shown in FIG. 1. In one embodiment shown in FIG. 2, the antenna interface circuit 102 shown in FIG. 1 can be formed by a plurality of circuit components such as resistors, inductors, and capacitors that can continuously adjust so that the input impedance of the antenna 124 matches the output impedance of the transmitter 110. The antenna interface circuit 102 can include an electromagnetic compatibility (EMC) filter 202, a matching network 204, and an attenuation circuit 206. Further, the EMC filter 202 can include two inductors L1 and L2, and two variable capacitors VC1 and VC2. The matching network 204 can include four capacitors C1, C2, C3, and C4. The attenuation circuit 206 can include two resistors R1 and R2. The equivalent antenna circuit can include a resistor R3, an inductor L, and a capacitor C7. The antenna interface circuit 102 can be connected to two nodes TX1 and TX2 of the switching converter 106 of the transmitter 110.

[0019] The switching converter 106 can send one or more drive signals 130, which can be rectangular waves, to the EMC filter 202 of the antenna interface circuit 102. The EMC filter 202 can convert the drive signal 130 into a sine wave signal 230 and reduce electromagnetic interference (EMI). Since the impedance in the antenna, such as antenna 124 or antenna 126, is essentially high, it is necessary to match the impedance between the output of the transmitter 110 and the input of the antenna 124. The sine wave signal 230 output by the EMC filter 202 can pass through the matching network 204, and the impedance in the antenna 124 can be matched to the output impedance of the transmitter 110 by the arrangement of the capacitors C1, C2, C3, and C4 in the matching network 204. In one embodiment, the attenuation circuit 206 can include any component configured to reduce the Q (quality) value of the antenna 124. The resistors R1 and R2 in the attenuation circuit 206 can increase the bandwidth of the system by reducing the Q value of the antenna. Also, as shown in FIG. 2, the antenna 124 can be modeled by at least the resistor R3, the inductor L3, and the capacitor C5. The antenna 124 can be configured to transmit a communication signal from the transmitter 110 to the receiver 120 by generating a magnetic field.

[0020] Referring to the embodiment shown in FIG. 1, circuit 107 can measure the voltage within switching converter 116 (e.g., the voltage across LS1 and LS2). Circuit 108 can detect whether there is a voltage spike, such as a negative voltage spike, in the voltage measured by circuit 107. Based on whether there is a voltage spike that can be indicated by the output of circuit 108, controller 104 can adjust one or more components within antenna interface circuit 102. In one embodiment, controller 104 can adjust variable capacitors VC1 and VC2 by changing their voltages. By adjusting variable capacitors VC1 and VC2, antenna 124 can be adjusted to match the output impedance of transmitter 110. By adjusting VC1 and VC2, the resonant frequency of antenna interface circuit 102 can be adjusted to correspond to the switching frequency of switching converter 106. The correspondence between the resonant frequency of antenna interface circuit 102 and the switching frequency of switching converter 106 can make the load impedance of transmitter 110 purely resistive, avoid reactive power loss, and match the impedance of antenna 124 to the output impedance of transmitter 110.

[0021] FIG. 3 is a diagram showing another exemplary circuit that can be implemented on a polar to perform runtime antenna matching for wireless power transfer by short-range wireless communication. In another exemplary embodiment shown in FIG. 3, the antenna interface circuit 102 can be configured to have capacitors and switches in series with the EMC filter 202 (C1a, C2a, ... Cna, and C1b, C2b, ... Cnb). As an alternative to using the variable capacitors VC1 and VC2 as shown in FIG. 2, the capacitors C1a, C2a, ... Cna, and C1b, C2b, ... Cnb can be switched inside or outside the EMC filter 202 to adjust the antenna 124. Each capacitor inside the EMC filter 202 is connected in series to a switch, and each connected switch can be controlled by the controller 104 to switch the connected capacitor inside or outside the EMC filter 202. Some of the capacitors inside the EMC filter 202 can be connected in series with each other, and other capacitors inside the EMC filter 202 can be connected in parallel with each other. The series connection and parallel connection can each have their own switch for each capacitor and enable the controller 104 to adjust the antenna 124 to different extents. The controller 104 can control the switch to enable or disable the corresponding capacitor to change the impedance of the antenna 124. For example, switching two capacitors connected in series inside and outside the EMC filter 202 can reduce the impact on the impedance of the antenna 124 compared to switching two capacitors connected in parallel. By selectively switching the capacitors inside the EMC filter 202, the resonant frequency of the antenna interface circuit 102 can be adjusted to correspond to the switching frequency of the switching converter 106.By the correspondence between the resonance frequency of the antenna interface circuit 102 and the switching frequency of the switching converter 106, the load impedance of the transmitter 110 can be made purely resistive, avoiding reactive power loss, and the impedance of the antenna 124 can be matched to the output impedance of the transmitter 110.

[0022] FIG. 4 is a diagram showing one or more circuits that can be implemented for runtime antenna matching of wireless power transmission by short-range wireless communication in one embodiment. In the embodiment shown in FIG. 4, the switching converter 106 can be an inverter configured to drive the antenna 124. The switching converter 106 can be formed by two half-bridge circuits including two high-side MOSFETs (metal-oxide-semiconductor field-effect transistors) HS1, HS2 and two low-side MOSFETs LS1, LS2. Two nodes TX1, TX2 can be driven by the switches HS1, HS2, LS1, LS2 of the switching converter 106 to generate two rectangular waves that are relatively 180-degree phase-shifted with a duty cycle of 50%. The circuit 107 can include a circuit 152 and a circuit 154. The circuit 152 can be configured to detect the voltage of LS1 by measuring the voltage between the node TX1 and the power supply ground (PVSS). The circuit 154 can be configured to detect the voltage of LS2 by measuring the voltage between the node TX2 and PVSS.

[0023] For example, the circuit 152 can include a clamp circuit 501 that can be connected between the node TX1 and the comparator 402. The clamp circuit 501 can be a circuit configured to limit the output voltage so as to shield any high voltage in the MOSFET or TX1. The comparator 402 can be configured to generate a voltage signal CO1. The circuit 154 can include a clamp circuit 502 that can be connected between the node TX2 and the comparator 404. The clamp circuit 502 can be a circuit configured to limit the output voltage so as to shield any high voltage in the MOSFET or TX2. The comparator 404 can be configured to generate a voltage signal CO2.

[0024] In one embodiment, the switching converter 106 can operate in a tri-state mode in which the switches HS1, HS2, LS1, and LS2 are turned off. Even when the switches HS1, HS2, LS1, and LS2 are turned off, their body diodes can still have conduction capabilities. Thus, the circuits 152 and 154 can still detect a low voltage signal (e.g., zero, near zero, or a relatively low voltage representing logic Lo). The detected low voltage signal can be supplied to the comparators 402 and 404 in the circuits 152 and 154, respectively. The comparator 402 can output a voltage signal CO1, and the comparator 404 can output a voltage signal CO2. In one embodiment, the circuit 108 can be configured to use the voltage signals CO1 and CO2 to detect a negative spike at the end of a switching cycle in the voltages measured from the nodes TX1 and TX2. In one embodiment, if there is a glitch or a negative voltage spike at the end of a switching cycle in the voltages measured from LS1 and LS2, the voltage signals CO1 and CO2 can be high voltage signals (e.g., a relatively high voltage representing "1" or logic Hi). In one embodiment, the circuit 108 can be configured to use the voltage signals CO1 and CO2 to detect a negative spike at the start of a switching cycle in the voltages measured from the nodes TX1 and TX2. In another embodiment, the circuit 108 can be configured to use the voltage signals CO1 and CO2 to detect a positive spike at the end of a switching cycle in the voltages measured from HS1 and HS2.

[0025] FIG. 5 is a diagram showing one or more circuits that can be implemented for runtime antenna matching for wireless power transfer by short-range wireless communication in one embodiment. In the embodiment shown in FIG. 5, circuit 152 and circuit 154 are respectively connected to circuits 156 and 158 within circuit 108. Circuit 156 includes an inverter 506, an AND gate 508, a rising edge filter 510, and a C element 512. Circuit 155 can receive a voltage signal CO1 from circuit 107. Also, circuit 155 can receive the gate-source voltage VGS_LS1 of LS1 from switching converter 106. Inverter 506 can invert VGS_LS1, and the inverted VGS_LS1 and the voltage signal CO1 can be supplied as inputs to AND gate 508. When LS1 turns off, VGS_LS1 gradually decreases to zero, and inverter 506 can output a voltage representing logic Hi (or "1"), whereby AND gate 508 passes CO1 to rising edge filter 510 regardless of the state or value of CO1. The rising edge filter 510 can be a circuit configured to filter the voltage signal CO1 to reduce the high-frequency bounce caused by comparator 402. The C element 512 can be a logic circuit that holds its current state unless both inputs are the same. If CO1 remains high for a predetermined time dT, the C element 512 can latch the high voltage at its output 514 for dT. The fact that the output 514 of the C element 512 remains high for dT can indicate that there is a glitch, i.e., a negative voltage spike, in the voltage at node TX1.

[0026] Circuit 158 includes an inverter 516, an AND gate 518, a rising-edge filter 520, and a C element 522. Circuit 158 can receive a voltage signal CO2 from circuit 107. Also, circuit 158 can receive the gate-source voltage VGS_LS2 of LS2 from the switching converter 106. The inverter 516 can invert VGS_LS2, and the inverted VGS_LS2 and the voltage signal CO2 can be supplied as inputs to the AND gate 518. When LS2 turns off, VGS_LS2 gradually decreases to zero, and the inverter 516 can output a voltage representing logic Hi (or "1"), whereby the AND gate 518 passes CO2 to the rising-edge filter 520 regardless of the state or value of CO2. The rising-edge filter 520 can be a circuit configured to filter the voltage signal CO2 to reduce high-frequency bounce caused by the comparator 404. The C element 522 can be a logic circuit that holds its current state unless both inputs are the same. If CO2 remains at a high voltage for a predetermined time dT, the C element 522 can latch a high voltage at its output 524 for dT. The output 524 of the C element 522 remaining at a high voltage for dT can indicate that there is a glitch, i.e., a negative voltage spike, in the voltage at node TX2.

[0027] FIG. 6 is a flowchart of a process for updating a count that can be used for runtime antenna matching of wireless power transfer by near-field wireless communication in one embodiment. The process 600 shown in FIG. 6 may include one or more operations, actions, or functions represented by one or more of blocks S601, S602, S603, S604, S605, S606, S607, S608, S609, S610, S611, S612, S613, S614, and / or S615. Although shown as individual blocks in the figure, depending on the desired application, various blocks may be divided into additional blocks, combined into fewer blocks, omitted, executed in a different order, or executed in parallel. The description of FIG. 6 can refer to the components shown in FIGS. 1-5.

[0028] In one aspect, to achieve exact matching between the output impedance of the transmitter 110 and the antenna 124, the input impedance of the matching network 204 needs to be purely resistive. To make the input impedance of the matching network 204 purely resistive, the voltages at nodes TX1 and TX2 need to be in the same phase as the currents flowing through TX1 and TX2. When the voltages and currents at nodes TX1 and TX2 are in the same phase, zero-current events occur in the same phase as zero-voltage events. In one aspect, the voltages at nodes TX1 and TX2 are known because they are supplied by the transmitter 110. To measure the currents flowing through nodes TX1 and TX2, the controller 104 can execute the process 600 shown in FIG. 6 to insert the tri-state mode of the switching converter 106 at a time close to a zero-voltage event. During the tri-state mode, the controller 104 can detect whether a negative voltage spike exists in the voltages at nodes TX1 and TX2. Whether a negative voltage spike exists can indicate the direction of the current flowing through nodes TX1 and TX2 (e.g., positive or negative). The direction of the current can indicate the relative phase between the voltage and the current and can be used to determine how to adjust VC1 and VC2 in FIG. 2 (or which switch to activate in FIG. 3).

[0029] The process 600 starts from block S601. Here, the controller 104 initializes a count C set to an initial value such as C = 32. The count C can represent the number of consecutive negative voltage spikes counted by the controller 104. The maximum value of the count C is programmable, and the minimum value of the count C can be set to zero. In one embodiment, the initial value of C can be a median value between the maximum and minimum values of C (e.g., rounded to the nearest integer). For example, if the maximum value of C is 63 and the minimum value is zero, the initial value of C can be set to 32 in block S601.

[0030] In block S603, the controller 104 can drive the switching converter 106 as an inverter by alternately switching a pair of HS1, LS2 and a pair of HS2, LS1. In block S603, while HS1 and LS2 are turned on, HS2 and LS1 are turned off. In block S605, the clock of the controller 104 transitions from a low state to a high state. That is, a rising edge event occurs. In response to the rising edge event, process 600 proceeds to block S607. Here, the controller 104 can start the tri-state mode by turning off HS1, HS2, LS1, and LS2. In one aspect, since HS1 and LS2 are turned on in block S603, when the controller 104 turns off HS1 and LS2 for the tri-state mode, it may take time for the voltage at LS2 to drop to zero. When the tri-state mode is inserted in response to the rising edge event, sufficient voltage can be supplied from nodes TX2 and PVSS to the comparator 404 of circuit 154 for measuring the voltage across LS2. Therefore, in block S607, the controller 104 inserts the tri-state mode near the zero voltage event (for example, before the voltage at LS2 becomes zero).

[0031] During the tri-state time or tri-state mode, the controller 104 can execute blocks S609, S611, S613, and S615. In block S609, the controller 104 can use circuits 107, 108 to detect whether there is a voltage spike in the voltages measured from nodes TX1, TX2. In response to the controller 104 detecting no voltage spike in block S609, process 600 can proceed to block S611. Here, the value of count C is updated. The absence of a negative voltage spike in block S609 may indicate that it is necessary to increase the resonant frequency Fres. In response to the controller 104 detecting the presence of a voltage spike in block S609, process 600 can proceed to S613. Here, the value of count C is updated. The presence of a negative voltage spike in block S609 may indicate that it is necessary to reduce the resonant frequency Fres. In block S611, the absence of a voltage spike may indicate that the resonant frequency ("Fres") is less than or equal to the switching frequency ("Fsw") of the switching converter 106. Therefore, the controller 104 can determine in block S611 that Fres≦Fsw. Further, in block S611, the count C can be set to a large value between zero and C-1. For example, if C = 32, since 32-1 is greater than zero, the count C is set to 31 in block S613. Therefore, the count C will not become less than zero. In block S615, when the tri-state time has elapsed, the controller 104 can return to switching HS1, HS2, LS1, LS2 to operate the switching converter 106 by proceeding to block S602.

[0032] In block S613, the presence of a voltage spike may indicate that the resonant frequency Fres is greater than or equal to the switching frequency Fsw of the switching converter 106. Therefore, the controller 104 can determine in block S613 that Fres > Fsw. Further, in block S613, the count C can be set to a smaller value between the maximum value of C such as 63 and C + 1. For example, when C = 32, the count C is set to 33 in block S611.

[0033] In the embodiment shown in FIG. 6, since HS1 and LS2 are turned on and HS2 and LS1 are turned off in block S603, the controller 104 can turn off HS1 and LS2 and turn on HS2 and LS1 in block S602. In block S604, the clock of the controller 104 can transition from a high state to a low state. That is, a falling edge event occurs. In response to the falling edge event, process 600 proceeds to block S606. Here, the controller 104 can start the tri-state mode by turning off HS1, HS2, LS1, and LS2. In one aspect, since HS2 and LS1 are turned on in block S602, when the controller 104 turns off HS2 and LS1 for the tri-state mode, it may take time for the voltage at LS1 to drop to zero. When the tri-state mode is inserted in response to the falling edge event, sufficient voltage can be supplied from nodes TX1 and PVSS to the comparator 402 of the circuit 152 for measuring the voltage across LS1. Therefore, in block S606, the controller 104 inserts the tri-state mode near the zero voltage event (e.g., before the voltage at LS1 becomes zero). Blocks S608, S610, S612, and S614 can be the same as blocks S609, S611, S613, and S615, respectively. By the end of the tri-state time in block S614, process 600 can return to block S603.

[0034] According to process 600, controller 104 can perform negative voltage spike detection and update count C for each transition including the rising and falling edges of the clock of transmitter 110. Thus, count C can be updated for each clock cycle of transmitter 110. As will be described in FIG. 7 below, count C can be used to determine whether to increase the capacitances of VC1 and VC2 shown in FIG. 2 or selectively switch the capacitors shown in FIG. 3 to adjust antenna 124 of transmitter 110.

[0035] FIG. 7 is a diagram showing a process for determining capacitance adjustment in runtime antenna matching of wireless power transfer by short-range wireless communication in one embodiment. The process 700 shown in FIG. 7 may include one or more operations, actions, or functions represented by one or more blocks S701, S703, S705, S707, S709, and / or S711. Although shown as individual blocks in the figure, depending on the desired application, various blocks may be divided into additional blocks, combined into fewer blocks, omitted, executed in a different order, or executed in parallel. The description of FIG. 7 can refer to the components shown in FIGS. 1-6.

[0036] Process 700 can be executed by controller 104 to determine whether to increase or decrease the capacitance of the EMC filter shown in FIGS. 2 and 3 based on the accumulation of count C. Process 700 can start from block S701. Here, controller 104 can start the execution of process 700. In block S703, controller 104 can determine whether the polling timer has expired. In one embodiment, the polling timer can be configured to track the number of clock cycles of transmitter 110. For example, the polling timer can track the clock cycles of transmitter 110 and assert expiration every 5 clock cycles or other programmable number of cycles less than the maximum value of C.

[0037] In response to the expiration of the polling timer in block S703, the controller 104 can determine whether the count C has reached the maximum value of 63 in block S705. If the count C reaches the maximum value of 63, in block S709, the controller 104 can increase the capacitance of the EMC filter 202 shown in FIG. 2 or FIG. 3. For example, the controller 104 can increase the capacitance of the EMC filter 202 by increasing the capacitance of VC1 and VC2 in FIG. 2, or by switching an additional capacitor to the EMC filter 202 in FIG. 3. If the count C has not reached the maximum value of 63, the process 700 can proceed to block S707. Here, it is possible to check whether the value of the count C has reached the minimum value of zero.

[0038] If the count C reaches zero, in block S711, the controller 104 can decrease the capacitance of the EMC filter 202 shown in FIG. 2 or FIG. 3. For example, the controller 104 can decrease the capacitance of the EMC filter 202 by decreasing the capacitance of VC1 and VC2 in FIG. 2, or by switching a capacitor from the EMC filter 202 in FIG. 3. After increasing the capacitance in block S709 or decreasing the capacitance in block S711, the process 700 can return to block S701 and wait for the next expiration of the polling timer in block S703.

[0039] FIG. 8 is a diagram showing waveforms of an example of runtime antenna matching for wireless power transmission by short-range wireless communication in one embodiment. The description of FIG. 8 can refer to the components shown in FIGS. 1 to 7. Waveform 802 shows the voltages at nodes TX1 and TX2 of the half-cycle switching converter 106. Waveform 804 shows the voltages applied to VC1 and VC2 of the antenna interface circuit 102 shown in FIG. 2. Waveform 806 shows the measured values of the variable capacitors, for example VC1 and VC2, of the antenna interface circuit 102 shown in FIG. 2. In the first time period 812, the resonance frequency Fres can become much larger than the switching frequency Fsw as a result of the presence of negative voltage spikes in the voltages measured from nodes TX1 and TX2. According to the process 600 of FIG. 6, when Fres is greater than Fsw, the count C can increase. Next, according to the process 700 of FIG. 7, when the count C reaches the maximum value, the controller 104 can increase the capacitances of VC1 and VC2. Note that in waveform 804, the voltages applied to VC1 and VC2 are similar to a step function by which the controller 104 adjusts the capacitances of VC1 and VC2 based on the expiration of the polling time of FIG. 7 and based on whether the count C has reached the maximum value. In other words, the adjustment of the voltages applied to VC1 and VC2 does not need to be performed in all cycles in order to maintain the processing power. In the second time period 814, the resonance frequency Fres remains greater than the switching frequency Fsw as a result of the presence of negative voltage spikes in the voltages measured from nodes TX1 and TX2 at the start of the switching cycle. Therefore, the controller 104 can continue to increase the capacitances of VC1 and VC2 in the time period 814.

[0040] In the third time period 816, the resonance frequency Fres becomes equal to the switching frequency Fsw as a result of no negative voltage spike in the voltage measured from nodes TX1 and TX2 at the start of the switching cycle. Therefore, the capacitances of VC1 and VC2 can be considered as the optimal capacitances for matching the impedance of the antenna 124 to the output impedance of the transmitter 110. In one embodiment, according to the process 600 of FIG. 6, when Fres is equal to Fsw, the count C can be decreased. Next, according to the process 700 of FIG. 7, when the count C reaches its minimum value or zero, the controller 104 can decrease the capacitances of VC1 and VC2.

[0041] In the fourth time period 818, the resonance frequency Fres becomes less than the switching frequency Fsw as a result of no negative voltage spike in the voltage measured from nodes TX1, TX2 at the start of the switching cycle. According to the process 600 of FIG. 6, when Fres is less than Fsw, the count C can be decreased. Next, according to the process 700 of FIG. 7, when the count C reaches its minimum value or zero, the controller 104 can decrease the capacitances of VC1 and VC2. In the fifth time period 820, the resonance frequency Fres remains less than the switching frequency Fsw as a result of no negative voltage spike in the voltage measured from nodes TX1 and TX2 at the start of the switching cycle. Therefore, the controller 104 can continue to decrease the capacitances of VC1 and VC2 in the time period 820.

[0042] FIG. 9 is a flowchart of a process for performing runtime antenna matching for wireless power transfer by short-range wireless communication in one embodiment. Process 900 may include one or more operations, actions, or functions indicated by one or more blocks 901, 903, and / or 905. Although shown as individual blocks in the figure, depending on the desired application, various blocks may be divided into additional blocks, combined into fewer blocks, omitted, executed in a different order, or executed in parallel.

[0043] Process 900 may be implemented by a wireless power transfer device (e.g., a transmitter, a receiver, or a transceiver). Process 900 can start at block 901. Here, the circuit in the wireless power transfer device can sense the voltage in the switching converter. In one embodiment, the circuit can detect the clock event of the clock signal. The circuit can operate the switching converter in a tri-state mode in response to the detection of the clock event. The circuit can sense the voltage in the switching converter during the tri-state mode.

[0044] Process 900 can proceed from block 901 to block 903. At block 903, the circuit can determine whether a negative voltage spike exists in the detected voltage. Process 900 can proceed from block 903 to block 905. At block 905, the circuit can adjust the capacitance of the antenna interface circuit between the switching converter and the antenna to perform impedance matching based on whether a negative voltage spike exists in the detected voltage. In one embodiment, the circuit can adjust the capacitance of the antenna interface circuit by determining that a negative voltage spike exists in the detected voltage. The circuit can increase the capacitance of the antenna interface circuit in response to the determination that a negative voltage spike exists in the detected voltage. Further, the circuit can determine that no negative voltage spike exists in the detected voltage. The circuit can decrease the capacitance of the antenna interface circuit in response to the determination that no negative voltage spike exists in the detected voltage.

[0045] In one embodiment, the circuit determines that the number of consecutive negative voltage spikes present in the detected voltage has reached a first predetermined value, and in response to the determination that the number of consecutive negative voltage spikes has reached the first predetermined value, the circuit can increase the capacitance of the antenna interface circuit. In one embodiment, the circuit determines that the number of absences of consecutive negative voltage spikes in the detected voltage has reached a second predetermined value, and in response to the determination that the absence of consecutive negative voltage spikes has reached the second predetermined value, the circuit can decrease the capacitance of the antenna interface circuit.

[0046] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, segment, or portion of instructions that include one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may, in fact, be implemented substantially simultaneously, or in the reverse order depending on the relevant functions, in some cases. It should also be noted that each block of the block diagrams and / or flowcharts, as well as combinations of those blocks, can be implemented by a special-purpose hardware-based system that performs the specified functions or operations, or by a combination of special-purpose hardware and computer instructions.

[0047] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. The singular forms used herein are also intended to include the plural forms unless specifically stated otherwise. It should also be noted that the term "comprising" used herein defines the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0048] All means or steps and corresponding structures, materials, acts, and equivalents of the functional elements recited in the appended claims are intended to include any structure, material, or act for achieving the functions in combination with other elements specifically recited. The description of the disclosed embodiments of the present invention is provided for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. It will be apparent to those skilled in the art that many modifications and variations can be made without departing from the scope and spirit of the invention. The above-described embodiments were chosen and described in order to best explain the principles and practical application of the invention and to enable those skilled in the art to understand the invention with various modifications made for the particular applications under consideration.

Claims

1. 1. An integrated circuit comprising: A controller; a circuit configured to sense a voltage in the switching converter and determine whether a negative voltage spike is present in the sensed voltage; Including, the controller is configured to adjust a capacitance of an antenna interface circuit between the switching converter and an antenna to perform impedance matching based on the presence or absence of the negative voltage spike in the sensed voltage. Integrated circuits.

2. The integrated circuit of claim 1 , wherein the controller, the switching converter, and the circuit are part of a poler of a Near Field Communication (NFC) wireless power transfer system.

3. The integrated circuit of claim 1 , wherein the circuit is configured to sense the voltage from a low-side switch in the switching converter.

4. The integrated circuit of claim 1 , wherein the circuit is configured to sense a voltage across the switching converter during a tri-state mode of the switching converter.

5. The controller: determining that the negative voltage spike is present in the sensed voltage; increasing a capacitance of the antenna interface circuit in response to determining that the negative voltage spike is present in the sensed voltage; determining that the sensed voltage is free of the negative voltage spike; configured to reduce a capacitance of the antenna interface circuit in response to determining that the sensed voltage is absent of the negative voltage spike.

10. The integrated circuit of claim 1.

6. The integrated circuit of claim 1 , wherein the controller is configured to adjust a capacitance of the antenna interface circuit by adjusting a capacitance of an electromagnetic compatibility (EMC) filter in the antenna interface circuit.

7. The controller: determining that a number of consecutive negative voltage spikes present in the sensed voltage has reached a first predetermined value; increasing a capacitance of the antenna interface circuit in response to determining that a number of consecutive negative voltage spikes has reached the first predetermined value; determining that the number of consecutive absences of the negative voltage spikes in the sensed voltage has reached a second predetermined value; configured to decrease a capacitance of the antenna interface circuit in response to determining that the absence of consecutive negative voltage spikes has reached the second predetermined value.

10. The integrated circuit of claim 1.

8. The controller: Detecting clock events on a clock signal; configured to operate the switching converter in a tri-state mode in response to detecting the clock event; the circuitry is configured to sense the voltage across the switching converter during the tri-state mode; 10. The integrated circuit of claim 1.

9. The antenna, An antenna interface circuit; A transmitter; Including, The transmitter includes: Sensing a voltage across a switching converter of the transmitter; determining whether a negative voltage spike is present in the sensed voltage; configured to adjust a capacitance of the antenna interface circuit between the switching converter and the antenna to perform impedance matching based on the presence or absence of the negative voltage spike in the sensed voltage. Device.

10. The device of claim 9 , wherein the transmitter is a poller of a Near Field Communication (NFC) wireless power transfer system.

11. 10. The apparatus of claim 9, wherein the transmitter is configured to sense the voltage from a low-side switch in the switching converter.

12. 10. The apparatus of claim 9, wherein the transmitter is configured to sense a voltage across the switching converter during a tri-state mode of the switching converter.

13. The transmitter includes: determining that the negative voltage spike is present in the sensed voltage; increasing a capacitance of the antenna interface circuit in response to determining that the negative voltage spike is present in the sensed voltage; determining that the sensed voltage is free of the negative voltage spike; configured to reduce a capacitance of the antenna interface circuit in response to determining that the sensed voltage is absent of the negative voltage spike.

10. The apparatus of claim 9.

14. 10. The apparatus of claim 9, wherein the transmitter is configured to adjust a capacitance of the antenna interface circuit by adjusting a capacitance of an electromagnetic compatibility (EMC) filter in the antenna interface circuit.

15. The transmitter includes: determining that a number of consecutive negative voltage spikes present in the sensed voltage has reached a first predetermined value; increasing a capacitance of the antenna interface circuit in response to determining that a number of consecutive negative voltage spikes has reached the first predetermined value; determining that the number of consecutive absences of the negative voltage spikes in the sensed voltage has reached a second predetermined value; configured to decrease a capacitance of the antenna interface circuit in response to determining that the absence of consecutive negative voltage spikes has reached the second predetermined value.

10. The apparatus of claim 9.

16. The transmitter includes: Detecting clock events on a clock signal; responsive to detecting the clock event, operating the switching converter in a tri-state mode; configured to sense the voltage across the switching converter during the tri-state mode; 10. The apparatus of claim 9.

17. 1. A method for operating a wireless powered device, comprising: sensing a voltage in a switching converter; determining whether a negative voltage spike is present in the sensed voltage; adjusting a capacitance of an antenna interface circuit between the switching converter and an antenna to perform impedance matching based on the presence or absence of the negative voltage spike in the sensed voltage; A method comprising:

18. The step of adjusting the capacitance of the antenna interface circuit includes: determining that the negative voltage spike is present in the sensed voltage; increasing a capacitance of the antenna interface circuit in response to determining that the negative voltage spike is present in the sensed voltage; determining that the sensed voltage is free of the negative voltage spike; in response to determining that the sensed voltage is absent the negative voltage spike, decreasing a capacitance of the antenna interface circuit; 20. The method of claim 17, comprising:

19. determining that a number of consecutive negative voltage spikes present in the sensed voltage reaches a first predetermined value; increasing a capacitance of the antenna interface circuit in response to determining that a number of consecutive negative voltage spikes has reached the first predetermined value; determining that the number of consecutive absences of the negative voltage spikes in the sensed voltage reaches a second predetermined value; decreasing a capacitance of the antenna interface circuit in response to determining that the absence of consecutive negative voltage spikes has reached the second predetermined value; 20. The method of claim 17, further comprising:

20. Detecting a clock event in a clock signal; in response to detecting the clock event, operating the switching converter in a tri-state mode; sensing the voltage across the switching converter while in the tri-state mode; 20. The method of claim 17, further comprising:

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