Systems and methods for tuning capacitance of qubits

Abstract

To tune physical characteristics of quantum devices.SOLUTION: An analog computing system having a qubit is provided with inductors positioned near the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. The near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitances for the qubit. The inductors may be tuned to homogenize both the capacitance and the inductance.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Field The present disclosure generally relates to analog computing, and more particularly to the design and operation of devices for tuning the physical properties of quantum devices.

Background Art

[0002] Background Quantum Device A quantum device is a structure in which quantum mechanical effects are observable. A quantum device includes a circuit in which current transport is governed by quantum mechanical effects. Such devices include spintronics in which electron spin is used as a resource and superconducting circuits. A superconducting circuit is a circuit that includes superconducting devices. A superconducting device is a device that includes a superconducting material. A superconducting material is a material that has no electrical resistance below critical levels of current, magnetic field, and temperature. Both spin and superconductivity are quantum mechanical phenomena. Superconductivity is a physical phenomenon well known in the art at the time of filing of the present application. Quantum devices can be used in measuring instruments such as computing machines.

[0003] Quantum Computing Quantum computing and quantum information processing are active research areas and define several classes of commercially available products. A quantum computer is a system that directly utilizes at least one quantum mechanical phenomenon such as superposition, tunneling, and entanglement to perform operations on data. The elements of a quantum computer are quantum bits, which are quantum binary numbers. Quantum computers have the potential to provide an exponential speedup for several classes of computational problems, such as computational problems that simulate quantum physics. Useful speedups may exist for other classes of problems.

[0004] One model of quantum computing is adiabatic quantum computing. Adiabatic quantum computing may be suitable for solving, for example, difficult optimization problems. Further details regarding adiabatic quantum computing systems, methods, and apparatuses are described, for example, in U.S. Patent No. 7,135,701 and U.S. Patent No. 7,418,283.

[0005] Quantum annealing Quantum annealing is a computational method that can be used to find the low-energy state of a system (generally preferably the ground state of the system). Conceptually similar to classical simulated annealing, this method relies on the fundamental principle that "natural systems tend towards lower energy states because lower energy states are more stable." Classical annealing uses classical thermal fluctuations to drive the system to a low-energy state, while quantum annealing can utilize quantum effects such as quantum tunneling as a source of delocalization to reach the energy minimum more precisely and / or rapidly than classical annealing. In quantum annealing, thermal effects and other noises can be present. The final low-energy state may not be the global energy minimum.

[0006] Adiabatic quantum computing can be considered a special case of quantum annealing. In adiabatic quantum computing, the system ideally starts in its ground state and remains there through adiabatic evolution. Thus, one of ordinary skill in the art will understand that quantum annealing systems and methods can generally be implemented on adiabatic quantum computers. Throughout this application, any reference to quantum annealing is intended to encompass adiabatic quantum computing unless the context requires otherwise.

[0007] Superconducting qubit The quantum processor can be a superconducting quantum processor including superconducting qubits. Wendin G. and Shumeiko v.S., "Superconducting Quantum Circuits, Qubits, and Computing" (arXiv:cond-mat / 0508729v1, 2005) provides a guide to the physics and principles of the operation of quantized superconducting electrical circuits for quantum information processing.

[0008] Coupling A coupler can provide a communicable coupling between quantum devices within a quantum processor. The coupling can be, for example, between adjacent and / or non-adjacent qubits. Unless explicitly indicated otherwise, as used herein and in the claims, the terms: couple, couples, coupling and their variations mean a direct or indirect communicable coupling or communication between two or more components.

[0009] Tuning of Qubit Characteristics Quantum devices such as qubits and couplers can possess various characteristics such as magnetic flux, persistent current, inductance, capacitance, etc. Since such characteristics can affect the results of quantum calculations performed by such qubits, it may be desirable to tune one or more of these characteristics to match the parameters of a given calculation. Exemplary systems and methods for tuning qubit characteristics including exemplary qubits and couplers are provided by U.S. Patent No. 8,536,566, U.S. Patent No. 9,152,923, PCT Application No. US2018 / 066613.

[0010] It is advantageous for qubits in an analog computing system, such as a quantum processor, to possess the same (or nearly the same) characteristics, such as inductance and capacitance. This aids in precisely mapping a problem (e.g., represented as a Hamiltonian) onto a physical analog processor. To that end, some analog processors include a device called an L-tuner for tuning the inductance of qubits (as described, for example, by U.S. Patent No. 8,536,566). Adding a "C-tuner" for tuning capacitance has been found to be difficult due to various factors such as structural complexity, resulting bandwidth limitations, interference with the flux qubit's eigenstates, operational flexibility, and / or other factors. Accordingly, there continues to be a need for systems and methods for tuning the capacitance of qubits.

[0011] The foregoing examples of related art and associated limitations are illustrative and are thus intended not to be exclusive. Other limitations of related art will become apparent to those of ordinary skill in the art upon reading this specification and studying the accompanying drawings. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0012] BRIEF SUMMARY Some aspects of the present disclosure provide an analog computing system that includes qubits. The qubits include a qubit loop formed by a first superconducting current path and at least one Josephson junction that interrupts the qubit loop. The at least one Josephson junction has a critical distance such that adding a concentrated inductance closer than the critical distance to at least one Josephson junction along the qubit loop reduces the qubit capacitance at the at least one Josephson junction, and adding a concentrated inductance farther than the critical distance from at least one Josephson junction along the qubit loop increases the qubit capacitance. The qubit further includes a plurality of inductors disposed along the qubit loop. Each of the plurality of inductors is tunable to provide a tunable inductance. The plurality of inductors includes one or more near inductors disposed along the qubit loop closer than the critical distance from at least one Josephson junction and one or more far inductors disposed along the qubit loop farther than the critical distance from at least one Josephson junction.

[0013] In some implementations, the analog computing system includes one or more couplers that are tunably couplable to the qubit loop. Each of the one or more couplers is tunable to provide a respective coupling strength to the qubit.

[0014] In some implementations, the tunable inductance of each inductor of the plurality of inductors is tunable within a corresponding inductance range, each of the one or more couplers has a corresponding coupler-induced inductance range, each coupler-induced inductance range includes a difference in qubit inductance at at least one Josephson junction between corresponding states of one of the one or more couplers, and the sum of the tunable inductance ranges of the plurality of inductors is greater than each of the respective ranges of the corresponding coupler-induced inductance ranges.

[0015] In some implementations, one of the plurality of inductors includes one or more inductor Josephson junctions that interrupt the qubit loop to provide respective tunable inductance ranges and are tunable. In some implementations, one of the plurality of inductors includes one or more DC-SQUIDs that include one or more inductor Josephson junctions. In some implementations, one of the plurality of inductors includes a plurality of DC-SQUIDs connected in series along the qubit loop.

[0016] In some implementations, the sum of the tunable inductance ranges of the plurality of inductors is greater than the full coupler induced inductance range, which includes the difference between a first coupler induced inductance and a second coupler induced inductance, where the first coupler induced inductance includes the qubit inductance in a first state in which each of one or more couplers is ferromagnetically coupled to the qubit, and the second coupler induced inductance includes the qubit inductance in a second state in which each of one or more couplers is antiferromagnetically coupled to the qubit.

[0017] In some implementations, one or more near inductors are collectively tunable to reduce the qubit capacitance from a first coupler induced capacitance to within a first threshold of a target capacitance; one or more far inductors are collectively tunable to increase the qubit capacitance from a second coupler induced capacitance to within a second threshold of the target capacitance.

[0018] In some implementations, the first coupler-induced capacitance includes qubit capacitance in a third state in which each of one or more couplers closer to at least one Josephson junction along the qubit loop than a critical distance, if any, is antiferromagnetically coupled to the qubit loop, and each of one or more couplers farther from at least one Josephson junction along the qubit loop than the critical distance, if any, is ferromagnetically coupled to the qubit loop; the second coupler-induced capacitance includes qubit capacitance in a fourth state in which each of one or more couplers closer to at least one Josephson junction along the qubit loop than a critical distance, if any, is ferromagnetically coupled to the qubit loop, and each of one or more couplers farther from at least one Josephson junction along the qubit loop than the critical distance, if any, is antiferromagnetically coupled to the qubit loop.

[0019] In some implementations, for a given target qubit inductance and a given set of coupling strengths of one or more couplers, a plurality of inductors are tunable to provide a tunable inductance for each of the first, second, third, and fourth states that increases the qubit inductance within a third threshold of the given target qubit inductance and performs at least one of increasing and decreasing the qubit capacitance within a fourth threshold of the target capacitance.

[0020] In some implementations, a qubit includes a second qubit loop, at least one Josephson junction interrupting the second qubit loop, and at least one secondary inductor disposed along the second qubit loop. In some implementations, the qubit loop and the second qubit loop partially overlap along a shared portion, and a shared inductor of the plurality of inductors is disposed along the shared portion. In some implementations, the shared inductor includes one of one or more close inductors.

[0021] In some implementations, at least one secondary inductor includes one or more secondary near inductors disposed along a second qubit loop each closer than a second critical distance from at least one Josephson junction; and one or more secondary far inductors disposed along a second qubit loop each farther than the second critical distance from at least one Josephson junction. In some implementations, the plurality of inductors and at least one secondary inductor collectively provide a collectively tunable inductance range of at least twice the full coupler induced inductance range.

[0022] Some aspects of the present disclosure provide systems and methods for tuning the effective capacitance of qubits within an analog computing system. The method is performed by a processor in communication with the analog computing system (e.g., by executing at least one of processor-executable instructions or data stored on at least one non-transitory processor-readable storage medium), and includes determining a predicted capacitance of a qubit, determining a target capacitance of the qubit, determining a total capacitance change ΔC based on the target capacitance and the predicted capacitance, and tuning a plurality of inductors. Each inductor is disposed at a corresponding distance from one or more Josephson junctions of the qubit along the qubit loop and is tuned to change the effective capacitance of the qubit based on the corresponding distance from the one or more Josephson junctions and the total capacitance change.

[0023] In some implementations, adding a lumped inductance closer to one or more Josephson junctions than a critical distance to one or more Josephson junctions along a qubit loop reduces the qubit capacitance in the one or more Josephson junctions, and adding a lumped inductance farther from the critical distance from the one or more Josephson junctions has a critical distance such that it increases the qubit capacitance. In some implementations, tuning a plurality of inductors includes tuning a first inductor of the plurality of inductors closer to one or more Josephson junctions than a critical distance along the qubit loop to reduce the qubit capacitance; and tuning a second inductor of the plurality of inductors farther from one or more Josephson junctions along the qubit loop than the critical distance to increase the qubit capacitance.

[0024] In some implementations, tuning a plurality of inductors based on a corresponding distance from one or more Josephson junctions includes tuning the first and second inductors based on their respective distances from a point located at a critical distance along the qubit loop from the one or more Josephson junctions.

[0025] In some implementations, the method includes determining a predicted inductance of a qubit; determining a target inductance of the qubit; and determining a total inductance change ΔL based on the target and predicted inductances. In some implementations, tuning a plurality of inductors to change the effective capacitance of a qubit includes tuning the plurality of inductors such that the sum of the corresponding tunable inductances of the plurality of inductors is within a threshold of the total inductance change ΔL, and tuning the plurality of inductors such that the sum of the tunable inductances is distributed among the plurality of inductors based on a total capacitance change ΔC.

[0026] In some implementations, tuning a plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC includes tuning the tunable inductance of a first inductor of the plurality of inductors to reduce the effective qubit capacitance and increase the effective qubit inductance; and tuning the tunable inductance of a second inductor of the plurality of inductors to increase the effective qubit capacitance and increase the effective qubit inductance.

[0027] In some implementations, tuning a plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC includes selecting a selection distribution from a plurality of candidate distributions of inductor tuning values based on the total capacitance change ΔC and the total inductance change ΔL; and tuning the plurality of tunable inductors based on the inductor tuning values of the selection distribution.

[0028] In some implementations, each candidate distribution corresponds to a candidate capacitance change, and selecting the selection distribution includes selecting the selection distribution based on the difference between the candidate capacitance change and the total capacitance change ΔC.

[0029] In some implementations, tuning the plurality of tunable inductors based on the selection distribution includes interpolating an interpolated inductor tuning value for each inductor of the plurality of inductors based on the inductor tuning value of the selection distribution and the inductor tuning value of an additional candidate distribution among the plurality of candidate distributions; and tuning the plurality of tunable inductors based on the interpolated inductor tuning values.

[0030] In some implementations, identifying a plurality of candidate distributions includes identifying a plurality of candidate distributions in a look-up table based on at least one of a total capacitance change ΔC and a total inductance change ΔL; an additional candidate distribution among the plurality of candidate distributions is close to the distribution selected in the look-up table.

[0031] In some implementations, identifying a plurality of candidate distributions of inductance tuning values includes examining a first set of inductance tuning values of one of a first inductor and a second inductor along a first axis of a look-up table, and for each of the first set of inductance tuning values such that the sum of the first and second inductance tuning values is within a threshold of the total inductance change ΔL, identifying corresponding inductance tuning values of additional inductors of the first and second inductors along a second axis of the look-up table, wherein each inductance tuning value from the first set pairs with the corresponding inductance tuning values of the additional inductors of the first and second inductors that include a candidate distribution and correspond to a predicted capacitance change.

[0032] In some implementations, selecting a selected distribution from a plurality of candidate distributions includes selecting a candidate distribution having a corresponding predicted capacitance change closest to the total capacitance change ΔC among the plurality of candidate distributions.

[0033] In some implementations, tuning a plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC includes examining the total capacitance change ΔC along a first axis of a look-up table; examining the total inductance change ΔL along a second axis of the look-up table; identifying a candidate distribution of inductance tuning values in the look-up table corresponding to the total capacitance change ΔC and the total inductance change ΔL; and tuning the plurality of inductors based on the candidate distribution.

[0034] In some implementations, examining at least one of the total capacitance change ΔC and the total inductance change ΔL includes determining an entry along at least one of the first and second axes of a look-up table that approximates at least one of the total capacitance change ΔC and the total inductance change ΔL.

[0035] In some implementations, tuning a plurality of inductors includes tuning a first inductor at a first distance from one or more Josephson junctions along a qubit loop to reduce the effective qubit capacitance and increase the effective qubit inductance; and tuning a second inductor at a second distance (the second distance being greater than the first distance) from one or more Josephson junctions along the qubit loop to increase the effective qubit capacitance and increase the effective qubit inductance.

[0036] In some implementations, determining the predicted capacitance of a qubit includes determining a coupler-induced capacitance load based on one or more coupling strengths of one or more couplers coupled to the qubit.

[0037] In some implementations, tuning a plurality of inductors to change the effective capacitance of a qubit based on the total capacitance change includes tuning a plurality of inductors to compensate for the coupler-induced capacitance load.

[0038] Some aspects of the present disclosure provide a computing system including at least one processor in communication with an analog processor having at least one qubit and at least one non-transitory processor-readable storage medium storing at least one of processor-executable instructions or data. The processor-executable instructions or data, when executed by the at least one processor, cause the at least one processor to perform acts including: determining a predicted capacitance of a qubit; determining a target capacitance of the qubit; determining a total capacitance change ΔC based on the target capacitance and the predicted capacitance; and causing the analog processor to tune a plurality of inductors to change an effective capacitance of the qubit based on a corresponding distance from one or more Josephson junctions and the total capacitance change, wherein each inductor is disposed at a corresponding distance from one or more Josephson junctions along a qubit loop.

[0039] In some implementations, these acts may further include determining a predicted inductance of the qubit, determining a target inductance of the qubit, and determining a total inductance change ΔL based on the target and predicted inductances. Tuning a plurality of inductors to change the effective capacitance of the qubit may include tuning the plurality of inductors such that a sum of corresponding tunable inductances of the plurality of inductors is within a threshold of the total inductance change ΔL, and tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC.

[0040] In some implementations, tuning a plurality of inductors based on a corresponding distance from one or more Josephson junctions may include tuning a first inductor and a second inductor based on respective distances of the first and second inductors from a point disposed at a critical distance along a qubit loop from one or more Josephson junctions. Tuning a plurality of inductors such that a sum of a plurality of tunable inductances is distributed among the plurality of inductors based on a total capacitance change ΔC may include tuning a tunable inductance of the first inductor to reduce an effective qubit capacitance and increase an effective qubit inductance; and tuning a tunable inductance of the second inductor to increase an effective qubit capacitance and increase an effective qubit inductance.

[0041] In some implementations, tuning a plurality of inductors such that a sum of a plurality of tunable inductances is distributed among the plurality of inductors based on a total capacitance change ΔC may include selecting a selection distribution from a plurality of candidate distributions of inductor tuning values based on the total capacitance change ΔC and a total inductance change ΔL; and tuning the plurality of tunable inductors based on the inductor tuning values of the selection distribution. Selecting the selection distribution may include selecting the selection distribution based on a difference between a candidate capacitance change corresponding to the selection distribution and the total capacitance change ΔC.

[0042] In some implementations, tuning a plurality of tunable inductors based on a selection distribution may include interpolating an inductor tuning value of each of the plurality of inductors based on an inductor tuning value of the selection distribution and an inductor tuning value of an additional candidate distribution among a plurality of candidate distributions; and tuning the plurality of tunable inductors based on the interpolated inductor tuning value. Identifying the plurality of candidate distributions may include identifying the plurality of candidate distributions in a look-up table based on at least one of a total capacitance change ΔC and a total inductance change ΔL, and the additional candidate distribution among the plurality of candidate distributions is close to the distribution selected in the look-up table. Identifying a plurality of candidate distributions of inductor tuning values may include examining a first set of inductor tuning values of one of a first inductor and a second inductor along a first axis of a look-up table, and for each of the first set of inductor tuning values, identifying corresponding inductor tuning values of additional inductors of the first and second inductors along a second axis of the look-up table such that the sum of the first and second inductor tuning values is within a threshold of the total inductance change ΔL, wherein each inductor tuning value from the first set pairs with corresponding inductor tuning values of additional inductors of the first and second inductors that include a candidate distribution and correspond to a predicted capacitance change.

[0043] In some implementations, selecting a selected distribution from a plurality of candidate distributions may include selecting the candidate distribution having the corresponding predicted capacitance change closest to the total capacitance change ΔC among the plurality of candidate distributions. Tuning a plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC may include examining the total capacitance change ΔC along a first axis of a look-up table, examining the total inductance change ΔL along a second axis of the look-up table, identifying a candidate distribution of inductor tuning values within the look-up table corresponding to the total capacitance change ΔC and the total inductance change ΔL; and tuning the plurality of inductors based on the candidate distribution. Examining at least one of the total capacitance change ΔC and the total inductance change ΔL may include determining an entry along at least one of the first and second axes of a look-up table that approximates at least one of the total capacitance change ΔC and the total inductance change ΔL.

[0044] In some implementations, tuning a plurality of inductors may include tuning a first inductor at a first distance from one or more Josephson junctions along a qubit loop to reduce the effective qubit capacitance and increase the effective qubit inductance; and tuning a second inductor at a second distance (the second distance being greater than the first distance) from one or more Josephson junctions along the qubit loop to increase the effective qubit capacitance and increase the effective qubit inductance. Determining the predicted capacitance of a qubit may include determining a coupler-induced capacitance load based on one or more coupling strengths of one or more couplers coupled to the qubit. Tuning a plurality of inductors to change the effective capacitance of a qubit based on a total capacitance change may include tuning the plurality of inductors to compensate for the coupler-induced capacitance load.

[0045] Some aspects of the present disclosure provide an analog computing system including a qubit including a Josephson junction; a first qubit loop formed by a first superconducting current path; and a second qubit loop formed by a second superconducting current path, wherein the first qubit loop and the second qubit loop are electrically connected in parallel to both ends of the Josephson junction.

[0046] In some implementations, the analog computing system may further include a first magnetic flux bias line in communication with the first qubit loop and a second magnetic flux bias line in communication with the second qubit loop, wherein the first magnetic flux bias line receives signals independently from the second magnetic flux bias line. The second qubit loop may include a first portion in communication with the Josephson junction and a second portion spaced apart from the Josephson junction, wherein the first portion and the second portion are separated by an intersection, and a current in the second qubit loop propagates in a first rotational direction in the first portion and in a second rotational direction opposite to the first rotational direction in the second portion.

[0047] In some implementations, the Josephson junction may include one of a compound Josephson junction or a compound-compound Josephson junction. The first qubit loop and the second qubit loop may partially overlap along a shared portion. The analog computing system may further include a coupler tunably coupled to one of the first qubit loop and the second qubit loop. The analog computing system may further include a second qubit coupled to the coupler. The first qubit loop and the second qubit loop may be symmetric about an axis of the Josephson junction, and the axis of the Josephson junction intersects a first connection between the first qubit loop, the second qubit loop, and the Josephson junction and a second connection between the first qubit loop, the second qubit loop, and the Josephson junction.

[0048] In some implementations, an analog computing system may further include one or more additional quantum bit loops electrically connected in parallel across the Josephson junctions. The analog computing system may also further include a plurality of inductors disposed along each of the first and second quantum bit loops, each of the plurality of inductors being tunable to provide a corresponding tunable inductance.

[0049] In other aspects, the above features may be combined in any reasonable combination as would be recognized by one of ordinary skill in the art.

[0050] Brief Description of the Drawings In the accompanying drawings, like reference numerals identify like elements or acts. The dimensions and relative positions of the elements in the drawings are not necessarily drawn to scale. For example, the shapes and angles of the various elements are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the drawn elements are not necessarily intended to convey any information regarding the actual shape of the particular elements, and may have been solely selected for ease of recognition in the accompanying drawings.

Brief Description of the Drawings

[0051]

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DETAILED DESCRIPTION OF THE INVENTION

[0052] Detailed Description In the following description, some specific details are set forth in order to provide a thorough understanding of various disclosed implementations. However, one of ordinary skill in the art will recognize that the implementations may be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures associated with computer systems, server computers, and / or communication networks have not been illustrated or described in order not to unnecessarily obscure the description of the implementations.

[0053] Unless the context requires otherwise, throughout the following specification and claims, the term "comprising" is synonymous with "including" and is inclusive or open-ended (i.e., does not exclude additional, non-enumerated elements or method acts).

[0054] References to "an implementation" or "implementations" throughout this specification mean that a particular feature, structure, or characteristic described in connection with the implementation is included in at least one implementation. Thus, the appearances of the phrases "in one implementation" or "in an implementation" in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations.

[0055] As used in this specification and the appended claims, the singular forms of the articles and indefinite articles include plural referents unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally employed in the sense of "and / or" unless the context clearly dictates otherwise.

[0056] The headings and abstracts of the disclosure provided herein are for convenience only and do not interpret the scope or meaning of the implementations.

[0057] L Tuner FIG. 1A is a schematic diagram of a superconducting flux qubit 100a. The qubit 100a includes a qubit loop 102 (e.g., a loop of superconducting material) interrupted by one or more Josephson junctions. In the exemplary implementation of FIG. 1A, the qubit loop 102 is interrupted by a compound Josephson junction 104 (also referred to as a “CJJ”) that includes current paths 131, 132, each interrupted by respective Josephson junctions 111, 112.

[0058] FIG. 1B is a schematic diagram of a superconducting flux qubit 100b. The qubit 100b includes a qubit loop 102 and a compound Josephson junction 104 that are substantially the same as those of the qubit 100a. The qubit 100b further includes an inductance tuner 140 (or “L tuner”) that provides a tunable inductance to the qubit 100b. The inductance tuner 140 can include, for example, a CJJ connected in series with the compound Josephson junction 104 within the qubit loop 102. As described, for example, in U.S. Patent No. 9,152,923, the inductance tuner 140 can be tuned by using a programmable interface 142: for example, by inductively and / or electrochemically coupling a control signal to the inductance tuner 140 and thereby tuning (and by extension) the Josephson inductance of the compound Josephson junction 140 of the qubit 100b.

[0059] Qubits 100a, 100b can be inductively or otherwise coupled to other devices. For example, in some implementations, qubits 100a, 100b are inductively coupled to other qubits via an inter - qubit coupler (not shown). Such coupling can affect the electromagnetic properties of qubits 100a, 100b. For example, the capacitance of qubit 100b can be a complex function of both the coupler settings and the L - tuner settings. In the past, this effect was small enough to be practically ignored, but as quantum processors scale up, some experiments have shown that this effect increases. For example, in some implementations, tuning both the coupler and the L - tuner can cause a change in qubit capacitance on the order of 10 fF, potentially causing errors in calibration, coupler - dependent asynchronization of qubit dynamics, and other difficult - to - address behaviors.

[0060] Division of the L - tuner The effect of the lumped inductance on the capacitance (such as that contributed by the L - tuner) changes not only with the scale of the inductance but also with the location along the qubit loop where the lumped inductance is placed with respect to one or more Josephson junctions that form part of the qubit. For example, an inductor having an inductance L near coupled in series (and positioned near) to one or more Josephson junctions can result in an effective qubit capacitance modeled as follows:

Equation

Equation

[0061] L near = L far = 0, both models yield C eff = C Q / 3, which results from the input impedance (the 1 / 3 factor results from the input impedance). However, when L near > 0, the resulting C eff is less than the predicted C Q / 3. That is, increasing the inductance of the nearby inductor causes a decrease in the effective qubit capacitance. Thus, the nearby inductor may be thought to prevent some of the intrinsic capacitance of the superconducting loop from being observed in one or more Josephson junctions. However, the distant inductor may have the opposite effect; that is, C eff tends to increase as L far increases.

[0062] The capacitance reduction behavior of the nearby inductor can be dominated by other dynamics if L near is large enough, and the effective qubit capacitance C effIt should be noted that an increase with respect to may potentially occur. However, it was determined through experiments that the capacitance reduction behavior of nearby inductors can be extended well beyond the typical programmable range of nearby inductors that are suitably positioned / scaled. (As used herein, the "scale" of an inductor refers to the structural features that govern the amount of inductance that the inductor can contribute to the qubit 201. For example, the scale of the exemplary inductor 206 can be at least partially determined by the size of the Josephson junctions that make it up, and smaller Josephson junctions (e.g., having a smaller area) generally correspond to a larger inductance and thus a larger scale. For some inductors such as spiral inductors, a larger area generally corresponds to more inductance and thus a larger scale).

[0063] Some aspects of the present disclosure include a plurality of tunable inductors (referred to herein and in the claims as "nearby inductors") that exhibit the capacitance reduction behavior described above with reference to L near and inductors (referred to herein and in the claims as "distant inductors") that exhibit the capacitance increase behavior described above with reference to L far to advantageously provide an analog computing system that includes qubits. The nearby inductors and the distant inductors can be independently tuned to provide a homogeneous (or at least substantially homogeneous) capacitance over a range of programmable states of the qubits. In some implementations, the inductors are tuned to provide both a homogeneous (or at least substantially homogeneous) capacitance and a homogeneous (or at least substantially homogeneous) inductance.

[0064] Figure 2 shows an exemplary analog computing system 200 that includes a qubit loop 202 and a qubit 201 having one or more Josephson junctions 204 (in the depicted exemplary implementation, the one or more Josephson junctions 204 include CJJ). The near inductor 206 interrupts the qubit loop 202 and is tunable to provide a corresponding tunable inductance L near The far inductor 208 interrupts the qubit loop 202 and is tunable to provide a corresponding tunable inductance L far (in some implementations, one, some, or all of the inductors 206, 208 are inductively coupled to the qubit loop 202). In the exemplary depicted implementation of FIG. 2, the analog computing system 200 further includes a coupler 222 communicatively coupled to the qubit loop 202. The various devices of the analog computing system 200 can be programmed via one or more programmable interfaces; in the exemplary depicted implementation, one or more of the Josephson junctions 204, the near inductor 206, the far inductor 208, and the coupler 222 are programmable via programmable interfaces 220a, 220b, 220c, 220d. The exemplary implementation of FIG. 2 shows one near inductor 206 and one far inductor 208, but it will be understood in the context of the disclosure presented herein that multiple near and far inductors can be provided without departing from the scope of the present disclosure.

[0065] The inductors 206, 208 may include any tunable inductor. In some implementations, at least one of the inductors 206, 208 may include an L-tuner, as described in U.S. Pat. No. 8,536,566, and may include, for example, one or more Josephson junctions disposed within, for example, one or more DC-SQUIDs. In an exemplary depicted implementation, each inductor 206, 208 includes a DC-SQUID having two Josephson junctions connected in parallel and tunable via respective programming interfaces 220b, 220c. The inductors 206, 208 may alternatively or additionally include other sources of lumped inductance (such as quantum flux parametrons inductively coupled to the qubit loop or mutual inductance). The inductors 206, 208 may have the same or different structures; for example, the inductor 206 may include a single DC-SQUID and the inductor 208 may include two DC-SQUIDs in series (inductor 308 in FIG. 3 is an example of the latter).

[0066] The inductors 206, 208 have respective inductances L within a tunable inductance range. near ,L far For example, the inductor 206 can be tuned (e.g., via respective programmable interfaces 220b, 220c) to provide an L near The tunable inductance range of inductor 206 is said to be 10 fF if it is tunable to provide an inductance between 2 fF and 12 fF. These figures exclude any parasitic / fundamental inductances that are not tunable. For example, continuing with the previous example, if inductor 206 also provides a parasitic inductance of 2 fF and therefore provides an inductance between 2 fF and 12 fF depending on its tuning, then the tunable inductance range of inductor 206 is still said to be 10 fF. Inductors 206, 208 may have the same or different tunable inductance ranges.

[0067] The near inductor 206 and the far inductor 208 are distinguished by their positions relative to one or more Josephson junctions 204 of the qubit 201. Since the near inductor 206 is positioned closer along the qubit loop 202 to one or more Josephson junctions 204, the near inductor 206 will tend to reduce the capacitance more significantly (for a given increase in L near ). The far inductor 208 is positioned further along the qubit loop 202 from one or more Josephson junctions 204, so the far inductor 208 will tend to increase the capacitance more significantly (for a given increase in L far ). An inductor closer to one or more Josephson junctions than the critical distance 212 will generally act as the near inductor 206 (i.e., reducing the capacitance), and an inductor further from one or more Josephson junctions than the critical distance 212 will generally act as the far inductor 208.

[0068] Thus, there may be an estimated critical point 210 along the qubit loop 202 located at the critical distance 212 from one or more Josephson junctions 204. The critical point 210 separates a near-inductor regime and a far-inductor regime such that an inductor between one or more Josephson junctions 204 and the critical point acts as a near inductor and an inductor along a portion of the qubit loop 202 that does not include (e.g., is opposite to) one or more Josephson junctions 204 acts as a far inductor. An inductor closer to the critical point will tend to have a less significant effect on the qubit capacitance (for a given change in inductance) than an inductor farther from the critical point. This scaling of the capacitance increase or capacitance decrease behavior is not necessarily symmetric between the near inductor and the far inductor (e.g., a near inductor may tend to reduce the qubit capacitance by a lesser amount than a far inductor even if both have the same inductance and distance from the critical point 210). In at least some implementations, it is not necessary to explicitly identify the location of the critical point 210, but in some implementations, the inductors 206, 208 (and / or other devices of the system 200) are positioned relative to the critical point 210 to determine their relationship between their inductance and their effect on the qubit capacitance.

[0069] The inductors 206, 208 can be tuned to compensate for the capacitance and / or inductance (so-called capacitive and / or inductive loading) contributed to the qubit 201 by various devices. For example, the coupler 222 can induce capacitive and inductive loading within the qubit 201, and the inductors 206, 208 can be tuned to compensate for one or both of such loading. In some implementations, the inductors 206, 208 are positioned and operable to provide a tunable inductance range such that the inductors 206, 208 can homogenize the qubit capacitance and / or inductance over multiple states of the qubit 201.

[0070] For example, analog computing system 200 may be operable to place qubit 201 in a state of maximum inductance by setting all couplers 222 to couple antiferromagnetically to qubit loop 202. For example, if all couplers 222 are programmable to provide a coupling strength in the range represented by [-1,1] (where negative values are ferromagnetic and positive values are antiferromagnetic), the maximum inductance state may include a state in which all couplers 222 are programmed to provide a coupling strength of -1. Continuing with the previous example, analog computing system 200 may be able to place qubit 201 in a state of minimum inductance by setting all couplers 222 to couple antiferromagnetically to qubit loop 202 (e.g., corresponding to a coupling strength of 1).

[0071] In some implementations, the difference between the qubit inductance in the maximum inductance state and the qubit inductance in the minimum inductance state is less than or equal to the sum of the tunable inductance ranges of inductors 206, 208. That is, tunable inductors 206, 208 are collectively tunable to provide a tunable inductance range sufficient to equalize the qubit inductances in the minimum and maximum inductance states. For example, consider the following states of an exemplary implementation of qubit 201:

[0072] [Table 1]

[0073] The difference in qubit inductance between the minimum inductance state and the maximum inductance state (referred to herein as the target inductance range) is 100 pH. In some implementations, inductors 206, 208 provide a collective tunable inductance range of at least 100 pH. For example, inductor 206 may provide a tunable inductance range of 40 pH, and inductor 208 may provide a tunable inductance range of 60 pH. In some implementations, inductors 206, 208 provide a collective tunable inductance range that is larger than the target inductance range (e.g., larger than 100 pH in the foregoing example) to tolerate variations in manufacturing, for example.

[0074] Inductors 206, 208 are also, or alternatively, tunable to homogenize the capacitance between the maximum capacitance state and the minimum capacitance state of qubit 201. For example, analog computing system 200 sets all couplers 222 within the critical distance 212 of one of the more Josephson junctions 204 to antiferromagnetically couple to qubit loop 202 (in this case, the couplers 222 within the critical distance 212 are in the inductor region near qubit loop 202, reducing inductance and increasing capacitance), and sets all couplers 222 farther than the critical distance 212 from one or more Josephson junctions 204 to antiferromagnetically couple to qubit loop 202 (in this case, the couplers 222 farther than the critical distance 212 are in the inductor region far from qubit loop 202, increasing both inductance and capacitance), and may be operable to place qubit 201 in the maximum capacitance state. For example, consider the following states of an exemplary implementation of qubit 201:

[0075]

Table 2

[0076] In some implementations, inductors 206, 208 are tunable to equalize the qubit capacitance for both the maximum and minimum capacitance states, for example, by increasing or decreasing the qubit capacitance to a target capacitance as needed for qubit capacitance. For example, inductors 206, 208 can be tunable to increase the qubit capacitance of qubit 201 from the qubit capacitance of the minimum capacitance state to within a threshold of the target capacitance, and to decrease the qubit capacitance from the qubit capacitance of the maximum capacitance state to within a threshold of the target capacitance (these two thresholds may be the same or different from each other).

[0077] For example, if the target capacitance of analog computing system 200 is 150 fF, a nearby inductor (e.g., inductor 206) may be tunable to reduce the capacitance by at least 50 fF (to handle the case of maximum capacitance), and a far inductor may be tunable to increase the capacitance by at least 50 fF (to handle the case of minimum capacitance).

[0078] The foregoing discussion has referred to states induced by the coupler, which is the primary source of varying inductive or capacitive load in many implementations, but the minimum and maximum inductance and capacitance states can be determined based on the programmable states of any device that contributes to the inductive and / or capacitive load on qubit 201. Such devices include, for example, quantum flux parametrons and mutual inductors coupled to qubit 201 (e.g., a flux bias device).

[0079] In some implementations, inductors 206, 208 are tunable to equalize both qubit inductance and qubit capacitance across each of four extreme states (minimum inductance, maximum inductance, minimum capacitance, and maximum capacitance). Since the relationship between inductance and capacitance is not always linear, it can be expected that meeting these constraints on both inductance and capacitance will substantially affect the parameters of inductors 206, 208 in most environments. However, since the four extreme states define the extrema within the state space of qubit 201, it is expected that in at least some implementations, inductors 206, 208 that are tunable to equalize all four extreme states across both inductance and capacitance (or more specifically, across any programmable state of the device that varies between the four extreme states) will be tunable to equalize all programmable states of system 200. For example, consider the following states of an exemplary implementation of qubit 201:

[0080]

Table 3

[0081] In such an implementation, the near inductor and the far inductor 206, 208 must be positioned and provided with a tunable inductance range that allows each of the four extreme states to have the same (approximately, within a threshold) inductance and capacitance when the inductor is suitably tuned.

[0082] For example, assume that an analog computing system has a target inductance of 220 pH and a target capacitance of 160 fF. Then, for an exemplary implementation of qubit 401 with a given positioning of inductors 206, 208, the inductance and capacitance may be equalized as follows across various program states (sometimes referred to herein as "scenarios") of analog system 200:

[0083]

Table 4

[0084] Here, the "qubit capacitance" column excludes the capacitance of one or more Josephson junctions 204, and L near is the tuned inductance of the near inductor 206, and L far is the tuned inductance of the far inductor 208. This exemplary scenario means that each of L near and L far requires 80 pH of the tunable inductance range.

[0085] In some implementations, the near inductor and the far inductors 206, 208 provide a total tunable inductance range (i.e., the sum of their tunable inductance ranges) that is approximately the same as the entire tunable inductance range of a single L tuner (e.g., as described in U.S. Patent No. 8,536,566). For example, if a 50 pH tunable inductance range is required for a single L tuner, the near inductor and the far inductors 206, 208 can collectively provide a 50 pH tunable inductance range. This tunable inductance range can be distributed between the inductors 206, 208 in any suitable manner (e.g., a 20 pH tunable inductance range for inductor 206 and a 30 pH tunable inductance range for inductor 208). Such a distribution of the tunable inductance range and the selection of the positions of the inductors 206, 208 are intertwined: for example, an inductor with a smaller tunable inductance range may need to be positioned further away from the critical point 210 in order to provide an appropriate capacitance reduction / increase.

[0086] Various arrangements of inductors 206, 208 can satisfy such conditions. Various arrangements can be compared (e.g., by simulation), and the selection of a particular arrangement can be influenced by factors such as the space available on the processor for the device arrangement, proximity to other devices, manufacturing tolerances, and / or other factors. The simulation can be assisted by adding the constraint that "for each scenario, there are several fixed total inductance values L such that L = L + L, where L can vary between scenarios". L can be determined based on a single L tuner implementation as described above; that is, the range of the simulation can be reduced to exploring the tunable inductance range distributions of various combinations between inductors 206, 208 and their arrangements. total =L near +L far for some fixed total inductance values L total where L total can vary between scenarios). total L can be determined based on a single L tuner implementation as described above; that is, the range of the simulation can be reduced to exploring the tunable inductance range distributions of various combinations between inductors 206, 208 and their arrangements.

[0087] In some implementations, system 200 includes two or more near inductors 206 and / or two or more far inductors 208 (e.g., by providing secondary near inductors and / or far inductors). Next, the collective near inductors 206 can collectively provide a tunable inductance L and a corresponding tunable inductance range; that is, the various arrangements of near inductors 206 determine the collective influence of near inductors 206 on qubit capacity. Similarly, the collective far inductors 208 can collectively provide a tunable inductance L and a corresponding tunable inductance range; that is, the various arrangements of far inductors 208 determine the collective influence of far inductors 208 on qubit capacity. near and a corresponding tunable inductance range; that is, the various arrangements of near inductors 206 determine the collective influence of near inductors 206 on qubit capacity. Similarly, the collective far inductors 208 can collectively provide a tunable inductance L far and a corresponding tunable inductance range; that is, the various arrangements of far inductors 208 determine the collective influence of far inductors 208 on qubit capacity.

[0088] Figure 2 is simplified for illustration purposes.

[0089] FIG. 3 shows a more complex exemplary analog computing system 300 that includes a qubit loop 302 and a qubit 301 having one or more Josephson junctions 304. In the depicted exemplary implementation, the one or more Josephson junctions 304 include a compound-compound Josephson junction (i.e., CCJJ) that includes two compound Josephson junctions. The near inductor 306 and the far inductor 308 each include two DC-SQUIDs connected in series, providing tunable inductances L near and L far respectively. In at least some implementations, the composite nature of the one or more Josephson junctions 304 and inductors 306, 308 may allow for more precise tuning within the programmable range for the simpler devices of FIG. 2.

[0090] System 300 also provides a plurality of couplers (including a far coupler 322 and a near coupler 324) that can be coupled to qubit 301. The far coupler 322 is located farther (i.e., on the far side of the critical point 310) than a critical distance from one or more Josephson junctions 304 along the qubit loop 302, and the near coupler 324 is located closer (i.e., on the near side of the critical point 310) than the critical distance from one or more Josephson junctions 304. Thus, couplers 322, 324 will tend to have different effects on the qubit capacitance as their inductive loads on qubit 301 change.

[0091] In some implementations where inductors 306, 308 are positioned and sized appropriately to compensate for such inductive and / or capacitive loads, the position and / or scale of one or both of inductors 306, 308 can be affected by the arrangement of couplers 322, 324. For example, in some implementations, inductors 306, 308 are positioned and / or scaled to compensate for capacitance in a maximum capacitance scenario where the nearby coupler 324 is antiferromagnetically coupled to qubit 301 and the far coupler 322 is antiferromagnetically coupled to qubit 301 (e.g., as described above), and similarly for the minimum capacitance scenario.

[0092] One or more Josephson junctions 304, inductors 306, 308, couplers 322, 324 are each programmable via programmable interfaces 320a, 320b, 320c, 320d, 320e. System 300 further provides exemplary other devices such as a quantum flux parametron 330 that interrupts qubit loop 302 and a programmable magnetic flux bias 332 that can be coupled to qubit 301. Such other devices can be used to interact with qubit 301 (e.g., to read out its state and / or to program it according to relevant parameters of the Hamiltonian problem) and can contribute to the inductive and / or capacitive load of qubit 301. In some implementations, inductors 306, 308 are positioned and / or scaled to compensate for inductive and / or capacitive loads contributed by such other devices (e.g., by operating such other devices to increase or decrease inductive or capacitive load as needed in various scenarios described elsewhere herein to compensate for the load contributed).

[0093] The systems disclosed herein are not limited to single qubit loop implementations. FIG. 4A shows an exemplary analog computing system 400 that includes a qubit 401 having a plurality of qubit loops 402a, 402b interrupted by one or more Josephson junctions 404 shared between qubit loops 402a, 402b (qubit loops 402a, 402b may partially overlap along a shared portion 440 as shown, for example, in FIG. 4A). In at least the depicted exemplary implementation, each qubit loop 402a, 402b is coupleable to and / or includes devices that are substantially similar to those of systems 200, 300.

[0094] For example, in the depicted embodiment, qubit loop 402a is interrupted by a near inductor 406a and a far inductor 408a (disposed on either side of a critical point 410a) and is communicatively coupleable to a plurality of couplers 422a, 424a, 426a. Qubit loop 402a may further be coupleable to and / or include other devices such as a quantum flux parametron 430a and / or a flux bias 432a. Qubit loop 402b may be coupleable to and / or include similar or different devices: that is, in the depicted exemplary implementation, qubit loop 402b is substantially similar to qubit loop 402a and is interrupted by a near inductor 406b and a far inductor 408b (disposed on either side of a critical point 410b) and is coupleable to a plurality of couplers 422b, 424b, 426b. Qubit loop 402b may further be coupleable to and / or include other devices such as a quantum flux parametron 430b and / or a flux bias 432b.

[0095] In some implementations, the qubit loops 402a, 402b have critical points 410a, 410b that are disposed at different critical distances from one or more Josephson junctions 404: for example, if the qubit loops 402a, 402b are not identical (e.g., are made of different materials, have an asymmetric layout, and / or are asymmetrically couplable to other devices of the system 400a). Thus, it may be said that the critical point 410b is disposed by a second critical distance (which may be the same as or different from the critical distance of the critical point 410a) from one or more Josephson junctions along the qubit loop 402b.

[0096] In some implementations, each qubit loop 402a, 402b includes at least one near inductor 406a and at least one far inductor 408a, thereby enabling the inductive and / or capacitive loading on each loop to be independently compensated. In some implementations, the qubit loops 402a, 402b share at least one near inductor 406a and / or far inductor 408a. For example, as depicted in the exemplary system 400b of FIG. 4B, the shared near inductor 406 can be positioned along the shared portion 440. In some implementations, the shared near inductor 406 provides a larger tunable inductance range than either of the near inductors 406a, 406b of a system 400 that would otherwise be similar, in order to compensate for the inductance across both qubit loops 402a, 402b. A potential advantage of such an arrangement is space savings; that is, in addition to reducing the minimum number of inductors required (from one per wing side to one per qubit), the shared inductor 406 itself can be physically smaller (e.g., by providing a smaller Josephson junction, which generally provides a larger inductance than a larger Josephson junction). This difference in size is not depicted in order to maintain the readability of FIG. 4B.

[0097] In some implementations, the collective tuning range of the near and far inductors 406a, 406b, 408a, 408b of qubit 401 having multiple loops 402a, 402b is greater by a tolerance amount (e.g., 20 pH) than the amount indicated by the difference in inductance between the maximum inductance state and the minimum inductance state. This tolerance amount may be large enough to allow the near and far inductors 406a, 406b, 408a, 408b to be tuned to compensate for variations between the wings resulting from manufacturing defects, design variations, and / or other asymmetries. This tolerance value may be further increased to account for variations between qubits (e.g., as described elsewhere in this specification).

[0098] Tuning of the Split L Tuner FIG. 5 is a flowchart of a method 500 for tuning the effective capacitance of qubits (such as qubit 201, 301, or 401 of system 200, 300, or 400) within an analog computing system, respectively. The method is performed by one or more processors (e.g., classical processors) in communication with the analog computing system.

[0099] At 502, one or more processors determine a predicted capacitance (C predicted represented) of the qubit based on the problem to be executed by the analog computing system. For example, if a given problem is transformed into a Hamiltonian for encoding onto the analog computing system (this process is sometimes referred to as "embedding"), one or more processors apply a portion of the Hamiltonian relevant to the qubit (e.g., a parameter corresponding to the coupling strength of a coupler that can couple to the qubit) to a physical model of the qubit to determine the C predictedcan be determined. For example, one or more processors can determine the associated inductive load of a qubit for each coupler based on the respective coupling strength of each coupler, and further based on the respective inductive load of each coupler and the respective distance of each coupler from one or more Josephson junctions of the qubits along the qubit loop (e.g., based on the model of C eff above), the associated capacitive load of the qubit can be determined. One or more processors can combine these capacitive loads (e.g., by adding up the capacitive loads and / or by weighting or non-linearly combining them), and based on the combined capacitive load and any other suitable factors (such as the capacitive loads of other devices, the reference capacitance of the qubit, and the program state of one or more Josephson junctions), the predicted capacitance C predicted of the qubit can be determined.

[0100] In 504, one or more processors determine the target capacitance of the qubit represented by C target . The method 500 aims to tune the effective capacitance of the qubit to be within the threshold of the target capacitance C target . The target capacitance C target can be determined in advance (e.g., the target capacitance C target can be a fixed value of the qubit determined at design time): in this case, the determination by the processor can include retrieving the value of the target capacitance C target from data storage. The predetermined target capacitance C target can be determined, for example, by experimental methods (such as using magnetic resonance tunneling, qubit spectroscopy, and / or other techniques for identifying qubit capacitance). For example, in a quantum annealing system, this can involve observing the behavior of qubits (and / or larger systems such as systems 200, 300, 400, etc.) at the quantum critical point (i.e., at the energy scale where the Hamiltonian disordering and the Hamiltonian problem have equal energy) in order to ensure that for a given capacitance, it exceeds a certain reference noise threshold.

[0101] In some implementations, the target capacitance Ctarget is dynamically determined by a processor (e.g., after receiving a given problem for execution by a quantum processor). For example, the target capacity is the predicted capacity C of each qubit of a plurality of qubits of an analog computing system for a given problem predicted by determining, and based on these predicted capacities C predicted determining the target capacity C target thereby (such as by taking the average of the target capacities), and / or minimizing an objective function for the value of C target (e.g., the sum of the L1 or L2 norms between each qubit's C predicted and C target ). Such determination may follow one or more constraints; for example, the selection of C target is constrained such that the analog computing system is operable to increase or decrease (as necessary) the effective capacity C of each qubit of the plurality of qubits such that the predicted capacity C of each qubit is within a threshold of the target capacity C predicted target eff

[0102] 506, one or more processors determine the total capacity change of the qubit, represented by ΔC, based on the predicted capacity C predicted and the target capacity C target . In at least some implementations, the total capacity change ΔC is the difference between C target and C predicted .

[0103] 510, one or more processors tune a plurality of inductors of the analog computing system to change the effective capacity of the qubit based on the distance of each inductor from one or more Josephson junctions of the qubit along the qubit loop and based on the total capacity change ΔC. For example, one or more processors determine the effective capacity C of the qubit eff ​​Multiple inductors can be tuned by a certain amount within the threshold of ΔC to increase or decrease (if necessary). Such tuning includes, for example, sending (and thus causing the analog computing system to execute) a representation of the problem that includes parameters for programming the analog computing system with multiple inductors to provide a tunable inductance as determined in the process of performing method 500 to the analog computing system for execution. In some implementations, one or more processors tune the inductor to compensate for the coupler-induced capacitive load (e.g., as predicted as described above with reference to act 502).

[0104] In at least some implementations, tuning in act 510 includes tuning an inductor closer than one or more Josephson junctions to a critical distance along the qubit loop (in act 512) to reduce qubit capacitance, and tuning an inductor farther from one or more Josephson junctions than a critical distance along the qubit loop (in act 514) to increase qubit capacitance.

[0105] The close inductor and the far inductor can be tuned based on their respective distances from one or more Josephson junctions: for example, by tuning the close inductor and the far inductor based on their distances from a critical point (such as the nearest critical point). As pointed out elsewhere in this specification, the capacitive load of an inductor per unit inductance generally varies with the position of the inductor along the qubit loop. Thus, C effTo determine the inductance required to achieve a specific change in the effective qubit capacitance that it may include, for example, examining a value from a data storage (such as a lookup table) that stores the capacitive change value of the corresponding change in the inductance of an inductor at a certain distance from one or more Josephson junctions (such values can be predefined, for example, experimentally), and based on the distance of the inductor from one or more Josephson junctions (for example, by using a model that explicitly includes such a distance as a parameter, and / or by selecting a model (such as one of the models of C eff among the models) based on such a distance), and / or may include applying a qubit capacitance model to the inductor based on other techniques.

[0106] Tuning the act 510 can be just as simple as, for example, increasing the inductance of a distant inductor to increase the capacitance by ΔC (or at least within the threshold of ΔC), or increasing the inductance of a nearby inductor to reduce the capacitance by ΔC to achieve (or at least approximate) the desired total capacitance change ΔC by tuning one of the nearby or distant inductors. However, in at least some environments, such tuning can make the effective inductance of the qubit less uniform across the various program states of the qubit.

[0107] Such non-uniformity may be undesirable in at least some applications. In at least some implementations, method 500 further includes determining the predicted and target inductance of the qubit, determining the total inductance change ΔL based on the predicted and target inductance, and tuning a plurality of inductors to increase the collective inductance of the inductors (i.e., the sum of their inductances) by an amount within the threshold of ΔL.

[0108] Note that "the change in qubit inductance may not necessarily be the same as the value of ΔL because the inductance contributed by the inductor to the effective qubit capacitance can be less than the inductance locally contributed by the inductor." For example, in the case of qubit 401 of FIG. 4A, the effective qubit inductance can increase by approximately 1 / 4 unit per unit of tunable inductance contributed by inductors 406a, 406b, 408a, 408b due to the parallel arrangement of qubit loops 402a, 402b in some situations (e.g., when the inductances of qubit loops 402a, 402b are approximately equal). Thus, in some embodiments, determining the total inductance change ΔL includes determining the total inductance change for the inductor to achieve (or at least approximate) the total inductance change of the qubit, and the total inductance change is determinable (e.g., based on the difference between the target inductance and the predicted inductance).

[0109] In at least some implementations, the total inductance change is distributed among the inductors based not only on ΔL but also on ΔC. For example, method 500 can homogenize both ΔL and ΔC (within a threshold) across various program states of an analog computing system (such as the states described elsewhere in this specification). A given total inductance change ΔL can be distributed among the inductors in various ways, but in most situations, most such distributions will not result in achieving (or at least approximating) a particular desired change in qubit capacitance.

[0110] FIG. 6 is a flowchart of a method 600 for distributing inductance between a near inductor and a far inductor. This method is performed by one or more processors (e.g., classical processors) in communication with an analog computing system and can be performed as part of method 500. At 602, the one or more processors determine a total inductance change ΔL (e.g., based on the target and predicted inductances as described above), and at 604, the one or more processors determine a total capacitance change ΔC (e.g., based on the target capacitance and predicted capacitance as described above with reference to act 506 of method 500).

[0111] At 606, the one or more processors determine the distribution of the total inductance change ΔL among the inductors of the analog computing system such that the corresponding tunable inductances of the inductors collectively are within a threshold of the total inductance change ΔL based on the total capacitance change ΔC (e.g., such that the sum of these tunable inductances is within the threshold of the total inductance change ΔL). In some implementations, act 606 includes identifying a plurality of candidate distributions of inductor tuning values. Each candidate distribution includes the values of the tunable inductances of each of the inductors and thus corresponds to the capacitance change that results from (and / or is predicted to result from) tuning the inductors to provide these values of the tunable inductances. Next, the distribution can be selected from the plurality of candidates, for example, by selecting the candidate having the (predicted) capacitance change closest to the total capacitance change ΔC.

[0112] Multiple candidate distributions can be determined by, for example, examining the values in a lookup table that associates values of ΔL with values of ΔC. In some implementations, the lookup table has ΔL and ΔC values as axes, and each (ΔL, ΔC) coordinate in the lookup table maps to a candidate distribution that provides (or is predicted to provide) the corresponding ΔL and ΔC values being examined (at least within a threshold). For example, in an exemplary two-inductor system 200 such as that shown in FIG. 2, if a total inductance change ΔL = 100.1 pH is determined in act 602 and a total capacitance change ΔC = 59.9 fF is determined in act 604, act 606 involves examining the coordinate (100 pH, 60 fF) in the lookup table and identifying candidate distributions L near = 80 pH, L far = 20 pH (assuming that the lookup table does not represent coordinates that more precisely approximate the search values in the foregoing example).

[0113] In some implementations, the lookup table has values of tunable inductance (e.g., L near and L far ) as axes, and each coordinate (e.g., (L near , L far ) coordinates) maps to a candidate ΔC value. (In some implementations, ΔL is also mapped by the table; in other implementations, ΔL is omitted by the lookup table, in which case ΔL can be estimated by combining coordinate values (e.g., by calculating ΔL = L near + L far ). Multiple candidate distributions can be identified in the table by, for example, identifying all coordinates (at least within a threshold) corresponding to a total inductance change ΔL. For example, in an exemplary two-axis table having L near and L far as axes, a diagonal can be identified (e.g., for each value of L near , if such a value exists, at least approximately L near = ΔL - L far (L near , L far) can be defined by coordinates, and a value along a diagonal having the corresponding candidate ΔC value closest to the total conductance change ΔC can be selected. Such a look-up table can include more than three dimensions (e.g., to explicitly represent three or more inductors along its axes). However, even when three or more tunable inductors are provided, the look-up table can provide fewer axes; that is, for example, the look-up table can provide L near and L far and enable one or more processors to distribute inductance between nearby and distant inductors. The sub-distribution between nearby inductors (based on L near ) and distant inductors (based on L far ) can then be determined by referring to other look-up tables, applying models, or via other suitable techniques.

[0114] In some implementations, act 606 includes interpolating inductor tuning values of inductors of an analog computing system. For example, coordinates (e.g., (ΔL,ΔC), (L near ,L far) and / or other coordinates) may be interpolated based on the selected distribution and based on additional candidate distributions (such as candidate distributions that are close (e.g., adjacent) to the selected distribution in the lookup table). As used herein, "close" refers to a distribution that is within a small threshold of variation (e.g., one integer value (±1%) of each coordinate value) around the selected distribution. This threshold would define an area around the coordinates of the selected distribution that is considered "close." For example, returning to the previous example where a total inductance change ΔL=100.1 pH was determined in act 602 and a total capacitance change ΔC=59.9 fF was determined in act 604, act 606 may include selecting a candidate distribution in distribution (100 pH, 60 fF), for example, as described above, and interpolating a value for coordinate (100.1 pH, 59.9 fF) by interpolating the inductor tuning value of (100 pH, 60 fF) with the inductor tuning value of the additional candidate distribution having coordinate (101 pH, 59 fF). Interpolation involves taking a weighted average of the selected distribution and other candidate distributions, weighted, for example, based on the distance (e.g., Cartesian distance) from each distribution's coordinate (100.1pH, 59.9fF), with closer distributions receiving greater weighting. In this example, the "closer" distributions are one integer value greater at each coordinate than the selected distribution.

[0115] At 606, the one or more processors tune the inductors based on the selected distribution: for example, by programming each inductor to provide (or at least approximate) the tunable inductance provided therefor in the selected distribution. Act 606 may be performed as part of act 510 of method 500.

[0116] Computing Systems The foregoing method can be performed by a hybrid computing system (e.g., a hybrid computing system including the foregoing analog computing system). FIG. 7 shows an exemplary hybrid computing system 700 including a digital computer 702 coupled to an analog computer 704. In some implementations, the analog computer 704 is a quantum computer and the digital computer 702 is a classical computer.

[0117] The exemplary digital computer 702 includes a digital processor (such as one or more central processing unit units 706) that can be used to perform the classical digital processing tasks described in the present system and method. Those skilled in the art will understand that the present system and method can be implemented by other digital computer configurations including portable devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, personal computers (PCs), network PCs, minicomputers, mainframe computers, etc., when the system and method are properly configured or programmed to form a dedicated machine and / or communicatively coupled to control an analog computer (e.g., a quantum computer).

[0118] The digital computer 702 will be referred to herein in the singular, but this is not intended to limit the application to a single digital computer. The present system and method can also be implemented in a distributed computing environment where tasks or a set of processor-readable instructions are performed or executed by a remote processing device linked via a communication network. In a distributed computing environment, computer-readable and / or processor-readable instructions (sometimes known as program modules), application programs, and / or data can be stored in local and / or remote memory storage devices (e.g., non-transitory computer-readable or processor-readable media).

[0119] The digital computer 702 may include at least one or a plurality of digital processors (e.g., one or a plurality of central processing unit units 706), one or a plurality of system memories 708, and one or a plurality of system buses 710 that couple various system components including the system memory 708 to the central processing unit unit 706.

[0120] The digital processor may be any logical processing unit such as one or a plurality of central processing units ("CPUs") having one or a plurality of cores, a graphics processing unit ("GPU"), a digital signal processor ("DSP"), an application specific integrated circuit ("ASIC"), a field programmable gate array ("FPGA"), a programmable logic controller (PLC), etc.

[0121] The digital computer 702 may include a user input / output subsystem 712. In some implementations, the user input / output subsystem includes one or a plurality of user input / output components such as a display 714, a mouse 716, and / or a keyboard 718. The system bus 710 may employ any known bus structure or architecture including a memory bus to a memory controller, a peripheral bus, and a local bus. The system memory 708 may include non-volatile memory (e.g., one or a plurality of read-only memories ("ROM"), static random access memories ("SRAM"), flash NAND) and volatile memory (e.g., random access memory) ("RAM") (not shown), all of which are examples of non-transitory computer-readable and / or processor-readable media.

[0122] The basic input / output system (BIOS) 720, which may form part of the ROM, includes basic routines that assist in transferring information between elements within the digital computer 702 during startup periods and the like.

[0123] Digital computer 702 may also include other non-volatile memories 722. The non-volatile memories 722 may adopt various forms including a hard disk drive for reading from and writing to a hard disk, an optical disk drive for reading from and writing to a removable optical disk, and / or a magnetic disk drive for reading from and writing to a magnetic disk, all of which are examples of non-transitory computer-readable and / or processor-readable media. The optical disk may be a CD-ROM or a DVD, while the magnetic disk may be a magnetic floppy disk or a diskette. The non-volatile memories 722 may communicate with the digital processor via the system bus 710. The non-volatile memories 722 may include an appropriate interface or controller 724 coupled to the system bus 710. The non-volatile memories 722 may serve as non-transitory long-term storage for computer-readable and / or processor-readable instructions, data structures, or other data (also referred to as program modules) of the digital computer 702.

[0124] Although digital computer 702 has been described as employing a hard disk, an optical disk, and / or a magnetic disk, those skilled in the art will understand that other types of non-volatile computer-readable media such as magnetic cassettes, flash memory cards, flash, ROM, smart cards, etc., all of which are another example of non-transitory computer-readable and / or processor-readable media, may be employed. Those skilled in the art will understand that some computer architectures combine volatile memory and non-volatile memory. For example, data in volatile memory may be cached to non-volatile memory or a solid-state disk that employs an integrated circuit to provide non-volatile memory. Some computers place data that is traditionally stored on a disk into memory. Similarly, some media that are traditionally considered volatile may have a non-volatile form (e.g., a non-volatile dual in-line memory module, which is a variant of a dual in-line memory module).

[0125] Various sets of computer-readable and / or processor-readable instructions (also referred to as program modules), application programs, and / or data may be stored in system memory 708. For example, system memory 708 may store an operating system 726, server instructions 728, compute instructions 730, and / or runtime instructions 732.

[0126] Although shown as being stored in system memory 708 in FIG. 7, program modules and other data may be stored elsewhere, including within non-volatile memory 722 or one or more other non-transitory computer-readable and / or processor-readable media.

[0127] Analog computer 704 may be provided within an isolated environment (not shown). For example, if analog computer 704 is a quantum computer, the environment shields the internal components of the quantum computer from heat, magnetic fields, etc. Analog computer 704 includes one or more analog processors, such as quantum processor 734.

[0128] The quantum processor includes programmable elements such as qubits, couplers, and other devices. In one implementation, the qubits are superconducting flux qubits. The qubits are read out via readout system 736. These results may be sent to various sets of computer-readable and / or processor-readable instructions of digital computer 702. Analog computer 704 may include qubit control system 738 and coupler control system 740. Coupler control system 740 may provide control of communicable couplings between qubits, such as inductive and capacitive communicable couplings described in this application.

[0129] In some embodiments, hybrid computer 700 is used to perform quantum annealing on quantum processor 734.

[0130] In some implementations, digital computer 702 may operate in a network environment by using logical connections to at least one client computer system. In some implementations, digital computer 702 is coupled via a logical connection to at least one database system. These logical connections may be formed by using any means of digital communication (e.g., via a network such as a local area network ("LAN") or a wide area network ("WAN") including, for example, the Internet). The network environment may include a wired or wireless enterprise-scale computer network, an intranet, an extranet, and / or the Internet. Other embodiments may include other types of communication networks such as communication networks, cellular networks, paging networks, and other mobile networks. The information transmitted or received via the logical connection may or may not be encrypted. When used within a LAN network environment, digital computer 702 may be connected to the LAN via an adapter or network interface card (NIC) communicatively coupled to system bus 710. When used within a WAN network environment, digital computer 702 may include an interface and a modem (not shown) for establishing communication on the WAN, or a device such as a NIC. Non-network communication may be employed in addition to or alternatively.

[0131] According to some embodiments of the present system and device, a quantum processor (such as quantum processor 734 of FIG. 7) may be designed to perform quantum annealing and / or adiabatic quantum computing. The Hamiltonian evolution proportional to the sum of a first term proportional to the Hamiltonian problem and a second term proportional to the Hamiltonian delocalization may be constructed as follows: H E ∝A(t)H P +B(t)H D where H E is the Hamiltonian evolution, H P is the Hamiltonian problem, H Dis Hamiltonian delocalization, and A(t) and B(t) are coefficients that control the rate of evolution and can typically be within the range [0,1].

[0132] In some implementations, a time-varying envelope function is placed on the Hamiltonian problem. A suitable Hamiltonian delocalization is given by:

Number

Number

Number

[0133] A general Hamiltonian problem includes a first component proportional to the diagonal single-qubit terms and a second component proportional to the diagonal multi-qubit terms, and can be in the following form:

Number

Number

Number

Number

[0134] Homogenized inductance and / or capacitance across the programmable states of individual qubits and / or across all qubits across the quantum processor can help to homogenize their physical behavior. Such homogenization of fundamental physics, in suitable circumstances, enables the quantum processor to more precisely instantiate the aforementioned computational model, thereby more broadly improving the performance of the quantum processor and consequently the performance of the hybrid computing system 700.

[0135] Butterfly qubit As discussed above, a superconducting flux qubit (e.g., superconducting flux qubit 100a) can include a loop of superconducting material (e.g., qubit loop 102) interrupted by a Josephson junction (e.g., CJJ104). Qubits are connected to each other by couplers (e.g., coupler 222) within the quantum processor, and the type and complexity of problems that can be solved by the processor can be affected by the connectivity between the qubits. In some implementations, increasing the connectivity between single-loop flux qubits (e.g., flux qubits 100a, 201) is at least partially achieved by increasing the length of the qubits to accommodate additional couplers. The increased qubit length can result in increased inductance and capacitance and a corresponding decrease in the energy scale. In some implementations, it may be beneficial to provide multi-loop flux qubits (e.g., qubit 401) as discussed above with respect to FIGS. 4A, 4B and discussed in further detail below. Multi-loop flux qubits can enable increased connectivity without a corresponding decrease in the energy scale.

[0136] In the exemplary implementation of FIG. 8, the analog computing system 800 includes a qubit 802 having a Josephson junction 804, a first qubit loop 806 formed by a first superconducting current path, and a second qubit loop 808 formed by a second superconducting current path. The first qubit loop 806 and the second qubit loop 808 are electrically connected in parallel to both ends of the Josephson junction 804. A qubit having two loops each forming one of the wings may also be referred to as a two-wing qubit or a butterfly qubit. In the exemplary implementation of FIG. 8, the first qubit loop 806 and the second qubit loop 808 are symmetric about the axis 816 of the Josephson junction 804, and the axis 816 intersects the first connection 818 between the first and second qubit loops 806, 808 and the Josephson junction 804 and the second connection 820 between the first and second qubit loops 806, 808 and the Josephson junction 804. From the perspective of the Josephson junction, the two-wing qubit will behave in the same way as an RF SQUID flux qubit such as those in FIGS. 1A and 1B. At zero applied magnetic flux, the magnitude of the current flowing in each wing is half of that flowing through the Josephson junction. The persistent current flowing through the Josephson junction is divided when flowing into the parallel wings such that the total persistent current flowing through the Josephson junction is the sum of the persistent currents flowing in each wing. The total effective body inductance is equal to the parallel combination of the inductances of the two wings. In the implementation of FIG. 8, the direction of rotation of the current flow is reversed between the two wings. In the exemplary implementation of FIG. 8, the Josephson junction is a composite Josephson junction. In other implementations, the Josephson junction is a compound composite Josephson junction, which refers to a composite Josephson junction in which at least one junction is also a composite Josephson junction.

[0137] Independent control of each wing of the qubit 802 can be provided by a flux bias source (such as a flux bias line that externally applies a bias current to the qubit loop). The first qubit loop 806 can be in communication with the first flux bias line 810, and the second qubit loop 808 can be in communication with the second flux bias line 812. The first flux bias line 810 can receive signals independently from the second flux bias line 812, enabling independent control of each qubit loop. As discussed above, the first qubit loop 806 and the second qubit loop 808 can partially overlap along the shared portion 814. The two wings 806, 808 of the qubit 802 enable the following two different current paths: one is a current path having a current flowing through the Josephson junction and into the wing (corresponding to the difference in flux bias between the wings), and the second is a current path having a current flowing only around the outer loop formed by the two wings (corresponding to the total flux within the wings).

[0138] In the exemplary implementation of FIG. 9A, the analog computing system 900a has a qubit 902 having a Josephson junction 904. In contrast to FIG. 8 where the first qubit loop 806 and the second qubit loop 808 are symmetric, in FIG. 9A, the first qubit loop 906 and the second qubit loop 908 are asymmetric. The first and second flux bias lines 910, 912 are in communication with the first and second qubit loops 906, 908. In the exemplary implementation of FIG. 9B, the analog computing system 900b has a qubit 902 having a Josephson junction 904, first and second qubit loops 906, 908, and first and second flux bias lines 910, 912. In FIG. 9B, an additional qubit loop 916 is electrically connected in parallel across the two ends of the Josephson junction 904 and has an independent flux bias line 918. In other implementations, the qubit can be designed with one or more additional qubit loops, and additional wings can be added in parallel. Increasing the number of wings can result in a scaling of the positional energy of all qubits by a factor proportional to the number of wings.

[0139] In the exemplary implementation of FIG. 10, the analog computing system 1000 includes a qubit 1002 having a compound composite Josephson junction (CCJJ) 1004, a first qubit loop 1006 formed by a first superconducting current path, and a second qubit loop 1008 formed by a second superconducting current path. The first qubit loop 1006 and the second qubit loop 1008 are electrically connected in parallel to both ends of the Josephson junction 1004. The second qubit loop 1002 has a first portion 1010 in communication with the Josephson junction 1004, a second portion 1012 spaced apart from the Josephson junction 1004, and an intersection 1014 separating the first portion 1010 and the second portion 1012. The current in the first portion 1010 propagates in a first rotation direction (e.g., shown as clockwise), and the current in the second portion 1012 propagates in a second rotation direction opposite to the first rotation direction (e.g., shown as counterclockwise). It will be understood that the orientation shown in the exemplary implementation of FIG. 10 can be reversed such that the first rotation direction is counterclockwise and the second rotation direction is clockwise. The intersection acts as a "twist" within the second qubit loop and can be formed by superconducting materials that intersect within layers spaced orthogonally (e.g., vertically) in a multilayer circuit. By providing the twist within one wing of the qubit, it may be possible for the entire qubit to act like a single-loop qubit that is longer than one without the twist. The twist within one wing can homogenize the sensing of the persistent current within the circuit. As shown in FIG. 10, the current direction is reversed near the CCJJ, but the current propagating through the outer portion of the qubit is generally counterclockwise.

[0140] The analog computing system 1000 further includes not only a first magnetic flux bias line 1016 and a second magnetic flux bias line 1018, but also a first coupler 1020 and a second coupler 1022 that are tunably coupled to a first qubit loop 1006 and a second qubit loop 1008. In other implementations, the analog computing system may have one or more couplers that are tunably coupled to one of the first qubit loop and the second qubit loop. The first coupler 1020 and the second coupler 1022 may couple qubit 1002 to another qubit 1024, or to a plurality of other qubits or other devices. The coupling may be made to neighboring qubits along the length of the wing. By reducing the wing length when additional wings are added, the connectivity can be increased for the same energy scale. Conversely, for a fixed connectivity, the energy scale can be increased by reducing the wing length and increasing the number of wings.

[0141] In the exemplary implementation of FIG. 11, the analog computing system 1100 includes qubits 1102, CCJJs 1104, a first qubit loop 1106, and a second qubit loop 1108. The second qubit loop 1108 includes a first portion 1110, a second portion 1112, and an intersection 1114. The qubits 1102 are similar to the qubits 1002, but have additional devices in communication with the qubit loops 1106, 1108 beyond the flux bias lines 1116, 1118 and the couplers 1120, 1122. The qubits 1102 include a plurality of inductors 1126 disposed along each of the first qubit loop 1106 and the second qubit loop 1108, and each of the plurality of inductors 1126 is tunable to provide a corresponding tunable inductance as discussed in detail above. Also shown is a permanent current compensator (a compensator herein called a multiplier) 1128 coupled to a signal line and capable of providing various waveforms as discussed in U.S. Patent No. 9,015,215. The qubits described herein may include other devices such as programming devices, readout devices, and calibration devices, and may include other amounts of devices than the amounts of devices shown.

[0142] It will be understood that the structures shown in FIGS. 10 and 11 are exemplary implementations of a butterfly qubit. For example, Josephson junction 1004 is shown as a multiplexed compound Josephson junction, but may also be a compound Josephson junction having one junction on each side of the loop, or may have any other number of junctions. The biasing lines shown may provide independent biasing, or may be connected in series with and driven by a single source. The bias provided to either side of the loop may be the same, or different biases may be provided. Each of the biasing lines shown (including biases 1016, 1018), as well as the biasing lines connected to the Josephson junctions and couplers, may be provided by two or more biases. For example, in some implementations, each of the biasing lines shown may be provided by the following two independent lines: one driven by an external room temperature source and one driven by an on-chip digital-to-analog converter (DAC). As discussed above, these are exemplary implementations, and the circuit may not include all of the devices shown, may include other devices such as programming devices, readout devices, calibration devices, etc., or may include any other amount of devices than the amount of devices shown.

[0143] The methods (500, 600) described above may be used with the qubits (802, 902, 1002, 1102) described above.

[0144] Throughout this specification, the terms "Hamiltonian problem" and "final Hamiltonian" are used interchangeably unless the context otherwise indicates. Some states of a quantum processor are energetically preferred or simply preferred by a Hamiltonian problem. These include the ground state, but may include excited states.

[0145] The H in the above two equations D and H P such Hamiltonians can each be physically realized in a variety of ways. Specific examples are realized by implementations of superconducting qubits.

[0146] Examples of superconducting qubits include superconducting flux qubits, superconducting charge qubits, etc. In superconducting flux qubits, the Josephson energy is greater than or equal to the charging energy. In charge qubits, this is the reverse. Examples of flux qubits that can be used include rfSQUIDs including a superconducting loop interrupted by one Josephson junction, persistent current qubits including a superconducting loop interrupted by three Josephson junctions, etc. See, for example, the examples of RF-SQUID qubits in Bocko, et al., 1997, IEEE Trans. on Appl. Supercond. 7, 3638; Friedman, et al., 2000, Nature 406, 43; and Harris, et al., 2010, Phys. Rev. B 81, 134510; or the examples of persistent current qubits in Mooij et al., 1999, Science 285, 1036; and Orlando et al., 1999, Phys. Rev. B 60, 15398. Additionally, hybrid charge-phase qubits with equal energy can also be used. Further details of superconducting qubits can be found in Makhlin, et al., 2001, Rev. Mod. Phys. 73, 357; Devoret et al., 2004, arXiv:cond-mat / 0411174; Zagoskin and Blais, 2007, Physics in Canada 63, 215; Clarke and Wilhelm, 2008, Nature 453, 1031; Martinis, 2009, Quantum Inf. Process. 8, 81; and Devoret and Schoelkopf, 2013, Science 339, 1169. In some embodiments, the qubits and couplers are controlled by an on-chip circuit configuration. Examples of on-chip control circuit configurations can be found in U.S. Patent No. 7,876,248; U.S. Patent No. 7,843,209; U.S. Patent No. 8,018,244; U.S. Patent No. 8,098,179; U.S. Patent No. 8,169,231; and U.S. Patent No. 8,786,476.Further details and implementations of an exemplary quantum processor that can be used in conjunction with the present system and apparatus are described, for example, in U.S. Patent No. 7,533,068, U.S. Patent No. 8,008,942, U.S. Patent No. 8,195,596, U.S. Patent No. 8,190,548, and U.S. Patent No. 8,421,053.

[0147] The methods, processes, or techniques described above may be implemented by a series of processor-readable instructions stored on one or more non-transitory processor-readable media. Some examples of the methods, processes, or techniques described above are performed in part by special devices or systems, such as adiabatic quantum computers or quantum annealers (e.g., a computer including at least one digital processor), that program or otherwise control their operation. The methods, processes, or techniques described above may include various acts, but one of ordinary skill in the art will recognize that in alternative examples some acts may be omitted and / or additional acts may be added. One of ordinary skill in the art will recognize that the order of the acts shown is provided for illustrative purposes only and may vary in alternative examples. Some of the illustrative acts or operations of the methods, processes, or techniques described above are performed repeatedly. Some of the methods, processes, or techniques described above may be performed during each iteration, after a plurality of iterations, or at the end of all iterations.

[0148] The above description of the illustrated implementations, including what is set forth in the abstract, is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Specific implementations and examples are described herein for illustrative purposes, but various equivalent modifications can be made without departing from the spirit and scope of the disclosure as recognized by one of ordinary skill in the art. The teachings provided herein for the various implementations may not necessarily apply to the exemplary methods of quantum computing generally described above, but may apply to other methods of quantum computing.

[0149] The various implementations described above can be combined to provide another implementation. All of the U.S. Patent Application Publications, U.S. Patent Applications, foreign patents, and foreign patent applications, including but not limited to the following patents, which are referenced herein and / or listed in the Application Data Sheet, are hereby incorporated by reference in their entirety: U.S. Patent No. 7,135,701; U.S. Patent No. 7,418,283; U.S. Patent No. 8,536,566; U.S. Patent No. 9,015,215; U.S. Patent No. 9,152,923; PCT Application No. US2018 / 066613; and U.S. Patent Application No. 62 / 951,738.

[0150] These and other modifications may be made to the above implementations in light of the above detailed description. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific implementations disclosed herein and the claims should be construed to include all possible implementations along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims of this patent are not limited by the disclosure.

Claims

1. 1. An analog computing system including a qubit, the qubit comprising: a qubit loop formed by a first superconducting current path; at least one Josephson junction interposed in the qubit loop, the at least one Josephson junction having a critical distance such that adding a lumped inductance closer than the critical distance to the at least one Josephson junction along the qubit loop reduces a qubit capacity at the at least one Josephson junction, and adding the lumped inductance further than the critical distance from the at least one Josephson junction along the qubit loop increases the qubit capacity; 1. An analog computing system comprising: a plurality of inductors disposed along the qubit loop, each of the plurality of inductors being tunable to provide a tunable inductance, the plurality of inductors including: one or more near inductors each disposed along the qubit loop closer than the critical distance from the at least one Josephson junction; and one or more far inductors each disposed along the qubit loop farther than the critical distance from the at least one Josephson junction.

2. 10. The analog computing system of claim 1, further comprising: one or more couplers tunably coupleable to the quantum bit loop, each tunable to provide a respective coupling strength to the quantum bit.

3. the tunable inductance of each inductor of the plurality of inductors is tunable within a corresponding inductance range; each of the one or more couplers having a corresponding coupler induced inductance range; each coupler induced inductance range includes a difference in qubit inductance at the at least one Josephson junction between states of the corresponding one of the one or more couplers; The analog computing system of claim 2 , wherein a sum of the tunable inductance ranges of the plurality of inductors is greater than each of the corresponding coupler induced inductance ranges.

4. 3. The analog computing system of claim 2, wherein an inductor of the plurality of inductors comprises one or more inductor Josephson junctions interrupting the qubit loop and tunable to provide a respective tunable inductance range of the one of the plurality of inductors.

5. 5. The analog computing system of claim 4, wherein said one of said plurality of inductors comprises one or more DC-SQUIDs including said one or more inductor Josephson junctions.

6. 6. The analog computing system of claim 5, wherein said one of said plurality of inductors comprises a plurality of DC-SQUIDs connected in series along said qubit loop.

7. the sum of the tunable inductance ranges of the plurality of inductors is greater than a total coupler induced inductance range; the total coupler induced inductance range includes a difference between a first coupler induced inductance and a second coupler induced inductance; The first coupler induced inductance includes a qubit inductance in a first state in which each of the one or more couplers is ferromagnetically coupled to the qubit.

4. The analog computing system of claim 3, wherein the second coupler induced inductance comprises a qubit inductance in a second state in which each of the one or more couplers is antiferromagnetically coupled to the qubit.

8. the one or more nearby inductors are collectively tunable to reduce the qubit capacitance from a first coupler induced capacitance to within a first threshold of a target capacitance; the one or more distant inductors are collectively tunable to increase the qubit capacitance from a second coupler induced capacitance to within a second threshold of the target capacitance; the first coupler induced capacitance includes the qubit capacitance in a third state in which each of the one or more couplers (if present) that are closer to the at least one Josephson junction along the qubit loop than the critical distance are antiferromagnetically coupled to the qubit loop, and each of the one or more couplers (if present) that are farther from the at least one Josephson junction along the qubit loop than the critical distance are ferromagnetically coupled to the qubit loop; 8. The analog computing system of claim 7, wherein the second coupler induced capacitance comprises a qubit capacitance in a fourth state in which each of the one or more couplers (if present) that are closer to the at least one Josephson junction along the qubit loop than the critical distance is ferromagnetically coupled to the qubit loop, and each of the one or more couplers (if present) that are farther from the at least one Josephson junction along the qubit loop than the critical distance is antiferromagnetically coupled to the qubit loop.

9. 9. The analog computing system of claim 8, wherein for a given target qubit inductance and a given set of coupling strengths of the one or more couplers, the plurality of inductors are tunable to provide a total tunable inductance for each of the first, second, third, and fourth states that increases the qubit inductance to within a third threshold of the given target qubit inductance and at least one of increases and decreases the qubit capacitance to within a fourth threshold of the target capacitance.

10. 2. The analog computing system of claim 1 , wherein the qubit includes a second qubit loop, at least one Josephson junction interrupting the second qubit loop, and at least one secondary inductor disposed along the second qubit loop.

11. 11. The analog computing system of claim 10, wherein the qubit loop and the second qubit loop overlap along the shared portion, and a shared inductor of the plurality of inductors is disposed along the shared portion.

12. The analog computing system of claim 11 , wherein the shared inductor comprises one of the one or more nearby inductors.

13. the at least one secondary inductor comprising one or more secondary near inductors each disposed along the second qubit loop closer than a second critical distance from the at least one Josephson junction; and 11. The analog computing system of claim 10, further comprising: one or more secondary far inductors each disposed along the second qubit loop farther than the second critical distance from the at least one Josephson junction.

14. 14. The analog computing system of claim 13, wherein the plurality of inductors and the at least one secondary inductor collectively provide a collective tunable inductance range that is at least twice a total combiner induced inductance range.

15. 16. A method for tuning an effective capacity of a qubit in an analog computing system, the method being performed by a processor in communication with the analog computing system, the method comprising: determining an expected capacity of the qubit; determining a target capacity of the qubit; determining a total volume change, ΔC, based on the target volume and the predicted volume; and tuning a plurality of inductors to change the effective capacitance of the quantum bit based on the corresponding distances from the one or more Josephson junctions and the total capacitance change, each inductor being positioned at a corresponding distance from one or more Josephson junctions of the quantum bit along a quantum bit loop.

16. the one or more Josephson junctions have a critical distance such that adding a lumped inductance closer than the critical distance to the one or more Josephson junctions along the qubit loop reduces a qubit capacitance at the one or more Josephson junctions, and adding the lumped inductance further than the critical distance from the one or more Josephson junctions increases the qubit capacitance; Tuning multiple inductors: tuning a first inductor of the plurality of inductors closer to the one or more Josephson junctions than the critical distance along the qubit loop to reduce the qubit capacitance; and 16. The method of claim 15, comprising tuning a second inductor of the plurality of inductors farther from the one or more Josephson junctions along the qubit loop than the critical distance to increase the qubit capacity.

17. 17. The method of claim 16, wherein tuning the multiple inductors based on the corresponding distances from the one or more Josephson junctions comprises tuning the first and second inductors based on the respective distances of the first and second inductors from a point located at the critical distance along the qubit loop from the one or more Josephson junctions.

18. determining an expected inductance of the qubit; determining a target inductance of the qubit; and 16. The method of claim 15, comprising determining a total inductance change ΔL based on the target and the predicted inductance, Tuning the plurality of inductors to vary the effective capacitance of the qubit includes: tuning the plurality of inductors such that a sum of a plurality of corresponding tunable inductances of the plurality of inductors is within a threshold total inductance change ΔL; and tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC.

19. Tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC, tuning a tunable inductance of the first inductor of the plurality of inductors to reduce the effective qubit capacitance and increase the effective qubit inductance; and 20. The method of claim 18, comprising tuning the tunable inductance of the second inductor of the plurality of inductors to increase the effective qubit capacitance and increase the effective qubit inductance.

20. Tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC, selecting a selected distribution from a plurality of candidate distributions of inductor tuning values ​​based on the total capacitance change ΔC and the total inductance change ΔL; and The method of claim 18 , comprising tuning the plurality of tunable inductors based on the inductor tuning values ​​of the selected distribution.

21. 21. The method of claim 20, wherein each candidate distribution corresponds to a candidate capacitance change, and selecting the selected distribution comprises selecting the selected distribution based on a difference between the candidate capacitance change and the total capacitance change ΔC.

22. Tuning the plurality of tunable inductors based on the selection distribution includes: interpolating an interpolated inductor tuning value for each inductor of the plurality of inductors based on the inductor tuning value of the selected distribution and the inductor tuning value of an additional candidate distribution of the plurality of candidate distributions; and The method of claim 20 comprising tuning the plurality of tunable inductors based on the interpolated inductor tuning values.

23. 23. The method of claim 22, wherein identifying the plurality of candidate distributions comprises identifying the plurality of candidate distributions in a lookup table based on at least one of the total capacitance change ΔC and the total inductance change ΔL, wherein the additional candidate distributions among the plurality of candidate distributions are close to the selected distribution in the lookup table.

24. Identifying the plurality of candidate distributions of inductor tuning values ​​includes: looking up a first set of inductor tuning values ​​for one of the first inductor and the second inductor along a first axis of a lookup table; and 21. The method of claim 20, comprising: for each of the first set of inductor tuning values, identifying a corresponding inductor tuning value of an additional inductor of the first and second inductors along a second axis of the lookup table such that the sum of the first and second inductor tuning values ​​is within a threshold of the total inductance change ΔL, wherein each inductor tuning value from the first set is paired with the corresponding inductor tuning value of the additional inductor of the first and second inductors that includes a candidate distribution and corresponds to a predicted capacitance change.

25. 25. The method of claim 24, wherein selecting a selected distribution from the plurality of candidate distributions comprises selecting a candidate distribution among the plurality of candidate distributions having a corresponding predicted capacity change closest to the total capacity change ΔC.

26. Tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC, looking up said total capacitance change ΔC along a first axis in a lookup table; looking up the total inductance change ΔL along a second axis in the lookup table; identifying a candidate distribution of inductor tuning values ​​in the lookup table corresponding to the total capacitance change ΔC and the total inductance change ΔL; and The method of claim 18 , comprising tuning the plurality of inductors based on the candidate distribution.

27. 27. The method of claim 26, wherein examining at least one of the total capacitance change ΔC and the total inductance change ΔL comprises determining an entry along at least one of the first and second axes of the lookup table that approximates the at least one of the total capacitance change ΔC and the total inductance change ΔL.

28. Tuning multiple inductors is tuning a first inductor at a first distance from the one or more Josephson junctions along the qubit loop to reduce the effective qubit capacitance and increase the effective qubit inductance; and 16. The method of claim 15, comprising tuning a second inductor at a second distance from the one or more Josephson junctions along the qubit loop, the second distance being greater than the first distance, to increase the effective qubit capacitance and increase the effective qubit inductance.

29. 16. The method of claim 15, wherein determining the predicted capacity of the qubit comprises determining a coupler induced capacitive loading based on one or more coupling strengths of one or more couplers coupled to the qubit.

30. 30. The method of claim 29, wherein tuning the plurality of inductors to modify the effective capacitance of the qubit based on the total capacitance change comprises tuning the plurality of inductors to compensate for the coupler induced capacitive loading.

31. at least one processor in communication with an analog processor having at least one quantum bit; and 1. A computing system including at least one non-transitory processor-readable storage medium storing at least one of processor-executable instructions or data, The processor-executable instructions or data, when executed by the at least one processor, cause the at least one processor to: determining an expected capacity of the qubit; determining a target capacity of the qubit; determining a total volume change, ΔC, based on the target volume and the predicted volume; and causing the analog processor to perform acts including tuning a plurality of inductors to change the effective capacitance of the quantum bit based on the corresponding distances from the one or more Josephson junctions and the total capacitance change, each inductor being positioned at a corresponding distance from one or more Josephson junctions of the quantum bit along a quantum bit loop.

32. The act further comprises: determining an expected inductance of the qubit; determining a target inductance of the qubit; and determining a total inductance change ΔL based on the target and predicted inductances; Including, Tuning the plurality of inductors to vary the effective capacitance of the qubit includes: tuning the plurality of inductors such that a sum of a plurality of corresponding tunable inductances of the plurality of inductors is within the threshold total inductance change ΔL; and 32. The computing system of claim 31, further comprising tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC.

33. 33. The computing system of claim 32, wherein tuning the plurality of inductors based on the corresponding distances from the one or more Josephson junctions comprises tuning the first and second inductors based on the respective distances of the first and second inductors from a point located at a critical distance along the qubit loop from the one or more Josephson junctions.

34. Tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC, tuning the tunable inductance of the first inductor to reduce the effective qubit capacitance and increase the effective qubit inductance; and 34. The computing system of claim 33, comprising tuning the tunable inductance of the second inductor to increase the effective qubit capacitance and increase the effective qubit inductance.

35. Tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC, selecting a selected distribution from a plurality of candidate distributions of inductor tuning values ​​based on the total capacitance change ΔC and the total inductance change ΔL; and 34. The computing system of claim 33, further comprising tuning the plurality of tunable inductors based on the inductor tuning values ​​of the selected distribution.

36. 36. The computing system of claim 35, wherein selecting the selected distribution comprises selecting the selected distribution based on a difference between a candidate capacitance change corresponding to the selected distribution and the total capacitance change ΔC.

37. Tuning the plurality of tunable inductors based on the selection distribution includes: interpolating an interpolated inductor tuning value for each inductor of the plurality of inductors based on the inductor tuning value of the selected distribution and the inductor tuning value of an additional candidate distribution of the plurality of candidate distributions; and The computing system of claim 35 further comprising tuning the plurality of tunable inductors based on the interpolated inductor tuning values.

38. identifying the plurality of candidate distributions includes identifying the plurality of candidate distributions in a lookup table based on at least one of the total capacitance change ΔC and the total inductance change ΔL; 38. The computing system of claim 37, wherein the additional candidate distribution of the plurality of candidate distributions is close to the selected distribution in the lookup table.

39. Identifying the plurality of candidate distributions of inductor tuning values ​​comprises: looking up a first set of inductor tuning values ​​for one of the first inductor and the second inductor along a first axis of a lookup table; and 38. The computing system of claim 37, further comprising: for each of the first set of inductor tuning values, identifying a corresponding inductor tuning value of an additional inductor of the first and second inductors along a second axis of the lookup table such that the sum of the first and second inductor tuning values ​​is within a threshold of the total inductance change ΔL, wherein each inductor tuning value from the first set is paired with the corresponding inductor tuning value of the additional inductor of the first and second inductors that includes a candidate distribution and corresponds to a predicted capacitance change.

40. 40. The computing system of claim 39, wherein selecting a selected distribution from the plurality of candidate distributions comprises selecting a candidate distribution among the plurality of candidate distributions having a corresponding predicted capacity change closest to the total capacity change ΔC.

41. Tuning the plurality of inductors such that the sum of the plurality of tunable inductances is distributed among the plurality of inductors based on the total capacitance change ΔC, looking up said total capacitance change ΔC along a first axis in a lookup table; looking up the total inductance change ΔL along a second axis in the lookup table; identifying a candidate distribution of inductor tuning values ​​in the lookup table corresponding to the total capacitance change ΔC and the total inductance change ΔL; and 34. The computing system of claim 33, further comprising tuning the plurality of inductors based on the candidate distribution.

42. 42. The computing system of claim 41 , wherein examining at least one of the total capacitance change ΔC and the total inductance change ΔL comprises determining an entry along at least one of the first and second axes of the lookup table that approximates the at least one of the total capacitance change ΔC and the total inductance change ΔL.

43. Tuning multiple inductors is tuning a first inductor at a first distance from the one or more Josephson junctions along the qubit loop to reduce the effective qubit capacitance and increase the effective qubit inductance; and 32. The computing system of claim 31 , comprising tuning a second inductor at a second distance from the one or more Josephson junctions along the qubit loop, the second distance being greater than the first distance, to increase the effective qubit capacitance and increase the effective qubit inductance.

44. 32. The computing system of claim 31 , wherein determining the predicted capacity of the qubit comprises determining a coupler induced capacitive loading based on one or more coupling strengths of one or more couplers coupled to the qubit.

45. 32. The computing system of claim 31 , wherein tuning the plurality of inductors to modify the effective capacitance of the qubit based on the total capacitance change comprises tuning the plurality of inductors to compensate for the coupler induced capacitive loading.

46. 1. An analog computing system including a qubit, the qubit comprising: Josephson junction; a first qubit loop formed by a first superconducting current path; and a second qubit loop formed by a second superconducting current path; the first qubit loop and the second qubit loop are electrically connected in parallel across the Josephson junction; Analog computing systems.

47. 47. The analog computing system of claim 46, further comprising a first flux bias line in communication with the first quantum bit loop and a second flux bias line in communication with the second quantum bit loop, wherein the first flux bias line receives a signal independently from the second flux bias line.

48. the second qubit loop includes a first portion in communication with the Josephson junction and a second portion spaced from the Josephson junction; the first portion and the second portion are separated by an intersection; 47. The analog computing system of claim 46, wherein current in the second qubit loop propagates in a first rotational direction in the first portion and in a second rotational direction that is opposite to the first rotational direction in the second portion.

49. 47. The analog computing system of claim 46, wherein the Josephson junction comprises one of a compound Josephson junction or a compounded compound Josephson junction.

50. 47. The analog computing system of claim 46, wherein the first qubit loop and the second qubit loop overlap along a shared portion.

51. 47. The analog computing system of claim 46, further comprising a combiner tunably coupled to one of the first qubit loop and the second qubit loop.

52. 52. The analog computing system of claim 51 further comprising a second qubit coupled to the combiner.

53. the first qubit loop and the second qubit loop are symmetric about an axis of the Josephson junction; 47. The analog computing system of claim 46, wherein the axis of the Josephson junction intersects a first connection between the first qubit loop, the second qubit loop, and the Josephson junction and a second connection between the first qubit loop, the second qubit loop, and the Josephson junction.

54. 47. The analog computing system of claim 46, further comprising one or more additional qubit loops electrically connected in parallel across the Josephson junction.

55. 47. The analog computing system of claim 46, further comprising a plurality of inductors disposed along each of the first qubit loop and the second qubit loop, each of the plurality of inductors being tunable to provide a corresponding tunable inductance.

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