Imaging device

Abstract

To provide an imaging device capable of effectively reducing power consumption during moving image shooting without affecting AF processing.SOLUTION: In an imaging device having an FPGA capable of high-speed transfer of image signals of moving images received from an imaging element to an image processing circuit at a predetermined frame rate, the FPGA has at least a communication circuit block that transmits and receives the image signals between the imaging element and the image processing circuit, an image processing block that performs predetermined image processing on the received image signals, an AF processing block that performs arithmetic processing related to AF using the received image signals, and a PLL circuit block that outputs high-speed clock signals to the communication circuit block, the image processing block, and the AF processing block. The FPGA stops driving the PLL circuit block by detecting that both transfer processing of one frame's worth of image signals in the communication circuit block and AF processing in the AF processing block have been completed.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an imaging device capable of capturing a moving image and reducing power consumption.

Background Art

[0002] Conventionally, in an imaging device having an intermediate device (FPGA) for image processing, when transmitting captured image data from the FPGA to a subsequent image processing device (DSP) via serial communication, a PLL circuit (Phase-locked loop circuit) is used as a means for generating a high-speed clock signal to enable high-speed transmission.

[0003] However, since a PLL circuit generally consumes a large amount of power, it has been desired to suppress power consumption by appropriately controlling the PLL circuit.

[0004] For example, in the invention disclosed in Patent Document 1, in an imaging device having an image sensor, an intermediate device, and an image processing device, and obtaining a moving image by the image sensor continuously acquiring a plurality of image signals, the intermediate device includes a PLL circuit that adjusts the speed of a clock signal, a synchronization signal generation circuit that notifies the PLL circuit of the start and completion of transmission of the captured image signal to the intermediate device, and a high-speed serial transmission circuit that performs high-speed serial communication with the image processing device using the clock signal adjusted by the PLL circuit. The PLL circuit has a pause period in which it stops operating after the transmission of the image signal for one frame among the image signals of the moving image captured by the image sensor is completed. The pause period of the PLL circuit is a time preset with respect to a predetermined frame rate in the acquisition of a plurality of consecutive image signals. The intermediate device is configured to independently stop and start the PLL circuit by being given a predetermined frame rate.

[0005] According to this invention, it is said that an imaging device capable of suppressing power consumption without reducing the processing efficiency of the captured image signal during moving image shooting can be provided.

Prior Art Documents

Patent Documents

[0006] Patent Document 1 Japanese Patent Publication No. 6042676 Summary of the Invention Problems to be Solved by the Invention

[0007] On the other hand, in recent years, in order to meet the need for enhancing the autofocus (AF) function, digital cameras equipped with pixels for detecting image plane phase difference within the imaging device have become widespread. Along with this, the burden on the DSP side responsible for the processing of image plane phase difference AF has been increasing. Therefore, it is desirable to configure the system so that a part of the processing that was previously performed by the DSP in the subsequent stage is transferred to the FPGA side in the previous stage, and the load on the DSP side is shared with the FPGA (Field-Programmable Gate Array).

[0008] Even in the case where such a configuration is adopted where a part of the processing (AF processing) is taken charge of by the FPGA, it is still necessary to continuously reduce the power consumption of the PLL circuit. In such a configuration, there may be a case where the circuit block for AF processing is operating even during the blanking period of image transfer. Therefore, as disclosed in Patent Document 1, if the control to stop the PLL circuit is performed during the pause period of image transfer, there is a problem that the PLL circuit during AF processing will also stop, leading to malfunction.

[0009] The present invention has been made in view of such a situation, and an object thereof is to provide an imaging device capable of effectively reducing the power consumption during video shooting without affecting AF processing. Means for Solving the Problems

[0010] In order to achieve the above object, an imaging device according to the present invention has an FPGA (Field-Programmable Gate Array) as an intermediate device capable of transferring the image signal of the moving image received from the imaging element to the image processing circuit at a predetermined frame rate. In the imaging device, the FPGA has at least a communication circuit block for transmitting and receiving the image signal between the imaging element and the image processing circuit, an image processing block for performing predetermined image processing on the received image signal, an AF processing block for performing arithmetic processing related to autofocus using the received image signal, and a PLL circuit block for outputting a high-speed clock signal to the communication circuit block, the image processing block, and the AF processing block. The FPGA is characterized in that it stops driving the PLL circuit block by detecting that both the transfer process of the image signal for one frame in the communication circuit block and the AF processing in the AF processing block are completed.

[0011] Further, in the imaging device according to the present invention, preferably, after a predetermined standby period has elapsed since the transfer of the image signal for one frame is completed, the image processing circuit instructs the FPGA to resume driving the PLL circuit block to end the driving stop period of the PLL circuit block. Also, preferably, the image processing circuit detects which of the frame transfer period from the start of transfer of the image signal for one frame to the FPGA to the completion of transfer to the image processing circuit and the AF processing period from the start to the end of the arithmetic processing in the AF processing block ends earlier, and calculates the driving stop period using different calculation formulas.

[0012] Further, in the imaging device according to the present invention, preferably, the image processing circuit calculates the standby period based on at least the frame transfer pause period from the completion of transfer of the image signal for one frame to the image processing circuit to the start of transfer of the image signal for the next frame to the FPGA and the period required for the stabilization of the PLL circuit block.

Advantages of the Invention

[0013] According to the imaging device for implementing the present invention, it is possible to effectively reduce the power consumption during video shooting without affecting the AF processing.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0015] Hereinafter, the best mode for carrying out the present invention will be described with reference to the accompanying drawings. Note that the present invention is not limited by this embodiment.

[0016] The block diagram shown in FIG. 1 shows the main configuration of an imaging device which is an embodiment of the present invention. In this figure, the imaging device 100 includes a photographing optical system 110, an imaging element 120, an FPGA 130, a DSP 140, a main CPU 150, a user interface (I / F) 161, a recording medium interface (I / F) 162, an image display unit 170, and a lens control unit 180.

[0017] The photographing optical system 110 is composed of a plurality of lens groups (not shown) including a focus lens group and a zoom lens group. In this figure, only one lens is shown as an example.

[0018] The imaging device 120 receives the light rays condensed by the imaging optical system 110, performs photoelectric conversion thereon, and outputs an image signal. The imaging device 120 includes a gain variable amplifier and an A / D converter (not shown) inside, and the image signal is output as digital data. When an imaging device 120 that does not incorporate these gain variable amplifier and A / D converter is adopted, these devices may be individually mounted.

[0019] The FPGA 130 is an intermediate device that performs predetermined processing on the image signal read from the imaging device 120 and outputs it to the subsequent DSP 140. Details of the FPGA 130 will be described later.

[0020] The DSP 140 performs various signal processes on the image signal output from the FPGA 130. Examples of the signal process include, for example, color reproduction process, development process to image data in JPEG format or TIFF format, etc.

[0021] The main CPU 150 performs overall control of the entire imaging apparatus 100 by executing the stored program. For example, it performs read control of the imaging device 120. That is, by outputting a signal for which the main CPU 150 determines the drive timing of the imaging device 120, the horizontal drive and the vertical drive for each pixel are controlled, and the image signal generated at each pixel is read out.

[0022] The lens control unit 180 is connected to be communicable with the main CPU 150, and cooperatively controls the imaging optical system 110.

[0023] The user I / F 161 has operation members such as a release button, a power button, a command dial, a cross key, etc. For example, when the user operates these operation members, the main CPU 150 issues an instruction to perform corresponding operations.

[0024] The recording medium I / F 162 writes and reads RAW data and developed image data to and from a recording medium (not shown). This recording medium is a removable recording medium such as a semiconductor memory.

[0025] The image display unit 170 displays so-called live view (LV) images, image data read from a recording medium (not shown), and the like.

[0026] Next, the operation of the FPGA 130 in the imaging apparatus 100 of the present invention described above will be described in detail. FIG. 2 is a block diagram for explaining the processing in the FPGA 130 that functions to transfer the image signal read from the imaging element 120 to the DSP 140.

[0027] In this figure, the FPGA 130 includes a reception circuit block 131, an image processing block 132, a transmission circuit block 133, a main clock generation block 134, a PLL circuit block 135, and an AF processing block 136.

[0028] The reception circuit block 131 receives the image signal output from the imaging element 120.

[0029] The image processing block 132 performs predetermined image processing on the image signal output from the imaging element 120. Examples of the image processing include, for example, defective pixel correction, white balance processing, shading correction of the photographing lens, and the like. Further, the image signal subjected to the image processing is output to the transmission circuit block 133.

[0030] The transmission circuit block 133 transfers the image signal output from the image processing block 132 to the DSP 140. Thereby, the image signal subjected to various processes is delivered from the FPGA 130 to the DSP 140. Further, the transmission circuit block 133 detects the completion of the transfer of the image signal to the DSP 140 by a known method. This transfer completion detection is used to stop the driving of the PLL circuit block 135 described later.

[0031] The AF processing block 136 receives an image signal from the image processing block 132 as necessary and performs predetermined AF processing on it. Examples of AF processing include, for example, contrast AF processing, correlation operation processing using the output of image plane phase difference pixels, etc. Also, the AF processing block 136 detects the completion of AF processing by a known method. This detection of processing completion is used to stop the driving of the PLL circuit block 135 described later.

[0032] The main clock generation block 134 generates a clock signal. The clock signal generated here is input to the PLL circuit block 135.

[0033] The PLL circuit block 135 uses the clock signal generated by the main clock generation block 134 as an input signal and generates a high-speed clock signal synchronized with it. The high-speed clock signal generated here is input to the image processing block 132, the transmission circuit block 133, and the AF processing block 136. With this high-speed clock signal, high-speed internal processing can be executed in each circuit.

[0034] Also, when the FPGA 130 detects that both the image signal transfer of the transmission circuit block 133 and the AF processing of the AF processing block 136 described above are completed, it stops the driving of the PLL circuit block 135.

[0035] Regarding the synchronization signals related to the transfer of the image signal between each circuit in the FPGA 130 and from the FPGA 130 to the DSP 140, it is assumed that they are generated by a synchronization signal generation block (not shown) in the reception circuit block 131 in this embodiment. The synchronization signals generated here are input to the image processing block 132, the transmission circuit block 133, and the AF processing block 136 via a communication path (not shown). Each circuit such as the reception circuit block 131 transfers the image signal to the subsequent circuit in synchronization with this synchronization signal.

[0036] Next, the processing flow when the imaging device 100 of the present invention captures a moving image at a predetermined frame rate (for example, 30 fps) will be described. FIG. 3 is an example of a time chart showing the processing flow from the imaging element 120 to the DSP 140 during moving image capture.

[0037] In this figure, the signal VAct_In is a signal representing the state of transfer of one frame of the image signal acquired by the imaging element 120 from the imaging element 120 to the FPGA 130. In this embodiment, it corresponds to the state of the signal input to the reception circuit block 131 in the FPGA 130. If this signal is Hi, it means that the transfer state is for one frame, and this period is the vertical active period. On the other hand, if this signal is Low, it means that it is a non-active period of frame transfer.

[0038] The signal VAct_Out is a signal representing the state of transfer of one frame of the image signal processed in the FPGA 130 from the FPGA 130 to the DSP 140. In this embodiment, it corresponds to the state of the signal output from the transmission circuit block 133 in the FPGA 130. If this signal is Hi, it means that the transfer state is for one frame, and this period is the vertical active period. On the other hand, if this signal is Low, it means that it is a non-active period of frame transfer.

[0039] The FPGA 130 sequentially performs processes such as image processing on the transferred image signal and transfers it to the DSP 140. Therefore, hereinafter, for the image signal of one frame, the period from the start of transfer to the FPGA 130 (the signal VAct_In is Hi) to the completion of transfer to the DSP 140 (the signal VAct_Out is Low) may also be referred to as the frame transfer period Ton_Ft. In this figure, the period (1) corresponds to this frame transfer period Ton_Ft.

[0040] Note that this frame transfer period Ton_Ft is calculated by a known calculation according to the frame rate in the LV mode and the exposure time in the DSP 140.

[0041] Also, the period from the completion of transfer to the DSP140 (signal VAct_Out is Low) to the start of transfer to the FPGA120 of the next frame (signal VAct_In is Hi) may also be referred to as the frame transfer pause period Toff_Ft. In this figure, period (2) corresponds to this frame transfer pause period Toff_Ft.

[0042] In the LV mode of the imaging device 100 of this embodiment, the frame rate is fixed, and the period from when the signal VAct_In rises to Hi until it rises again in the next frame transfer is constant. Therefore, this frame transfer pause period Toff_Ft is calculated based on the difference between the frame rate in the LV mode at the DSP140 and the above-described frame transfer period Ton_Ft.

[0043] The AF processing signal S_AF is a signal representing the execution state of a predetermined AF process in the AF processing block 136 within the FPGA130. If this signal is Hi, it means that the AF process is being executed in the AF processing block 136, while if this signal is Low, it means that the AF process is not being performed. For example, when the AF focus determination is successful, this signal transitions from Hi to Low. Hereinafter, the period during which this signal is Hi may also be referred to as the AF processing period Ton_AF. In this figure, period (3) corresponds to this AF processing period Ton_AF.

[0044] This AF processing period Ton_AF can be calculated in advance at the DSP140 by a known calculation according to the AF settings of the imaging device 100, for example, the position and size of the distance measurement frame.

[0045] Also, the period from the start of transfer to the FPGA130 (signal VAct_In is Hi) to the start of the AF process (signal S_AF is Hi) may also be referred to as the AF processing standby period Toff_AF. In this figure, period (4) corresponds to this AF processing standby period Toff_AF.

[0046] This AF processing waiting period Toff_AF can be calculated in advance in the DSP 140 by a known operation according to the AF settings of the imaging device 100, for example, the position and size of the distance measurement frame.

[0047] In this figure, although the AF processing period Ton_AF ends after the frame transfer period Ton_Ft ends, this is not the only case. When the AF processing is completed lightly and in a short time due to settings such as so-called single-point AF (pinpoint AF), the order of these may be reversed.

[0048] The PLL drive signal S_PLL is a signal representing the drive state of the PLL circuit block 135 in the FPGA 130. If this signal is Hi, it means that the PLL circuit block 135 is being driven, and thus some circuit in the FPGA 130 is performing processing. On the other hand, if this signal is Low, it means that the PLL circuit block 135 is in a drive-stop state.

[0049] In this embodiment, during the shooting mode of the imaging device 100, the PLL circuit block 135 is basically in a driven state, and the PLL circuit block 135 enters a drive-stop state according to a drive-stop command from the FPGA 130. Therefore, the period from the drive-stop (signal S_PLL is Low) to the recovery (signal S_PLL is Hi) of the PLL circuit block 135 becomes the power management period Toff_PLL in the imaging device 100 for implementing the present invention. In this figure, period (5) corresponds to this power management period Toff_PLL.

[0050] This power management period Toff_PLL starts at the timing when both the above-mentioned signal VAct_Out and signal S_AF become Low.

[0051] Also, this power management period Toff_PLL is calculated based on various related periods in the DSP 140. Details of the calculation will be described later.

[0052] The PLL stabilization period Tstb_PLL represents the period required for the drive of the PLL circuit block 135 to become stable after the power management period Toff_PLL ends and the drive resumes from the stopped state. In this embodiment, the values obtained from the specifications table of the PLL circuit block 135 are held in advance in the DSP140 as preset values, and the DSP140 refers to them as needed. In this figure, period (6) corresponds to this PLL stabilization period Tstb_PLL.

[0053] The PLL return trigger signal Strig_PLL represents the signal transmitted by the DSP140 to the FPGA130 to instruct the return of the PLL circuit block 135. In this embodiment, the timing of the transmission of this PLL return trigger signal Strig_PLL is managed by the DSP140.

[0054] Specifically, when detecting that the frame transfer from the FPGA130 to the DSP140 is completed, the DSP140 starts counting the time until the transmission of the PLL return trigger signal Strig_PLL. Then, when detecting that a predetermined period has elapsed, the DSP140 transmits the PLL return trigger signal Strig_PLL to the FPGA130 to return the PLL circuit block 135. Hereinafter, this period may also be referred to as the PLL return trigger waiting period Ttrig_PLL. In this figure, period (7) corresponds to this PLL return trigger waiting period Ttrig_PLL.

[0055] In order to achieve effective power consumption reduction, it is effective to maintain this PLL return trigger waiting period Ttrig_PLL as long as possible and increase the period during which the PLL circuit block 135 stops. Therefore, in this embodiment, the DSP140 can transmit the PLL return trigger signal Strig_PLL at the timing that is traced back by the PLL stabilization period Tstb_PLL required for the drive stabilization of the PLL circuit block 135 from the timing when the next frame transfer is started from the imaging device 120.

[0056] Specifically, the PLL return trigger waiting period Ttrig_PLL can be calculated using the frame transfer pause period Toff_Ft and the PLL stabilization period Tstb_PLL described above. That is, the PLL return trigger waiting period Ttrig_PLL is obtained by the following formula. Ttrig_PLL = Toff_Ft - Tstb_PLL ··· (Equation 1)

[0057] Next, the calculation of the above-mentioned power management period Toff_PLL will be described. The power management period Toff_PLL in this embodiment has different calculation methods depending on which of the end of the frame transfer period Ton_Ft and the end of the AF processing period Ton_AF is later, so each will be considered.

[0058] First, consider the case where the AF processing period Ton_AF ends after the end of the frame transfer period Ton_Ft as shown in Figure 3, that is, the case where the AF processing is completed after the completion of the frame transfer.

[0059] In this case, it is necessary to drive the PLL circuit block 135 until the AF processing is completed even after the completion of the frame transfer. Therefore, the period during which the ideal PLL circuit block can be stopped driving, ignoring the stabilization period, is the difference between the period from the start of transfer of the imaging device 120 to the start of transfer of the next frame (= frame rate) and the period from the start of transfer of the imaging device 120 to the completion of the AF processing.

[0060] From the above, the actual power management period Toff_PLL is obtained by the following formula using the frame transfer period Ton_Ft, the frame transfer pause period Toff_Ft, the AF processing period Ton_AF, the AF processing waiting period Toff_AF, and the PLL stabilization period Tstb_PLL. Toff_PLL = (Ton_Ft + Toff_Ft) - (Toff_AF + Ton_AF) - Tstb_PLL ··· (Equation 2)

[0061] Next, consider the case where, contrary to the above-described case, the frame transfer period Ton_Ft ends after the end of the AF processing period Ton_AF, that is, the AF processing is completed during the frame transfer.

[0062] In this case, without worrying about the AF processing, it is no problem to stop driving the PLL circuit block 135 when the frame transfer is completed. Therefore, the ideal period during which the driving of the PLL circuit block can be stopped is directly the frame transfer pause period Toff_Ft.

[0063] From the above, the actual power management period Toff_PLL is obtained by the following formula using the frame transfer pause period Toff_Ft and the PLL stabilization period Tstb_PLL. Toff_PLL = Toff_Ft - Tstb_PLL ··· (Equation 3)

[0064] As described above, the power management period Toff_PLL of the PLL circuit block 135 in the imaging device 100 for implementing the present invention is the period obtained by each formula according to whether the frame transfer or the AF processing is completed later. However, if the calculated power management period Toff_PLL is too short, the processing of the imaging device 100 may become unstable. Therefore, it is desirable to determine whether to actually perform power management.

[0065] FIG. 4 is an example of a flowchart for explaining the processing flow of the LV mode including the determination of whether power management of the PLL circuit block 135 is possible. Although not shown in this figure, this flowchart explains the case where the AF processing is included during the LV processing.

[0066] This flowchart is started when the imaging device 100 enters the LV mode. The LV mode is started, for example, by the user turning on the power of the imaging device 100 or selecting the shooting mode using LV.

[0067] First, in step S101 of this flowchart, the LV drive settings of the imaging device 100 are confirmed. Specifically, operations such as magnifying the LV image to check the details and changing the position of the distance measurement frame are confirmed and reflected.

[0068] Next, in step S102, a determination is made regarding the power management availability of the PLL circuit block 135. Details of the power management availability determination will be described later.

[0069] Next, in step S103, branching occurs based on the determination result in the previous step. That is, if the determination result is that the PLL circuit block 135 is power management available, the process proceeds to step S104. On the other hand, if the determination result is that the PLL circuit block 135 is power management unavailable, the process proceeds to step S106.

[0070] In step S104, the PLL return trigger waiting period Ttrig_PLL is calculated. As described above, specifically, the DSP 140 calculates it from the frame transfer pause period Toff_Ft and the PLL stabilization period Tstb_PLL.

[0071] Next, in step S105, the LV processing loop with power management is executed. Details of this processing loop will be described later. When the LV processing loop with power management ends, the process proceeds to step S107.

[0072] On the other hand, in step S106, a known LV processing loop without power management is executed. When the LV processing loop without power management ends, the process proceeds to step S107.

[0073] Next, in step S107, it is determined whether or not the LV mode of the imaging device 100 has ended. Cases where the LV mode ends include, for example, turning off the power of the imaging device 100 by the user, selecting a still shooting mode that does not use LV, or shifting to a menu screen or the like. When the LV mode of the imaging device 100 does not end and continues, the process returns to step S102, where the determination regarding the power management availability of the PLL circuit block 13 is made again. On the other hand, when the LV mode of the imaging device 100 ends, this flowchart ends as it is.

[0074] Next, the power management availability determination step S102 in the overall flow described above will be described in detail. FIG. 5 is an example of a flowchart for explaining the flow of power management availability determination.

[0075] When the power management availability determination S102 in FIG. 4 is started, first in step S201, the DSP 140 calculates the power management period Toff_PLL. As described above, in this embodiment, the calculation formula of this power management period Toff_PLL differs depending on which of the frame transfer and AF processing is completed later. Therefore, the DSP 140 first determines which process is completed later.

[0076] Specifically, the DSP 140 compares the total length of the frame transfer period Ton_Ft, the AF processing standby period Toff_AF, and the AF processing period Ton_AF. As a result, if the frame transfer period Ton_Ft is shorter, the above-described formula (1) is used, and conversely, if the frame transfer period Ton_Ft is longer, the power management period Toff_PLL is calculated using the above-described formula (2).

[0077] Next, in step S202, it is determined whether or not the power management period Toff_PLL calculated in the previous step is longer than a predetermined period Tth_PLL. This predetermined period Tth_PLL can be, for example, 0, or a period considering the stability of the process can also be set.

[0078] If, as a result of the determination, the power management period Toff_PLL is longer than or equal to the period Tth_PLL, the DSP140 determines that power management is possible and proceeds to step S203. Conversely, if the power management period Toff_PLL is shorter than the period Tth_PLL, the DSP140 determines that power management is not possible and proceeds to step S204.

[0079] Next, in step S203, the power management enable flag is turned ON according to the determination result of the previous step. On the other hand, in step S204, the power management enable flag is turned OFF according to the determination result of the previous step.

[0080] When each of the above steps is completed, this flowchart ends and proceeds to step S103.

[0081] In this way, by having the DSP140 determine whether power management of the PLL circuit block 135 is possible, there is no need for unnecessary communication with the FPGA130, and thus the configuration for implementing the invention can be made simpler.

[0082] Next, the power management enabled LV processing loop S105 of the overall flow described above will be described in detail. FIG. 6 is an example of a flowchart for explaining the flow of the power management enabled LV processing loop. When proceeding to step S105 in FIG. 4, the power management enabled LV processing loop of this flowchart is started.

[0083] Each step of step S301, step S303, step S304, step S307, step S308, and step S310 in this flowchart is a process executed by the DSP140. On the other hand, each step of step S302, step S305, step S306, and step S309 is a process executed by the FPGA130.

[0084] First, in step S301, the DSP140 instructs the FPGA130 to start frame transfer.

[0085] Next, in step S302, FPGA 130 starts frame transfer upon receiving an instruction from DSP 140. As a result, reception of one frame of the image signal generated by image sensor 120 and transfer of one frame of the image signal processed within FPGA 130 to DSP 140 are performed at a predetermined frame rate. FPGA 130 further starts AF processing on the image signal received from image sensor 120.

[0086] Next, in step S303, DSP 140 detects that reception of one frame from FPGA 130 has been completed. For example, there is a method in which DSP 140 detects the start and end of frame transfer by embedding a synchronization code that indicates the start and end of frame transfer in the high-speed serial communication used for transfer and detecting that synchronization code when receiving.

[0087] Next, in step S304, DSP 140 starts counting the period to wait until it transmits a PLL return trigger signal Strig_PLL for restoring PLL circuit block 135, that is, the PLL return trigger waiting period Ttrig_PLL, upon detecting completion of frame reception in the previous step S303. Specifically, DSP 140 starts counting from the end of the frame transfer period Ton_Ft and continues this counting until the PLL return trigger waiting period Ttrig_PLL calculated in step S104 of FIG. 4 has elapsed.

[0088] On the other hand, in step S305, FPGA 130 detects that both frame transfer to DSP 140 and AF processing in AF processing block 136 have been completed.

[0089] Next, in step S306, FPGA 130 stops driving PLL circuit block 135 upon detecting completion of frame transfer and AF processing in the previous step S305. Thereby, it enters the power management period Toff_PLL.

[0090] In this way, by the FPGA 130 alone stopping the drive of the PLL circuit block 135 to enter the power management period, communication with the DSP 140 becomes unnecessary, and it becomes possible to quickly enter the power management period without loss of time. Also, since the DSP 140 does not need to be involved in the stop of the FPGA 130, it becomes possible to prevent delays in the processing within the DSP 140.

[0091] On the other hand, in step S307, in the count of the elapsed time that the DSP 140 has been continuing, it is detected that the PLL return trigger waiting period Ttrig_PLL calculated in advance has elapsed. Thereby, the DSP 140 stops the count and performs a reset.

[0092] Next, in step S308, since the DSP 140 has detected the elapse of the PLL return trigger waiting period Ttrig_PLL, it transmits a PLL return trigger signal Strig_PLL to the FPGA 130 to resume the drive of the PLL circuit block 135.

[0093] In this way, by transmitting a trigger signal for instructing the return of the PLL circuit block 135 from the DSP 140, the DSP 140 can determine that the transfer of the next frame is unnecessary, for example, when an interrupt process occurs due to a mode switch or the like, and more fine-grained stop control of the PLL circuit block 135 becomes possible compared to the case where the FPGA 130 makes a return determination.

[0094] On the other hand, in step S309, the FPGA 130 receives the PLL circuit block 135 return instruction from the DSP 140 and resumes the drive of the PLL circuit block 135. Thereby, the power management period Toff_PLL ends.

[0095] Next, in step S310, the DSP 140 determines the end of this LV loop. Specifically, the DSP 140 detects whether the driving mode of the imaging device 120 has been changed. If the driving mode has been changed, the DSP 140 ends this LV loop and proceeds to step S107 in FIG. 4. On the other hand, if the driving mode of the imaging device 120 has not been changed, the process returns to step S301 to continue repeating this loop, and each step is executed again.

[0096] As described above, according to the imaging device described in the present invention, even in a configuration where AF processing is performed in the FPGA, it is possible to stop driving the PLL circuit block provided in the FPGA without affecting the AF processing, and it is possible to efficiently reduce power consumption.

Explanation of Reference Numerals

[0097] 110 Imaging optical system 120 Imaging device 130 FPGA 131 Reception circuit block 132 Image processing block 133 Transmission circuit block 134 Main clock generation block 135 PLL circuit block 136 AF processing block 140 DSP 150 Main CPU 161 User interface 162 Recording medium interface 170 Image display unit 180 Lens control unit

Claims

1. An imaging device having an FPGA (Field-Programmable Gate Array) as an intermediate device capable of transferring an image signal of a moving image received from an imaging element to an image processing circuit at a predetermined frame rate at high speed, the FPGA has at least a communication circuit block for transmitting and receiving an image signal between the imaging element and the image processing circuit, an image processing block for performing a predetermined image processing on the received image signal, an AF processing block for performing an arithmetic processing related to autofocus using the received image signal, and a PLL circuit block for outputting a high-speed clock signal to the communication circuit block, the image processing block, and the AF processing block; An imaging device characterized in that the FPGA stops driving the PLL circuit block when it detects that both the transfer process of one frame of image signals in the communication circuit block and the AF processing in the AF processing block have been completed.

2. 2. The imaging device according to claim 1, wherein the image processing circuit instructs the FPGA to resume driving the PLL circuit block after a predetermined waiting period has elapsed since completion of transfer of one frame of image signals, thereby ending the period during which the PLL circuit block is stopped from being driven.

3. The imaging device according to claim 2, characterized in that the image processing circuit detects which of a frame transfer period from the start of transfer of one frame's worth of image signals to the FPGA to the completion of transfer to the image processing circuit and an AF processing period from the start of calculation processing in the AF processing block to its end, which ends earlier, and calculates the drive stop period using different calculation formulas for each period.

4. 4. The image processing device according to claim 2, wherein the image processing circuit calculates the waiting period based on at least a frame transfer pause period from the completion of transfer of one frame's worth of image signals to the image processing circuit to the start of transfer of the next frame's image signals to the FPGA, and a period required for stabilization of the PLL circuit block.

Images