Electronic device

Abstract

To provide an electronic device capable of reducing noise and surges.SOLUTION: There is provided an electronic device 1 in which high-side chips 11-13 include built-in upper arm elements 111-113 connected to a high potential side, respectively, and low-side chips 14-16 include built-in lower arm elements 114-116 connected to a lower potential side, respectively, the low-side chips being connected to the paired high-side chips 11-13 inside a module. A control chip 18 includes a built-in pre-driver IC 180 that outputs a drive signal. A sealing part 35 seals the high-side chips 11-13, the low-side chips 14-16, and the control chip 18. The chips 11-16 are arranged on the side of one side of the control chip 18 with gate electrodes thereof facing the control chip 18 side. In the control chip 18, the connected portions of signal lines connected to the chips 11-16 are provided along the one side thereof on the side where the chips 11-16 are disposed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an electronic device.

Background Art

[0002] Conventionally, a semiconductor device in which a semiconductor element is encapsulated is known. For example, in the semiconductor device of Patent Document 1, a semiconductor chip incorporating a power transistor for a high-side switch, a semiconductor chip incorporating a power transistor for a low-side switch, and a semiconductor chip incorporating a control circuit are encapsulated by an encapsulation portion.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, since semiconductor chips for a high-side switch and a low-side switch are arranged on both sides of a semiconductor chip incorporating a control circuit, it is necessary to provide wiring for connecting the high-side element and the low-side element outside the semiconductor device. For example, when connecting the high-side element and the low-side element on a substrate, power wiring through which a relatively large current flows and signal wiring for control are mixed, noise and surges increase, and there is a risk of malfunction. In addition, if wiring for connecting the high-side element and the low-side element is provided on the substrate, it is difficult to miniaturize, and it is also difficult to draw out the signal wiring.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide an electronic device capable of reducing noise and surges.

Means for Solving the Problems

[0006] The electronic device according to the first aspect of the present invention includes a plurality of high-side chips (11 to 13), a plurality of low-side chips (14 to 16), a control chip (18), and a sealing portion (35). The electronic device according to the second aspect of the present invention includes a plurality of high-side chips (11 to 13), a plurality of low-side chips (14 to 16), a sealing portion (35), and terminals (36).

[0007] The high-side chip incorporates an upper arm element (111 to 113) connected to the high potential side. The low-side chip incorporates a lower arm element (114 to 116) connected to the low potential side of each upper arm element, and is connected to the paired high-side chip inside the module.

[0008] In the first aspect, the control chip incorporates a pre-driver IC (180) that outputs drive signals for the upper arm element and the lower arm element. The sealing portion seals the high-side chip, the low-side chip, and the control chip. The high-side chip and the low-side chip are arranged on one side of the control chip with their gate electrodes facing the control chip side. In the control chip, the connection locations of the signal lines connected to the high-side chip or the low-side chip are provided along one side on the side where the high-side chip and the low-side chip are arranged.

[0009] In the second aspect, the sealing portion seals the high-side chip and the low-side chip. The terminals include a power supply terminal (361), a ground terminal (362), an output terminal (363), and an output terminal (364) connected to the high-side chip and the low-side chip, and are provided along the outer edge of the sealing portion. The output terminal is provided on one side of the sealing portion, and the signal terminal is provided on the side opposite to the side where the output terminal of the sealing portion is provided. The power supply terminal and the ground terminal are provided on the side of the side where the output terminal is provided. Thereby, the region where a relatively large current flows can be concentrated, and the generation of noise and surge can be suppressed.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Mode for Carrying Out the Invention

[0011] Hereinafter, an electronic device according to the present invention will be described with reference to the drawings. In the following, in a plurality of embodiments, substantially the same configurations are denoted by the same reference numerals and the description thereof is omitted.

[0012] (First Embodiment) The first embodiment is shown in FIGS. 1 to 3. As shown in FIGS. 1 and 2, the electronic device 1 includes high-side chips 11 to 13, low-side chips 14 to 16, a control chip 18, a lead frame 20, clips 31 to 34, a sealing portion 35, and the like. The chips 11 to 16, 21, the lead frame 20, and the clips 31 to 34 are integrally sealed by the sealing portion 35, formed in a substantially rectangular shape in plan view as a whole, and provided on the top surface side so as to be able to dissipate heat to the heat dissipation portion 95. For the sake of explanation, the sealing portion 35 is omitted in FIG. 1 and the hatching is omitted in FIG. 2.

[0013] A terminal 36 is provided at the outer edge of the sealing portion 35. The terminal 36 may be of a non-leaded type or may have leads protruding therefrom. The terminal 36 includes a power supply terminal 361, a ground terminal 362, an output terminal 363, and a signal terminal 364. The corresponding phase is described in parentheses for the output terminal 363. The lateral terminals within the control region Rc can be used as the signal terminals 364, but among the terminals connected to the control land 21, the terminals arranged on the boundary side with the power region Rp are assigned to the power supply terminal or the ground terminal related to the power supply to the pre-driver IC180.

[0014] The upper arm elements 111 to 113 are built in the high-side chips 11 to 13, and the lower arm elements 114 to 116 are built in the low-side chips 14 to 16 (see FIG. 3). The upper arm elements 111 to 113 and the lower arm elements 114 to 116 of the present embodiment are MOSFETs, but may be IGBTs, bipolar transistors, or the like. Source electrodes are formed on the top surface sides of the high-side chips 11 to 13 and the low-side chips 14 to 16, and drain electrodes are formed on the back surface sides. The chips 11 to 16 are connected to the control chip 18 by signal lines 19. The signal lines 19 include signal lines for gate driving, current detection, temperature detection, and the like.

[0015] As shown in FIG. 3, the upper arm elements 111 to 113 and the lower arm elements 114 to 116, which are six switching elements, are bridge-connected to constitute a driver circuit 10 for driving a motor 800 as a load. The drains of the upper arm elements 111 to 113 are connected to the power supply, and the sources are connected to the drains of the corresponding lower arm elements 114 to 116 provided respectively. The sources of the lower arm elements 114 to 116 are connected to the ground. The gates of the upper arm elements 111 to 113 and the lower arm elements 114 to 116 are connected to a pre-driver IC180 built in the control chip 18.

[0016] The connection point between the upper arm element 111 and the lower arm element 114 of the paired U phase is connected to one end side of the motor winding 801 of the U phase. The connection point between the upper arm element 112 and the lower arm element 115 of the paired V phase is connected to one end side of the motor winding 802 of the V phase. The connection point between the upper arm element 113 and the lower arm element 116 of the paired W phase is connected to one end side of the motor winding 803 of the W phase. The other end sides of the motor windings 801 to 803 are connected. Note that the motor windings 801 to 803 are not limited to Y connection and may be Δ connection.

[0017] Returning to FIGS. 1 and 2, the lead frame 20 includes lands 21 to 26. The back side of the lead frame 20 is exposed from the sealing portion 35 and is electrically connected to the wiring pattern of the substrate 90 by soldering or the like. Note that not all the lands need to be connected to the substrate 90 on the back side. Each of the lands 21 to 26 is formed integrally with or connected to the terminal 36 at the outer peripheral side of the sealing portion 35. The control chip 18 is mounted on the control land 21, and the high-side chips 11 to 13 are mounted on the power land 22.

[0018] The control chip 18 is formed in a substantially rectangular shape in plan view. Hereinafter, the direction parallel to the long side of the control chip 18 is defined as the "first direction", and the direction orthogonal to the first direction is defined as the "second direction". Also, inside the mold, the lead frame 20 side is defined as the "lower side" and the top surface side is defined as the "upper side".

[0019] The lands 21 to 25 are arranged in the order of the control land 21, the power land 22, and the three output lands 23 to 25 from one side in the second direction. The ground land 26 is provided adjacent to the power land 22 and the output land 25. The control land 21 has a ground potential, and the terminals arranged on both sides of the short side and at the end opposite to the power land 22 are used as signal terminals 364.

[0020] The power land 22 is provided adjacent to the long side of the control land 21. The power land 22 abuts against the power pattern of the substrate 90 on the back side and has a power potential. Also, the power land 22 uses, as a power terminal 361, a terminal arranged at an end opposite to the ground land 26 in the first direction. The high-side chips 11 to 13 are arranged side by side horizontally on the power land 22 such that the upper side is the source, the lower side is the drain, and the gate faces the long side of the control chip 18. The drain electrodes of the high-side chips 11 to 13 are connected to the power land 22.

[0021] The output lands 23 to 25 are arranged side by side horizontally adjacent to the power land 22 on the side opposite to the control land 21. Output terminals 363 are formed at the ends of the output lands 23 to 25 opposite to the power land 22. The output terminals 363 are connected to each phase of the motor winding via substrate wiring (not shown). A ground terminal 362 is formed at the end of the ground land 26 opposite to the land 25.

[0022] The intermediate clips 31 to 33 are placed on the high-side chips 11 to 13 respectively. The intermediate clips 31 to 33 are conductive metal plates, such as copper, formed in a plate shape wider than the chips 11 to 16. One end side is connected to the high-side chips 11 to 13 and the low-side chips 14 to 16, and the other end side is connected to the output lands 23 to 25. The ends of one end side of the intermediate clips 31 to 33 are arranged offset so as to be on the side away from the control chip 18 rather than the end on the control chip 18 side of the high-side chips 11 to 13, so that the gate electrodes of the high-side chips 11 to 13 and the control chip 18 can be connected.

[0023] Above the middle clips 31 to 33, the low-side chips 14 to 16 are arranged. The low-side chips 14 to 16 have a drain on the lower side and a source on the upper side, and are arranged such that the gates face the long sides of the control chip 18. Thereby, the sources of the high-side chips 11 to 13 and the drains of the low-side chips 14 to 16 are connected by the middle clips 31 to 33. The other end sides of the middle clips 31 to 33 are bent downward and are respectively connected to the output lands 23 to 25.

[0024] The ground clip 34 is a conductive plate such as copper formed in a plate shape. The ground clip 34 covers the upper sides of the low-side chips 14 to 16, is bent downward on one side in the first direction, and is connected to the ground land 26. In FIG. 1, the ground land 26 is arranged on the right side of the power land 22 in the drawing plane, but the ground land 26 may be arranged on the left side of the power land 22 in the drawing plane, or may be arranged on both sides. When the ground land 26 is arranged on both sides, the ground clip 34 is bent downward on both sides and connected to the ground land 26. The same applies to the ground land 46 in the embodiments described later.

[0025] In the electronic device 1, the drain electrodes of the high-side chips 11 to 13 are connected by a power land 22 which is a common metal plate, and the source electrodes of the low-side chips 14 to 16 are connected by a ground clip 34 which is a common metal plate.

[0026] The end of the ground clip 34 on the control chip 18 side is displaced so as to be on the side separated from the control chip 18 more than the ends of the low-side chips 14 to 16 on the control chip 18 side, so that the gates of the low-side chips 14 to 16 and the control chip 18 can be connected.

[0027] The ground clip 34 is formed wide so as to cover above the bent portions of the intermediate clips 31 to 33. By forming the area of the ground clip 34 as large as possible, the heat dissipation efficiency can be enhanced. On the top surface side of the ground clip 34, it is preferable for the heat dissipation surface to form the thickness of the sealing portion 35 thinly.

[0028] In the electronic device 1, the control chip 18 is provided on one side in the second direction, and the chips 11 to 16 constituting the driver circuit 10 are provided on the other side. The power region Rp through which a relatively large current flows and the control region Rc through which a relatively small current flows are separated and intensively arranged by region. In the power region Rp, from the bottom, the power land 22, the high-side chips 11 to 13, the intermediate clips 31 to 33, the low-side chips 14 to 16, and the ground clip 34 are laminated in this order, forming a stack structure.

[0029] Also, the gate electrodes of the chips 11 to 16 face the control chip 18 side, and are laminated in a stepped manner with a shift so as to be connectable to the control chip 18, securing a non-overlapping region that does not overlap with the members provided above the chips 11 to 16. Thereby, the chips 11 to 16 and the control chip 18 can be connected by wire bonding using the signal line 19. Further, in the control chip 18, the connection locations with the gate electrodes of the chips 11 to 16 are aggregated on one side facing the chips 11 to 16 side.

[0030] In the electronic device 1, in the power region Rp, the power supply terminal 361 is provided on one side in the first direction, the ground terminal 362 is provided on the other side in the first direction, and the output terminal 363 is provided at the end on the second direction side. When viewed as a whole, the power supply and the ground are input in the first direction, and the power related to motor drive is output in the second direction. Thereby, the wiring connecting the power supply and the ground in the power region and the signal line 19 of the control chip 18 can be separated, and the influence of noise and surge can be reduced. Also, the power land 22 having the power supply potential and the ground land 26 are arranged adjacent to each other. Thereby, since the loop of the power portion that becomes the noise source becomes small, noise can be reduced.

[0031] FIG. 4 is a diagram for explaining the parasitic inductor (hereinafter, "ESL") in the driver circuit 10, and here the U-phase arm is described as an example. When a large current is applied to the electronic device 1, a magnetic field is generated around it, and the portion surrounded by the dashed circle becomes the ESL, and the energy accumulated here is applied to the element and becomes switching loss. For example, as a reference example, when the upper arm element is arranged on one side of the control chip and the lower arm element is arranged on the other side, and the source of the upper arm element and the drain of the lower arm element are connected by a printed circuit board wiring outside the module, the wiring length becomes long, so the ESL becomes large.

[0032] In the present embodiment, the sources of the high-side chips 11 to 13 and the drains of the low-side chips 14 to 16 are connected on both sides of the intermediate clips 31 to 33. That is, the wiring length between the drain and the source indicated by A1 in FIG. 4 is the thickness of the intermediate clips 31 to 33, and the wiring length is shorter compared to the case of connecting via a printed circuit board wiring outside the module or the like. Therefore, the ESL can be reduced.

[0033] Also, the drains of the upper arm elements 111 to 113 indicated by A2 in FIG. 4 are connected to the 3-phase common power land 22, and the sources of the lower arm elements 114 to 116 indicated by A3 are connected by the 3-phase common ground clip 34. As a result, the ESL difference between phases disappears, so the commutation switching becomes faster and the switching loss can be reduced.

[0034] By providing the control chip 18 constituting the pre-driver IC 180 in the module and wiring the gate signal line inside the module, compared with the case of providing the gate wiring on a printed circuit board, for example, there is no need to provide vias or the like, so the ESL can be reduced.

[0035] As described above, the electronic device 1 includes a plurality of high-side chips 11 to 13, a plurality of low-side chips 14 to 16, a control chip 18, and a sealing portion 35. The high-side chips 11 to 13 incorporate upper arm elements 111 to 113 connected to the high potential side. The low-side chips 14 to 16 incorporate lower arm elements 114 to 116 connected to the low potential sides of the respective upper arm elements 111 to 113, and are connected to the corresponding high-side chips 11 to 13 inside the module. Specifically, the high-side chip 11 and the low-side chip 14 of the U phase are connected, the high-side chip 12 and the low-side chip 15 of the V phase are connected, and the high-side chip 13 and the low-side chip 16 of the W phase are connected.

[0036] The control chip 18 incorporates a pre-driver IC 180 that outputs drive signals for the upper arm elements 111 to 113 and the lower arm elements 114 to 116. The pre-driver IC 180 has at least the function of a pre-driver. The sealing portion 35 seals the high-side chips 11 to 13, the low-side chips 14 to 16, and the control chip 18.

[0037] The high-side chips 11 to 13 and the low-side chips 14 to 16 are arranged on one side of the long side of the control chip 18 with the gate electrodes to which drive signals are input facing the control chip 18 side. In the control chip 18, the connection locations of the signal lines 19 connected to the high-side chips 11 to 13 or the low-side chips 14 to 16 are provided along one side on the side where the high-side chips 11 to 13 and the low-side chips 14 to 16 are arranged. Here, it is not necessary for all signal terminals to be arranged on a straight line parallel to the long side. For example, due to space constraints or the like, a deviation in arrangement is allowed and is included in the concept of "provided along one side". By arranging the signal line connection locations between the chips 11 to 16 and the control chip 18 to face each other, the control region Rc and the power region Rp through which a relatively large current flows can be separated.

[0038] The electronic device 1 includes high-side chips 11 to 13, low-side chips 14 to 16, a sealing portion 35, and terminals 36. The terminals 36 include a power supply terminal 361, a ground terminal 362, a signal terminal 364, and an output terminal 363 connected to the high-side chips 11 to 13 and the low-side chips 14 to 16, and are provided along the outer edge of the sealing portion 35.

[0039] The sealing portion 35 is formed in a rectangular shape, and the output terminal 363 is provided on one side of the sealing portion 35. The signal terminal 364 is provided on the side opposite to the side where the output terminal 363 of the sealing portion 35 is provided. The power supply terminal 361 and the ground terminal 362 are provided on the side adjacent to the side where the output terminal 363 is provided. Note that on each side, it is not necessary for all terminals to be assigned to the corresponding terminals, and there may be empty terminals. Also, on the side adjacent to the side where the power supply terminal 361 and the ground terminal 362 are provided, for example, a signal terminal 364 may be provided on the control region Rc side. By providing the output terminal 363 on the side opposite to the signal terminal 364, the control region Rc and the power region Rp can be separated.

[0040] Thereby, in the electronic device 1, generation of noise and surges can be suppressed. Also, since the power line through which a relatively large current flows and the signal line can be separated, malfunction can be suppressed. Further, the substrate wiring becomes easier.

[0041] The high-side chips 11 to 13 and the low-side chips 14 to 16 are provided on one side of the control chip 18. The output terminal 363 is provided on the side where the high-side chips 11 to 13 and the low-side chips 14 to 16 are provided. The signal terminal is provided on the side where the control chip 18 is provided. Thereby, the control region Rc and the power region Rp can be appropriately separated.

[0042] The paired high-side chips 11 to 13 and low-side chips 14 to 16 are stacked in a state where the low-side chips 14 to 16 are on the top surface side and a part of the top surface side of the high-side chips 11 to 13 is shifted so as not to overlap with the low-side chips 14 to 16. Thereby, the size of the electronic device 1 can be reduced. Also, by stacking the low-side chips 14 to 16 with a shift and securing a non-overlapping region on the top surface side of the high-side chips 11 to 13, the signal lines 19 can be appropriately connected.

[0043] (Second Embodiment) The second embodiment of the electronic device 2 is shown in FIG. 5. The electronic device 2 of the second embodiment includes high-side chips 11 to 13, low-side chips 14 to 16, a control chip 18, a lead frame 40, clips 51 to 54, relay substrates 56, 57, a sealing portion 35 (not shown in FIG. 5), and the like. In this embodiment, the high-side chips 11 to 13 and the low-side chips 14 to 16 are not stacked, but are arranged flat on the lead frame 40.

[0044] The lead frame 40 includes lands 41 to 46, and each of the lands 41 to 46 is formed integrally with the terminal 36 or connected to the terminal 36 at the side on the outer peripheral side of the sealing portion 35. The control land 41 is substantially the same as the control land 21 of the first embodiment, and the control chip 18 is arranged thereon.

[0045] The power land 42 is at the power supply potential, similar to the power land 22 of the first embodiment, and is provided adjacent to the control land 41 so as to face one side of the long side of the control chip 18. Also, the high-side chips 11 to 13 are arranged on the power land 42 and are connected to the drain electrodes on the back surface.

[0046] The output lands 43 to 45 are provided side by side along the long side of the power land 42 on the side opposite to the control land 41 of the power land 42. The low-side chips 14 to 16 are arranged on the output lands 43 to 45 and are connected to the drain electrodes on the back surface. The source electrodes provided on the upper side of the high-side chip 13 and the output lands 43 to 45 are connected by the intermediate clips 51 to 53. The intermediate clips 51 to 53 are substantially the same as the intermediate clips 31 to 33 of the first embodiment except that the low-side chips 14 to 16 are not placed on the upper surface.

[0047] The ground clip 54 covers the upper sides of the low-side chips 14 to 16 and is formed to bend downward on one side in the first direction, and is connected to the ground land 46. The ground land 46 is arranged side by side with the output land 45. The clips 51 to 54 are arranged such that the ends on the control chip 18 side are shifted to the side away from the control chip 18 so that the gate terminals of the chips 11 to 16 can be connected to the control chip 18.

[0048] In this embodiment, the chips 11 to 16 are placed flat, and since the high-side chips 11 to 13 are arranged between the low-side chips 14 to 16 and the control chip 18, it is difficult to directly connect the gate electrodes of the low-side chips 14 to 16 and the control chip 18.

[0049] Therefore, in this embodiment, relay substrates 56 and 57 are provided on the power land 42, and the gate electrodes of the low-side chips 14 to 16 and the control chip 18 are connected via the relay substrates 56 and 57. The relay substrates 56 and 57 are, for example, printed circuit boards or ceramic substrates, etc., and have wiring patterns formed thereon that can connect wires connecting the gate electrodes and the control chip. In this embodiment, they are arranged in the order of the high-side chip 11, the relay substrate 56, the high-side chips 12 and 13, and the relay substrate 57 from one side in the first direction.

[0050] The relay substrate 56 is provided between the high-side chips 11 and 12 and relays the connection between the gate electrodes of the low-side chips 14 and 15 and the control chip 18. That is, the relay substrate 56 is shared for relaying the gate electrode connections of the high-side chips 11 and 12. The relay substrate 57 is provided on the side opposite to the high-side chip 12 of the high-side chip 13 and relays the connection between the gate electrode of the low-side chip 16 and the control chip 18. Note that the relay substrate only needs to be able to relay the connection between the gate electrodes of the low-side chips 14 to 16 and the control chip 18, and the number, shape, arrangement, etc. may be different.

[0051] In the electronic device 2 of the present embodiment, the high-side chips 11 to 13 are arranged side by side along one side of the control chip 18, and the low-side chips 14 to 16 are arranged side by side on the side opposite to the control chip 18 of the high-side chips 11 to 13.

[0052] The electronic device 2 includes relay substrates 56 and 57 disposed between or on the sides of the high-side chips 11 to 13 arranged side by side. The gate electrodes of the low-side chips 14 to 16 are connected to the control chip 18 via the relay substrate. Thereby, even when the chips 11 to 16 are arranged flat, the control region Rc and the power region Rp can be appropriately separated. Also, the gate electrodes of the low-side chips 14 to 16 disposed apart from the control chip 18 and the control chip 18 can be appropriately connected.

[0053] (Third Embodiment) The third embodiment is shown in FIG. 6. The electronic device 3 of the third embodiment includes high-side chips 11 to 13, low-side chips 14 to 16, a control chip 18, a lead frame 60, clips 51 to 54, a sealing portion 35 (not shown in FIG. 6), etc. The lead frame 60 includes lands 43 to 46, 61. The land 61 is at a power supply potential, and the high-side chips 11 to 13 and the control chip 18 are disposed thereon.

[0054] In the control chip 18 of this embodiment, the back surface side of the element is insulated. Therefore, the potential of the land on which the control chip 18 is mounted may be not only the ground potential but also the power supply potential. By using a back-surface-insulated control chip 18 and sharing the land 61 among the high-side chips 11 to 13 and the control chip 18, the electronic device 3 can be miniaturized. In the first and second embodiments, the lands may be configured to be shared among the high-side chips 11 to 13 and the control chip 18, or in this embodiment, the lands may be separated between the high-side chips 11 to 13 and the control chip 18.

[0055] In this embodiment, since the chips 11 to 16 are arranged flat, as in the second embodiment, it is difficult to directly connect the gate electrodes of the low-side chips 14 to 16 and the control chip 18. In this embodiment, the gate electrodes of the low-side chips 14 to 16 and the control chip 18 are connected via an empty terminal 365 to which no power supply potential, ground potential, or various signals are assigned.

[0056] Specifically, the gate electrode of the low-side chip 14 is connected to the control chip 18 via the empty terminal 365 on the left side of the paper surface. The gate electrode of the low-side chip 16 is connected to the control chip 18 via the empty terminal 365 on the right side of the paper surface. The gate electrode of the low-side chip 15 arranged between the low-side chips 14 and 16 is connected to the control chip 18 via a relay pad formed on the low-side chip 16 and the empty terminal 365 on the right side of the paper surface. Note that a relay pad may be provided on the low-side chip 14, and the gate electrode of the low-side chip 15 may be configured to be connected to the control chip 18 via the empty terminal on the left side of the paper surface.

[0057] In the electronic device 3 of this embodiment, similar to the second embodiment, the chips 11 to 16 are arranged flat. Also, the gate electrodes of the low-side chips 14 to 16 are connected to the control chip 18 via the empty terminals 365 provided on the side of the sealing portion 35. Even with such a configuration, the gate electrodes of the low-side chips 14 to 16 arranged apart from the control chip 18 and the control chip 18 can be appropriately connected.

[0058] (Other embodiments) In the above embodiment, the low-side chips are connected by the ground clip which is a plate-shaped metal plate. In other embodiments, the member for connecting the source of the low-potential side element is not limited to a metal plate, and ribbon bonding or aluminum bonding may be used. The same applies to the member for connecting the high-side chip.

[0059] In the above embodiment, the ground clip 34 is sealed in the sealing portion 35. In other embodiments, as shown in FIG. 7, the ground clip 34 is exposed from the top surface side of the sealing portion 35, and heat may be directly dissipated to the heat dissipation portion. Thereby, the heat dissipation efficiency can be improved. Note that, although the electronic device 1 of the first embodiment is illustrated in FIG. 7, the top surface side of the ground clip may be exposed from the sealing portion in the second embodiment or the third embodiment.

[0060] In the above embodiment, the driver circuit is a three-phase inverter having three sets of upper and lower arm elements. In other embodiments, the number of arms may be two or four or more. As described above, the present invention is not limited to the above embodiments, and can be implemented in various forms without departing from the spirit of the invention.

Explanation of reference numerals

[0061] 1 to 3... Electronic device 11 to 13... High-side chips 111 to 113... Upper arm elements 14 to 16... Low-side chips 114 to 116... Lower arm elements 18... Control chip 180... Driver IC 35... Sealing part 36... Terminal 361... Power supply terminal 362... Ground terminal 363... Signal terminal 364... Output terminal 363... Spare terminal

Claims

1. Multiple high-side chips (11-13) containing upper arm elements (111-113) connected to the high-potential side, Each upper arm element has a lower arm element (114-116) located on the low-potential side, and a pair of low-side chips (14-16) are connected to the high-side chips inside the module. A sealing portion (35) that seals the high-side tip and the low-side tip, A plurality of terminals (36) are provided along the outer edge of the sealing portion, including a power terminal (361), a ground terminal (362), a signal terminal (364), and an output terminal (363) connected to the high-side chip and the low-side chip, Equipped with, The output terminal is provided on one side of the sealing portion. The signal terminal is provided on the side of the sealing portion opposite to the side on which the output terminal is provided. The power terminal and the ground terminal are provided on the side of the side where the output terminal is provided. An electronic device in which a pair of high-side chips and low-side chips are stacked such that the low-side chip faces upward and a portion of the high-side chip's upward surface does not overlap with the low-side chip.

2. The system further includes a pre-driver IC (180) that outputs drive signals for the upper arm element and the lower arm element, and a control chip (18) that is integrally sealed in the sealing portion. The high-side chip and the low-side chip are provided on one side of the control chip. The output terminal is provided on the side where the high-side chip and the low-side chip are provided. The electronic device according to claim 1, wherein the signal terminal is provided on the side on which the control chip is provided.

3. Multiple high-side chips (11-13) containing upper arm elements (111-113) connected to the high-potential side, Each upper arm element has a lower arm element (114-116) located on the low-potential side, and a pair of low-side chips (14-16) are connected to the high-side chips inside the module. A sealing portion (35) that seals the high-side tip and the low-side tip, A plurality of terminals (36) are provided along the outer edge of the sealing portion, including a power terminal (361), a ground terminal (362), a signal terminal (364), and an output terminal (363) connected to the high-side chip and the low-side chip, A pre-driver IC (180) that outputs drive signals for the upper arm element and the lower arm element is built into the control chip (18) which is sealed integrally with the sealing portion, Equipped with, The output terminal is provided on one side of the sealing portion. The signal terminal is provided on the side of the sealing portion opposite to the side on which the output terminal is provided. The power terminal and the ground terminal are provided on the side of the side where the output terminal is provided. The high-side chip and the low-side chip are provided on one side of the control chip. The output terminal is provided on the side where the high-side chip and the low-side chip are provided. The aforementioned signal terminal is provided on the side where the control chip is located. The high-side tip and the low-side tip are arranged side by side, From one side, the control chip, the high-side chip, and the low-side chip are arranged in that order. The system further comprises relay substrates (56, 57) arranged between or to the sides of the high-side chips arranged side by side, An electronic device in which the gate electrode of the low-side chip to which the drive signal is input is connected to the control chip via the relay board.

4. Multiple high-side chips (11-13) containing upper arm elements (111-113) connected to the high-potential side, Each upper arm element has a lower arm element (114-116) located on the low-potential side, and a pair of low-side chips (14-16) are connected to the high-side chips inside the module. A sealing portion (35) that seals the high-side tip and the low-side tip, A plurality of terminals (36) are provided along the outer edge of the sealing portion, including a power terminal (361), a ground terminal (362), a signal terminal (364), and an output terminal (363) connected to the high-side chip and the low-side chip, A pre-driver IC (180) that outputs drive signals for the upper arm element and the lower arm element is built into the control chip (18) which is sealed integrally with the sealing portion, Equipped with, The output terminal is provided on one side of the sealing portion. The signal terminal is provided on the side of the sealing portion opposite to the side on which the output terminal is provided. The power terminal and the ground terminal are provided on the side of the side where the output terminal is provided. The high-side chip and the low-side chip are provided on one side of the control chip. The output terminal is provided on the side where the high-side chip and the low-side chip are provided. The aforementioned signal terminal is provided on the side where the control chip is located. The high-side tip and the low-side tip are arranged side by side, From one side, the control chip, the high-side chip, and the low-side chip are arranged in that order. An electronic device in which the gate electrode of the low-side chip to which the drive signal is input is connected to the control chip via an empty terminal (365) provided on the side of the sealing portion.

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