Electronic device

Abstract

To provide an electronic device capable of reducing the phase difference of a parasitic inductor.SOLUTION: High-side chips 11-13 of an electronic device 1 are incorporated with upper arm elements 111 to 113 that are connected to a high potential side. Low-side chips 14-16 are incorporated with lower arm elements 114 to 116 that are connected to low potential sides of the upper arm elements 111 to 113 respectively, and are connected to their paired high-side chips inside a module. A power land 22 connects the high-side chips 11 to 13 to a power supply potential. A ground clip 34 connects the low-side chips 14 to 16 to a ground potential. A sealing section 35 seals the high-side chips 11 to 13, the low-side chips 14 to 16, the power land 22, and the ground clip 34 integrally with one another. The ground clip 34 is shared by plurality of low-side chips 14-16.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an electronic device.

Background Art

[0002] Conventionally, a semiconductor device in which a semiconductor element is encapsulated is known. For example, in Patent Document 1, two semiconductor switch elements are encapsulated in an encapsulating resin member to form a half bridge.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a combination of an upper arm element, which is an element on the high potential side in a bridge circuit, and a lower arm element, which is an element on the low potential side, is used as an arm, if the wirings are not shared when a plurality of arms are modularized integrally, the difference in parasitic inductance between phases becomes large, and the switching loss and surge voltage increase.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide an electronic device capable of reducing the difference in parasitic inductance between phases.

Means for Solving the Problems

[0006] The electronic device of the present invention includes a plurality of high-side chips (11 to 13), a plurality of low-side chips (14 to 16), a power supply wiring member (21), ground wiring members (34, 81 to 85), and a sealing portion (35). The high-side chips incorporate upper arm elements (111 to 113) connected to the high potential side. Each of the low-side chips incorporates a lower arm element (114 to 116) connected to the low potential side of the upper arm element, and is connected to the corresponding high-side chip inside the module.

[0007] The power supply wiring member connects the high-side chips to the power supply potential. The ground wiring members connect the low-side chips to the ground potential. The sealing portion integrally seals the high-side chips, the low-side chips, the power supply wiring member, and the ground wiring members. The ground wiring members are shared by the plurality of low-side chips. Thereby, the phase difference of the parasitic inductors can be reduced.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Mode for Carrying Out the Invention

[0009] Hereinafter, an electronic device according to the present invention will be described with reference to the drawings. Hereinafter, in a plurality of embodiments, substantially the same configurations will be denoted by the same reference numerals and the description thereof will be omitted.

[0010] (First Embodiment) The first embodiment is shown in FIGS. 1 to 3. As shown in FIGS. 1 and 2, the electronic device 1 includes high-side chips 11 to 13, low-side chips 14 to 16, a control chip 18, a lead frame 20, clips 31 to 34, a sealing portion 35, and the like. The chips 11 to 16, 21, the lead frame 20, and the clips 31 to 34 are integrally sealed by the sealing portion 35, are formed in a substantially rectangular shape in plan view as a whole, and are provided on the top surface side so as to be able to dissipate heat to the heat dissipation portion 95. For the sake of explanation, the sealing portion 35 is omitted in FIG. 1 and the like, and the hatching is omitted in FIG. 2.

[0011] A terminal 36 is provided at the outer edge of the sealing portion 35. The terminal 36 may be of a non-leaded type or may have leads protruding therefrom. The terminal 36 includes a power terminal 361, a ground terminal 362, an output terminal 363, and a signal terminal 364. The corresponding phase is described in parentheses for the output terminal 363. The lateral terminals within the control region Rc can be used as the signal terminal 364, but among the terminals connected to the control land 21, the terminals arranged on the boundary side with the power region Rp are assigned to the power terminal or the ground terminal related to the power supply to the pre-driver IC180.

[0012] The high-side chips 11 to 13 incorporate upper arm elements 111 to 113, and the low-side chips 14 to 16 incorporate lower arm elements 114 to 116 (see FIG. 3). The upper arm elements 111 to 113 and the lower arm elements 114 to 116 of the present embodiment are MOSFETs, but may also be IGBTs, bipolar transistors, or the like. Source electrodes are formed on the top surface sides of the high-side chips 11 to 13 and the low-side chips 14 to 16, and drain electrodes are formed on the back surface sides. The chips 11 to 16 are connected to the control chip 18 by signal lines 19. The signal lines 19 include signal lines for gate drive, current detection, temperature detection, and the like.

[0013] As shown in FIG. 3, the upper arm elements 111 to 113 and the lower arm elements 114 to 116, which are six switching elements, are bridge-connected to constitute a driver circuit 10 for driving a motor 800 as a load. The drains of the upper arm elements 111 to 113 are connected to the power supply, and the sources are connected to the drains of the corresponding lower arm elements 114 to 116. The sources of the lower arm elements 114 to 116 are connected to the ground. The gates of the upper arm elements 111 to 113 and the lower arm elements 114 to 116 are connected to a pre-driver IC180 incorporated in the control chip 18.

[0014] The connection point between the upper arm element 111 and the lower arm element 114 of the paired U phase is connected to one end side of the motor winding 801 of the U phase. The connection point between the upper arm element 112 and the lower arm element 115 of the paired V phase is connected to one end side of the motor winding 802 of the V phase. The connection point between the upper arm element 113 and the lower arm element 116 of the paired W phase is connected to one end side of the motor winding 803 of the W phase. The other end sides of the motor windings 801 to 803 are connected. Note that the motor windings 801 to 803 are not limited to Y connection and may be Δ connection.

[0015] Returning to FIGS. 1 and 2, the lead frame 20 includes lands 21 to 26. The back side of the lead frame 20 is exposed from the sealing portion 35 and is electrically connected to the wiring pattern of the substrate 90 by soldering or the like. Note that not all the lands need to be connected to the substrate 90 on the back side. Each of the lands 21 to 26 is formed integrally with or connected to the terminal 36 at the outer peripheral side of the sealing portion 35. The control chip 18 is mounted on the control land 21, and the high-side chips 11 to 13 are mounted on the power land 22.

[0016] The control chip 18 is formed in a substantially rectangular shape in plan view. Hereinafter, the direction parallel to the long side of the control chip 18 is defined as the "first direction", and the direction orthogonal to the first direction is defined as the "second direction". Also, inside the mold, the lead frame 20 side is defined as the "lower side" and the top surface side is defined as the "upper side".

[0017] The lands 21 to 25 are arranged in the order of the control land 21, the power land 22, and the three output lands 23 to 25 from one side in the second direction. The ground land 26 is provided adjacent to the power land 22 and the output land 25. The control land 21 has a ground potential, and the terminals arranged on both sides of the short side and at the end opposite to the power land 22 are used as signal terminals 364.

[0018] Power land 22 is provided adjacent to the long side of control land 21. Power land 22 abuts against the power pattern of substrate 90 on the back side and has a power potential. Also, in the first direction, power land 22 uses a terminal arranged at the end opposite to ground land 26 as power terminal 361. High-side chips 11 to 13 are arranged side by side on power land 22 such that the upper side is the source, the lower side is the drain, and the gate faces the long side of control chip 18. The drain electrodes of high-side chips 11 to 13 are connected to power land 22.

[0019] Output lands 23 to 25 are arranged side by side adjacent to power land 22 on the side opposite to control land 21. Output terminals 363 are formed at the ends of output lands 23 to 25 on the side opposite to power land 22. Output terminals 363 are connected to each phase of the motor winding via substrate wiring (not shown). A ground terminal 362 is formed at the end of ground land 26 on the side opposite to land 25.

[0020] Intermediate clips 31 to 33 are placed on high-side chips 11 to 13 respectively. Intermediate clips 31 to 33 are conductive metal plates such as copper formed in a plate shape wider than chips 11 to 16. One end side is connected to high-side chips 11 to 13 and low-side chips 14 to 16, and the other end side is connected to output lands 23 to 25. The ends of one end side of intermediate clips 31 to 33 are arranged offset so as to be on the side away from control chip 18 rather than the end side of high-side chips 11 to 13 on the control chip 18 side, so that the gate electrodes of high-side chips 11 to 13 and control chip 18 can be connected.

[0021] Above the middle clips 31 to 33, the low side chips 14 to 16 are arranged. The low side chips 14 to 16 have a drain on the lower side and a source on the upper side, and are arranged such that the gates face the long sides of the control chip 18. Thereby, the sources of the high side chips 11 to 13 and the drains of the low side chips 14 to 16 are connected by the middle clips 31 to 33. The other end sides of the middle clips 31 to 33 are bent downward and are respectively connected to the output lands 23 to 25.

[0022] The ground clip 34 is a conductive plate such as copper formed in a plate shape. The ground clip 34 covers the upper sides of the low side chips 14 to 16, is bent downward on one side in the first direction, and is connected to the ground land 26. In the electronic device 1, the drain electrodes of the high side chips 11 to 13 are connected by the power land 22 which is a common metal plate, and the source electrodes of the low side chips 14 to 16 are connected by the ground clip 34 which is a common metal plate.

[0023] The end of the ground clip 34 on the control chip 18 side is arranged to be shifted to the side away from the control chip 18 more than the ends of the low side chips 14 to 16 on the control chip 18 side so as to be able to connect the gates of the low side chips 14 to 16 and the control chip 18.

[0024] The ground clip 34 is formed wide so as to cover up to the upper side of the bent portions of the middle clips 31 to 33. By forming the area of the ground clip 34 as large as possible, the heat dissipation efficiency can be improved. On the top surface side of the ground clip 34, it is preferable to form the thickness of the sealing portion 35 thinner for the heat dissipation surface.

[0025] In the electronic device 1, a control chip 18 is provided on one side in the second direction, and chips 11 to 16 constituting the driver circuit 10 are provided on the other side. A power region Rp through which a relatively large current flows and a control region Rc through which a relatively small current flows are separately aggregated and arranged. In the power region Rp, from the bottom, a power land 22, high-side chips 11 to 13, intermediate clips 31 to 33, low-side chips 14 to 16, and a ground clip 34 are laminated in this order, forming a stack structure.

[0026] Also, the gate electrodes of chips 11 to 16 face the control chip 18 side, and they are laminated in a stepped manner with a shift so as to be connectable to the control chip 18, ensuring a non-overlapping region that does not overlap with the members provided above chips 11 to 16. Thereby, chips 11 to 16 and the control chip 18 can be connected by wire bonding using the signal line 19. Also, in the control chip 18, the connection points with the gate electrodes of chips 11 to 16 are aggregated on one side facing the chips 11 to 16 side.

[0027] In the electronic device 1, in the power region Rp, a power supply terminal 361 is provided on one side in the first direction, a ground terminal 362 is provided on the other side in the first direction, and an output terminal 363 is provided at the end on the second direction side. When viewed as a whole, power supply and ground are input in the first direction, and power related to motor drive is output in the second direction. Thereby, the wiring connecting the power supply and ground in the power region and the signal line 19 of the control chip 18 can be separated, and the influence of noise and surges can be reduced. Also, the power land 22 having a power supply potential and the ground land 26 are arranged adjacent to each other. Thereby, the loop of the power part that becomes a noise source becomes smaller, so noise can be reduced.

[0028] FIG. 4 is a diagram for explaining the parasitic inductor (hereinafter referred to as "ESL") in the driver circuit 10, where the U-phase arm is described as an example. When a large current is applied to the electronic device 1, a magnetic field is generated around it, and the part surrounded by the dashed circle becomes the ESL, and the energy accumulated here is applied to the element to cause switching loss. For example, as a reference example, when the upper arm element is arranged on one side of the control chip and the lower arm element is arranged on the other side, and the source of the upper arm element and the drain of the lower arm element are connected by the substrate wiring outside the module, the wiring length becomes long, so the ESL becomes large.

[0029] In this embodiment, the sources of the high-side chips 11 to 13 and the drains of the low-side chips 14 to 16 are connected on both sides of the intermediate clips 31 to 33. That is, the wiring length between the drain and the source indicated by A1 in FIG. 4 is the thickness of the intermediate clips 31 to 33, and the wiring length is shorter compared with the case of connecting via the substrate wiring outside the module or the like. Therefore, the ESL can be reduced.

[0030] Also, the drains of the upper arm elements 111 to 113 indicated by A2 in FIG. 4 are connected to the 3-phase common power land 22, and the sources of the lower arm elements 114 to 116 indicated by A3 are connected by the 3-phase common ground clip 34. As a result, the difference in ELS between phases disappears, so the commutation switching becomes faster and the switching loss can be reduced.

[0031] By providing the control chip 18 constituting the pre-driver IC 180 in the module and wiring the gate signal line inside the module, compared with the case of providing the gate wiring on, for example, a printed circuit board, there is no need to provide vias or the like, so the ESL can be reduced.

[0032] As described above, the electronic device 1 includes a plurality of high-side chips 11 to 13, a plurality of low-side chips 14 to 16, a power land 22, a ground clip 34, and a sealing portion 35. The high-side chips 11 to 13 incorporate upper arm elements 111 to 113 connected to the high potential side. The low-side chips 14 to 16 incorporate lower arm elements 114 to 116 connected to the low potential sides of the respective upper arm elements 111 to 113, and are connected to the paired high-side chips inside the module. Specifically, the paired U-phase high-side chip 11 and low-side chip 14 are connected, the paired V-phase high-side chip 12 and low-side chip 15 are connected, and the paired W-phase high-side chip 13 and low-side chip 16 are connected.

[0033] The power land 22, which is a power wiring member, connects the high-side chips 11 to 13 to the power potential. The ground clip 34, which is a ground wiring member, connects the low-side chips 14 to 16 to the ground potential. The sealing portion 35 integrally seals the high-side chips 11 to 13, the low-side chips 14 to 16, the power land 22, and the ground clip 34.

[0034] The ground clip 34 is shared by the plurality of low-side chips 14 to 16. Also, the power land 22 is shared by the plurality of high-side chips 11 to 13. Thereby, since the ESL of each phase is made common, the surge voltage difference and the switching loss difference between the arms can be reduced.

[0035] The power wiring member of the present embodiment is the power land 22 where the high-side chips 11 to 13 are arranged, and the power land 22 is arranged adjacent to the ground land 26 connected to the ground clip 34. Thereby, since the wiring distance between the power and the ground is shortened, the ESL can be reduced.

[0036] The intermediate connection member that connects the paired high-side chips 11 to 13 and low-side chips 14 to 16 is composed of two or fewer members. In this embodiment, the high-side chip 11, the intermediate clip 31, and the low-side chip 14 paired with the high-side chip 11 are laminated in this order, and the high-side chip 11 and the low-side chip 14 are connected on both sides of the intermediate clip 31. Also, the high-side chip 12, the intermediate clip 32, and the low-side chip 15 paired with the high-side chip 12 are laminated in this order, and the high-side chip 12 and the low-side chip 15 are connected on both sides of the intermediate clip 32. Furthermore, the high-side chip 13, the intermediate clip 33, and the low-side chip 16 paired with the high-side chip 13 are laminated in this order, and the high-side chip 13 and the low-side chip 16 are connected on both sides of the intermediate clip 33. That is, in this embodiment, the paired high-side chips 11 to 13 and low-side chips 14 to 16 are each connected by one intermediate clip 31 to 33.

[0037] By minimizing the number of intermediate connection members, the wiring length can be shortened and the ESL can be reduced. Also, by adopting a laminated structure for the high-side chips 11 to 13, the intermediate clips 31 to 33, and the low-side chips 14 to 16, the electronic device 1 can be miniaturized.

[0038] The intermediate clips 31 to 33 and the low-side chips 14 to 16 are provided on the top surface side of the high-side chips 11 to 13 and are laminated in a shifted state so that a part of the high-side chips 11 to 13 does not overlap. By laminating the intermediate clips 31 to 33 and the low-side chips 14 to 16 in a shifted manner and securing a non-overlapping region on the top surface side of the high-side chips 11 to 13, the signal lines 19 can be appropriately connected.

[0039] The electronic device 1 includes a pre-driver IC 180 that outputs drive signals for the upper arm elements 111 to 113 and the lower arm elements 114 to 116, and includes a control chip 18 sealed in a sealing portion 35. The high-side chips 11 to 13 and the low-side chips 14 to 16 are arranged on one side of the control chip 18 with their gate electrodes facing the control chip side. By incorporating the control chip 18, the number of terminals can be reduced. Also, by aggregating and arranging the high-side chips 11 to 13 and the low-side chips 14 to 16 on one side of the control chip 18, the control region Rc and the power region Rp can be separated.

[0040] (Second Embodiment) The second embodiment is shown in FIG. 5. The electronic device 2 is the same as the first embodiment in terms of the arrangement and connection of the chips 11 to 16. In FIG. 5, it is shown in a simplified manner, terminals other than signal terminals are omitted, the gate signal lines are mainly described for the signal lines, and other signal lines are omitted as appropriate. The same applies to the figures related to the embodiments described later. In this embodiment, the land 27 which is a ground land is integrally formed with a control land 271 that is adjacent to the power land 22 on the second direction side and where the control chip 18 is arranged, and a ground land 272 that is adjacent to the power land 22 on the first direction side and is connected to the ground clip 34. Even with this configuration, the same effects as the above embodiment can be achieved.

[0041] (Third Embodiment) The third embodiment is shown in FIG. 6. The electronic device 3 is the same as the first embodiment in terms of the arrangement of the chips 11 to 16. The land 28 which is the ground land in this embodiment is integrally formed with a control land 281 where the control chip 18 is arranged, and ground lands 282 and 283. The ground lands 282 and 283 are formed on both sides of the power land 22.

[0042] The ground clip 81 is provided above the lower side chips 14 to 16, bent downward on both sides in the first direction, and connected to the ground lands 282 and 283. By providing the ground lands 282 and 283 on both sides, it is possible to connect to the ground pattern of the substrate from either side, improving the degree of freedom in substrate layout. Also, the same effects as those of the above-described embodiment are achieved.

[0043] (Fourth Embodiment) The fourth embodiment is shown in FIGS. 7 to 9. In the cross-sectional view of FIG. 8, the hatching of the capacitor 93 is omitted. FIG. 9 schematically shows FIG. 7 and is upside down. The lead frame 40 of the electronic device 4 has a power land 41, output lands 42 to 44, and ground lands 45 to 47. In this embodiment, no control chip is built in, but a control chip may be built in as in the above-described embodiment. The same applies to the sixth and seventh embodiments.

[0044] The power land 41 is generally the same as the power land 22 of the above-described embodiment, and the high-side chips 11 to 13 are arranged side by side. Intermediate clips 31 to 33 are provided on the high-side chips 11 to 13, and lower-side chips 14 to 16 are stacked on the intermediate clips 31 to 33. The intermediate clips 31 to 33 are connected to the high-side chips 11 to 13 and the lower-side chips 14 to 16 on both sides of one end side, and are connected to the output lands 42 to 44 at the other end side. The stacked structure of the chips 11 to 16 is the same as that of the above-described embodiment. Also, the gate terminals GUH, GUL, GVH, GVL, GWH, GWL are assigned to the terminals on one side in the second direction.

[0045] The output lands 42 to 44 are arranged between the power land 41 and the ground lands 45 to 47 in the second direction. The output land 43 arranged in the middle in the first direction is provided with a terminal connection portion 431 extending to both sides in the first direction. The output lands 42 and 44 are provided on both sides of the output land 43 on the ground land side of the terminal connection portion 431. The output terminals 363 connected to the output lands 42 to 44 are provided on the first direction side.

[0046] The ground lands 45 to 47 are provided on the side opposite to the power land 41 with the output lands 42 to 44 interposed therebetween. That is, in the present embodiment, they are arranged in the order of the power land 41, the terminal connection portion 431 of the output land 43, the output lands 42 to 44, and the ground lands 45 to 47 from one side in the second direction. The ground terminal 362 connected to the ground lands 45 to 47 is provided on the side opposite to the gate terminal in the second direction.

[0047] The ground clip 82 has a base portion 821 and protruding portions 822 to 824. The base portion 821 is provided so as to cover the upper side of the low side chips 14 to 16 while being shifted so as not to overlap with the gate electrodes of the low side chips 14 to 16. The protruding portions 822 to 824 are bent downward and connected to the ground lands 45 to 47. The ground clip 82 of the present embodiment is provided so as to cover the upper side of the intermediate clips 31 to 33.

[0048] As shown in FIG. 8, the power land 41, which is a power supply potential, and the ground lands 45 to 47 are exposed from the sealing portion 35 on the lower side, and are electrically connected to the power supply pattern 901 and the ground pattern 902 of the substrate 90 by soldering or the like. In other words, the electronic device 4 is connected to the substrate 90 by back surface connection.

[0049] When the mounting surface on the side where the electronic device 4 of the substrate 90 is mounted is defined as the first mounting surface B1 and the mounting surface on the opposite side is defined as the second mounting surface B2, the power pattern 901 and the ground pattern 902 are formed to extend to the second mounting surface B2 side via the via 903. A capacitor 93 is connected to the second mounting surface B2 side of the power pattern 91 and the ground pattern 92. That is, the capacitor 93 is provided on the back surface of the driver circuit 10 and is connected by the common power pattern 901 and ground pattern 902. Thereby, since the wiring length between the driver circuit 10 and the capacitor 93 can be shortened, the ESL can be reduced with high efficiency. Note that, similarly in embodiments other than the present embodiment, a capacitor may be connected to the second mounting surface side of the power pattern and the ground pattern to which the electronic device is connected on the back surface.

[0050] In the present embodiment, the power land 41 and the ground lands 45 to 47 connected via the low-side chips 14 to 16 and the ground clip 82 have the surfaces in contact with the substrate 90 exposed from the sealing portion 35 and are respectively connected to the power pattern and the ground pattern of the substrate 90.

[0051] The power pattern 901 and the ground pattern 902 are formed to extend to the back surface side via the via 903 penetrating the substrate 90 and are connected to the capacitor 93. Thereby, the ESL can be reduced with high efficiency.

[0052] (Fifth Embodiment) The fifth embodiment is shown in FIG. 10. In the following embodiments, the high-side chips 11 to 13 and the low-side chips 14 to 16 are not laminated but are arranged flat. The lead frame 50 of the electronic device 5 has a power land 51, output lands 52 to 54, and a ground land 55.

[0053] In the power land 51, high-side chips 11 to 13 are arranged and are connected to drain electrodes provided on the back surfaces of the high-side chips 11 to 13. Source electrodes provided on the upper surfaces of the high-side chips 11 to 13 are connected to intermediate clips 71 to 73. The intermediate clips 71 to 73 are provided so as to cover the upper side surfaces of the high-side chips 11 to 13 in a state where the gate electrodes and the gate terminals of the high-side chips 11 to 13 can be connected, and are bent downward at one end on the side in the second direction and are connected to output lands 52 to 54.

[0054] The output lands 52 to 54 are provided adjacent to the power land 51 on the second direction side, and low-side chips 14 to 16 are arranged. Drain electrodes provided on the back surfaces of the low-side chips 14 to 16 are connected to the output lands 52 to 54. That is, the source electrodes of the high-side chips 11 to 13 and the drain electrodes of the low-side chips 14 to 16 are connected via two members, namely, the intermediate clips 71 to 73 and the output lands 52 to 54.

[0055] That is, in the present embodiment, the intermediate clips 71 to 73 and the output lands 52 to 54 are "intermediate connection members", and the number of intermediate connection members connecting the paired U-phase high-side chip 11 and low-side chip 14 is two. Similarly, the number of intermediate connection members connecting the paired V-phase high-side chip 12 and low-side chip 15 is two, and the number of intermediate connection members connecting the paired W-phase high-side chip 13 and low-side chip 15 is two.

[0056] The ground land 55 is provided adjacent to the power land 51 and the output land 52 on the first direction side. The ground clip 34 is generally the same as that in the first embodiment except that it is narrower in width than the first embodiment, covers the upper sides of the low-side chips 14 to 16, is bent downward on the ground land 55 side, and is connected to the ground land 55.

[0057] The gate electrodes of chips 11 to 16 are connected to the gate terminals at locations not covered by clips 71 to 73 and 34. In this embodiment, there is no built-in control IC in the module, and the gate terminals connected to the gate electrodes of the high-side chips 11 to 13 are provided on one side in the second direction, while the gate terminals connected to the gate electrodes of the low-side chips 14 to 16 are provided on the other side in the second direction. Even with such a configuration, the same effects as those of the above-described embodiment can be achieved.

[0058] (Sixth Embodiment, Seventh Embodiment) The sixth embodiment is shown in FIGS. 11 and 12. The lead frame 56 of the electronic device 6 is different from that of the fifth embodiment in that the ground lands 571 to 573 are provided on the opposite side of the power land 51 with the output lands 52 to 54 interposed therebetween. That is, in this embodiment, they are arranged in the order of the power land 51, the output lands 52 to 54, and the ground lands 571 to 573 from one side in the second direction.

[0059] The intermediate clips 71 to 73 are provided with cutouts 711 to 713 for connecting the gate electrodes of the high-side chips 11 to 13 to the gate terminals. The cutouts 711 to 713 are provided at the corner portions on the end side opposite to the output lands 52 to 54.

[0060] The ground clip 83 is provided above the low-side chips 14 to 16. The three protrusions formed on the ground land 571 to 573 side of the ground clip 83 are bent downward and are respectively connected to the ground lands 571 to 573. The ground clip 83 is provided with cutouts 831 and 832 so as to be able to connect the gate electrodes provided on the ground land 571 to 573 side of the low-side chips 14 to 16 to the gate terminals. The cutout 831 is provided at a position corresponding to the gate electrode of the U-phase low-side chip 14. The cutout 832 is provided at a position corresponding to the gate electrodes of the adjacent V-phase and W-phase low-side chips 15 and 16.

[0061] The electronic device 7 of the seventh embodiment shown in FIG. 13 is a modification of the sixth embodiment, in which the intermediate clips 71 to 73 are formed narrower than the high-side chips 11 to 13. The gate electrodes of the high-side chips 11 to 13 are connected to the gate terminals at the sides on the first direction side of the intermediate clips 71 to 73. Further, notches 833 to 835 for connecting the gate electrodes and the gate terminals of the low-side chips 14 to 16 are provided in the ground clip 83 for each phase.

[0062] In the sixth embodiment, the position of the low-side chip 16 of the W phase in the second direction is shifted from the low-side chips 14 and 15 of the U phase and the V phase. However, a shift that allows the source electrodes to be connected by the common ground clip 83 is allowed and is regarded as being "arranged side by side". Also, the same degree of shift is allowed for the high-side chips 11 to 13. Even with this configuration, the same effects as those of the above embodiment are achieved.

[0063] (Eighth Embodiment, Ninth Embodiment) The eighth embodiment is shown in FIG. 14, and the ninth embodiment is shown in FIG. 15. In the eighth and ninth embodiments, the chips 11 to 16 are placed flat, and the control chip 18 is built in the module.

[0064] The lead frame 60 of the electronic device 8 of the eighth embodiment has a power land 61, output lands 62 to 64, and ground lands 65 to 67. The power land 61 has element mounting portions 611 to 613 and an IC mounting portion 615. The element mounting portions 611 and 613 project from both sides in the first direction of the IC mounting portion 615, and the high-side chips 11 and 13 are arranged thereon. The element mounting portion 612 projects from the second direction side of the IC mounting portion 615, and the high-side chip 12 is arranged thereon. The drain electrodes of the high-side chips 11 to 13 are connected to the power land 61.

[0065] The control chip 18 is provided in the IC mounting portion 615. Since the back side of the element of the control chip 18 of the present embodiment is insulated, it can be arranged not only on the land of the ground potential but also on the land of the power supply potential as in the present embodiment. In embodiments other than the present embodiment, a control chip with an insulated back side may also be used.

[0066] The output land 62 is provided adjacent to the second direction side of the element mounting portion 611. The output land 63 is provided on the second direction side of the IC mounting portion 615 and between the output land 62 and the element mounting portion 612. The output land 63 is provided adjacent to the second direction side of the element mounting portion 613. Therefore, the output lands 62 to 64 and the element mounting portion 612 are arranged in the order of the output land 62, the output land 63, the element mounting portion 612, and the output land 64 from one side in the first direction.

[0067] Low-side chips 14 to 16 are provided on the output lands 62 to 64 and are connected to the drain electrodes of the low-side chips 14 to 16. The intermediate clips 71 to 73 connect the sources of the high-side chips 11 to 13 and the output lands 62 to 64. The ground clip 84 connects the sources of the low-side chips 14 to 16 and the ground lands 65 to 67. The ground clip 84 is formed in a substantially rectangular shape, and a notch 841 is provided at a location where the intermediate clip 72 is provided.

[0068] The chips 11 to 16 are arranged so as to surround three sides of the control chip 18 as a whole. Also, the clips 71 to 73 and 84 are provided on the chips 11 to 16 so as to be shifted so that the control chip 18 sides of the chips 11 to 16 do not overlap, so that various signal lines including the gate signal line connecting the gate electrode and the control chip 18 can be connected.

[0069] The electronic device 9 of the ninth embodiment shown in FIG. 15 is generally the same as the seventh embodiment, except that the shape of the ground clip 85 is different. The ground clip 85 has a ground connection portion 851 connected to the ground lands 65 to 67, and protruding portions 852 to 854 protruding from the ground connection portion 851 toward the second direction side. The protruding portions 852 to 853 are provided at positions where the low side chips 14 to 16 are arranged, and are connected to the source electrodes of the low side chips 14 to 16 on the lower side surface. In FIG. 14, the description of the terminals on the second direction side, the terminals on the ground side, and the signal lines such as gate connection is omitted. Even with this configuration, the same effects as those of the above embodiments can be obtained.

[0070] In the embodiment, the power lands 22, 41, 51, 61 correspond to the "power wiring member", the ground clips 34, 81 to 85 correspond to the "ground wiring member", the intermediate clips 31 to 33, 71 to 73, and the output lands 52 to 54 correspond to the "intermediate connection member". Also, the capacitor 93 corresponds to the "noise prevention element".

[0071] (Other embodiments) In the above embodiment, the low side chips are connected by a ground clip which is a plate-shaped metal plate. In other embodiments, the member for connecting the source of the low potential side element is not limited to a metal plate, and ribbon bonding or aluminum bonding may be used. The same applies to the member for connecting the high side chips.

[0072] In the above embodiment, the ground clip is sealed by the sealing portion 35. In other embodiments, as shown in FIG. 16, the ground clip may be exposed from the top surface side of the sealing portion so as to directly dissipate heat to the heat dissipation housing. That is, the ground clip is a metal plate connected to the top surface side of the low side chip, and the surface on the side opposite to the low side chip is exposed from the sealing portion. Thereby, the heat dissipation efficiency can be improved. Although the electronic device 1 of the first embodiment is illustrated in FIG. 16, the top surface side of the ground clip may be exposed from the sealing portion in embodiments other than the first embodiment.

[0073] In the above embodiment, the noise prevention element is a capacitor. In other embodiments, the noise prevention element may be other than a capacitor, such as a snubber circuit, as long as it is an electronic component capable of reducing noise.

[0074] In the present disclosure, "the electronic device according to any one of Items 1 to 5, wherein the intermediate connection member (31 to 33, 51 to 53, 71 to 73) connecting the paired high-side chip and low-side chip is composed of two or fewer members."; "the electronic device according to any one of Items 1 to 8, wherein the ground wiring member is a metal plate connected to the top surface side of the low-side chip and is exposed on the top surface side of the sealing portion."; "the electronic device according to any one of Items 1 to 9, further including a driver IC (180) that outputs drive signals for the upper arm element and the lower arm element, and further including a control chip (18) sealed in the sealing portion, wherein the high-side chip and the low-side chip are arranged on one side of the control chip with the gate electrode to which the drive signal is input facing the control chip side." may also be applicable.

[0075] As described above, the present invention is not limited to the above embodiments, and can be implemented in various forms without departing from the spirit of the invention.

Explanation of Reference Numerals

[0076] 1 to 9... Electronic device 11 to 13... High-side chip 111 to 113... Upper arm element 14 to 16... Low-side chip 114 to 116... Lower arm element 22, 41, 51, 61... Power land (power wiring member) 23 to 24, 42 to 44, 52 to 54, 62 to 64... Output land 26 to 28, 45 to 47, 55, 571 to 573, 65 to 67... Ground land 31 to 33, 71 to 73... Intermediate clip (intermediate connection member) 34, 81 to 85... Ground clip (ground wiring member) 35 ··· Sealing part

Claims

1. Multiple high-side chips (11-13) containing upper arm elements (111-113) connected to the high-potential side, Each upper arm element has a lower arm element (114-116) connected to the low-potential side, and a pair of low-side chips (14-16) are connected to the high-side chips inside the module. Power supply wiring members (22, 41, 51, 61) that connect the high-side chip to the power supply potential, Ground wiring members (34, 81-85) that connect the low-side chip to the ground potential, A sealing portion (35) that integrally seals the high-side chip, the low-side chip, the power wiring member, and the ground wiring member, Equipped with, The aforementioned ground wiring member is shared by multiple low-side chips. The power wiring member is a power land on which the high-side chip is placed, The power lands and the ground lands (26-28, 45-47, 55, 571-573, 65-67) connected to the low-side chip via the ground wiring member have surfaces that contact the substrate (90) that are exposed from the sealing portion and are connected to the power pattern (901) and ground pattern (902) of the substrate, respectively. The power supply pattern and the ground pattern are formed extending to the back side via vias (903) that penetrate the substrate, and are connected to a noise suppression element (93) in this electronic device.

2. Multiple high-side chips (11-13) containing upper arm elements (111-113) connected to the high-potential side, Each upper arm element has a lower arm element (114-116) connected to the low-potential side, and a pair of low-side chips (14-16) are connected to the high-side chips inside the module. Power supply wiring members (22, 41, 51, 61) that connect the high-side chip to the power supply potential, Ground wiring members (34, 81-85) that connect the low-side chip to the ground potential, A sealing portion (35) that integrally seals the high-side chip, the low-side chip, the power supply wiring member, and the ground wiring member, Equipped with, The aforementioned ground wiring member is shared by multiple low-side chips. An electronic device in which an intermediate connecting member (31-33, 51-53, 71-73) connecting a pair of high-side chips and low-side chips is composed of two or fewer members.

3. The electronic device according to claim 2, wherein the high-side chip, the intermediate connecting member, and the low-side chip paired with the high-side chip are stacked in that order, and the high-side chip and the low-side chip are connected on both sides of the intermediate connecting member.

4. The electronic device according to claim 3, wherein the intermediate connecting member and the low-side chip are provided on the top surface side of the high-side chip, and are stacked in a state in which a portion of the top surface side of the high-side chip does not overlap.

5. Multiple high-side chips (11-13) containing upper arm elements (111-113) connected to the high-potential side, Each upper arm element has a lower arm element (114-116) connected to the low-potential side, and a pair of low-side chips (14-16) are connected to the high-side chips inside the module. Power supply wiring members (22, 41, 51, 61) that connect the high-side chip to the power supply potential, Ground wiring members (34, 81-85) that connect the low-side chip to the ground potential, A sealing portion (35) that integrally seals the high-side chip, the low-side chip, the power supply wiring member, and the ground wiring member, Equipped with, The aforementioned ground wiring member is shared by multiple low-side chips. The ground wiring member is a metal plate connected to the top surface of the low-side chip, and the side opposite to the low-side chip is exposed from the sealing portion in this electronic device.

6. The electronic device according to claim 1, 2, or 5, wherein the power supply wiring member is shared by a plurality of high-side chips.

7. The electronic device according to claim 2 or 5, wherein the power supply wiring member is a power land on which the high-side chip is arranged, and is arranged adjacent to a ground land (26-28, 55) connected to the ground wiring member.

8. The system includes a pre-driver IC (180) that outputs drive signals for the upper arm element and the lower arm element, and further comprises a control chip (18) that is sealed in the sealing portion. The electronic device according to claim 1, 2, or 5, wherein the high-side chip and the low-side chip are arranged on one side of the control chip such that the gate electrodes to which the drive signal is input face the control chip side.

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