Power conversion device

Abstract

To provide a power conversion device capable of identifying a location where phase interruption occurs.SOLUTION: A power conversion device comprises: a multi-phase transformer which converts AC power into multi-phase AC power; a rectification section which converts the multi-phase AC power into DC power; and a phase interruption detection section which, in a case where it is detected based on reduction of an output voltage of the rectification section that phase interruption occurs, identifies a location where the phase interruption occurs based on a time in which the output voltage is reduced.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a power conversion device.

Background Art

[0002] A power conversion device uses a polyphase transformer and a rectifier to convert an AC voltage into a DC voltage. When a phase loss occurs in the polyphase transformer, the ripple component of the DC output voltage increases. If the operation continues with the phase loss, the current to the phases other than the phase with the phase loss increases, resulting in damage to the diodes in the rectifier circuit.

[0003] Regarding power conversion devices, there is known a technique that enables the generation of DC power without using an AC / DC converter and further enables miniaturization of a polyphase transformer (see, for example, Patent Document 1). According to this technique, the polyphase transformer has a first winding constituting a primary side winding and windings generating four different three-phase phases of a second to a fifth winding constituting a secondary side winding. All the windings are wound around a common iron core. The second to fifth windings are all star-connected. The third winding is wound around the iron core with 0.73 times the number of turns of the second winding and with the polarity reversed with respect to the second winding. The neutral points of the second winding and the third winding are connected to each other. The fourth winding and the fifth winding are branched from a common predetermined portion in the middle of the second winding and are generated. Each of the second to fifth windings outputs three-phase power of different phases and outputs a polyphase AC voltage.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a power conversion device, when one-phase open-phase occurs in the output circuit of a polyphase transformer or in a rectifying section, the ripple of the DC output voltage from the rectifying section is missing by one, and an excessive current flows in other phases to compensate for the missing phase. For this reason, in the power conversion device, there are cases where a diode generates heat and is damaged or an electric circuit generates heat. Causes of open-phase include failures of a polyphase transformer, connections between the polyphase transformer and a rectifying circuit, diodes included in the rectifying circuit, etc. However, since there are many electric circuits in these locations, it is difficult to identify the cause. An object of the present invention is to provide a power conversion device capable of identifying a location where open-phase has occurred.

Means for Solving the Problem

[0006] (1) One aspect of the present invention is a power conversion device including a polyphase transformer that converts AC power into polyphase AC power, a rectifying section that converts the polyphase AC power into DC power, and an open-phase detection section that identifies a location where open-phase has occurred based on the time when the output voltage has dropped when it is detected that open-phase has occurred based on a decrease in the output voltage of the rectifying section. (2) One aspect of the present invention is the power conversion device according to (1) above, wherein the open-phase detection section includes a line voltage phase synchronization section that synchronizes the phases of line voltages input to the polyphase transformer, and an open-phase location identification section that identifies a location where open-phase has occurred based on the time required until the output voltage drops, with reference to the line voltages synchronized by the line voltage phase synchronization section. (3) One aspect of the present invention is the power conversion device according to (1) above, wherein the open-phase detection section includes a line voltage phase synchronization section that synchronizes the phases of line voltages input to the polyphase transformer, and an open-phase location identification section that identifies a location where open-phase has occurred based on the time from when the output voltage has dropped until the next reference of the line voltages synchronized by the line voltage phase synchronization section. (4) One aspect of the present invention is the power conversion device according to any one of (1) to (3) above, wherein the open-phase detection unit includes an average value derivation unit that derives an average value of the output voltage based on the output voltage of the rectification unit, a threshold value derivation unit that derives a threshold value based on the average value derived by the average value derivation unit, and a determination unit that determines whether an open-phase has occurred based on the output voltage of the rectification unit and the threshold value. (5) One aspect of the present invention is the power conversion device according to (4) above, further comprising a circuit breaker that cuts off the AC power input to the polyphase transformer, and a drive unit that operates the circuit breaker when it is determined by the determination unit that an open-phase has occurred. (6) One aspect of the present invention is the power conversion device according to (4) above, further comprising an alarm unit that sounds an alarm when it is determined by the determination unit that an open-phase has occurred.

Advantages of the Invention

[0007] According to the present invention, it is possible to provide a power conversion device capable of identifying the location where an open-phase has occurred.

Brief Description of the Drawings

[0008]

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Mode for Carrying Out the Invention

[0009] Next, the power conversion device of the present embodiment will be described with reference to the drawings. The embodiments described below are merely examples, and the embodiments to which the present invention is applied are not limited to the following embodiments. In all the drawings for explaining the embodiments, those having the same function are denoted by the same reference numerals, and repeated explanations are omitted. In addition, "based on XX" as used in the present application means "based on at least XX", and includes cases where it is based on another element in addition to XX. Also, "based on XX" is not limited to the case where XX is directly used, and includes cases where it is based on something obtained by performing operations or processing on XX. "XX" is an arbitrary element (for example, arbitrary information).

[0010] (Embodiment) (Power Conversion Device) FIG. 1 is a schematic configuration diagram showing an example of the power conversion device 1 according to the present embodiment. The power conversion device 1 includes a polyphase transformer 3 that converts AC power into polyphase AC power, a rectifying unit 4 that converts the polyphase AC power into DC power, a phase loss detection unit 100 that detects that a phase loss has occurred based on the output voltage of the rectifying unit 4 and specifies the location where the phase loss has occurred when it is detected that a phase loss has occurred, and a circuit breaker 2 that shuts off the voltage input to the polyphase transformer 3 when it is detected by the phase loss detection unit 100 that a phase loss has occurred.

[0011] An example of the power conversion device 1 receives 6600V high-voltage three-phase AC power received from a high-voltage three-phase power source, converts it into low-voltage AC power of a specific voltage such as 380V, and converts the converted low-voltage AC power into DC power and outputs it. Hereinafter, the case where high-voltage three-phase AC power is input to the power conversion device 1 will be described, but it is not limited to this example. For example, it can also be applied when low-voltage three-phase AC power is input to the power conversion device 1. An example of the polyphase transformer 3 is a 12-phase transformer. The 12-phase transformer outputs a low-voltage 12-phase voltage. The polyphase transformer 3 includes three-phase AC terminals on the input side and polyphase AC terminals on the output side.

[0012] FIGS. 2 to 3 are diagrams showing an example of the specific configuration of the 12-phase transformer 3. As shown in FIG. 2, the 12-phase transformer 3 includes a first winding 11 that constitutes the primary winding L1 and four windings (a second winding 12, a third winding 13, a fourth winding 14, and a fifth winding 15) that constitute the secondary winding L2. Each winding has three winding portions (11a to 11c, 12a to 12c, 13a to 13c, 14a to 14c, 15a to 15c) corresponding to the three-phase power input.

[0013] The first winding 11 may be either delta-connected or star-connected. Here, the case of star connection is shown. High-voltage three-phase AC power is connected to the three terminals (Rin, Sin, Tin). The second to fifth windings 12, 13, 14, and 15 are all star-connected. However, the fourth winding 14 and the fifth winding 15 are not star-connected in a complete form. Hereinafter, the three phases will be described as the R phase, the S phase, and the T phase.

[0014] The secondary side of the 12-phase transformer 3 has output terminals R1, S1, T1 of the second winding 12, output terminals R2, S2, T2 of the third winding 13, output terminals R3, S3, T3 of the fourth winding 14, and output terminals R4, S4, T4 of the fifth winding 15, and is provided with a total of 12 terminals. The star-connected neutral points Q of the second winding 12 and the third winding 13 are connected to each other. The third winding 13 is wound around the iron core 8 so that the polarity is reversed with respect to the second winding 12, and is formed with 0.73 times the number of turns of the second winding. In addition, the fourth winding 14 and the fifth winding 15 are formed by branching from the same point in the middle of the second winding 12, and the fourth winding 14 and the fifth winding 15 share the neutral point Q of the second winding 12.

[0015] The fourth winding 14 and the fifth winding 15 are wound around the iron core 8 as specifically described below. For the fourth winding, the T-phase winding 14a is branched off from the middle of the R-phase winding 12a of the second winding 12 and wound around the leg core 8c common to the primary-side T-phase. And its tip is the output terminal T3. The R-phase winding 14b is branched off from the middle of the S-phase winding 12b of the second winding 12 and wound around the leg core 8a common to the R-phase of the first winding 11. And its tip is the output terminal R3. Also, the S-phase winding 14c is branched off from the middle of the T-phase winding 12c of the second winding 12 and wound around the leg core 8b common to the primary-side S-phase. And its tip is the output terminal S3.

[0016] For the fifth winding 15, the S-phase winding 15a is branched off from the middle of the R-phase winding 12a of the second winding 12, which is the same part as the fourth winding 14, and wound around the leg core 8c common to the S-phase of the first winding 11. And its tip is the output terminal S4. The T-phase winding 15b is branched off from the middle of the S-phase winding 12b of the second winding 12, which is the same part as the fourth winding 14, and wound around the leg core 8c common to the T-phase of the first winding 11. And its tip is the output terminal T4. Also, the R-phase winding 15c is branched off from the middle of the T-phase winding 12c of the second winding 12, which is the same part as the fourth winding 14, and wound around the leg core 8a common to the R-phase of the first winding 11. And its tip is the output terminal R4.

[0017] Figure 3 is a vector explanatory diagram of the individual windings of the secondary winding L2, showing each phase with reference to the R1 phase of the second winding 12. As shown in this Figure 3, the three-phase windings 12a, 12b, 12c of the second winding 12 output voltages having a phase difference of 120 degrees each from the output terminals R1, S1, T1, similar to the three-phase power input. The phases of the windings 13a, 13b, and 13c of the third winding 13 show polarities opposite to those of the second winding 12 as described above, and the phases of the output terminals R2, S2, and T2 have a phase difference of 180 degrees with respect to the respective phases of R1, S1, and T1 of the second winding 12. Note that the number of turns of the third winding 13 with respect to the second winding 12 is 0.73 times (√3 - 1 times).

[0018] Also, the phases of the output terminals R3, S3, and T3 of the windings 14a, 14b, and 14c drawn from the second winding 12 of the fourth winding 14 generate voltages in the same phase as the respective phases of the third winding 13. Further, the phases of the output terminals R4, S4, and T4 of the windings 15a, 15b, and 15c drawn from the second winding 12 of the fifth winding 15 generate voltages in the same phase as the output terminals R2, S2, and T2 of the corresponding phases of the third winding 13, similar to the fourth winding 14. Returning to FIG. 1, the description will continue.

[0019] An example of the rectifying section 4 is configured to include four three-phase full-wave rectifier circuits 4-1 to 4-4. The four three-phase full-wave rectifier circuits 4-1 to 4-4 generate a set of DC output voltages.

[0020] The three-phase full-wave rectifier 4-1 includes six diodes D11 to D16. The cathodes of the diode D11, the diode D13, and the diode D15 are connected to the positive-side DC circuit 4-1P, and the anodes of the diode D12, the diode D14, and the diode D16 are connected to the negative-side DC circuit 4-1N. Also, the output terminals R1, S1, and T1 of the second winding 12 of the polyphase transformer 3 are respectively connected to the connection points between the anode of the diode D11 and the cathode of the diode D12, the connection point between the anode of the diode D13 and the cathode of the diode D14, and the connection point between the anode of the diode D15 and the cathode of the diode D16. The three-phase voltages of the three-phase output voltages input from the output terminals R1, S1, and T1 of the polyphase transformer 3 to the three-phase full-wave rectifier 4-1 are respectively rectified by the six diodes D11 to D16.

[0021] The three-phase full-wave rectifier 4-2 includes six diodes D21 to D26. The cathodes of diode D21, diode D23, and diode D25 are connected to the positive-side DC circuit 4-2P, and the anodes of diode D22, diode D24, and diode D26 are connected to the negative-side DC circuit 4-2N. Also, the output terminals R2, S2, T2 of the third winding 13 of the polyphase transformer 3 are respectively connected to the connection point between the anode of diode D21 and the cathode of diode D22, the connection point between the anode of diode D23 and the cathode of diode D24, and the connection point between the anode of diode D25 and the cathode of diode D26. The three-phase voltages of the three-phase output voltage input from the output terminals R2, S2, T2 of the polyphase transformer 3 to the three-phase full-wave rectifier 4-2 are respectively rectified by the six diodes D21 to D26.

[0022] The three-phase full-wave rectifier 4-3 includes six diodes D31 to D36. The cathodes of diode D31, diode D33, and diode D35 are connected to the positive-side DC circuit 4-3P, and the anodes of diode D32, diode D34, and diode D36 are connected to the negative-side DC circuit 4-3N. Also, the output terminals R3, S3, T3 of the fourth winding 14 of the polyphase transformer 3 are respectively connected to the connection point between the anode of diode D31 and the cathode of diode D32, the connection point between the anode of diode D33 and the cathode of diode D34, and the connection point between the anode of diode D35 and the cathode of diode D36. The three-phase voltages of the three-phase output voltage input from the output terminals R3, S3, T3 of the polyphase transformer 3 to the three-phase full-wave rectifier 4-3 are respectively rectified by the six diodes D31 to D36.

[0023] The three-phase full-wave rectifier 4-4 includes six diodes D41 to D46. The cathodes of diode D41, diode D43, and diode D45 are connected to the positive-side DC circuit 4-4P, and the anodes of diode D42, diode D44, and diode D46 are connected to the negative-side DC circuit 4-4N. Also, the output terminals R4, S4, and T4 of the fifth winding 15 of the polyphase transformer 3 are connected to the connection point between the anode of the diode D41 and the cathode of the diode D42, the connection point between the anode of the diode D43 and the cathode of the diode D44, and the connection point between the anode of the diode D45 and the cathode of the diode D46, respectively. The three-phase voltages of the three-phase output voltage input from the output terminals R4, S4, and T4 of the polyphase transformer 3 to the three-phase full-wave rectifier 4-4 are rectified by the six diodes D41 to D46, respectively. The three-phase full-wave rectifier 4-1, the three-phase full-wave rectifier 4-2, the three-phase full-wave rectifier 4-3, and the three-phase full-wave rectifier 4-4 are connected in parallel with each other.

[0024] A set of DC voltages generated by each of the four three-phase full-wave rectifier circuits 4-1 to 4-4 are output to a DC circuit M1 including two output lines and input to the phase failure detection unit 100. The phase failure detection unit 100 includes a voltage detection unit 101, an AD (Analog-to-Digital) conversion unit 102, a control unit 103, an inter-phase voltage synchronization unit 104, a timer measurement unit 105, and a drive unit 106.

[0025] The voltage detection unit 101 is connected to the DC circuit M1 and detects the DC voltage waveform between the DC circuits M1. Specifically, the voltage detection unit 101 detects the DC voltage waveform between the DC circuits M1 in synchronization with the input voltage phase signal output by the inter-phase voltage synchronization unit 104 to synchronize the phase of the inter-phase voltage. FIG. 4 is a diagram showing an example of the DC voltage waveform detected by the voltage detection unit 101 of the power conversion device 1 according to the present embodiment. In FIG. 4, the horizontal axis represents time [s], and the vertical axis represents the output voltage [V]. For example, the voltage detection unit 101 detects a full-wave rectified waveform (DC voltage waveform) of the low-voltage 12 phases output by the 12-phase transformer. The full-wave rectified waveform becomes the waveform of the ripple voltage obtained by rectifying the AC voltage with a diode. The full-wave rectified waveform is not constant, and minute voltage fluctuations occur. The magnitude of this voltage fluctuation is called the ripple voltage. In an example shown in FIG. 4, the power supply frequency is 50 Hz, and the power supply voltage is 269 Vrms. The voltage detection unit 101 detects a voltage that outputs 380 V in DC from the voltage waveform.

[0026] FIGS. 5A and 5B are diagrams showing an example of the voltage waveform detected by the voltage detection unit 101 of the power conversion device 1 according to the present embodiment. In FIGS. 5A and 5B, the horizontal axis represents time [s], and the vertical axis represents the output voltage [V]. FIG. 5A is an enlarged view of part A in FIG. 4. FIG. 5B shows an example of the DC voltage waveform detected by the voltage detection unit 101 when a phase failure occurs. As shown in FIG. 5B, when a phase failure occurs, a portion where the DC voltage waveform detected by the voltage detection unit 101 decreases at a predetermined period can be seen. As shown in FIGS. 5A and 5B, it can be understood that the DC voltage waveform detected by the voltage detection unit 101 changes periodically. In an example shown in FIGS. 5A and 5B, the period is 0.7 ms. Returning to FIG. 1, the description will continue.

[0027] The AD conversion unit 102 is connected to the voltage detection unit 101. The AD conversion unit 102 acquires the voltage waveform between the DC circuits M1 detected by the voltage detection unit 101. Based on the acquired voltage waveform, the AD conversion unit 102 converts an analog signal into a digital signal at a predetermined measurement period. The AD conversion unit 102 outputs the voltage value obtained by converting the analog signal into a digital signal to the control unit 103. The control unit 103 is connected to the voltage detection unit 101, the line voltage phase synchronization unit 104, and the AD conversion unit 102. The control unit 103 acquires the DC voltage waveform from the voltage detection unit 101, acquires the input voltage phase signal from the line voltage phase synchronization unit 104, and acquires the digital signal from the AD conversion unit 102. The control unit 103 determines whether or not an open phase has occurred based on the DC voltage waveform in synchronization with the acquired input voltage phase signal. When an open phase occurs, the control unit 103 outputs a high-level signal to the drive unit 106. When no open phase occurs, the control unit 103 outputs a low-level signal to the drive unit 106. Further, when it is determined that an open phase has occurred, the control unit 103 specifies the location where the open phase has occurred. Details of the control unit 103 will be described later.

[0028] The line voltage phase synchronization unit 104 is connected to the Rin terminal and the Sin terminal among the three terminals of the first winding 11, namely, the Rin terminal, the Sin terminal, and the Tin terminal. Further, the line voltage phase synchronization unit 104 is connected to the voltage detection unit 101 and the control unit 103. The line voltage phase synchronization unit 104 detects the intersection point where the voltage difference between the R phase and the S phase becomes 0, and sets the phase of this intersection point as 0° (reference). The line voltage phase synchronization unit 104 outputs the input voltage phase signal to the voltage detection unit 101 and the control unit 103 in order to synchronize the phase of the line voltage.

[0029] FIG. 6A is a diagram showing an example of the input voltage to the polyphase transformer 3 of the power conversion device 1 according to the present embodiment. In FIG. 6A, the horizontal axis is the phase [°], and the vertical axis is the voltage [V]. FIG. 6A shows the line voltage (R-S) between the R phase and the S phase, the line voltage (S-T) between the S phase and the T phase, and the line voltage (T-R) between the T phase and the R phase. The phase of the intersection point where the voltage difference between the R phase and the S phase becomes 0 is 0°. The phase differences between the line voltage between the R phase and the S phase, the line voltage between the S phase and the T phase, and the line voltage between the T phase and the R phase are each 120 degrees.

[0030] FIG. 6B is a diagram showing an example of an input voltage phase signal to the polyphase transformer 3 of the power conversion device 1 according to the present embodiment. In FIG. 6B, the horizontal axis represents the phase [°], and the vertical axis represents the input voltage phase signal. FIG. 6B is the input voltage phase signal corresponding to the input voltage shown in FIG. 6A. The input voltage phase signal is at a high level when the line voltage between the R-phase voltage and the S-phase voltage is positive, and at a low level when the correlation voltage between the R-phase voltage and the S-phase voltage is negative.

[0031] FIG. 7 is a diagram showing an example of the output voltage waveform of the polyphase transformer 3 of the power conversion device 1 according to the present embodiment. In FIG. 7, the horizontal axis represents the phase [°], and the vertical axis represents the voltage [V]. The phase of the intersection point where the voltage difference between the R-phase and the S-phase becomes 0 is 0°. In FIG. 7, among a plurality of output terminals, the output voltage waveforms between output terminal T1 and output terminal T4 (T1 - T4), between output terminal T1 and output terminal T2 (T1 - T2), between output terminal T1 and output terminal T3 (T1 - T3), and between output terminal T1 and output terminal R1 (T1 - R1) are shown.

[0032] Furthermore, in FIG. 7, the output voltage waveforms between output terminal S1 and output terminal S4 (S1 - S4), between output terminal S1 and output terminal S2 (S1 - S2), between output terminal S1 and output terminal S3 (S1 - S3), and between output terminal S1 and output terminal T1 (S1 - T1) are shown. Furthermore, in FIG. 7, the output voltage waveforms between output terminal R1 and output terminal R4 (R1 - R4), between output terminal R1 and output terminal R2 (R1 - R2), between output terminal R1 and output terminal R3 (R1 - R3), and between output terminal R1 and output terminal S1 (R1 - S1) are shown.

[0033] FIG. 8 is a diagram showing an example of a DC voltage waveform output from the rectifying unit 4 of the power conversion device 1 according to the present embodiment. In FIG. 8, the horizontal axis represents the phase [°], and the vertical axis represents the voltage [V]. The phase of the intersection point where the voltage difference between the R phase and the S phase becomes 0 is 0°. In FIG. 8, among a plurality of output voltages, the DC voltage waveform (T1-T4) after the output voltage between the output terminal T1 and the output terminal T4 is full-wave rectified by the rectifying unit 4, the DC voltage waveform (T1-T2) after the output voltage between the output terminal T1 and the output terminal T2 is full-wave rectified by the rectifying unit 4, the DC voltage waveform (T1-T3) after the output voltage between the output terminal T1 and the output terminal T3 is full-wave rectified by the rectifying unit 4, and the DC voltage waveform (T1-R1) after the output voltage between the output terminal T1 and the output terminal R1 is full-wave rectified by the rectifying unit 4 are shown.

[0034] Furthermore, in FIG. 8, the DC voltage waveform (S1-S4) after the output voltage between the output terminal S1 and the output terminal S4 is full-wave rectified by the rectifying unit 4, the DC voltage waveform (S1-S2) after the output voltage between the output terminal S1 and the output terminal S2 is full-wave rectified by the rectifying unit 4, the DC voltage waveform (S1-S3) after the output voltage between the output terminal S1 and the output terminal S3 is full-wave rectified by the rectifying unit 4, and the DC voltage waveform (S1-T1) after the output voltage between the output terminal S1 and the output terminal T1 is full-wave rectified by the rectifying unit 4 are shown. Furthermore, in FIG. 8, the DC voltage waveform (R1-R4) after the output voltage between the output terminal R1 and the output terminal R4 is full-wave rectified by the rectifying unit 4, the DC voltage waveform (R1-R2) after the output voltage between the output terminal R1 and the output terminal R2 is full-wave rectified by the rectifying unit 4, the DC voltage waveform (R1-R3) after the output voltage between the output terminal R1 and the output terminal R3 is full-wave rectified by the rectifying unit 4, and the DC voltage waveform (R1-S1) after the output voltage between the output terminal R1 and the output terminal S1 is full-wave rectified by the rectifying unit 4 are shown. Returning to FIG. 1, the description will be continued.

[0035] The timer measurement unit 105 is connected to the control unit 103. The timer measurement unit 105 is turned on and off by the control unit 103. When the control unit 103 starts measuring the output voltage based on the input voltage phase signal, the control unit 103 turns on the timer measurement unit 105, and when it detects a decrease in the output voltage, it turns it off. That is, the timer measurement unit 105 measures the time from the start of the output voltage measurement to the decrease in the output voltage.

[0036] The drive unit 106 is connected to the control unit 103. The drive unit 106 cuts off the voltage input to the polyphase transformer 3 in the cutoff unit 2 based on the signal output by the control unit 103. When a high-level signal is input from the control unit 103, the drive unit 106 cuts off the voltage input to the polyphase transformer 3 in the cutoff unit 2, and when a low-level signal is input from the control unit 103, it does not cut off the voltage input to the polyphase transformer 3 in the cutoff unit 2. An example of the cutoff unit 2 is an electric vacuum circuit breaker (VCB) and a shunt type MCB (Miniature Circuit Breaker). The electric vacuum circuit breaker is used when the input voltage is high, and the shunt type MCB is used when the input voltage is low.

[0037] The voltage detection unit 101, the AD conversion unit 102, the control unit 103, the line voltage phase synchronization unit 104, the timer measurement unit 105, and the drive unit 106 are realized, for example, by a hardware processor such as a CPU (Central Processing Unit) executing a computer program (software) stored in a storage unit (not shown). Also, some or all of these functional units may be realized by hardware (including a circuit unit; circuitry) such as an LSI (Large Scale Integration), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a GPU (Graphics Processing Unit), or may be realized by the cooperation of software and hardware.

[0038] The details of the control unit 103 will be described. FIG. 9 is a diagram showing an example of the control unit 103 of the power conversion device 1 according to the present embodiment. The control unit 103 includes an average value derivation unit 103-1, a voltage level adjustment unit 103-2, a comparison unit 103-3, an open-phase location identification unit 103-4, a signal holding unit 103-5, and a holding release unit 103-6.

[0039] The average value derivation unit 103-1 is connected to the AD conversion unit 102. The average value derivation unit 103-1 derives the average value of the voltage values based on the voltage values output by the AD conversion unit 102. The average value derivation unit 103-1 derives, for example, the average value of the voltage for at least one cycle (e.g., 0.7 ms). Hereinafter, as an example, the case where the average value derivation unit 103-1 derives the average value of the voltage every cycle will be continued to be described.

[0040] Specifically, the period during which one diode of the rectifying unit 4 is conducting is set as one measurement range. The voltage detection unit 101 detects (measures) the output voltage up to 0.7 ms, which is the period for deriving the average value, at a measurement period of 0.1 ms. The average value derivation unit 103-1 acquires the voltage value from the AD conversion unit 102 0.1 ms after the voltage detection unit 101 detects (measures) the output voltage. Thereafter, the average value derivation unit 103-1 acquires the voltage value every 0.1 ms until 0.7 ms, which is the period for deriving the average value, elapses. When 0.7 ms has elapsed, the acquisition of one set of measurement values ends. The average value derivation unit 103-1 derives the average value of the voltage according to Equation (1). Average value of voltage = Sum of measurement values / Number of measurements × Measurement period (1)

[0041] The voltage level adjustment unit 103-2 is connected to the average value derivation unit 103-1. The voltage level adjustment unit 103-2 acquires the average value of the voltage values from the average value derivation unit 103-1, and obtains the voltage threshold by reducing the voltage level of the acquired average value of the voltage values. For example, the voltage level adjustment unit 103-2 obtains the voltage threshold by reducing the voltage level of the average value of the voltage by about 10% to 40%. Further, the voltage level adjustment unit 103-2 may obtain the voltage threshold by reducing the voltage level of the average value of the voltage by about 10% to 30%. Thus, even when the AC voltage input to the polyphase transformer 3 fluctuates and the DC output voltage from the rectifying unit 4 fluctuates, the threshold fluctuates in accordance with the fluctuation. Therefore, the detection accuracy of the open phase can be improved as compared with the case where the threshold is fixed. Here, as an example, the case where the voltage level adjustment unit 103-2 obtains the voltage threshold by reducing the voltage level of the average value of the voltage by 20% will be continued to be described.

[0042] The comparison unit 103-3 is connected to the AD conversion unit 102 and the voltage level adjustment unit 103-2. The comparison unit 103-3 acquires the voltage value from the AD conversion unit 102 and acquires the voltage threshold from the voltage level adjustment unit 103-2. Here, the voltage value acquired by the comparison unit 103-3 is detected by the voltage detection unit 101 after the measurement value used for deriving the voltage threshold. For example, the voltage value acquired by the comparison unit 103-3 may be detected by the voltage detection unit 101 immediately after the measurement value used for deriving the voltage threshold.

[0043] The comparison unit 103-3 compares the acquired voltage value with the voltage threshold, and when the voltage value is less than the voltage threshold, outputs a high-level signal to the signal holding unit 103-5 and the open phase location specifying unit 103-4, and when the voltage value is greater than or equal to the voltage threshold, outputs a low-level signal to the signal holding unit 103-5 and the open phase location specifying unit 103-4. For example, when the voltage waveform as shown in FIG. 5A is obtained, the comparison unit 103-3 outputs a low-level signal (for example, "0") to the signal holding unit 103-5 and the open phase location specifying unit 103-4 because the voltage value is greater than or equal to the voltage threshold. Further, for example, when the voltage waveform as shown in FIG. 5B is obtained, the comparison unit 103-3 outputs a high-level signal (for example, "1") to the open phase location specifying unit 103-4 and the signal holding unit 103-5 because the voltage value is less than the voltage threshold.

[0044] The signal holding unit 103-5 performs signal holding processing. The signal holding processing will be described. The signal holding unit 103-5 acquires the signal output by the comparison unit 103-3. When the acquired signal is a low-level signal, the signal holding unit 103-5 outputs a low-level signal. Also, when the acquired signal is a high-level signal, the signal holding unit 103-5 outputs a high-level signal. Thereafter, the signal holding unit 103-5 holds the output of the high-level signal regardless of whether a low-level signal or a high-level signal is acquired.

[0045] The hold release unit 103-6 causes the signal holding unit 103-5 to release the hold of the signal (high-level signal). When causing the signal holding unit 103-5 to release the hold of the signal, the hold release unit 103-6 outputs a high-level signal to the signal holding unit 103-5. When a low-level signal is input from the hold release unit 103-6 while the signal holding unit 103-5 is outputting a high-level signal, the signal holding unit 103-5 maintains the output of the high-level signal. Also, when the signal holding unit 103-5 is outputting a high-level signal, if a high-level signal is input from the hold release unit 103-6 and the hold of the signal is released from the signal holding unit 103-5, and then a low-level signal is acquired from the comparison unit 103-3, a low-level signal is output. This concludes the description of the signal holding processing.

[0046] The phase loss location specifying unit 103-4 includes a failed diode specifying table used when specifying a failed diode. The failed diode specifying table is a table-form information that associates an input voltage phase signal, a plurality of combinations of two energizable output terminals among the output terminals R1, S1, T1, R2, S2, T2, R3, S3, T3, R4, S4, and T4 of the polyphase transformer 3, and information indicating a diode that is determined to be failed when energization is not possible for each of the plurality of combinations of two energizable output terminals.

[0047] FIG. 10 is a diagram showing an example of a failed diode identification table included in the power conversion device 1 according to the present embodiment. In FIG. 10, from No. 1 to No. 24, for each of No. 1 to No. 24, information indicating the R-S input voltage phase signal, information indicating the output line-to-line voltage, information indicating the conducting diode, and information indicating the failed diode are associated in a table format. No. 1 to No. 24 are information for specifying combinations of two output terminals that can be energized. The R-S input voltage phase signal is an input voltage phase signal applied between the R phase and the S phase. The failed diode is information indicating a diode that has failed when it cannot be energized.

[0048] Specifically, the failed diode identification table shows the following. No. 1 indicates that when the input voltage phase signal is a high-level signal and a voltage is applied between output terminal T1 and output terminal T2 and it cannot be energized, diodes D15 and D26 have failed. No. 2 indicates that when the input voltage phase signal is a high-level signal and a voltage is applied between output terminal T1 and output terminal T4 and it cannot be energized, diodes D15 and D46 have failed. No. 3 indicates that when the input voltage phase signal is a high-level signal and a voltage is applied between output terminal T1 and output terminal S1 and it cannot be energized, diodes D15 and D14 have failed. Note that the fact that diodes D15 and D26 have failed means that either D15 or D26 has failed or both have failed. (The same applies hereinafter.)

[0049] No. 4 indicates that when the input voltage phase signal is a high-level signal and the voltage cannot be applied between output terminal S3 and output terminal S1, diodes D33 and D14 are faulty. No. 5 indicates that when the input voltage phase signal is a high-level signal and the voltage cannot be applied between output terminal S2 and output terminal S1, diodes D23 and D14 are faulty. No. 6 indicates that when the input voltage phase signal is a high-level signal and the voltage cannot be applied between output terminal S4 and output terminal S1, diodes D43 and D14 are faulty.

[0050] No. 7 indicates that when the input voltage phase signal is a high-level signal and the voltage cannot be applied between output terminal R1 and output terminal S1, diodes D11 and D14 are faulty. No. 8 indicates that when the input voltage phase signal is a high-level signal and the voltage cannot be applied between output terminal R1 and output terminal R3, diodes D11 and D32 are faulty. No. 9 indicates that when the input voltage phase signal is a high-level signal and the voltage cannot be applied between output terminal R1 and output terminal R2, diodes D11 and D22 are faulty.

[0051] No. 10 indicates that when the input voltage phase signal is a high-level signal and the voltage cannot be applied between output terminal R1 and output terminal R4, diodes D11 and D42 are faulty. No. 11 indicates that when the input voltage phase signal is a high-level signal and the voltage cannot be applied between output terminal R1 and output terminal T1, diodes D11 and D16 are faulty. No. 12 indicates that when the input voltage phase signal is a high-level signal and the voltage cannot be applied between output terminal T3 and output terminal T1, diodes D35 and D16 are faulty.

[0052] For No. 13, when the input voltage phase signal is a low-level signal and the voltage cannot be conducted when a voltage is applied between output terminal T2 and output terminal T1, it indicates that diodes D25 and D16 are faulty. For No. 14, when the input voltage phase signal is a low-level signal and the voltage cannot be conducted when a voltage is applied between output terminal T4 and output terminal T1, it indicates that diodes D45 and D16 are faulty. For No. 15, when the input voltage phase signal is a low-level signal and the voltage cannot be conducted when a voltage is applied between output terminal S1 and output terminal T1, it indicates that diodes D13 and D16 are faulty.

[0053] For No. 16, when the input voltage phase signal is a low-level signal and the voltage cannot be conducted when a voltage is applied between output terminal S1 and output terminal S3, it indicates that diodes D13 and D34 are faulty. For No. 17, when the input voltage phase signal is a low-level signal and the voltage cannot be conducted when a voltage is applied between output terminal S1 and output terminal S2, it indicates that diodes D13 and D24 are faulty. For No. 18, when the input voltage phase signal is a low-level signal and the voltage cannot be conducted when a voltage is applied between output terminal S1 and output terminal S4, it indicates that diodes D13 and D44 are faulty.

[0054] For No. 19, when the input voltage phase signal is a low-level signal and the voltage cannot be conducted when a voltage is applied between output terminal S1 and output terminal R1, it indicates that diodes D13 and D12 are faulty. For No. 20, when the input voltage phase signal is a low-level signal and the voltage cannot be conducted when a voltage is applied between output terminal R3 and output terminal R1, it indicates that diodes D31 and D12 are faulty. For No. 21, when the input voltage phase signal is a low-level signal and the voltage cannot be conducted when a voltage is applied between output terminal R2 and output terminal R1, it indicates that diodes D21 and D12 are faulty.

[0055] When the input voltage phase signal is a low-level signal and the diode D41 or diode D12 is faulty if it cannot be energized when a voltage is applied between output terminal R4 and output terminal R1, No. 22 indicates this. When the input voltage phase signal is a low-level signal and the diode D15 or diode D12 is faulty if it cannot be energized when a voltage is applied between output terminal T1 and output terminal R1, No. 23 indicates this. When the input voltage phase signal is a low-level signal and the diode D15 or diode D36 is faulty if it cannot be energized when a voltage is applied between output terminal T1 and output terminal T3, No. 24 indicates this. Return to FIG. 9 and continue the explanation.

[0056] The open-phase location specifying unit 103-4 receives the input voltage phase signal from the line voltage phase synchronization unit 104. When the input voltage phase signal is input, the open-phase location specifying unit 103-4 turns on the timer measurement unit 105 and acquires the DC voltage waveform from the voltage detection unit 101. When a high-level signal is input from the comparison unit 103-3, the open-phase location specifying unit 103-4 turns off the timer measurement unit 105. The open-phase location specifying unit 103-4 acquires information indicating the time when it was turned off from the timer measurement unit 105. The open-phase location specifying unit 103-4 detects the combination of two output terminals that could not be energized based on the acquired information indicating the time when it was turned off. For example, the open-phase location specifying unit 103-4 derives the phase from the time when it was turned off and detects the combination of two output terminals that could not be energized based on the derived phase.

[0057] The open-phase location specifying unit 103-4 acquires information indicating the diode determined to be faulty associated with the combination of two output terminals that could not be energized from the faulty diode specifying table. The defective location specifying unit 103-4 outputs the acquired information indicating the diode determined to be faulty. For example, the open-phase location specifying unit 103-4 may output the information indicating the diode determined to be faulty by displaying it on a display unit (not shown) or outputting it as voice from a speaker (not shown). FIG. 11 is a schematic configuration diagram showing an example of the power conversion device 1 according to the present embodiment. A case where the diode D43 has failed will be described as an example. FIG. 12 is a diagram showing an example of the DC voltage waveform output from the rectifier section 4 of the power conversion device 1 according to the present embodiment. The phase loss location specifying section 103-4 detects the combination of the output terminals S4 and S1 as a combination of two output terminals that could not be energized because they are not detected (missing) even when the timing comes when only the DC voltage waveform (S4-S1) after the output voltage between the output terminal S4 and the output terminal S1 is full-wave rectified by the rectifier section 4 is detected from the DC voltage waveform output from the voltage detection section 101. The phase loss location specifying section 103-4 specifies the diode D43 as the diode determined to be faulty based on the detected combination of the output terminals S4 and S1 from the faulty diode specification table.

[0058] FIG. 13 is a partial circuit diagram showing an example of the control section 103 of the power conversion device 1 according to the present embodiment. With reference to FIG. 13, a case where the average value derivation section 103-1, the voltage level adjustment section 103-2, the comparison section 103-3, the signal holding section 103-5, and the hold release section 103-6 of the control section 103 are realized by an electric circuit will be described. FIG. 13 also shows an example of a case where the voltage detection section 101 and the drive section 106 are realized by an electric circuit.

[0059] An example of the voltage detection section 101 is a resistor voltage division circuit, which includes a resistor R1 and a resistor R2. The resistor R1 and the resistor R2 are connected in series, and a DC circuit M1 is connected to both ends thereof. The negative side of the DC circuit M1 is grounded. The voltage detection section 101 divides the voltage supplied between the serially connected resistor R1 and resistor R2 at a predetermined ratio. By adjusting the resistor R1 and the resistor R2, the output voltage V1out of the voltage division circuit is adjusted. The voltage detection section 101 supplies the output voltage V1out to the average value derivation section 102.

[0060] An example of the average value derivation unit 103-1 is an integrating circuit, which includes a resistor R3, a capacitor C1, and an operational amplifier OP. The output voltage V1out of the voltage detection unit 101 is supplied as the input voltage V2in to the average value derivation unit 103-1. The voltage detection unit 101 obtains the output voltage V2out by integrating the input voltage V2in over time, and supplies it to the voltage level adjustment unit 103-2. For example, the voltage detection unit 101 derives the average value of the voltage by integrating the input voltage V2in over the period for deriving the average value.

[0061] An example of the voltage level adjustment unit 103-2 is a resistive voltage divider circuit, which includes a resistor R4 and a resistor R5. The resistor R4 and the resistor R5 are connected in series. The output voltage V2out of the average value derivation unit 103-1 is supplied as the input voltage V3in to one end of the series connection, and the other end is grounded. The voltage level adjustment unit 103-2 divides the voltage supplied between the series-connected resistor R4 and resistor R5 at a predetermined ratio. By adjusting the resistor R4 and the resistor R5, the output voltage V3out of the resistive voltage divider circuit is adjusted to be a voltage (voltage threshold) that reduces the voltage level of the input voltage V3in.

[0062] An example of the comparison unit 103-3 is a comparator. The output voltage V1out of the voltage detection unit 101 is supplied to the minus input terminal, and the output voltage V3out of the voltage level adjustment unit 103-2 is supplied to the plus input terminal. The comparison unit 103-3 outputs a high-level signal when the output voltage V3out is higher than the output voltage V1out, and outputs a low-level signal when the output voltage V3out is less than the output voltage V1out. When a phase loss occurs, the output voltage V1out of the voltage detection unit 101 decreases, so the output voltage V3out becomes higher than the output voltage V1out. Therefore, when a phase loss occurs, the comparison unit 103-3 outputs a high-level signal to the signal holding unit 103-5. Thereafter, since the output voltage V3out becomes less than the output voltage V1out, the comparison unit 103-3 outputs a low-level signal to the signal holding unit 103-5.

[0063] An example of the signal holding unit 103-5 is an RS flip-flop circuit, which includes two NOR gates. A low-level signal is supplied from the holding release unit 106 to the reset (R). The high-level signal output by the comparison unit 103-3 is supplied to the set (S). When a high-level signal is supplied to the set, the signal holding unit 103-5 supplies the high-level signal to the driving unit 106. Thereafter, the signal holding unit 103-5 holds the high-level signal even when a low-level signal or a high-level signal is supplied from the comparison unit 103-3 to the set. Also, when the signal holding unit 103-5 is outputting a high-level signal and a low-level signal is supplied from the holding release unit 103-6 to the reset (R), the signal holding unit 103-5 maintains the output of the high-level signal. Further, when the signal holding unit 103-5 is outputting a high-level signal and a high-level signal is supplied from the holding release unit 106 to the reset (R), the signal holding is released, and when a low-level signal is supplied from the comparison unit 103-3 to the set (S), the signal holding unit 103-5 supplies the low-level signal to the driving unit 106.

[0064] The holding release unit 103-6 includes a resistor R8, a NOT circuit, a capacitor C2, and a switch SW. When the switch SW is off, a voltage is supplied from a power source (not shown) to the input terminal of the NOT circuit, so a low-level signal is supplied to the reset (R) of the signal holding unit 103-5. When the switch SW is on, the input terminal of the NOT circuit is grounded through the contact circuit of the switch SW, so a high-level signal is supplied to the reset (R) of the signal holding unit 103-5.

[0065] The driving unit 106 includes a transistor TR, a resistor R6, a resistor R7, a diode DI, and a cutoff machine driving power source V7. The resistor 6 is connected to the base of the transistor TR and the resistor R7, and the signal holding unit 103-5 is connected to one end. When a high-level signal is supplied from the signal holding unit 103-5 to the driving unit 106 and the base voltage exceeds the on-voltage between the base and emitter, the transistor TR turns on. The collector current is adjusted by adjusting the base current with the resistor R6.

[0066] An example of the transistor TR is a bipolar transistor, and the emitter is grounded. The output voltage of the signal holding unit 103-5 is supplied to the base. When a low-level signal is supplied from the signal holding unit 103-5 to the drive unit 106 and the base voltage is less than the on-voltage between the base and emitter of the transistor TR, the transistor TR is off. Since the collector current does not flow because the transistor TR is off, no current flows through the external cutoff circuit of the cutoff device 2 connected to the drive unit 106, and the cutoff device 2 is not driven. When a high-level signal is supplied from the signal holding unit 103-5 to the drive unit 106 and the base voltage of the transistor TR exceeds the on-voltage between the base and emitter, the transistor TR turns on. When the transistor TR turns on, a collector current flows, and the cutoff device drive power supply V7 is supplied to the external cutoff circuit of the cutoff device 2 connected to the drive unit 106, and the cutoff device 2 is driven.

[0067] (Operation of the power conversion device 1) FIG. 14 is a flowchart showing an example of the operation of the power conversion device 1 according to the present embodiment. With reference to FIG. 14, the operation of the phase failure detection unit 100 will be mainly described. (Step S1-1) The voltage detection unit 101 detects one set of DC output voltages of the rectifying unit 4 and supplies them to the average value derivation unit 103-1 via the AD conversion unit 102. (Step S2-1) The average value derivation unit 103-1 derives the average value of the voltage based on the voltage supplied by the AD conversion unit 102.

[0068] (Step S3-1) The voltage level adjustment unit 103-2 acquires the average value of the voltage from the average value derivation unit 103-1. The voltage level adjustment unit 103-2 obtains the voltage threshold by reducing the voltage level of the acquired average value of the voltage. (Step S4-1) The comparison unit 103-3 acquires the voltage value from the AD conversion unit 102 and acquires the voltage threshold value from the voltage level adjustment unit 103-2. The comparison unit 103-3 compares the acquired voltage value with the voltage threshold value, and when the voltage value is less than the voltage threshold value, it outputs a high-level signal to the phase loss location identification unit 103-4 and the signal holding unit 103-5, and when the voltage value is greater than or equal to the voltage threshold value, it outputs a low-level signal to the phase loss location identification unit 103-4 and the signal holding unit 103-5.

[0069] (Step S5-1) The signal holding unit 103-5 performs signal holding processing. The processing flow of the signal holding processing will be described later. (Step S6-1) When a high-level signal is input from the signal holding unit 103-5, the drive unit 106 cuts off the voltage input to the polyphase transformer 3 in the cutoff unit 2, and when a low-level signal is input from the signal holding unit 103-5, the drive unit 106 does not cut off the voltage input to the polyphase transformer 3 in the cutoff unit 2.

[0070] FIG. 15 is a flowchart showing an example of the operation of the power conversion device 1 according to the present embodiment. With reference to FIG. 15, the signal holding processing will be described. As an example, the case where the signal holding unit 103-5 acquires a low-level signal from the hold release unit 103-6 will be described. (Step S1-2) The signal holding unit 103-5 acquires a signal from the comparison unit 103-3. (Step S2-2) The signal holding unit 103-5 determines whether the acquired signal is a low-level signal. (Step S3-2) When the acquired signal is a low-level signal, the signal holding unit 103-5 outputs a low-level signal. Then, it returns to step S1-2.

[0071] (Step S4-2) When the acquired signal is not a low-level signal, that is, when it is a high-level signal, the signal holding unit 103-5 outputs a high-level signal. (Step S5-2) The signal holding unit 103-5 acquires a signal (high-level signal or low-level signal) from the comparison unit 103-3.

[0072] (Step S6-2) The signal holding unit 103-5 holds the output of the high-level signal. (Step S7-2) The signal holding unit 103-5 determines whether it has acquired a signal from the holding release unit 103-6. If it has not acquired a signal, it returns to Step S5-2.

[0073] (Step S8-2) When the signal holding unit 103-5 has acquired a signal from the holding release unit 103-6, it determines whether the acquired signal is a low-level signal. (Step S9-2) When the acquired signal of the signal holding unit 103-5 is a low-level signal, it maintains the output of the high-level signal. Then, it proceeds to Step S5-2. (Step S10-2) When the acquired signal of the signal holding unit 103-5 is not a low-level signal, that is, a high-level signal, it releases the signal holding. Then, it proceeds to Step S1-2.

[0074] FIG. 16 is a flowchart showing an example of the operation of the power conversion device 1 according to the present embodiment. With reference to FIG. 16, the operation of the phase failure location specifying unit 103-4 will be mainly described. (Step S1-3) The phase failure location specifying unit 103-4 receives an input voltage phase signal from the line voltage phase synchronization unit 104. (Step S2-3) When the input voltage phase signal is input, the phase failure location specifying unit 103-4 turns on the timer measurement unit 105 and acquires a DC voltage waveform from the voltage detection unit 101.

[0075] (Step S3-3) The phase loss location identification unit 103-4 determines whether a high-level signal is input from the comparison unit 103-3. If no high-level signal is input, the process returns to step S3-3. (Step S4-3) When a high-level signal is input to the phase loss location identification unit 103-4, the timer measurement unit 105 is turned off.

[0076] (Step S5-3) The phase loss location identification unit 103-4 acquires information indicating the time when it was turned off from the timer measurement unit 105. The phase loss location identification unit 103-4 detects the combination of two output terminals that could not be energized based on the acquired information indicating the time when it was turned off. (Step S6-3) The phase loss location identification unit 103-4 acquires information indicating the diode that is determined to be a failure associated with the combination of two output terminals that could not be energized from the failure diode identification table.

[0077] An explanation will be given of the simulation results of the output waveform when a phase loss occurs in the power conversion device 1. FIG. 17 is a diagram showing an example of the circuit configuration of the polyphase transformer 3 and the rectifier unit 4 of the power conversion device 1 used in the simulation. FIG. 17 shows an example of the circuit configuration when no phase loss occurs (when it is normal). FIG. 18 is a diagram showing the simulation results in an example of the circuit configuration when no phase loss occurs. The power supply frequency is 50 Hz and the power supply voltage is 269 Vrms. The DC output voltage waveform is the waveform of the ripple voltage obtained by rectifying the AC voltage with a diode. The DC output voltage waveform is a voltage that outputs 380 V DC.

[0078] FIG. 19 is a diagram showing an example of the circuit configuration of the polyphase transformer 3 and the rectifier unit 4 of the power conversion device 1 used in the simulation. FIG. 19 shows an example of the circuit configuration when a phase loss occurs. One of the plurality of diodes included in the rectifier unit 4 has failed and is in an open state. That is, one phase is missing. FIG. 20 is a diagram showing simulation results in an example of a circuit configuration when a phase failure has occurred. The power supply frequency is 50 Hz, and the power supply voltage is 269 Vrms. The DC output voltage waveform becomes a waveform of a ripple voltage obtained by rectifying an AC voltage with a diode. The voltage is set to output 380 V in DC. Since a phase failure has occurred, a decrease in the DC output (\"D\" in FIG. 20) can be seen. When one of the diodes at a position different from the position shown in FIG. 19 has an open failure, one phase is missing and the output waveform is the same. However, the position of the decrease in the DC output is different. Therefore, it is possible to detect in which phase the phase failure has occurred.

[0079] In the above-described embodiment, as an example of the polyphase transformer 3, the case where a 12-phase transformer is applied has been described, but the present invention is not limited to this example. For example, a 3-phase transformer may be applied to the polyphase transformer 3, a 6-phase transformer may be applied, or a 24-phase transformer may be applied. FIG. 21 is a schematic configuration diagram showing another example of the power conversion device 1 according to the present embodiment. For example, when a 6-phase transformer is applied to the polyphase transformer 3, the polyphase transformer 3 may be configured to include a three-phase transformer 3-1 and a three-phase transformer 3-2. An example of the three-phase transformer 3-1 has a delta connection on the primary side and a delta connection on the secondary side. An example of the three-phase transformer 3-2 has a delta connection on the primary side and a star connection on the secondary side. Instead of the three-phase transformer 3-1 or the three-phase transformer 3-2, a three-phase transformer having a star connection on the primary side (high voltage side) and a delta connection on the secondary side (low voltage side) may be used.

[0080] In the above-described embodiment, the line voltage phase synchronization unit 104 has been described for the case where it is connected to the Rin terminal and the Sin terminal among the three terminals of the first winding 11, namely, the Rin terminal, the Sin terminal, and the Tin terminal, but the present invention is not limited to this example. For example, the line voltage phase synchronization unit 104 may be connected to the Sin terminal and the Tin terminal, or may be connected to the Tin terminal and the Sin terminal. In the foregoing embodiments, the case where the cutoff unit 2 cuts off the voltage input to the polyphase transformer 3 has been described, but the present invention is not limited to this example. For example, the cutoff unit 2 may be provided between the polyphase transformer 3 and the rectifier unit 4 to cut off the polyphase AC power supplied from the polyphase transformer 3 to the rectifier unit 4. Alternatively, the cutoff unit 2 may be provided at the subsequent stage of the rectifier unit 4 to cut off the DC power output from the rectifier unit 4. In the foregoing embodiments, the case where the average value derivation unit 103-1 derives the average value of the voltage every one cycle (e.g., 0.7 ms) has been described, but the present invention is not limited to this example. For example, the average value derivation unit 103-1 may derive the average value of the voltage every two cycles, or every three cycles, or every four or more cycles. The cycle at which the average value derivation unit 103-1 derives the average value of the voltage can be changed as appropriate.

[0081] In the foregoing embodiments, the case where the open-phase detection unit 100 identifies the location where the open-phase has occurred based on the time required until the output voltage drops, with reference to the phase-to-phase line voltage synchronized by the line-to-line phase voltage synchronization unit 104 has been described, but the present invention is not limited to this example. For example, the open-phase detection unit 100 may identify the location where the open-phase has occurred based on the time from when the output voltage drops until the next reference of the phase-to-phase line voltage synchronized by the line-to-line phase voltage synchronization unit 104. In the foregoing embodiments, the case where the voltage input to the polyphase transformer 3 is cut off when the open-phase detection unit 100 detects that an open-phase has occurred has been described, but the present invention is not limited to this example. For example, instead of the cutoff device 2, or together with the cutoff device 2, an alarm unit that sounds an alarm may be provided. For example, the alarm unit may be driven using a relay contact or the like. By configuring in this way, when it is determined that an open-phase has occurred, a notification can be made. For example, the operator of the power conversion device 1 can be made to take action. Thereafter, the operator of the power conversion device 1 can reset the signal holding unit 103-5 by turning on the switch SW of the hold release unit 103-6.

[0082] According to the power conversion device 1 according to this embodiment, it includes a polyphase transformer 3 that converts AC power into polyphase AC power, a rectifying unit 4 that converts polyphase AC power into DC power, and a phase failure detection unit 100 that identifies the location where the phase failure occurred based on the time when the output voltage decreased when it is detected that a phase failure occurred based on the decrease in the output voltage of the rectifying unit 4. By configuring it in this way, since it is possible to detect that a phase failure has occurred based on the output voltage of the rectifying unit 4, while reducing the size of the power conversion device 1 compared to the case of using a circuit breaker for wiring with neutral line phase failure protection, it is possible to detect that a phase failure has occurred. Furthermore, although there are many locations that can cause a phase failure, since it is possible to identify the location where the phase failure occurred based on the time when the output voltage decreased, restoration maintenance becomes easy. For example, it is possible to detect that a phase failure has occurred due to poor contact, disconnection between the polyphase transformer 3 and the rectifying unit 4, damage to the diodes of the rectifying unit 4, etc. based on the output voltage of the rectifying unit 4, and it is also possible to identify the location where the phase failure occurred.

[0083] Also, in the power conversion device 1, the phase failure detection unit 100 includes a line voltage phase synchronization unit 104 that synchronizes the phases of the line voltages input to the polyphase transformer 3, and a phase failure location identification unit 103-4 that identifies the location where the phase failure occurred based on the time required until the output voltage decreases, with reference to the line voltages synchronized by the line voltage phase synchronization unit 104. By configuring it in this way, since it is possible to synchronize the phases of the phase voltages input to the polyphase transformer 3, it is possible to detect the time required until the output voltage decreases with reference to the synchronized line voltages. Therefore, based on the time required until the output voltage decreases with reference to the synchronized line voltages, it is possible to identify the location where the phase failure occurred.

[0084] Also, in the power conversion device 1, the phase failure detection unit 100 includes a line voltage phase synchronization unit 104 that synchronizes the phases of the line voltages input to the polyphase transformer 3, and a phase failure location identification unit 103-4 that identifies the location where the phase failure has occurred based on the time from when the output voltage drops until the next reference of the line voltage synchronized by the line voltage phase synchronization unit 104. By configuring in this way, since the phases of the phase voltages input to the polyphase transformer 3 can be synchronized, the time from when the output voltage drops until the next reference of the line voltage can be detected. Therefore, based on the time from when the output voltage drops until the next reference of the line voltage, the location where the phase failure has occurred can be identified.

[0085] Also, in the power conversion device 1, the phase failure detection unit 100 includes an average value derivation unit 103-1 that derives the average value of the output voltage based on the output voltage of the rectification unit 4, a voltage level adjustment unit 103-2 as a threshold value derivation unit that derives a threshold value based on the average value derived by the average value derivation unit 103-1, and a comparison unit 103-3 as a determination unit that determines whether a phase failure has occurred based on the output voltage of the rectification unit 4 and the threshold value. By configuring in this way, since the average value of the output voltage of the rectification unit 4 can be derived and the threshold value can be derived based on the derived average value, it is possible to determine whether the output voltage of the rectification unit 4 has dropped by comparing with the threshold value. Therefore, it is possible to detect that a phase failure has occurred. In the power conversion device 1, the DC output voltage also varies in conjunction with fluctuations in the input voltage (for example, the system voltage). Also, the DC output voltage varies depending on the power consumption of the load (not shown). By deriving the average value of the output voltage of the rectification unit 4, a voltage threshold value can be derived in response to these fluctuations, so that it is possible to accurately detect the occurrence of a phase failure as compared with the case where the threshold value is a fixed value.

[0086] Also, in the power conversion device 1, it further includes a circuit breaker 2 that shuts off the AC power input to the polyphase transformer 3, and a drive unit 106 that operates the circuit breaker when it is determined by the determination unit that a phase failure has occurred. By configuring in this way, when it is determined that a phase failure has occurred, the AC power supplied to the polyphase transformer 3 can be shut off, thus ensuring safety.

[0087] Further, in the power conversion device 1, when it is determined by the determination unit that a phase failure has occurred, an alarm unit that sounds an alarm is further provided. By configuring in this way, when it is determined that a phase failure has occurred, an alarm can be sounded. Therefore, it is possible to notify the surroundings that a phase failure has occurred.

[0088] As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and design changes and the like within the scope not departing from the gist of the present invention are also included. For example, a computer program for realizing the function of the phase failure detection unit 100 of the power conversion device 1 described above may be recorded on a computer-readable recording medium, and the computer program recorded on this recording medium may be read into a computer system and executed. Here, the "computer system" may include hardware such as an OS and peripheral devices.

[0089] Further, the "computer-readable recording medium" refers to a writable non-volatile memory such as a flexible disk, a magneto-optical disk, a ROM, a flash memory, a portable medium such as a DVD (Digital Versatile Disc), a storage device such as a hard disk built in a computer system, and the like. Further, the "computer-readable recording medium" also includes a volatile memory (for example, DRAM (Dynamic Random Access Memory)) inside a computer system that becomes a server or a client when a computer program is transmitted via a network such as the Internet or a communication line such as a telephone line, and that holds the program for a certain period of time.

[0090] Also, the above program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the "transmission medium" for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) like the Internet or a communication line (communication wire) like a telephone line. Also, the above program may be for realizing a part of the functions described above. Furthermore, it may be a so-called differential file (differential program) that can realize the functions described above in combination with a program already recorded in the computer system.

Explanation of Signs

[0091] 1... Power conversion device, 2... Circuit breaker, 3... Polyphase transformer, 4... Rectifier section, 100... Open-phase detection section, 101... Voltage detection section, 102... AD conversion section, 103... Control section, 104... Inter-phase voltage synchronization section, 105... Timer measurement section, 106... Drive section, 103-1... Average value derivation section, 103-2... Voltage level adjustment section, 103-3... Comparison section, 103-4... Open-phase location determination section, 103-5... Signal holding section, 103-6... Holding release section

Claims

1. A polyphase transformer that converts AC power into polyphase AC power, a rectifier that converts the polyphase AC power into DC power, and a phase failure detection unit that identifies the location where a phase failure has occurred based on the time during which the output voltage has dropped when it is detected that a phase failure has occurred based on a decrease in the output voltage of the rectifier. A power conversion device comprising the above.

2. The phase failure detection unit includes a line voltage phase synchronization unit that synchronizes the phases of the line voltages input to the polyphase transformer, and a phase failure location identification unit that identifies the location where a phase failure has occurred based on the time required until the output voltage drops, with reference to the line voltages synchronized by the line voltage phase synchronization unit. The power conversion device according to Claim 1, comprising the above.

3. The phase failure detection unit includes a line voltage phase synchronization unit that synchronizes the phases of the line voltages input to the polyphase transformer, and a phase failure location identification unit that identifies the location where a phase failure has occurred based on the time from when the output voltage drops until the next reference of the line voltages synchronized by the line voltage phase synchronization unit. The power conversion device according to Claim 1, comprising the above.

4. The phase failure detection unit includes an average value derivation unit that derives the average value of the output voltage based on the output voltage of the rectifier, a threshold value derivation unit that derives a threshold value based on the average value derived by the average value derivation unit, and a determination unit that determines whether a phase failure has occurred based on the output voltage of the rectifier and the threshold value. The power conversion device according to any one of Claims 1 to 3, comprising the above.

5. A circuit breaker that interrupts the AC power input to the polyphase transformer, and a drive unit that operates the circuit breaker when it is determined by the determination unit that a phase failure has occurred. The power conversion device according to Claim 4, further comprising the above.

6. An alarm unit that sounds an alarm when it is determined by the determination unit that a phase failure has occurred. The power conversion device according to Claim 4, further comprising the above.

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