Memory system and memory chip

Abstract

To provide a memory system and a memory chip capable of transmitting data in parallel between a logic circuit and a memory chip.SOLUTION: A memory chip includes a memory bank, an I / O data bus, and a first plurality of sense amplifiers. The first plurality of sense amplifiers are located between the memory bank and the I / O data bus and configured to output a first plurality of data to the I / O data bus. There is no parallel-to-serial circuit and no serial-to-parallel circuit in the memory chip.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a memory system and a memory chip, and more particularly, to a memory system and a memory chip capable of parallelly transmitting data between a logic circuit and a memory chip.

Background Art

[0002] Currently, memory systems for high-performance computing or artificial intelligence (AI) systems typically include dynamic random access memory (DRAM) chips and logic circuits. Due to the stacked structure of DRAM chips, the scaling of DRAM chips cannot keep up with the scaling of logic circuits. Therefore, the memory wall effect occurs, resulting in a decrease in the data transfer speed between the logic circuit and the DRAM chip. To overcome the memory wall effect, the prior art typically either 1) uses a faster data rate (e.g., from DDR3 to DDR4 or DDR5) to transfer data between the DRAM chip and the logic circuit, or 2) uses a wide data bus of the logic circuit and a wide data bus of the DRAM chip (e.g., HBM) to transfer data between the DRAM chip and the logic circuit. However, a faster data rate has drawbacks (e.g., a more expensive tester and a smaller noise margin, etc.), and the wide data buses of the logic circuit and the DRAM chip also have drawbacks (e.g., higher power, larger die area, and an expensive through-silicon via (“TSV”) process, etc.). Also, whether it is a faster data rate of the above-mentioned DRAM or a wider data bus of the DRAM, both require serial-to-parallel circuits and parallel-to-serial circuits that increase clock latency and power consumption.

[0003] Please refer to FIG. 1. FIG. 1 is a diagram showing a memory system 10 according to the prior art. As shown in FIG. 1, the memory system 10 includes a memory 20 and a logic circuit 30, and the memory 20 is a dynamic random access memory (DRAM). As shown in FIG. 1, the memory 20 includes a cell array 21, a parallel-to-serial circuit 22, and a serial-to-parallel circuit 23. The logic circuit 30 includes a physical layer (PHY) 31 and a controller 32, and the physical layer 31 includes a serial-to-parallel circuit 312 and a parallel-to-serial circuit 314. Also, of course, the logic circuit 30 further includes other functional circuits (not shown in FIG. 1), and these other functional circuits can include a central processing unit (CPU), a digital signal processor (DSP), a peripheral interface, and the like. As shown in FIG. 1, when the logic circuit 30 writes data to the memory 20, the parallel-to-serial circuit 314 receives data (e.g., N-bit data) in parallel from the controller 32, converts the N-bit data into a group of Q-bit data (Q is smaller than N), and can transmit the group of Q-bit data to the serial-to-parallel circuit 23. The serial-to-parallel circuit 23 can receive the group of Q-bit data from the parallel-to-serial circuit 314, convert the group of Q-bit data into N-bit data, and transmit the N-bit data to the cell array 21 in parallel. Also, when the logic circuit 30 reads data from the memory 20, the parallel-to-serial circuit 22 receives data (e.g., N-bit data) in parallel from the cell array 21, converts the N-bit data into a group of Q-bit data, and can transmit the group of Q-bit data to the serial-to-parallel circuit 312. The serial-to-parallel circuit 312 can receive the group of Q-bit data from the parallel-to-serial circuit 22, convert the group of Q-bit data into N-bit data, and transmit the N-bit data to the controller 32 in parallel.

[0004] Please refer to FIGS. 2A and 2B. FIGS. 2A and 2B are diagrams showing a timing diagram corresponding to the logic circuit 30 writing data to the memory 20. Taking as an example the case where the logic circuit 30 writes 8-bit data D0 - D7 to the memory 20 as shown in FIG. 2A, when the logic circuit 30 writes 8-bit data D0 - D7 to the memory 20, a register (not shown in FIG. 1) of the parallel-to-serial circuit 314 can serially transmit the parallel 8-bit data D0 - D7 to the serial-to-parallel circuit 23 using three signals clk1, clk2, and clk3. For example, when clk1 = 1, clk2 = 1, and clk3 = 1, the parallel-to-serial circuit 314 transmits data D0 to the serial-to-parallel circuit 23, and when clk1 = 1, clk2 = 1, and clk3 = 0, the parallel-to-serial circuit 314 transmits data D1 to the serial-to-parallel circuit 23, and so on. Therefore, the parallel-to-serial circuit 314 starts transmitting data D0 at time point T0 and finally transmits data D7 at time point T4.

[0005] As shown in FIG. 2B, similarly, a register (not shown in FIG. 1) of the serial-to-parallel circuit 23 can also serially process the 8-bit data D0 - D7 from the parallel-to-serial circuit 314 using the same clock signals clk1, clk2, and clk3. As shown in FIG. 2B, when clk1 = 1, clk2 = 1, and clk3 = 1, the serial-to-parallel circuit 23 receives data D0 from the parallel-to-serial circuit 314, and when clk1 = 1, clk2 = 1, and clk3 = 0, the serial-to-parallel circuit 23 receives data D1 from the parallel-to-serial circuit 314, and so on. Therefore, the serial-to-parallel circuit 23 starts receiving data D0 at time point T0 and finally receives data D7 at time point T4, and there is a 4-clock latency of clock clk3 between time point T0 and time point T4. That is, the serial-to-parallel circuit 23 starts serially transmitting the 8-bit data D0 - D7 to the cell array 21 only after waiting for a 4-clock latency.

[0006] The prior art can shorten the 4-clock latency by optimizing the memory system 10 (for example, 3.5-clock latency). However, the above-described serial-to-parallel conversion process executed by the serial-to-parallel circuit 23 and the above-described parallel-to-serial conversion process executed by the parallel-to-serial circuit 314 consume extra power, transmission latency, and die area, resulting in low efficiency of the memory system 10. Therefore, how to reduce the costs of power, transmission latency, and die area becomes an important issue for the designers of the memory system. SUMMARY OF THE INVENTION

[0007] Embodiments of the present invention provide a memory chip that can be a DRAM chip, an SRAM chip, or other types of memory chips. The memory chip includes a memory bank, an I / O data bus, and a first plurality of sense amplifiers. The first plurality of sense amplifiers are between the memory bank and the I / O data bus and are configured to output a first plurality of data to the I / O data bus in parallel. There is no parallel-to-serial circuit or serial-to-parallel circuit in the memory chip.

[0008] According to one aspect of the present invention, the memory chip sends a handshake signal to selectively notify whether the memory chip executes a refresh operation.

[0009] According to one aspect of the present invention, the memory chip further includes an additional output pin, and the handshake signal is transmitted to the memory controller via the additional output pin, and the memory controller is physically separate from the memory chip.

[0010] According to one aspect of the present invention, the memory chip further includes a refresh counter, and the handshake signal is selectively activated according to the number of clocks counted by the refresh counter.

[0011] According to one aspect of the present invention, the handshake signal is active when the memory chip is performing a refresh operation, and the handshake signal is inactive when the memory chip is not performing a refresh operation.

[0012] According to one aspect of the present invention, the width of the I / O data bus is equal to the width of the first plurality of data output in parallel by the first plurality of sense amplifiers.

[0013] According to one aspect of the present invention, the memory chip further includes a plurality of transceivers between the first plurality of sense amplifiers and the I / O data bus, and the plurality of transceivers receive the first plurality of data in parallel from the first plurality of sense amplifiers and transmit the first plurality of data in parallel to the I / O data bus.

[0014] According to one aspect of the present invention, the memory chip further includes a second plurality of sense amplifiers between the memory bank and the first plurality of sense amplifiers, the second plurality of sense amplifiers includes M sense amplifiers and is connected to the bit lines of the memory chip, the first plurality of sense amplifiers has N sense amplifiers and is connected to the data lines of the memory chip, and both N and M are positive integers, and M is greater than or equal to N.

[0015] According to one aspect of the present invention, a part of the second plurality of sense amplifiers is selectively coupled to the first plurality of sense amplifiers, and the part of the second plurality of sense amplifiers outputs the first plurality of data in parallel to the first plurality of sense amplifiers, and the number of sense amplifiers in the part of the second plurality of sense amplifiers is equal to N.

[0016] According to one aspect of the present invention, the part of the second plurality of sense amplifiers is selectively coupled to the first plurality of sense amplifiers according to a control signal input to the memory chip.

[0017] According to one aspect of the present invention, the control signal includes a plurality of signal bits configured to be stored in a register of the memory chip.

[0018] According to one aspect of the present invention, the memory chip further includes a plurality of bit switches between a first plurality of sense amplifiers and a second plurality of sense amplifiers, and the plurality of bit switches are electrically connected to the part of the second plurality of sense amplifiers and the first plurality of sense amplifiers according to the control signal.

[0019] Another embodiment of the present invention provides a memory chip. The memory chip includes a plurality of memory banks, data lines, a plurality of sets of sense amplifiers, and an I / O data bus. The plurality of sets of sense amplifiers are coupled to the data lines, and each set of sense amplifiers corresponds to one of the plurality of memory banks and is configured to output a plurality of data in parallel. There is neither a parallel-to-serial circuit nor a serial-to-parallel circuit in the memory chip, and the memory chip sends a handshake signal to selectively notify whether the memory chip performs a refresh operation.

[0020] According to one aspect of the present invention, the memory chip further includes an additional output pin, and the handshake signal is transmitted to the memory controller via the additional output pin, and the memory controller is physically separate from the memory chip.

[0021] According to one aspect of the present invention, the handshake signal is active when the memory chip is performing a refresh operation, and the handshake signal is inactive when the memory chip is not performing a refresh operation.

[0022] According to one aspect of the present invention, the memory chip further includes a refresh counter, and the handshake signal is selectively activated according to the number of clocks counted by the refresh counter.

[0023] According to one aspect of the present invention, a plurality of memory banks includes a first memory bank and a second memory bank, a plurality of sets of sense amplifiers includes a first set of sense amplifiers coupled to data lines and a second set of sense amplifiers coupled to the data lines, the first set of sense amplifiers corresponds to the first memory bank and is configured to output a first plurality of data in parallel, the second set of sense amplifiers corresponds to the second memory bank and is configured to output a second plurality of data in parallel, and the width of the I / O data bus is equal to the sum of the width of the first plurality of data and the width of the second plurality of data.

[0024] According to one aspect of the present invention, the memory chip further includes bit lines, a third set of sense amplifiers, and a fourth set of sense amplifiers. The third set of sense amplifiers is coupled to the bit lines and configured between the first memory bank and the first set of sense amplifiers. The fourth set of sense amplifiers is coupled to the bit lines and configured between the second memory bank and the second set of sense amplifiers. A part of the third set of sense amplifiers is selectively coupled to the first set of sense amplifiers, and the number of sense amplifiers in the part of the third set of sense amplifiers is equal to the number of sense amplifiers in the first set of sense amplifiers. A part of the fourth set of sense amplifiers is selectively coupled to the second set of sense amplifiers, and the number of sense amplifiers in the part of the fourth set of sense amplifiers is equal to the number of sense amplifiers in the second set of sense amplifiers.

[0025] According to one aspect of the present invention, the part of the third set of sense amplifiers is selectively coupled to the first set of sense amplifiers according to a control signal input to the memory chip, and the part of the fourth set of sense amplifiers is selectively coupled to the second set of sense amplifiers according to the control signal.

[0026] Another embodiment of the present invention provides a memory controller for a DRAM system, the DRAM system including a system bus interface and a memory chip, the memory chip including an I / O data bus. The memory controller includes a control circuit and a physical layer circuit. The control circuit is configured to couple to the system bus interface. The physical layer circuit is coupled to the control circuit and is configured to receive a first plurality of data in parallel from the I / O data bus of the memory chip. There is neither a serial-to-parallel circuit nor a parallel-to-serial circuit in the physical layer circuit of the memory controller.

[0027] According to one aspect of the present invention, the physical layer circuit is further configured to output a second plurality of data in parallel to the I / O data bus of the memory chip.

[0028] According to one aspect of the present invention, the memory controller receives a handshake signal from the memory chip for selectively notifying the memory controller whether the memory chip performs a refresh operation.

[0029] According to one aspect of the present invention, the handshake signal is active when the memory chip is performing a refresh operation, and the handshake signal is inactive when the memory chip is not performing a refresh operation.

[0030] According to one aspect of the present invention, when the handshake signal is active, the memory controller holds an access command intended to read data from or write data to the memory chip.

[0031] According to one aspect of the present invention, after the handshake signal becomes inactive, the memory controller transmits the held access command to the memory chip.

[0032] Another embodiment of the present invention provides a memory system. The memory system includes a system bus interface, a memory controller, a memory chip, and a substrate. The memory controller has a controller I / O data bus coupled to a plurality of second bump groups, the memory controller is coupled to the system bus interface, the memory controller further includes a physical layer, and there is no parallel-to-serial circuit or serial-to-parallel circuit in the physical layer of the memory controller. The memory chip has a memory I / O data bus coupled to a plurality of first bump groups, the memory chip is coupled to the memory controller, and there is no parallel-to-serial circuit or serial-to-parallel circuit in the memory chip. The memory controller and the memory chip are disposed on the substrate and are horizontally spaced apart from each other.

[0033] According to one aspect of the present invention, the plurality of first bump groups are arranged side by side, the plurality of second bump groups are arranged side by side, each bump group of the plurality of first bump groups is connected to a corresponding bump group of the plurality of second bump groups via a corresponding track in the substrate, and the tracks connecting the plurality of first bump groups to the plurality of second bump groups do not cross each other.

[0034] Another embodiment of the present invention provides a memory chip. The memory chip includes a first set of memory banks and an I / O data bus of the memory chip. The I / O data bus of the memory chip is electrically coupled to the first set of memory banks, each memory bank transmits data of a first predetermined width in parallel to the I / O data bus, the width of the I / O data bus is equal to the sum of the data of the first predetermined width of each memory bank of the first set of memory banks, and the first predetermined width is programmable according to a set of control signals. There is no parallel-to-serial circuit or serial-to-parallel circuit in the memory chip.

[0035] According to one aspect of the present invention, the memory chip further includes a second set of memory banks, each memory bank of the second set of memory banks transmits data of a second predetermined width in parallel to the I / O data bus, and the width of the I / O data bus is selectively equal to the sum of the data of the first predetermined width of each memory bank of the first set of memory banks or the sum of the data of the second predetermined width of each memory bank of the second set of memory banks based on a selection signal.

[0036] According to one aspect of the present invention, when the width of the I / O data bus is equal to the sum of the data of the second predetermined width of each memory bank of the second set of memory banks, the second predetermined width is programmable according to a set of control signals.

[0037] After reading the following detailed description of the preferred embodiments shown in the various figures and drawings, these and other objects of the present invention will become apparent to those skilled in the art.

Brief Description of the Drawings

[0038]

Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0039] Please refer to FIG. 3. FIG. 3 is a diagram showing a memory system 100 according to a first embodiment of the present invention. As shown in FIG. 3, the memory system 100 includes a memory 101 and a logic circuit 102. The memory 101 can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, or other types of memory. The logic circuit 102 can be an artificial intelligence (AI) chip or a system-on-chip (SOC). In an embodiment of the present invention, the memory 101 can include a base DRAM chip and a plurality of DRAM chips stacked on the base DRAM chip. The logic circuit 102 is coupled to other devices or processors via an AXI (Advanced eXtensible Interface) bus. The AXI bus is a bus protocol, and the protocol is part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol. The AXI bus includes a write data bus and a read data bus. The operation method corresponding to the AXI bus is well known to those skilled in the art, and therefore, further description thereof is omitted for the sake of brevity.

[0040] The memory 101 includes a first alignment circuit 1011 and a plurality of first pads FP. The first alignment circuit 1011 is used to align data corresponding to the memory 101 and includes a plurality of transceivers. That is, the first alignment circuit 1011 is used to transmit data simultaneously or receive data simultaneously (for example, transmit data with the same clock or receive data with the same clock, that is, the plurality of transceivers of the first alignment circuit 1011 can transmit data in parallel or receive data in parallel). On the other hand, the logic circuit 102 includes a physical layer (PHY) 103 and a controller 105. The physical layer 103 is electrically connected to the controller 105 via a double data rate physical layer interface (DDR PHY Interface, DFI) bus. The DFI bus includes a plurality of wire pairs, and the plurality of wire pairs include a plurality of write wires and a plurality of read wires. Further, the physical layer 103 includes a second alignment circuit 1031 and a plurality of second pads SP. The second alignment circuit 1031 is used to align data and also includes a plurality of transceivers. That is, the second alignment circuit 1031 is also used to transmit data simultaneously or receive data simultaneously (for example, transmit data with the same clock or receive data with the same clock, that is, the plurality of transceivers of the second alignment circuit 1031 can transmit data in parallel or receive data in parallel).

[0041] In this embodiment of the present invention, the first alignment circuit 1011 and the second alignment circuit 1031 can transmit data by aligning them in parallel or receive data by aligning them in parallel, and the data can be transmitted between the memory 101 and the logic circuit 102 without any conventional parallel-to-serial circuits and serial-to-parallel circuits in either the memory 101 or the physical layer 103. Therefore, the controller (or memory controller) 105 can access the data corresponding to the memory 101 in parallel by using a plurality of wire pairs, the second alignment circuit 1031, a plurality of second pads SP, a plurality of first pads FP, and the first alignment circuit 1011. The number of the plurality of first pads FP may be equal to the number of the plurality of write wires (or the number of the plurality of read wires) of the plurality of wire pairs of the DFI bus. Also, the number of the plurality of second pads SP may be equal to the number of the plurality of write wires (or the number of the plurality of read wires) of the plurality of wire pairs of the DFI bus.

[0042] For example, as shown in FIG. 3, the number of a plurality of first pads FP or the number of a plurality of second pads SP is equal to N, and the data can be N-bit data RD read from the cell array of the memory 101 or N-bit data WD written into the cell array of the memory 101. When the logic circuit 102 reads N-bit data RD from the cell array of the memory 101 in parallel, the first alignment circuit 1011 receives the N-bit data RD from the cell array of the memory 101 in parallel and simultaneously transmits the N-bit data RD to the second alignment circuit 1031 in parallel via the plurality of first pads FP and the plurality of second pads SP. After the second alignment circuit 1031 receives the N-bit data RD in parallel, the second alignment circuit 1031 transmits the N-bit data RD to the controller 105 in parallel via the plurality of read wires of the plurality of wire pairs of the DFI bus. On the other hand, when the logic circuit 102 writes the N-bit data WD into the cell array of the memory 101 in parallel, the second alignment circuit 1031 receives the N-bit data WD from the controller 105 in parallel via the plurality of write wires of the plurality of wire pairs of the DFI bus. Then, the second alignment circuit 1031 can transmit the N-bit data WD to the first alignment circuit 1011 in parallel and simultaneously without passing through a conventional parallel-to-serial circuit and a serial-to-parallel circuit. After the first alignment circuit 1011 receives the N-bit data WD, the first alignment circuit 1011 writes the N-bit data WD into the cell array of the memory 101 in parallel.

[0043] Also, each of the first alignment circuit 1011 and the second alignment circuit 1031 has a plurality of transceivers. Each transceiver of the first alignment circuit 1011 is coupled to a corresponding pad among the plurality of first pads FP, and each transceiver of the second alignment circuit 1031 is coupled to a corresponding pad among the plurality of second pads SP. Refer to FIG. 4. FIG. 4 is a diagram showing the structure of two transceivers TR1 and TR2 according to another embodiment of the present invention. Each transceiver of the first alignment circuit 1011 (not shown in FIG. 4) can be assumed to be transceiver TR1, and each transceiver of the second alignment circuit 1031 (not shown in FIG. 4) can be assumed to be transceiver TR2. Also, the components of transceivers TR1 and TR2 are well known to those skilled in the art, and thus, further description thereof is omitted for the sake of brevity. Also, regarding the coupling relationship between the components of transceivers TR1 and TR2, reference can be made to FIG. 4, and thus, further description thereof is also omitted for the sake of brevity. When the write enable signal W_EN is enabled and the read enable signal R_EN is disabled, transceiver TR2 transmits the bit data WD_N of the N-bit data WD to transceiver TR1 via the first pad FPN and the second pad SPN. On the other hand, when the write enable signal W_EN is disabled and the read enable signal R_EN is enabled, transceiver TR1 transmits the bit data RD_N of the N-bit data RD to transceiver TR2 via the first pad FPN and the second pad SPN. Since the write enable signal W_EN and the read enable signal R_EN are common signals to the first alignment circuit 1011 and the second alignment circuit 1031, the first alignment circuit 1011 can transmit the N-bit data RD in parallel simultaneously or receive the N-bit data WD in parallel simultaneously, and the second alignment circuit 1031 can transmit the N-bit data WD in parallel simultaneously or receive the N-bit data RD in parallel simultaneously.

[0044] In another embodiment of the present invention, the first write enable signal and the first read enable signal are signals for the first alignment circuit 1011, and the second write enable signal and the second read enable signal are signals for the second alignment circuit 1031. The first write enable signal and the first read enable signal respectively correspond to the second write enable signal and the second read enable signal.

[0045] The first alignment circuit 1011 and the second alignment circuit 1031 can transmit data in parallel and receive data in parallel without passing through a conventional parallel-to-serial circuit and a serial-to-parallel circuit. Therefore, the first alignment circuit 1011 can simultaneously transmit N-bit data RD to the second alignment circuit 1031 in parallel or receive N-bit data WD from the second alignment circuit 1031 in parallel. Similarly, the second alignment circuit 1031 can simultaneously receive N-bit data RD from the first alignment circuit 1011 in parallel or transmit N-bit data WD to the first alignment circuit 1011 in parallel. Also, as shown in FIG. 4, the present invention is not limited to the case where each transceiver of the first alignment circuit 1011 is the transceiver TR1 and each transceiver of the second alignment circuit 1031 is the transceiver TR2. That is, each transceiver of the first alignment circuit 1011 and each transceiver of the second alignment circuit 1031 may be other transmission / reception circuits, buffers, or registers.

[0046] Please refer to FIG. 5. FIG. 5 is a timing diagram for comparing a conventional memory system with the memory system 100. For example, as shown in FIG. 5(a), when a conventional logic circuit reads 8-bit data D0-D7 from a conventional memory, the conventional memory needs to form 8 states using three clocks clk1, clk2, clk3 so that it can transmit the 8-bit data D0-D7 serially (for example, data D0 corresponds to the state (clk1 = 1, clk2 = 1, clk3 = 1), data D1 corresponds to the state (clk1 = 1, clk2 = 1, clk3 = 0), and so on). Therefore, the controller of the conventional logic circuit can start receiving the data D0-D7 in parallel only after time point T4. However, as shown in FIG. 5(b), since the data D0-D7 are transmitted simultaneously by the memory 101, the controller 105 can start receiving the data D0-D7 at time point T0. Therefore, compared with the conventional memory system, the present invention can reduce the latency of 4 clocks. Also, the operation method of writing the 8-bit data D0-D7 is the same as the above-described operation method, and thus its further description for the sake of brevity is omitted.

[0047] Please refer to FIG. 3 again. As shown in FIG. 3, the controller 105 is further coupled to the physical layer 103 via a plurality of control wires. The physical layer 103 further includes a plurality of second control pads SCP. The memory 101 further includes a plurality of first control pads FCP. The plurality of first control pads FCP are electrically connected to the plurality of second control pads SCP. Accordingly, the controller 105 can transmit the control signal CS to the memory 101 by using the plurality of control wires, the plurality of second control pads SCP, and the plurality of first control pads FCP. Also, FIG. 3 shows only three first control pads, three second control pads, and three control wires, but the present invention is not limited thereto. Further, the plurality of control wires and the plurality of wire pairs between the physical layer 103 and the controller 105 are included in the DFI bus. The DFI bus defines signals, timing parameters, and programmable parameters necessary for communication between the physical layer 103 and the controller 105. Accordingly, the control signal CS is defined by the DFI bus and can include, for example, a write enable signal, a read enable signal, and a chip select signal. Also, the operation method corresponding to the DFI bus is well known to those skilled in the art, and thus further description thereof for the sake of brevity is omitted. Also, the logic circuit 102 in another embodiment may further include a system circuit (not shown in FIG. 3). The system circuit can include other peripheral interfaces. The controller or the memory controller 105 communicates with the system circuit via an AXI (Advanced eXtensible Interface) bus. For example, the controller 105 can transmit N-bit data RD to the system circuit or receive N-bit data WD from the system circuit via the AXI bus to / from other devices or processors.

[0048] Also, the plurality of first pads FP can be electrically connected to the plurality of second pads SP by metal wires, metal bridges, flip chips, microbumps, or other bonding technologies. Also, in another embodiment of the present invention, since the plurality of first pads FP are electrically connected to the plurality of second pads SP, the plurality of first pads FP and the plurality of second pads SP are not coupled to the external environment of the memory system 100. Therefore, the plurality of first pads FP and the plurality of second pads SP do not need to include a conventional electrostatic discharge (ESD) protection circuit, and the sizes of the plurality of first pads FP and the plurality of second pads SP can be reduced.

[0049] In another embodiment of the present invention, the second alignment circuit 1031 of the physical layer 103 can be applied to different data widths depending on the data width of the AXI bus. However, in another embodiment of the present invention, both the second alignment circuit 1031 of the physical layer 103 and the first alignment circuit 1011 of the memory 101 can be applied to different data widths depending on the data width of the AXI bus at the same time. For example, when the logic circuit 102 is applied to a memory having a data width of Q bits, the controller 105 can notify the physical layer 103 to adjust the second alignment circuit 1031 so that only Q read wires out of a plurality of wire pairs are used by the second alignment circuit 1031 to transmit Q-bit data to the controller 105 (or, only Q write wires out of a plurality of wire pairs are used to receive Q-bit data from the controller 105), where Q is a positive integer greater than 1 and less than N. Therefore, the physical layer 103 and the controller 105 can be applied to different system circuits and different memories having different data widths.

[0050] The first alignment circuit 1011 and the second alignment circuit 1031 are smaller and simpler, and since the conventional parallel-to-serial circuit and serial-to-parallel circuit are omitted from the memory 101 and the physical layer 103, the read / write speed of the memory 101 is significantly increased. (As shown in FIG. 6), the area of the memory 101 is smaller than the area of the conventional memory and the area of the physical layer 103 is also smaller than the area of the physical layer of the conventional logic circuit, and the memory wall problem between the memory 101 and the logic circuit 102 can be suppressed. Also, the physical layer 103 can receive signals of Dfi cke, Dfi CK / CKB, Dfi BA, Dfi address, Dfi cs, Dfi_ras, Dfi cas, Dfi we, Dfi wrdata, Dfi wrdata mask, Dfi wrdata valid from the controller 105 via the DFI bus and transmit signals of Dfi rddata, Dfi rddata valid to the controller 105. These signals of Dfi cke, Dfi CK / CKB, Dfi BA, Dfi address, Dfi cs, Dfi_ras, Dfi cas, Dfi we, Dfi wrdata, Dfi wrdata mask, Dfi wrdata valid, and the signals of Dfi rddata, Dfi rddata valid are clearly defined in the DFI specification, and thus, further explanations thereof are omitted for simplicity. Also, the physical layer 103 can transmit signals of CKE, CK / CKB, BA, Addr, CSB, RASB, CASB, WEB, DQ, DM, DQS / DQSB to the memory 101, and these signals of CKE, CK / CKB, BA, Addr, CSB, RASB, CASB, WEB, DQ, DM, DQS / DQSB are also clearly defined in the DFI specification, and thus, further explanations thereof are omitted for simplicity. Therefore, even when the memory 101 and the logic circuit 102 are manufactured by different (heterogeneous) processes, the plurality of first pads FP and the plurality of second pads SP can be electrically connected.For example, the transistors of the memory 101 can be planar or trench transistors employed by current memory technologies (e.g., DRAM or HBM technology), while the transistors of the logic circuit 102 can be 3D transistors (e.g., tri-gate transistors, fin field-effect transistors (FinFETs), or gate-all-around transistors). However, in another embodiment of the present invention, the memory 101 and the logic circuit 102 are manufactured by the same type of (homogeneous) process. That is, the memory 101 and the logic circuit 102 can employ planar or trench transistors, tri-gate transistors, FinFETs, gate-all-around transistors, or other transistors. Also, instead of employing conventional parallel-to-serial circuits and serial-to-parallel circuits, by employing the first alignment circuit 1011 and the second alignment circuit 1031, the power of the memory 101 and the logic circuit 102 is reduced, the latency of accessing the memory 101 is decreased, and the area cost of the memory 101 and the logic circuit 102 is reduced. Accordingly, the read / write window margin of the memory system 100 is improved.

[0051] Also, please refer to FIG. 7. FIG. 7 is a diagram showing that the data width of the memory is changed by a control signal according to another embodiment of the present invention. For example (but not limited to), the memory 101 includes M second sense amplifiers BLSA (i.e., bit line sense amplifiers) and N first sense amplifiers DLSA (i.e., data line sense amplifiers), and the number of connections of the M second sense amplifiers BLSA electrically coupled to the first sense amplifier DLSA can be changed by a control signal (e.g., SB0 - SB4 according to Table 1, etc.). The second sense amplifier BLSA is between the cell array and the first sense amplifier DLSA, the first sense amplifier is between the second sense amplifier BLSA and the first alignment circuit 1011 including a plurality of transceivers, the first alignment circuit 1011 is between the first sense amplifier DLSA and the I / O data bus (not shown in FIG. 7) of the memory 101, N is a positive integer less than or equal to M, and the I / O data bus is coupled to a plurality of first pads FP.

[0052] In one embodiment, the control signal is stored in a register (not shown in FIG. 7) of the memory 101, such as a mode register. Also, the second sense amplifier BLSA is connected to the bit line (not shown in FIG. 7) of the memory 101, and the first sense amplifier DLSA is connected to the data line (not shown in FIG. 7) of the memory 101. The N first sense amplifiers DLSA are electrically coupled to a part of the M second sense amplifiers BLSA via a plurality of bit switches, and these bit switches can be selected or activated by the above-described control signal.

[0053] As shown in Table 1 and FIG. 7, when the control signals SB0 - SB4 are 0 / 0 / 0 / 0 / 1, 128 second sense amplifiers are electrically coupled to 128 first sense amplifiers via bit switches (not shown in FIG. 7, for example, a group of selected bit switches such as up to 128 bit switches based on one given column address is selected by the control signals SB0 - SB4 (0 / 0 / 0 / 0 / 1)), and 128 - bit data can be read from the cell array of the memory 101 via a part of the second sense amplifiers and the first sense amplifiers (for example, via 128 connected second sense amplifiers and 128 first sense amplifiers), or written to the cell array of the memory 101 by the first alignment circuit 1011 via a part of the second sense amplifiers and the first sense amplifiers (for example, via 128 connected second sense amplifiers and 128 first sense amplifiers). That is, when 128 - bit data is read from the cell array of the memory 101, a plurality of transceivers of the first alignment circuit 1011 receive 128 - bit data from 128 first sense amplifiers in parallel and transmit it to the I / O data bus of the memory 101, or when 128 - bit data is written to the cell array of the memory 101, a plurality of transceivers of the first alignment circuit 1011 receive 128 - bit data from the I / O data bus in parallel and transmit it to 128 first sense amplifiers. Alternatively, in other words, when 128 - bit data is read from the cell array of the memory 101, a part of the second sense amplifiers BLSA (for example, 128 connected second sense amplifiers) outputs 128 - bit data to the first sense amplifiers DLSA (for example, 128 first sense amplifiers), and then the first sense amplifiers DLSA output 128 - bit data to a plurality of transceivers in parallel, or when 128 - bit data is written to the cell array of the memory 101, 128 first sense amplifiers output 128 - bit data to a part of the connected second plurality of sense amplifiers (for example, 128 second sense amplifiers BLSA) in parallel.Also, the data width of the memory 101 (i.e., the width of the I / O data bus of the memory 101) is equal to 128 according to 128 first sense amplifiers. At the same time, since the data width of the memory 101 is 128, both the data width of the controller 105 and the data width of the AXI bus are equal to 128.

[0054] In another embodiment of the present invention, the read (or write) data width of the DFI bus coupled to the physical layer 103 is also equal to 128 or set to 128 according to the control signals SB0 - SB4. Also, as shown in FIG. 7, when the logic circuit 102 is included in a computing system having a system bus interface (i.e., AXI bus) including a read data bus and a write data bus, both the width of the read data bus and the width of the write data bus are equal to 128 according to the control signals SB0 - SB4 (0 / 0 / 0 / 0 / 1) input to the controller 105. Also, the width of the DFI bus is selectively adjusted according to the control signals SB0 - SB4 (0 / 0 / 0 / 0 / 1) input to the physical layer 103.

[0055] Similarly, as shown in Table 1 and FIG. 7, when the control signals SB0 - SB4 are 0 / 0 / 0 / 1 / 0, 256 of the M second sense amplifiers are electrically coupled to 256 first sense amplifiers via a selected bit switch of another group (e.g., 256 or fewer bit switches based on one given column address), so that the data width of the memory 101 is limited to be equal to 256 according to the 256 first sense amplifiers. When the control signals SB0 - SB4 are 0 / 0 / 0 / 1 / 1, 512 of the M second sense amplifiers are electrically coupled to 512 first sense amplifiers via another selected bit switch (e.g., 512 or fewer bit switches based on one given column address), so that the data width of the memory 101 is limited to be equal to 512 according to the 512 first sense amplifiers. When the control signals SB0 - SB4 are 0 / 0 / 1 / 0 / 0, 1024 of the M second sense amplifiers are electrically coupled to 1024 first sense amplifiers via another selected bit switch (e.g., 1024 or fewer bit switches based on one given column address), so that the data width of the memory 101 is limited to be equal to 1024 according to the 1024 first sense amplifiers. When the control signals SB0 - SB4 are 0 / 0 / 0 / 0 / 0, 64 of the M second sense amplifiers are electrically coupled to 64 first sense amplifiers via a selected bit switch (e.g., 64 or fewer bit switches based on one given column address), so that the data width of the memory 101 is limited to be equal to 64 according to the 64 first sense amplifiers. Further, the present invention is not limited to the configuration of the memory 101 including M second sense amplifiers and the control signals SB0 - SB4 shown in FIG. 7. Furthermore, the present invention is also not limited to the number of the control signals SB0 - SB4, that is, the present invention can have a number of control signals less than or more than the number of the control signals SB0 - SB4.

Table 1

[0056] Also, refer to FIG. 8. FIG. 8 is a diagram showing a memory 801 according to another embodiment of the present invention. The difference between the memory 801 and the memory 101 is that the memory 801 includes four memory banks B0 - B3, and each memory bank of the memory banks B0 - B3 is exactly the cell array of the memory 101. However, the present invention is not limited to the memory 801 including four memory banks B0 - B3 (that is, the memory 801 can include a plurality of memory banks). Also, for the sake of simplicity, the M second sense amplifiers BLSA and the N first sense amplifiers DLSA are not shown in FIG. 8.

[0057] As shown in Table 2 and FIG. 8, when the control signals SB0 - SB4 are 0 / 0 / 0 / 1 / 0, 256 second sense amplifiers of a specific memory bank of the memory 801 can be electrically coupled to 256 first sense amplifiers by the control signals SB0 - SB4. Therefore, 256 - bit data can be read from a specific memory bank of the memory 801 by the first alignment circuit 1011 via 256 connected second sense amplifiers and 256 first sense amplifiers, or written into a specific memory bank of the memory 801 by the first alignment circuit 1011 via 256 connected second sense amplifiers and 256 first sense amplifiers. A specific memory bank of the memory 801 can be selected by another signal such as a bank selection signal. That is, as shown in Table 2, the data width of the selected memory bank of the memory 801 can be adjusted to be equal to 256 according to 256 first sense amplifiers. Also, since the four memory banks B0 - B3 are independent of each other, the data width of the memory 801 (that is, the width of the I / O data bus of the memory 801) is also equal to 256. Also, in another embodiment, both the data width of the controller 105 and the data width of the DFI bus are equal to 256 according to the control signals SB0 - SB4 (0 / 0 / 0 / 1 / 0).

[0058] Also, for the other data widths of each memory bank of the memory 801 corresponding to the control signals SB0 - SB4 (0 / 0 / 1 / 0 / 0), (0 / 0 / 0 / 1 / 1), (0 / 0 / 0 / 0 / 1), (0 / 0 / 0 / 0 / 0) and the other data width of the memory 801, Table 2 can be referred to, and thus, for the sake of brevity, further description thereof is omitted. Also, the present invention is not limited to the configuration of the control signals SB0 - SB4 shown in FIG. 8.

Table 2

[0059] Also, refer to FIG. 9. FIG. 9 is a diagram showing a memory 901 according to another embodiment of the present invention. The difference between the memory 901 and the memory 801 is that the memory banks B0 and B1 are included in the bank group BG0, and the memory banks B2 and B3 are included in the bank group BG1. However, the present invention is not limited to the bank group BG0 including the memory banks B0 and B1 and the bank group BG1 including the memory banks B2 and B3. For example, all the banks B0, B1, B2, and B3 may be grouped as the bank group BGX.

[0060] Taking the bank group BG0 as an example, the first set of sense amplifiers is coupled to the data lines, the second set of sense amplifiers is coupled to the data lines, the first set of sense amplifiers corresponds to the memory bank B0 and is configured to output a first plurality of data in parallel, the second set of sense amplifiers corresponds to the memory bank B1 and is configured to output a second plurality of data in parallel, and the first set of sense amplifiers and the second set of sense amplifiers are exactly the aforementioned first sense amplifier (i.e., DLSA). Also, the third set of sense amplifiers is connected to the bit lines and is disposed between the memory bank B0 and the first set of sense amplifiers, the fourth set of sense amplifiers is connected to the bit lines and is disposed between the memory bank B1 and the second set of sense amplifiers, and the third set of sense amplifiers and the fourth set of sense amplifiers are exactly the aforementioned second sense amplifier (i.e., BLSA).

[0061] Therefore, as shown in Table 3 and FIG. 9, when the control signals SB0 - SB4 are 0 / 1 / 0 / 1 / 0, 128 second sense amplifiers corresponding to each memory bank of a specific bank group (for example, bank group BG0) are electrically coupled by the control signals SB0 - SB4 to 128 first sense amplifiers corresponding to each memory bank of the specific bank group. Thus, (the first alignment circuit 1011 reads 128 - bit data out of 256 - bit data from one memory bank of the specific bank group through 128 connected second sense amplifiers and 128 first sense amplifiers corresponding to the one memory bank, and reads another 128 - bit data out of 256 - bit data from another memory bank of the specific bank group through another 128 connected second sense amplifiers and another 128 first sense amplifiers corresponding to the another memory bank, so) 256 - bit data can be read from the specific bank group by the first alignment circuit 1011 through 256 connected second sense amplifiers and 256 first sense amplifiers, or (the first alignment circuit 1011 writes 128 - bit data out of 256 - bit data to one memory bank of the specific bank group through 128 connected second sense amplifiers and 128 first sense amplifiers corresponding to the one memory bank, and writes another 128 - bit data out of 256 - bit data to another memory bank of the specific bank group through another 128 connected second sense amplifiers and another 128 first sense amplifiers corresponding to the another memory bank, so) 256 - bit data can be written to the specific bank group by the first alignment circuit 1011 through 256 connected second sense amplifiers and 256 first sense amplifiers. That is, as shown in Table 3, the data width of each memory bank of a specific bank group is limited to be equal to 128 according to 128 first sense amplifiers.Also, since memory banks B0 and B1 are included in bank group BG0, the data width of memory 901 (i.e., the width of the I / O data bus of memory 901) is equal to the sum of the data widths of all memory banks in a specific bank group (i.e., 128 + 128 = 256). And the available banks will be reduced by half compared to FIG. 8.

[0062] Also, the other data widths of each memory bank of memory 901 corresponding to control signals SB0 - SB4 (0 / 1 / 0 / 0 / 0), (0 / 1 / 0 / 0 / 1), (0 / 1 / 0 / 1 / 1), (0 / 0 / 0 / 0 / 0) and the other data width of memory 901 can be referred to Table 3. Therefore, for the sake of brevity, further description thereof is omitted. Also, the present invention is not limited to the configuration of control signals SB0 - SB4 shown in FIG. 9.

Table 3

[0063] Next, refer to FIG. 10. FIG. 10 is a diagram showing that chip 1002 is connected to chip 1004 using a multilayer configuration within substrate 1006 according to another embodiment of the present invention. Chip 1002 can be referred to as logic circuit 102 in FIG. 7, and chip 1004 can also be referred to as memory 101 in FIG. 7. Chip 1002 and chip 1004 have microbumps (u-bumps) or any type of pillars (such as copper pillars, etc.) at their bottoms. As shown in FIG. 10(a), due to the larger width of the memory's data input / output bus or the larger number of u-bumps or pillars, when the substrate 1006 is small and layer 1 tracks 1008 in substrate 1006 are not sufficient for all connections between chip 1002 and chip 1004, simultaneously, for example, layer 2 tracks 1010, layer 3 tracks 1012, and layer 4 tracks 1014 are additionally provided within substrate 1006 to complete all connections between chip 1002 and chip 1004. Here, layer 1 tracks 1008, layer 2 tracks 1010, layer 3 tracks 1012, and layer 4 tracks 1014 are located at different depths within substrate 1006. Also, the present invention is not limited to the use of layer 1 tracks 1008, layer 2 tracks 1010, layer 3 tracks 1012, and layer 4 tracks 1014 to complete all connections between chip 1002 and chip 1004. That is, the present invention can use more than two layer tracks to complete all connections between chip 1002 and chip 1004. Also, the u-bumps or pillars under chip 1002 can be assigned to multiple regions (for example, region 1, region 2, region 3, region 4) according to the number of u-bumps (or pillars) and the size of substrate 1006. The u-bumps in region 1 are closest to chip 1002. The u-bumps in region 1 use layer 1 tracks to complete the connection between chip 1002 and chip 1004. Also, as shown in FIG. 10(b), the u-bumps in region 1 can be assigned to row 1, row 2 (or more than two rows).Similarly, the u-bumps in region 2 are the second closest to chip 1004. The u-bumps in region 2 complete the connection between chip 1002 and chip 1004 using the tracks in layer 2. Also, as shown in FIG. 10(b), the u-bumps in region 2 can be assigned to row 3, row 4 (or more than two rows). Also, for the configuration of the u-bumps in region 3 and the configuration of the u-bumps in region 4, reference can be made to the above-described configuration of the u-bumps in region 1 or region 2. Therefore, for the sake of brevity, further description thereof is omitted. Similarly, as shown in FIGS. 10(a) and 10(b), the u-bumps under chip 1004 can also be assigned to a plurality of regions (for example, region 1, region 2, region 3, region 4) according to the size of substrate 1006. For the configuration of the u-bumps under chip 1004, reference can be made to the configuration of the u-bumps under chip 1002. Therefore, for the sake of brevity, further description thereof is also omitted.

[0064] Also, as shown in FIG. 11, via 1016 connects a second-level track (e.g., layer 2 track 1010, the upwardly extending portion of layer 3 track 1012 within the second-level track, and / or the upwardly extending portion of layer 4 track 1014 within the second-level track, etc.) to a first-level track (e.g., layer 1 track 1008, etc.), via 1018 connects a third-level track (e.g., layer 2 track 1010, and / or the upwardly extending portion of layer 4 track 1014 within the third-level track, etc.) to the second-level track, and via 1020 connects a fourth-level track (e.g., layer 3 track 1012, etc.) to the third-level track. The position of the upwardly extending portion of layer 3 track 1012 is outside the position of the upwardly extending portion of layer 2 track 1010. Otherwise, as shown in FIG. 12, if layer 3 track 1012 is used instead of layer 2 track 1012 to connect some of the u-bumps in region 2, the layer 2 track 1010 passed by the aforementioned layer 3 track 1010 becomes unavailable (indicated by the cross marks in FIG. 12), and as a result, the number of available tracks of layer 2 track 1010 decreases. Similarly, the position of the upwardly extending portion of layer 4 track 1014 is outside the position of the upwardly extending portion of layer 3 track 1012. Otherwise, as shown in FIG. 13, the layer 3 track 1012 passed by the aforementioned layer 4 track 1014 becomes unavailable (indicated by the cross marks in FIG. 13), and as a result, the number of available tracks of layer 3 track 1012 decreases.

[0065] Next, the present invention shows (but is not limited to) parameter examples of two designed embodiments. Design embodiment 1 uses four-layer tracks (layer 1 track, layer 2 track, layer 3 track, layer 4 track), and design embodiment 2 uses nine-layer tracks (layer 1 track, layer 2 track, layer 3 track, layer 4 track, layer 5 track, layer 6 track, layer 7 track, layer 8 track, layer 9 track).

[0066] Design Embodiment 1 Table 4 shows the parameters of the designed Embodiment 1. "u-bump pitch 1" corresponds to the pitch of the u-bumps in Region 1, and "line pitch 1" corresponds to the pitch of the layer 1 tracks. "u-bump pitch 2" corresponds to the pitch of the u-bumps in Region 2, Region 3, and Region 4. "Line pitch 2" corresponds to the pitch of the layer 2 tracks, layer 3 tracks, and layer 4 tracks. The pitch of the vias connecting the first-level tracks and the second-level tracks is represented as "via 12 pitch", "via 23 pitch" represents the pitch of the vias connecting the second-level tracks and the third-level tracks, and "via 34 pitch" represents the pitch of the vias connecting the third-level tracks and the fourth-level tracks.

Table 4

[0067] Table 5 is shown as follows. The designed Embodiment 1 has 407 u-bumps. The via pitch corresponding to the layer 1 tracks and the layer 2 tracks means the via 12 pitch, the via pitch corresponding to the layer 3 tracks means the via 23 pitch, and the via pitch corresponding to the layer 4 tracks means the via 34 pitch.

Table 5

[0068] Designed Embodiment 2 Table 6 shows the parameters of the designed Embodiment 2 having 9-layer tracks and 400 u-bumps in the substrate. Also, the number of lines of each layer track of layer 1 - layer 8 tracks is 46, and the number of lines of layer 9 track is 32. Table 6 is shown as follows, "u-bump pitch" corresponds to the pitch of the u-bumps in Region 1 - Region 9, "line pitch" corresponds to the pitch of layer 1 - layer 9 tracks, and "via pitch" corresponds to the pitch of via 12, via 23, via 34, via 45, via 56, via 67, via 78, via 89 (where via 12 connects the first-level track and the second-level track, via 23 connects the second-level track and the third-level track, via 34 connects the third-level track and the fourth-level track, via 45 connects the fourth-level track and the fifth-level track, via 56 connects the fifth-level track and the sixth-level track, via 67 connects the sixth-level track and the seventh-level track, via 78 connects the seventh-level track and the eighth-level track, and via 89 connects the eighth-level track and the ninth-level track).

Table 6

[0069] Furthermore, the present invention also improves the refresh method of conventional memories. Refer to FIG. 14 of a conventional DRAM and its controller. FIG. 14(a) is a diagram showing a logic circuit 1402 and a DRAM (e.g., DDR3 to DDR5 or low-power DDR3 to DDR5) 1404, and FIG. 14(b) is an access command or read (R) / write (W) command (for the purpose of simplicity, this includes an active command - read / write command - precharge command), read (R) / write (W) time 1, refresh command RFC, and another R / W time 2 according to the prior art, which is a timing diagram of the DRAM 1404 corresponding thereto. As shown in FIG. 14(a), a refresh counter 14026 in a DRAM controller 14022 of the logic circuit 1402 counts a DRAM refresh interval tREFI according to the number of clocks (clk), and issues an auto-refresh command RFC when the number of clocks (clk) reaches a target according to the DRAM specification, and the auto-refresh command RFC is transmitted to the DRAM 1404 via the PHY 14024. For example, when 1 clk = 1 ns, tREFI = 4 us means every 4K clk (4 us), and tREFI = 8 us means every 8K clk (8 us).

[0070] Also, as shown in FIG. 14(a), while the refresh counter 14042 in the DRAM 1404 is receiving the auto-refresh command RFC, it transmits the next word line address for which a refresh needs to be executed. When a self-refresh command is issued, the refresh counter 14042 also counts the DRAM refresh interval tREFI according to the number of clocks (clk), and needs to issue an internal refresh when the number of clocks (clk) reaches a target according to the DRAM specification. For example, when 1 clk = 1 ns, tREFI = 4 us means every 4K clk (4 us), and tREFI = 8 us means every 8K clk (8 us).

[0071] The refresh counter 14042 counts the WL addresses in the auto-refresh mode or the self-refresh mode. The refresh counter 14042 further counts the DRAM refresh intervals in the self-refresh mode. On the other hand, the refresh counter 14026 in the DRAM controller 14022 does not count the WL addresses in the auto-refresh mode or the self-refresh mode. However, the refresh counter 14026 in the DRAM controller 14022 can count the DRAM refresh intervals in the auto-refresh mode.

[0072] Also, as shown in FIG. 14(b) of the conventional DRAM timing diagram, after issuing a read (R) / write (W) command, a R / W time 1, which is the time required to read from / write to the DRAM 1404, is needed. Thereafter, an idle time id1 exists between the R / W time 1 and the refresh command RFC. Next, the time tRFC is the time for refresh after receiving the refresh command, and then, a next idle time id2 exists between the time tRFC and the next read (R) / write (W) command. Similarly, a R / W time 2 is needed for further read or write to the DRAM. Therefore, an interval period (id1 + tRFC + id2) exists between the R / W time 1 and the R / W time 2.

[0073] Next, refer to FIG. 15 of the conventional pseudo-SRAM and its controller. FIG. 15(a) is a diagram showing a pseudo-SRAM controller 1502 and a pseudo-SRAM 1504, and FIG. 15(b) is a read (R) / write (W) command (for simplicity, this also includes an active command - read / write command - precharge command) according to the prior art, time trow1, R / W time 1, another read (R) / write (W) command, another time trow1, and a timing diagram of the pseudo-SRAM 1504 corresponding to another R / W time 2. As shown in FIG. 15(a), the difference between the DRAM controller 14022 and the pseudo-SRAM controller 1502 is that there is no refresh counter in the pseudo-SRAM controller 1502, and as a result, the pseudo-SRAM controller 1502 does not need to issue a refresh command to the pseudo-SRAM 1504. When the power is turned on, the refresh counter 15042 in the pseudo-SRAM 1504 starts counting and sends an internal refresh command and the next word line address that needs to perform an internal refresh to avoid defects in the memory cells in the pseudo-SRAM 1504. However, as shown in FIG. 15(b), when the pseudo-SRAM 1504 receives a read (R) / write (W) command from the pseudo-SRAM controller 1502, it needs to wait for a time trow1 assuming that a refresh has just been performed before executing the read / write command, thus causing additional read / write latency and longer read / write cycle time. Here, there is an idle time id before receiving the next read (R) / write (W) command from the pseudo-SRAM controller 1502, and another time trow1 is also required before executing that another read / write command.

[0074] Next, refer to FIG. 16. FIG. 16(a) is a diagram showing a logic circuit 1602 and a DRAM (e.g., DDR2, 3, 4, 5, or low-power DDR2, 3, 4) 1604, and FIG. 16(b) is a timing diagram of the DRAM 1604 corresponding to read (R) / write (W) commands 1 to 3, R / W times 1 to 3, and the signal of the output pin BUSY of the DRAM according to an embodiment of the present invention. As shown in FIG. 16(a), there is no refresh counter in the DRAM controller 16022 of the logic circuit 1602 of the present invention, and thus it does not issue a refresh command to the DRAM 1604. However, the refresh counter 16042 is still inside the DRAM 1604, and the DRAM 1604 can calculate the time to automatically perform a refresh according to the number of clocks (clk) counted by the refresh counter 16042. The difference between the conventional DRAM 1404 and this DRAM 1604 is that the DRAM 1604 has an additional output pin BUSY. For example, during the refresh period of the DRAM 1604 (or while the DRAM 1604 is performing a refresh operation), the signal of the output pin BUSY is active (e.g., the signal of the output pin BUSY becomes high or "1"), and when the DRAM 1604 is not performing a refresh operation, the signal of the output pin BUSY is inactive (e.g., the signal of the output pin BUSY becomes low or "0"). In addition to the output pin BUSY, any configuration that can provide a handshake method executed between the DRAM and the logic circuit 1602 also falls within the scope of the present invention. Also, since the DRAM 1604 can automatically perform a refresh, the DRAM controller 16022 of the logic circuit 1602 no longer needs to control the refresh of the DRAM 1604.

[0075] Therefore, as shown in Fig. 16(b), after the read (R) / write (W) command 1 is issued by the DRAM controller 16022, an R / W time 1 is required to read from / write to the DRAM 1604. On the other hand, since the DRAM 1604 does not execute a refresh operation at this time, the signal of the output pin BUSY goes low, and the DRAM controller 16022 can issue the next read (R) / write (W) command 2 to the DRAM 1604 according to the state (low) of the signal of the output pin BUSY. Then, the R / W time 2 is another time for reading from / writing to the DRAM 1604. As shown in Fig. 16(b), when the DRAM 1604 needs a refresh during the R / W time 2, the signal of the output pin BUSY goes high, and the DRAM controller 16022 stores another read (R) / write (W) command 3 in an additional register (e.g., a FIFO, not shown in Fig. 16(a)) of the logic circuit 1602, and issues a NOP (No Operation) while the signal of the output pin BUSY is high. After that, as shown in Fig. 16(b), when the signal of the output pin BUSY goes low, the DRAM controller 16022 can issue the stored read (R) / write (W) command 3 to the DRAM 1604, and the R / W time 3 is another time for reading from / writing to the DRAM 1604. Therefore, the TR time for refresh after the DRAM controller in Fig. 14(b) of the conventional DDRAM receives a refresh command becomes unnecessary.

[0076] Next, refer to FIG. 17. FIG. 17(a) is a diagram showing a pseudo SRAM controller 1702 and a pseudo SRAM (or other memory having DRAM memory cells therein) 1704 according to the present invention, and FIG. 17(b) is a timing diagram of the pseudo SRAM 1704 corresponding to read (R) / write (W) commands 1 to 4, R / W times 1 to 4, and the signal of the output pin BUSY of the pseudo SRAM according to an embodiment of the present invention. Similar to FIG. 16(a), as shown in FIG. 17(a), since there is a refresh counter 17042 in the pseudo SRAM 1704 and there is no refresh counter in the pseudo SRAM controller 1702, the pseudo SRAM 1704 can automatically execute a refresh according to the number of clocks (clk) counted by the refresh counter 17042. Also, similar to the DRAM 1604, the pseudo SRAM 1704 also has an additional output pin BUSY for notifying the pseudo SRAM controller 1702 whether the pseudo SRAM 1704 is in a refresh operation. Further, since the pseudo SRAM 1704 can automatically execute a refresh and notify its refresh state to the pseudo SRAM controller 1702 via the additional output pin BUSY, the pseudo SRAM 1704 does not need to wait for the time trow1 (shown in FIG. 15(b)), thereby causing neither extra R / W latency nor a longer R / W cycle time.

[0077] As shown in FIG. 17(b), after a read (R) / write (W) command 1 is issued by the pseudo SRAM controller 1702, a R / W time 1 is required to read from / write to the pseudo SRAM 1704. However, the time trow1 is not required. On the other hand, at this point, the pseudo SRAM 1704 does not perform a refresh operation, the signal of the output pin BUSY goes low, and the pseudo SRAM controller 1702 can issue the next read (R) / write (W) command 2 to the pseudo SRAM 1704 according to the state (low) of the signal of the output pin BUSY. And the R / W time 2 is another time for reading from / writing to the pseudo SRAM 1704, but the time trow1 is not required. Then, when the signal of the output pin BUSY is still low, the pseudo SRAM controller 1702 can issue the next read (R) / write (W) command 3 to the pseudo SRAM 1704, and the R / W time 3 is another time for reading from / writing to the pseudo SRAM 1704. As shown in FIG. 17(b), during the R / W time 3, the pseudo SRAM 1704 requires a refresh, so the signal of the output pin BUSY goes high, which results in the pseudo SRAM controller 1702 storing the next read (R) / write (W) command 4 in an additional register (e.g., FIFO) and issuing a NOP (No Operation) while the signal of the output pin BUSY is high. Then, as shown in FIG. 17(b), when the signal of the output pin BUSY goes low, the pseudo SRAM controller 1702 can issue the stored read (R) / write (W) command 4 to the pseudo SRAM 1704, and the R / W time 4 is another time for reading from / writing to the pseudo SRAM 1704. Therefore, the TR time for refresh after receiving a refresh command from the DRAM controller in FIG. 14(b) of the conventional DDRAM becomes unnecessary.

[0078] In short, by applying a multilayer configuration that connects a memory and a logic circuit to a small substrate as compared with the prior art, the area of the small substrate can be efficiently used, and the signal of an additional output pin for notifying a refresh state can efficiently shorten the R / W latency time during the refresh of the DRAM.

[0079] Although the present invention has been illustrated and described with reference to the embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. 1. A memory chip comprising: Memory bank, I / O data bus, and a first plurality of sense amplifiers between the memory bank and the I / O data bus, the first plurality of sense amplifiers configured to output a first plurality of data in parallel to the I / O data bus; having The memory chip does not have parallel-to-serial or serial-to-parallel circuitry; Memory chip.

2. 10. The memory chip of claim 1, wherein the memory chip sends a handshake signal to selectively indicate whether the memory chip will not perform a refresh operation.

3. 3. The memory chip of claim 2, wherein the memory chip further comprises an additional output pin, and the handshake signal is sent to a memory controller via the additional output pin, the memory controller being physically separate from the memory chip.

4. 3. The memory chip of claim 2, further comprising a refresh counter, the handshake signal being selectively activated according to a number of clocks counted by the refresh counter.

5. 3. The memory chip of claim 2, wherein the handshake signal is active when the memory chip is performing the refresh operation, and the handshake signal is inactive when the memory chip is not performing the refresh operation.

6. 2. The memory chip of claim 1, wherein a width of said I / O data bus is equal to a width of said first plurality of data output in parallel by said first plurality of sense amplifiers.

7. 2. The memory chip of claim 1, further comprising a plurality of transceivers between the first plurality of sense amplifiers and the I / O data bus, the transceivers receiving the first plurality of data in parallel from the first plurality of sense amplifiers and transmitting the first plurality of data in parallel to the I / O data bus.

8. 8. The memory chip of claim 7, further comprising a second plurality of sense amplifiers between the memory banks and the first plurality of sense amplifiers, the second plurality of sense amplifiers having M sense amplifiers and connected to bit lines of the memory chip, and the first plurality of sense amplifiers having N sense amplifiers and connected to data lines of the memory chip, both N and M being positive integers and M being greater than or equal to N.

9. 9. The memory chip of claim 8, wherein a portion of the second plurality of sense amplifiers is selectively coupled to the first plurality of sense amplifiers, the portion of the second plurality of sense amplifiers outputs the first plurality of data in parallel to the first plurality of sense amplifiers, and the number of sense amplifiers within the portion of the second plurality of sense amplifiers is equal to N.

10. 10. The memory chip of claim 9, wherein the portion of the second plurality of sense amplifiers are selectively coupled to the first plurality of sense amplifiers according to control signals input to the memory chip.

11. 11. The memory chip of claim 10, wherein the control signal comprises a plurality of signal bits configured to be stored in a register of the memory chip.

12. 11. The memory chip of claim 10, further comprising a plurality of bit switches between the first plurality of sense amplifiers and the second plurality of sense amplifiers, the plurality of bit switches electrically connecting to the portion of the second plurality of sense amplifiers and the first plurality of sense amplifiers according to the control signals.

13. 1. A memory chip comprising: Multiple memory banks, Data line, a plurality of sets of sense amplifiers coupled to the data lines, each set of sense amplifiers corresponding to one of the plurality of memory banks and configured to output a plurality of data in parallel; and I / O data bus, having the memory chip has no parallel-to-serial or serial-to-parallel circuitry, and the memory chip transmits a handshake signal to selectively indicate whether the memory chip will not perform a refresh operation; Memory chip.

14. 14. The memory chip of claim 13, wherein the memory chip further comprises an additional output pin, and wherein the handshake signals are sent to a memory controller via the additional output pin, the memory controller being physically separate from the memory chip.

15. 14. The memory chip of claim 13, wherein the handshake signal is active when the memory chip is performing the refresh operation, and the handshake signal is inactive when the memory chip is not performing the refresh operation.

16. 16. The memory chip of claim 15, further comprising a refresh counter, the handshake signals being selectively activated according to a number of clocks counted by the refresh counter.

17. the plurality of memory banks includes a first memory bank and a second memory bank; the plurality of sets of sense amplifiers includes a first set of sense amplifiers coupled to the data lines and a second set of sense amplifiers coupled to the data lines; the first set of sense amplifiers corresponds to the first memory bank and is configured to output a first plurality of data in parallel, the second set of sense amplifiers corresponds to the second memory bank and is configured to output a second plurality of data in parallel; the width of the I / O data bus is equal to the sum of the width of the first plurality of data and the width of the second plurality of data; The memory chip of claim 13.

18. The memory chip further comprises: Bit lines, a third set of sense amplifiers coupled to the bit lines and configured between the first memory bank and the first set of sense amplifiers; and a fourth set of sense amplifiers coupled to the bit lines and configured between the second memory bank and the second set of sense amplifiers; having a portion of the third set of sense amplifiers selectively coupled to the first set of sense amplifiers, the number of sense amplifiers in the portion of the third set of sense amplifiers being equal to the number of sense amplifiers in the first set of sense amplifiers; a portion of the fourth set of sense amplifiers selectively coupled to the second set of sense amplifiers, the number of sense amplifiers in the portion of the fourth set of sense amplifiers being equal to the number of sense amplifiers in the second set of sense amplifiers; 20. The memory chip of claim 17.

19. 20. The memory chip of claim 18, wherein the portions of the third set of sense amplifiers are selectively coupled to the first set of sense amplifiers in accordance with control signals input to the memory chip, and the portions of the fourth set of sense amplifiers are selectively coupled to the second set of sense amplifiers in accordance with the control signals.

20. 1. A memory controller for a DRAM system, the DRAM system having a system bus interface and memory chips, the memory chips having an I / O data bus, the memory controller comprising: a control circuit configured to couple to the system bus interface; a physical layer circuit coupled to the control circuit and configured to receive a first plurality of data in parallel from the I / O data bus of the memory chip; having The physical layer circuit of the memory controller does not have a serial-to-parallel circuit or a parallel-to-serial circuit; Memory controller.

21. 21. The memory controller of claim 20, wherein the physical layer circuitry is further configured to output a second plurality of data in parallel to the I / O data bus of the memory chip.

22. 21. The memory controller of claim 20, wherein the memory controller receives a handshake signal from the memory chip to selectively inform the memory controller whether the memory chip does not perform a refresh operation.

23. 23. The memory controller of claim 22, wherein the handshake signals are active when the memory chips are performing the refresh operations, and the handshake signals are inactive when the memory chips are not performing the refresh operations.

24. 24. The memory controller of claim 23, wherein when the handshake signal is active, the memory controller holds an access command intended to read data from or write data to the memory chip.

25. 25. The memory controller of claim 24, wherein the memory controller transmits the held access command to the memory chip after the handshake signal becomes inactive.

26. A system bus interface; a memory controller having a controller I / O data bus coupled to a second group of bumps, the memory controller coupled to the system bus interface, the memory controller further having a physical layer, the physical layer of the memory controller having no parallel-to-serial or serial-to-parallel circuitry; a memory chip having a memory I / O data bus coupled to a first group of bumps, the memory chip being coupled to the memory controller, the memory chip having no parallel-to-serial or serial-to-parallel circuitry; a substrate, the memory controller and the memory chips being disposed on the substrate and spaced apart from each other in a horizontal direction; A memory system having:

27. 27. The memory system of claim 26, wherein the plurality of first bump groups are arranged side by side and the plurality of second bump groups are arranged side by side, each bump group of the plurality of first bump groups is connected to a corresponding bump group of the plurality of second bump groups via a corresponding track in the substrate, and the tracks connecting the plurality of first bump groups to the plurality of second bump groups do not intersect each other.

28. 1. A memory chip comprising: a first set of memory banks; an I / O data bus for the memory chip electrically coupled to the first set of memory banks, each memory bank transmitting data of a first predetermined width in parallel onto the I / O data bus, the width of the I / O data bus being equal to the sum of the first predetermined width data of each memory bank of the first set of memory banks, the first predetermined width being programmable according to a set of control signals; having There is no parallel-to-serial or serial-to-parallel circuitry within the memory chip; Memory chip.

29. 30. The memory chip of claim 28, further comprising a second set of memory banks, each memory bank of the second set of memory banks transmitting data of a second predetermined width in parallel to the I / O data bus, the width of the I / O data bus being selectively equal to the sum of the first predetermined width data of each memory bank of the first set of memory banks or the sum of the second predetermined width data of each memory bank of the second set of memory banks based on a selection signal.

30. 30. The memory chip of claim 29, wherein the second predetermined width is programmable according to the set of control signals when the width of the I / O data bus is equal to the sum of the second predetermined width data of each memory bank of the second set of memory banks.

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