Memory system and semiconductor storage device

Abstract

To provide a memory system and a semiconductor storage device to improve electrical characteristics of the memory system.SOLUTION: In one embodiment, a memory system includes a first substrate, a controller, and a semiconductor storage device. The semiconductor storage device includes a second substrate and a plurality of semiconductor memory chips, and a plurality of connecting terminals. Each of the plurality of semiconductor memory chips has only a plurality of first terminals for one channel that is constituted by a predetermined number of terminals as terminals capable of transferring data signals or timing signals. The plurality of connecting terminals has only a plurality of second terminals for the one channel that is constituted by the predetermined number of terminals as terminals capable of transferring the data signals and the timing signals.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system and a semiconductor memory device.

Background Art

[0002] A memory system having a substrate, a controller mounted on the substrate, and a semiconductor memory device mounted on the substrate is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment aims to improve the electrical characteristics of a memory system.

Means for Solving the Problems

[0005] One embodiment includes a first substrate, a controller, and a semiconductor memory device. The controller is mounted on the first substrate. The semiconductor memory device is mounted on the first substrate. The semiconductor memory device includes a second substrate, a sealing member, a plurality of semiconductor memory chips, a plurality of bonding wires, and a plurality of connection terminals. The second substrate includes a first surface and a second surface located on the side opposite to the first surface. The sealing member covers the first surface when viewed in the thickness direction of the second substrate. The plurality of semiconductor memory chips are disposed between the first surface and the sealing member. The plurality of bonding wires connect the first surface and the plurality of semiconductor memory chips. The plurality of connection terminals are provided on the second surface and connected to the first substrate. Each of the plurality of semiconductor memory chips has only a plurality of first terminals for one channel, which are composed of a predetermined number of terminals, as terminals capable of transferring a data signal or a timing signal. The plurality of connection terminals include only a plurality of second terminals for one channel, which are composed of the predetermined number of terminals, as terminals capable of transferring the data signal or the timing signal.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

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Figure 6

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Figure 12

Embodiments for Carrying Out the Invention

[0007] Hereinafter, a memory system and a semiconductor memory device according to embodiments will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. And redundant descriptions of those components may be omitted. In the present application, "parallel", "orthogonal", or "the same" may each include the case of being "substantially parallel", "substantially orthogonal", or "substantially the same". In the present application, "connection" is not limited to mechanical connection and may include electrical connection. That is, "connection" is not limited to the case of being directly connected to an object and may include the case of being connected to the object with another member interposed therebetween.

[0008] In the present application, the +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as follows. The +X direction, -X direction, +Y direction, and -Y direction are directions parallel to the first surface 11a (see FIG. 1) of the substrate 11 described later. The +X direction is the direction from the controller 12 described later toward the NAND package 14 (see FIG. 1). The -X direction is the direction opposite to the +X direction. When the +X direction and the -X direction are not distinguished, it is simply referred to as the "X direction". The +Y direction and the -Y direction are directions intersecting (for example, orthogonal to) the X direction. The +Y direction is the direction from the third end portion 14e3 to the fourth end portion 14e4 of the NAND package 14 described later (see FIG. 1). The -Y direction is the direction opposite to the +Y direction. When the +Y direction and the -Y direction are not distinguished, it is simply referred to as the "Y direction".

[0009] The +Z direction and the -Z direction are directions that intersect (e.g., are orthogonal) to the X direction and the Y direction, and are the thickness direction of the substrate 11. The +Z direction is the direction from the second surface 11b to the first surface 11a of the substrate 11 (see FIG. 1). The -Z direction is the direction opposite to the +Z direction. When the +Z direction and the -Z direction are not distinguished, it is simply referred to as the "Z direction". The X direction is an example of the "first direction". Hereinafter, the +Z direction side may be referred to as "up", and the -Z direction side may be referred to as "down". However, these expressions are for convenience of explanation and do not define the direction of gravity.

[0010] (First Embodiment) <A1. Overall Configuration of Memory System> Referring to FIGS. 1 to 6, the memory system 1 of the first embodiment will be described. The memory system 1 is a storage device such as, for example, an SSD (Solid State Drive). The memory system 1 is connected to a host device and used as a storage device of the host device. The host device is a personal computer, a mobile device, a video recorder, an in-vehicle device, etc., but is not limited to these examples.

[0011] FIG. 1 is a perspective view showing the memory system 1. The memory system 1 has, for example, a substrate 11, a controller 12, a DRAM (Dynamic Random Access Memory) 13, and a plurality of NAND-type flash memories 14 (hereinafter referred to as "NAND packages 14" for convenience).

[0012] The substrate 11 is a plate member along the X and Y directions. The substrate 11 is a printed circuit board and includes an insulating base material 11i and a wiring pattern 11w provided on the insulating base material 11i (see FIG. 6). The insulating base material 11i is an insulating rigid member formed of an insulating material such as glass epoxy resin or polyimide. The wiring pattern 11w is a conductive part provided on the surface or inside of the insulating base material 11i. The substrate 11 has a first surface 11a and a second surface 11b located on the side opposite to the first surface 11a. The first surface 11a is a surface facing the +Z direction. The second surface 11b is a surface facing the -Z direction. Each of the first surface 11a and the second surface 11b extends in the X and Y directions. The substrate 11 is an example of the "first substrate".

[0013] The end portion of the substrate 11 on the -X direction side has a connection connector 11c. The connection connector 11c is a connection part connectable to the connector of the host device. The connection connector 11c has a plurality of metal terminals connectable to the connector of the host device.

[0014] The controller 12 is a component that comprehensively controls the entire memory system 1. The controller 12 is, for example, a semiconductor package including a SoC (System on a Chip) in which a host interface circuit for a host device, a control circuit for controlling the DRAM 13, and a control circuit for controlling a plurality of NAND packages 14 are integrated on one semiconductor chip. The controller 12 is, for example, mounted on the first surface 11a of the substrate 11.

[0015] The DRAM 13 is a semiconductor package including a volatile semiconductor memory chip. The DRAM 13 is a data buffer in which write target data received from the host device or read target data read from the NAND package 14 is temporarily stored. The DRAM 13 is, for example, mounted on the second surface 11b of the substrate 11. Note that the DRAM 13 may be provided in the controller 12 instead of being provided on the substrate 11.

[0016] The NAND package 14 is a semiconductor package including non-volatile semiconductor memory chips. A plurality of NAND packages 14 are mounted separately, for example, on the first surface 11a and the second surface 11b of the substrate 11. For example, the plurality of NAND packages 14 includes four NAND packages 14 (the first to fourth NAND packages 14A to 14D) mounted on the first surface 11a of the substrate 11. The first to fourth NAND packages 14A to 14D are arranged side by side in the X direction, for example. Each NAND package 14 is an example of a "semiconductor memory device".

[0017] In the present embodiment, when viewed from the Z direction, the NAND package 14 has a rectangular shape elongated in the Y direction. The NAND package 14 has, for example, a first end 14e1, a second end 14e2, a third end 14e3, and a fourth end 14e4. The first end 14e1 and the second end 14e2 are a pair of ends divided in the short side direction (X direction) of the NAND package 14. The third end 14e3 and the fourth end 14e4 are a pair of ends divided in the long side direction (Y direction) of the NAND package 14.

[0018] In the present embodiment, the width W1 in the Y direction of the NAND package 14 is larger than the width W2 in the X direction of the NAND package 14. For example, the width W1 in the Y direction of the NAND package 14 is 1.5 times or more the width W2 in the X direction of the NAND package 14. In an example of the NAND package 14, the width W1 is 10 mm and the width W2 is 5 mm. In another example of the NAND package 14, the width W1 is 15 mm and the width W2 is 10 mm. The NAND package 14 has a plurality of connection terminals 27 as described later (see FIG. 5). The center-to-center distance PT of the plurality of connection terminals 27 is, for example, 0.5 mm to 0.8 mm.

[0019] <A2. Types of signals transmitted and received> FIG. 2 is a diagram showing the connection relationship between the controller 12 and the NAND package 14. In FIG. 2, for convenience of explanation, only one NAND package 14 is illustrated. The signals transmitted and received between the controller 12 and the NAND package 14 include, for example, an 8-bit data signal DQ (DQ0 to DQ7), a data strobe signal DQS / DQSn, a read enable signal RE / REn, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a write protect signal WPn, and a ready / busy signal R / Bn. These signals are transmitted and / or received via individual transmission lines L provided between the controller 12 and the NAND package 14.

[0020] The data signal DQ (DQ0 to DQ7) is a signal indicating the content of data transferred between the controller 12 and the NAND package 14, for example. In the present embodiment, the data signal DQ (DQ0 to DQ7) includes a signal indicating the content of data to be written to the NAND package 14 (write data), a signal indicating the content of data to be read from the NAND package 14 (read data), a signal indicating various commands, a signal indicating the address of the write destination or read destination of the data, and the like. The data signal DQ (DQ0 to DQ7) is transmitted and received via eight transmission lines L independent of each other in units of, for example, 8 bits. Note that the data signal DQ may be transmitted and received via a plurality of transmission lines L corresponding to the other number of bits in units of the other number of bits (for example, 16 bits).

[0021] The data strobe signals DQS / DQSn are strobe signals used for latching data signals DQ or outputting data signals DQ. The data strobe signals DQS / DQSn include, for example, signals in a toggle pattern (hereinafter referred to as "toggle signals"). The data strobe signals DQS / DQSn include the data strobe signal DQS and the data strobe signal DQSn. The data strobe signal DQS and the data strobe signal DQSn are a pair of signals having a complementary relationship. For example, the data strobe signal DQS is a data strobe signal of positive logic. On the other hand, the data strobe signal DQSn is a data strobe signal of negative logic having a logically inverted relationship with respect to the data strobe signal DQS.

[0022] Here, each of the data strobe signal DQS and the data strobe signal DQSn includes, for example, a write data reception strobe signal, a read data transmission strobe signal, and a read data reception strobe signal. The write data reception strobe signal is a strobe signal that is output from the controller 12 to the NAND package 14 together with write data in the write operation of write data and is used to define the timing for latching the write data in the NAND package 14. The read data transmission strobe signal is a strobe signal that is output from the controller 12 to the NAND package 14 in synchronization with a read enable signal RE / REn (or a read enable signal RE) described later in the read operation of read data and is used in the NAND package 14 to output the read data from the NAND package 14 to the controller 12 in response to the edge thereof. The read data reception strobe signal is a strobe signal that is generated in the NAND package 14 in the read operation of read data, is output from the NAND package 14 to the controller 12 together with the read data, and is used to define the timing for latching the read data in the controller 12. Each of the data strobe signal DQS and the data strobe signal DQSn is an example of a "timing signal".

[0023] The read enable signal RE / REn is a signal that enables data to be read from the NAND package 14. The read enable signal RE / REn may include, for example, a toggle signal. The read enable signal RE / REn includes the read enable signal RE and the read enable signal REn. The read enable signal RE and the read enable signal REn are a pair of signals having a complementary relationship. For example, the read enable signal RE is a positive logic read enable signal. On the other hand, the read enable signal REn is a negative logic data strobe signal having a logically inverted relationship with respect to the read enable signal RE. Each of the read enable signal RE and the read enable signal REn is an example of a "timing signal".

[0024] The chip enable signal CEn is a signal that enables selection of the target NAND package 14 from among a plurality of NAND packages 14 and is asserted when selecting the NAND package 14. The command latch enable signal CLE is a signal that enables a command output from the controller 12 to the NAND package 14 to be latched in a command register within the NAND package 14. The address latch enable signal ALE is a signal that enables an address output from the controller 12 to the NAND package 14 to be latched in an address register within the NAND package 14. Each of the chip enable signal CEn, the command latch enable signal CLE, and the address latch enable signal ALE is an example of a "status notification signal".

[0025] The write enable signal WEn is a signal that enables the transfer of data (e.g., commands or addresses) to the NAND package 14. The write protect signal WPn is a signal that is asserted when writing and erasing are prohibited. The ready / busy signal R / Bn is a signal that distinguishable indicates whether the NAND package 14 is in a ready state or a busy state. The "ready state" means that the NAND package 14 is in a state where it can receive commands from the controller 12. The "busy state" means that the NAND package 14 is in a state where it cannot receive commands from the controller 12. Each of the write enable signal WEn, the write protect signal WPn, and the ready / busy signal R / Bn is an example of a "status notification signal".

[0026] <A3.Structure of the NAND Package> Next, the structure of the NAND package 14 will be described. FIG. 3 is a cross-sectional view showing the NAND package 14. Hereinafter, the NAND package 14 mounted on the first surface 11a of the substrate 11 will be taken as a representative and described. The NAND package 14 has, for example, a substrate 21, a plurality of semiconductor memory chips 22, a plurality of adhesive films 23, an adhesive film 24, a plurality of bonding wires 25, a sealing member 26, and a plurality of connection terminals 27. Hereinafter, in order to distinguish the substrate 21 included in the NAND package 14 from the above-described substrate 11, the substrate 21 is referred to as the "package substrate 21".

[0027] (Package Substrate) The package substrate 21 is a plate member along the X direction and the Y direction. The package substrate 21 is a printed circuit board and includes an insulating base material 21i and a wiring pattern 21w. The insulating base material 21i is an insulating hard member formed of an insulating material such as glass epoxy resin or polyimide. The wiring pattern 21w is a conductive part provided on the surface or inside of the insulating base material 21i. The package substrate 21 has a rectangular shape same as the outer shape of the NAND package 14 when viewed from the Z direction. The package substrate 21 is an example of a "second substrate".

[0028] The package substrate 21 has a first surface 21a and a second surface 21b located on the side opposite to the first surface 21a. The first surface 21a is a surface facing the side opposite to the substrate 11 (a surface facing in the +Z direction). The first surface 21a has a plurality of pads 31 to which bonding wires 25 described later are respectively connected. On the other hand, the second surface 21b is a surface facing the substrate 11 (for example, a surface facing in the -Z direction). The second surface 21b has a plurality of pads 32 to which connection terminals 27 described later are respectively connected.

[0029] (Semiconductor memory chip) The semiconductor memory chip 22 is a semiconductor component capable of storing data. The semiconductor memory chip 22 is, for example, a non-volatile semiconductor memory chip, and for example, a NAND type flash memory chip. The semiconductor memory chip 22 includes a plurality of memory cell transistors and a peripheral circuit for causing the plurality of memory cell transistors to function as memory elements. The semiconductor memory chip 22 is plate-shaped along the X and Y directions. When viewed from the Z direction, the semiconductor memory chip 22 has a rectangular shape elongated in the Y direction (see FIG. 4). The plurality of semiconductor memory chips 22 are arranged between the first surface 21a of the package substrate 21 and a sealing member 26 described later.

[0030] In the present embodiment, the plurality of semiconductor memory chips 22 include a plurality (for example, four) of first semiconductor memory chips 22A and a plurality (for example, four) of second semiconductor memory chips 22B.

[0031] A plurality of first semiconductor memory chips 22A are stacked in the Z direction with an adhesive film 23 interposed therebetween. The adhesive film 23 is, for example, a die attach film. The plurality of first semiconductor memory chips 22A are stacked on the first surface 21a of the package substrate 21. The plurality of first semiconductor memory chips 22A are arranged so as to be shifted toward the +X direction side as the first semiconductor memory chip 22A is farther from the package substrate 21. Each first semiconductor memory chip 22A has a plurality of pads 41 in a region that does not overlap with another first semiconductor memory chip 22A when viewed in the Z direction. The pad 41 is a pad to which a bonding wire 25 described later is connected.

[0032] In the present embodiment, an adhesive film 24 is provided on the uppermost first semiconductor memory chip 22A among the plurality of first semiconductor memory chips 22A. The adhesive film 24 is, for example, a thick die attach film. The thickness of the adhesive film 24 in the Z direction is larger than the thickness of the adhesive film 23 in the Z direction. The adhesive film 24 covers the pads 41 of the uppermost first semiconductor memory chip 22A and a part of the bonding wire 25 connected to the pads 41 of the uppermost first semiconductor memory chip 22A. For example, a part of the bonding wire 25 extends through the inside of the adhesive film 24.

[0033] A plurality of second semiconductor memory chips 22B are located on the side opposite to the package substrate 21 with respect to the plurality of first semiconductor memory chips 22A. The plurality of second semiconductor memory chips 22B are stacked in the Z direction with an adhesive film 23 interposed therebetween. The plurality of second semiconductor memory chips 22B are arranged to be shifted toward the +X direction side as the second semiconductor memory chip 22B is farther from the package substrate 21. The plurality of second semiconductor memory chips 22B are stacked on the plurality of first semiconductor memory chips 22A via an adhesive film 24. In the present embodiment, the lowermost second semiconductor memory chip 22B among the plurality of second semiconductor memory chips 22B is arranged to be shifted toward the -X direction side with respect to the uppermost first semiconductor memory chip 22A described above. Each second semiconductor memory chip 22B has a plurality of pads 41 in a region that does not overlap with another second semiconductor memory chip 22B when viewed from the Z direction. The pad 41 is a pad to which a bonding wire 25 described later is connected.

[0034] (Bonding wire) The bonding wire 25 is an electrical connection part that connects the package substrate 21 and the semiconductor memory chip 22. In the present embodiment, the plurality of bonding wires 25 include a plurality of first bonding wires 25A (only one is shown in FIG. 3) and a plurality of second bonding wires 25B (only one is shown in FIG. 3).

[0035] Each first bonding wire 25A electrically connects the pad 41 of the plurality of first semiconductor memory chips 22A and the pad 31 of the package substrate 21. Each first bonding wire 25A is provided at the -X direction side end of the plurality of first semiconductor memory chips 22A. In the present embodiment, one end of each first bonding wire 25A is joined to the pad 31 of the package substrate 21. Each first bonding wire 25A extends from the pad 31 of the package substrate 21 via the pads 41 of the plurality of first semiconductor memory chips 22A in order. Each first bonding wire 25A electrically connects the pads 41 of the plurality of first semiconductor memory chips 22A in series.

[0036] Each second bonding wire 25B electrically connects the pads 41 of the plurality of second semiconductor memory chips 22B and the pads 31 of the package substrate 21. Each second bonding wire 25B is provided at the -X direction side end of the plurality of second semiconductor memory chips 22B. One end of each second bonding wire 25B is bonded to the pad 31 of the package substrate 21. Each second bonding wire 25B extends from the pad 31 of the package substrate 21 via the pads 41 of the plurality of second semiconductor memory chips 22B in sequence. Each second bonding wire 25B electrically connects the pads 41 of the plurality of second semiconductor memory chips 22B in series.

[0037] (Sealing member) The sealing member 26 is an insulating part that protects the plurality of semiconductor memory chips 22 and the plurality of bonding wires 25. The sealing member 26 is, for example, a molding resin. The sealing member 26 is provided on the first surface 21a of the package substrate 21 and covers the first surface 21a of the package substrate 21 when viewed from the Z direction. The sealing member 26 covers the plurality of semiconductor memory chips 22 and the plurality of bonding wires 25 from the side opposite to the first surface 21a of the package substrate 21. For example, the sealing member 26 is formed in a rectangular shape that is the same as the outer shape of the NAND package 14 when viewed from the Z direction.

[0038] (Connection terminal) The connection terminal 27 is an electrical connection part that connects the NAND package 14 and the substrate 11. The plurality of connection terminals 27 are provided on the second surface 21b of the substrate 21 and are exposed outside the NAND package 14. The plurality of connection terminals 27 are arranged in a grid pattern along, for example, the X direction and the Y direction (see FIG. 5). In the present embodiment, the plurality of connection terminals 27 are BGA (Ball Grid Array) type solder joints. However, the connection terminal 27 is not limited to the above example. The connection terminal 27 may be a pad connected to the outside via a conductive paste, a terminal such as a lead frame or a pin, or a terminal connected to the outside in other manners.

[0039] <A4. Terminals of semiconductor memory chips> Next, the pads 41 of the semiconductor memory chip 22 will be described. FIG. 4 is a plan view showing the NAND package 14. In FIG. 4, for convenience of explanation, the illustration of the sealing member 26 is omitted. Each semiconductor memory chip 22 has a plurality of pads 41 to which a plurality of bonding wires 25 are respectively connected.

[0040] In the present embodiment, the plurality of pads 41 of each semiconductor memory chip 22 include only a plurality of pads 41S for one channel composed of a predetermined number (for example, 12) of terminals as terminals capable of transferring a data signal or a timing signal. In the present embodiment, the 12 pads 41S are an example of the "plurality of first terminals".

[0041] In the present embodiment, the 12 pads 41S which are the above-mentioned predetermined number of terminals (terminals for one channel) include, for example, 8 pads 41S capable of transferring an 8-bit data signal DQ, 1 pad 41S capable of transferring a data strobe signal DQS, 1 pad 41S capable of transferring a data strobe signal DQSn, 1 pad 41S capable of transferring a read enable signal RE, and 1 pad 41S capable of transferring a read enable signal REn. The 12 pads 41S are arranged side by side in the Y direction, for example.

[0042] In the present application, "each of the semiconductor memory chips has only a plurality of terminals for one channel composed of a predetermined number of terminals as terminals capable of transferring a data signal or a timing signal" means that as terminals capable of transferring a data signal or a timing signal, it has only the above-mentioned predetermined number of pads 41S (terminals for one channel), and it may include a case where there are other terminals used for purposes different from the transfer of the data signal and the timing signal. For example, the plurality of pads 41 of each semiconductor memory chip 22 include a plurality of pads 41T as terminals other than the above-mentioned predetermined number of pads 41S. The plurality of pads 41T are terminals for power supply or terminals for ground connection, etc.

[0043] In this embodiment, the plurality of pads 31 provided on the first surface 21a of the package substrate 21 include a plurality of pads 31S and a plurality of pads 31T. The plurality of pads 31S are the above-mentioned predetermined number (for example, 12) of pads. The plurality of pads 31S are electrically connected one-to-one to the plurality of pads 41S of each semiconductor memory chip 22 via a plurality of bonding wires 25. The "one-to-one" mentioned here means that when focusing on one semiconductor memory chip 22, the plurality of pads 31S on the package substrate 21 and the plurality of pads 41S of the one semiconductor memory chip 22 are electrically connected one-to-one. As described above, in this embodiment, each first bonding wire 25A electrically connects the pads 41 of a plurality of first semiconductor memory chips 22A in series. Also, each second bonding wire 25B electrically connects the pads 41 of a plurality of second semiconductor memory chips 22B in series. Therefore, when viewed as a whole of the NAND package 14, each pad 31S and the eight pads 41S separately existing in the eight semiconductor memory chips 22 are electrically connected in a one-to-eight relationship.

[0044] Similarly, the plurality of pads 31T are electrically connected one-to-one to the plurality of pads 41T of each semiconductor memory chip 22 via a plurality of bonding wires 25. The "one-to-one" mentioned here means that when focusing on one semiconductor memory chip 22, the plurality of pads 31T on the package substrate 21 and the plurality of pads 41T of the semiconductor memory chip 22 are electrically connected one-to-one. When viewed as a whole of the NAND package 14, each pad 31T and the eight pads 41T separately existing in the eight semiconductor memory chips 22 are electrically connected in a one-to-eight relationship.

[0045] <A5. Connection Terminals of NAND Package> Next, the connection terminal 27 of the NAND package 14 will be described. FIG. 5 is a bottom view showing the NAND package 14. As described above, the plurality of connection terminals 27 are arranged in a grid pattern along, for example, the X direction and the Y direction.

[0046] In this embodiment, the plurality of connection terminals 27 of the NAND package 14 include only a plurality of connection terminals 27S for one channel, which are composed of the predetermined number (for example, 12) of terminals as terminals capable of transferring data signals or timing signals. In this embodiment, the 12 connection terminals 27S are an example of the "plurality of second terminals".

[0047] In this embodiment, the 12 connection terminals 27S, which are the predetermined number of terminals (terminals for one channel), include, for example, 8 connection terminals 27S capable of transferring an 8-bit data signal DQ, 1 connection terminal 27S capable of transferring a data strobe signal DQS, 1 connection terminal 27S capable of transferring a data strobe signal DQSn, 1 connection terminal 27S capable of transferring a read enable signal RE, and 1 connection terminal 27S capable of transferring a read enable signal REn.

[0048] For the sake of explanation here, a center line CL1 passing in the Y direction is defined for the center C1 in the X direction of the package substrate 21 (the center in the X direction of the NAND package 14) when viewed from the Z direction. In this embodiment, the 12 connection terminals 27S are arranged asymmetrically on both sides of the center line CL1 with respect to the X direction (that is, the +X direction side and the -X direction side). In the example shown in FIG. 5, the 12 connection terminals 27S include a first number (for example, 10) of connection terminals 27S arranged on the side closer to the controller 12 (-X direction side) with respect to the center C1 in the X direction of the package substrate 21, and a second number (for example, 2) of connection terminals 27S arranged on the side farther from the controller 12 (+X direction side). The first number is larger than the second number.

[0049] In the present application, the phrase "a plurality of connection terminals include only a plurality of terminals for one channel composed of a predetermined number of terminals as terminals capable of transferring a data signal or a timing signal" means that as terminals capable of transferring a data signal or a timing signal, only the above-mentioned predetermined number of terminals (terminals for one channel) are provided, and it may include a case where there are other terminals used for purposes different from the transfer of the data signal and the timing signal. For example, the plurality of connection terminals 27 include a plurality of connection terminals 27T as terminals other than the above-mentioned predetermined number of connection terminals 27S. The plurality of connection terminals 27T are, for example, terminals capable of transferring control signals (such as status notification signals) such as a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a write protect signal WPn, or a ready / busy signal R / Bn, terminals for power supply, or terminals for ground connection.

[0050] <A6. Branch portion of the NAND package> Next, returning to FIG. 3, the branch portion DP of the NAND package 14 will be described. In the present embodiment, the NAND package 14 has a branch portion DP. In the branch portion DP, a path P1 that electrically connects a plurality of connection terminals 27S (the above-mentioned predetermined number of connection terminals 27S) included in the connection terminals 27 and a plurality of first bonding wires 25A, and a path P2 that electrically connects a plurality of connection terminals 27S (the above-mentioned predetermined number of connection terminals 27S) included in the connection terminals 27 and a plurality of second bonding wires 25B are branched in parallel with the path P1.

[0051] In this embodiment, the branching portion DP is provided on the package substrate 21. The branching portion DP includes, for example, a predetermined number (e.g., 12) of the pads 31S among the plurality of pads 31 provided on the package substrate 21. Each pad 31S is electrically connected to one connection terminal 27S included in the plurality of connection terminals 27S. Also, a first bonding wire 25A and a second bonding wire 25B are electrically connected to each pad 31 in parallel. Thereby, each pad 31 electrically connects one connection terminal 27S to one pad 41S of each first semiconductor memory chip 22A, and also electrically connects the one connection terminal 27S to one pad 41S of each second semiconductor memory chip 22B.

[0052] <A7. Configuration of the Substrate of the Memory System> Next, the substrate 11 of the memory system 1 will be described. FIG. 6 is a cross-sectional view taken along the F6-F6 line of the memory system 1 shown in FIG. 1. In this embodiment, the plurality of transmission lines L of the substrate 11 include a plurality of transmission lines L1 through which data signals DQ (DQ0 to DQ7), data strobe signals DQS, data strobe signals DQSn, read enable signals RE, or read enable signals REn are transferred (only one is shown in FIG. 6). The transmission line L1 has, for example, a wiring main body L1a and one or more connection portions L1b branched from the wiring main body L1a. The connection portion L1b is a wiring portion that connects the wiring main body L1a and the NAND package 14. The connection portion L1b is provided such that only one connection portion L1b is connected to each NAND package 14 for each transmission line L1.

[0053] <A8. Advantages> FIG. 7 is a cross-sectional view showing the memory system 1Q of the comparative example. Here, as a comparative example, consider a configuration in which each NAND package 14 has connection terminals 27S for two channels as terminals capable of transferring data signals or timing signals. In other words, the NAND package 14 of the comparative example has two connection terminals 27S corresponding to the same signal. And the transmission line L1 has two connection portions L1b connected to the two connection terminals 27S for each NAND package 14.

[0054] In the configuration of this comparative example, the number of branch portions (connection portions L1b) branched from the wiring main body L1a increases. According to such a configuration, due to the influence of signal reflection by the above branch portion, the signal quality of the signal transferred using the transmission line L1 may deteriorate. This influence tends to become prominent as the memory system 1 speeds up. Also, when connection terminals 27S for two channels are provided in the NAND package 14, it becomes difficult to reduce the size of the NAND package 14.

[0055] On the other hand, in the present embodiment, the NAND package 14 has a plurality of semiconductor memory chips 22 and a plurality of connection terminals 27. Each of the plurality of semiconductor memory chips 22 has only a plurality of pads 41S for one channel composed of a predetermined number of terminals as a plurality of terminals capable of transferring data signals or timing signals. The plurality of connection terminals 27 includes the plurality of connection terminals 27S for one channel composed of the predetermined number of terminals as a plurality of terminals capable of transferring data signals or timing signals. According to such a configuration, compared with the above comparative example, the number of branch portions (connection portions L1b) branched from the wiring main body L1a can be reduced. For this reason, the influence of signal reflection by the above branch portion becomes small, and the signal quality of the signal transferred using the transmission line L1 is less likely to deteriorate. Also, when the connection terminals 27S for one channel are provided in the NAND package 14, it becomes easier to reduce the size of the NAND package 14 compared with the above comparative example.

[0056] In this embodiment, the plurality of semiconductor memory chips 22 includes a plurality of first semiconductor memory chips 22A and a plurality of second semiconductor memory chips 22B. The plurality of bonding wires 25 includes a plurality of first bonding wires 25A connected to the plurality of pads 41S of each of the plurality of first semiconductor memory chips 22A, and a plurality of second bonding wires 25B connected to the plurality of pads 41S of each of the plurality of second semiconductor memory chips 22B. The NAND package 14 has a branching portion DP. In the branching portion DP, a path P1 that electrically connects the plurality of connection terminals 27S and the plurality of first bonding wires 25A, and a path P2 that electrically connects the plurality of connection terminals 27S and the plurality of second bonding wires 25B in parallel with the plurality of first bonding wires 25A are branched portions. According to such a configuration, within the NAND package 14, a connection relationship for two channels can be realized, and it becomes easy to improve the electrical characteristics (for example, high speed) of the NAND package 14.

[0057] In this embodiment, the package substrate 21 includes the branching portion DP. According to such a configuration, the branching portion DP can be realized by the package substrate 21. Thereby, it becomes easy to reduce the size of the NAND package 14 as compared with the case where special additional components are provided in the NAND package 14.

[0058] In this embodiment, the branching portion DP includes a plurality of pads 31S provided on the first surface 21a of the package substrate 21. The plurality of first bonding wires 25A are connected to the plurality of pads 31S. The plurality of second bonding wires 25B are connected to the plurality of pads 31S in parallel with the plurality of first bonding wires 25A. According to such a configuration, the branching portion DP can be realized by the pads 31 of the package substrate 21. Thereby, it becomes easy to reduce the size of the NAND package 14.

[0059] In this embodiment, the plurality of connection terminals 27S includes a first number of connection terminals 27S arranged closer to the controller 12 and a second number of connection terminals 27S arranged farther from the controller 12 with respect to the center C1 in the X direction of the package substrate 21. And the first number is larger than the second number. According to such a configuration, the distance between the connection terminal 27S and the controller 12 can be shortened. If the distance between the connection terminal 27S and the controller 12 can be shortened, it becomes easier to speed up the memory system 1.

[0060] <A9. Modification example> Hereinafter, several modification examples will be described. In each modification example, the configuration other than that described below is the same as the configuration of the first embodiment described above.

[0061] (First modification example) FIG. 8 is a bottom view showing the NAND package 14 of the first modification example. The plurality of connection terminals 27 in the first modification example includes only a plurality of connection terminals 27S for one channel composed of the above-mentioned predetermined number (for example, 12) of terminals as terminals capable of transferring data signals or timing signals, similar to the first embodiment described above.

[0062] In this modification example, the 12 connection terminals 27S are arranged asymmetrically on both sides of the center line CL1 in the X direction (that is, the +X direction side and the -X direction side). In this modification example, the 12 connection terminals 27S include a first number (for example, 6) of connection terminals 27S arranged closer to the controller 12 (-X direction side) with respect to the center C1 in the X direction of the package substrate 21, a second number (for example, 4) of connection terminals 27S arranged farther from the controller 12 (+X direction side), and a third number (for example, 2) of connection terminals 27S. The third number of connection terminals 27S is a connection terminal 27S that overlaps with the center line CL1 extending in the Y direction through the center C1 in the X direction of the package substrate 21 when viewed from the Z direction. The first number is larger than the second number. Note that this modification example may be applied in combination with the second embodiment described later. Even with such a configuration, the electrical characteristics of the memory system 1 can be improved.

[0063] (Second Modified Example) FIG. 9 is a cross-sectional view showing the NAND package 14 of the second modified example. In the second modified example, a plurality of second semiconductor memory chips 22B are stacked in the Z direction with an adhesive film 23 interposed therebetween. The plurality of second semiconductor memory chips 22B are arranged so as to be shifted toward the +X direction side as the second semiconductor memory chip 22B is farther from the package substrate 21. The plurality of second semiconductor memory chips 22B are stacked on the plurality of first semiconductor memory chips 22A via the adhesive film 23. In this modified example, the lowermost second semiconductor memory chip 22B among the plurality of second semiconductor memory chips 22B is arranged so as to be shifted toward the +X direction side with respect to the uppermost first semiconductor memory chip 22A.

[0064] In this modified example, a plurality of first bonding wires 25A are connected to the plurality of first semiconductor memory chips 22A. A plurality of second bonding wires 25B are connected to the plurality of second semiconductor memory chips 22B in electrical parallel with the plurality of first bonding wires 25A. Even with such a configuration, the electrical characteristics of the memory system 1 can be improved.

[0065] (Third Modified Example) FIG. 10 is a cross-sectional view showing the NAND package 14 of the third modification. In the third modification, all (for example, eight) semiconductor memory chips 22 included in one NAND package 14 are stacked in the Z direction with an adhesive film 23 interposed therebetween. All the semiconductor memory chips 22 are arranged so as to be shifted toward the +X direction side as the semiconductor memory chips 22 are farther from the package substrate 21. In this modification, each bonding wire 25 is provided at the -X direction side end of a plurality of semiconductor memory chips 22, and extends from the pad 31 of the package substrate 21 through the pads 41 of the plurality of semiconductor memory chips 22 in order. Each bonding wire 25 electrically connects the pads 41 of all (for example, eight) semiconductor memory chips 22 in series. In this modification, there may not be pads 41 that are electrically connected in parallel. In this modification, the path for electrically connecting each pad 31S of the package substrate 21 and the plurality of pads 41S (for example, eight pads 41S) that are separately present in a plurality of semiconductor memory chips 22 (for example, all eight semiconductor memory chips 22) does not have to be divided into the path P1 and the path P2 as described above. In this modification, for each pad 31S, one path P is provided for electrically connecting the pad 31S and the plurality of pads 41S (for example, eight pads 41S) that are separately present in a plurality of semiconductor memory chips 22 (for example, all eight semiconductor memory chips 22) in series.

[0066] (Second Embodiment) Next, the second embodiment will be described. The second embodiment is different from the first embodiment in that a NAND package 14' including an intermediate component 60 is provided. The configuration other than that described below is the same as the configuration of the first embodiment described above.

[0067] <B1. Configuration of NAND Package> FIG. 11 is a cross-sectional view showing the NAND package 14' of the second embodiment. The NAND package 14' includes, for example, a package substrate 21', a plurality (e.g., eight) of semiconductor memory chips 22, a plurality of adhesive films 23, a plurality of bonding wires 25, a sealing member 26, a plurality of connection terminals 27, and an intermediate component 60. Note that the "intermediate component" may be referred to as, for example, a "distribution component" or an "interface component".

[0068] (Intermediate component) The intermediate component 60 is a semiconductor chip including one or more circuits. The intermediate component 60 includes, for example, an interface circuit provided between the package substrate 21 and the plurality of semiconductor memory chips 22. The intermediate component 60 may include, for example, a control circuit for controlling the plurality of semiconductor memory chips 22. In the present embodiment, the intermediate component 60 is a package component including a plurality of connection terminals. The intermediate component 60 includes, for example, a component body 61 and a plurality of connection terminals 62.

[0069] The component body 61 includes an interface circuit 60a described later. The component body 61 is plate-shaped. The component body 61 has a first surface 61a and a second surface 61b located on the side opposite to the first surface 61a. The first surface 61a is a surface facing in the +Z direction. The second surface 61b is a surface facing in the -Z direction. The interface circuit 60a (for example, elements included in the interface circuit 60a) is arranged closer to the second surface 61b than the first surface 61a.

[0070] The connection terminal 62 is an electrical connection portion that connects the component body 61 and the package substrate 21. The plurality of connection terminals 62 are provided on the second surface 61b of the component body 61. The plurality of connection terminals 62 are arranged, for example, in a grid pattern along the X direction and the Y direction. In the present embodiment, the plurality of connection terminals 62 are BGA-type solder joints (so-called micro-bumps). However, the connection terminal 62 is not limited to the above example.

[0071] In this embodiment, the first surface 21a of the package substrate 21 has a plurality of pads 33 (see FIG. 12) that are electrically connected to the relay component 60. The relay component 60 is flip-chip mounted on the first surface 21a of the package substrate 21. A plurality of connection terminals 62 of the relay component 60 are connected to the plurality of pads 33 of the package substrate 21.

[0072] As shown in FIG. 11, the center C2 of the relay component 60 in the X direction is displaced and arranged closer to the controller 12 (-X direction side) with respect to the center C1 of the package substrate 21 in the X direction (the center of the NAND package 14' in the X direction). For example, the center C2 of the relay component 60 in the X direction is displaced by 1 mm or more closer to the controller 12 (-X direction side) with respect to the center C1 of the package substrate 21 in the X direction. Stated from another perspective, the center C2 of the relay component 60 in the X direction is displaced by a predetermined distance or more closer to the controller 12 (-X direction side) with respect to the center C1 of the package substrate 21 in the X direction. The predetermined distance is a distance greater than the center-to-center distance PT of the plurality of connection terminals 27.

[0073] (Semiconductor memory chip) A plurality (for example, four) of first semiconductor memory chips 22A are stacked on the relay component 60 from the side opposite to the package substrate 21. The plurality of first semiconductor memory chips 22A are stacked on the first surface 61a of the component body 61 of the relay component 60 with an adhesive film 23 interposed therebetween. The plurality of first semiconductor memory chips 22A are arranged to be displaced more toward the +X direction side as the first semiconductor memory chip 22A is farther from the package substrate 21.

[0074] A plurality (e.g., four) of second semiconductor memory chips 22B are arranged at positions offset from the relay component 60 when viewed from the Z direction. For example, the plurality of second semiconductor memory chips 22B are arranged on the +X direction side with respect to the plurality of first semiconductor memory chips 22A and the relay component 60. The plurality of second semiconductor memory chips 22B are stacked on the first surface 21a of the package substrate 21 with an adhesive film 23 interposed therebetween. The plurality of second semiconductor memory chips 22B are arranged so as to be shifted more toward the +X direction side as the second semiconductor memory chip 22B is farther from the package substrate 21.

[0075] In the present embodiment, a part of the lowermost second semiconductor memory chip 22B is located between the uppermost first semiconductor memory chip 22A and the package substrate 21. In other words, when viewed from the Z direction, a part of the lowermost second semiconductor memory chip 22B overlaps with a part of the uppermost first semiconductor memory chip 22A.

[0076] (Pads of the package substrate) In the present embodiment, the plurality of pads 31 of the package substrate 21 include the above-mentioned predetermined number (e.g., twelve) of pads 31SA and the above-mentioned predetermined number (e.g., twelve) of pads 31SB.

[0077] The above-mentioned predetermined number of pads 31SA are located on the -X direction side with respect to the relay component 60. From another perspective, the above-mentioned predetermined number of pads 31SA are located on the -X direction side with respect to the plurality of first semiconductor memory chips 22A. The above-mentioned predetermined number of pads 31SA are arranged side by side in the Y direction.

[0078] The above-mentioned predetermined number of pads 31SB are located on the +X direction side with respect to the relay component 60. From another perspective, the above-mentioned predetermined number of pads 31SA are located on the -X direction side with respect to the plurality of second semiconductor memory chips 22B. In the present embodiment, the above-mentioned predetermined number of pads 31SB are located between the relay component 60 and the plurality of second semiconductor memory chips 22B in the X direction. The above-mentioned predetermined number of pads 31SB are arranged side by side in the Y direction.

[0079] (Bonding Wire) Each first bonding wire 25A electrically connects the pads 41S of a plurality of first semiconductor memory chips 22A and the pads 31SA of the package substrate 21. Each first bonding wire 25A is disposed on the -X direction side with respect to the plurality of first semiconductor memory chips 22A. Each first bonding wire 25A is provided at the end portion on the -X direction side of the plurality of first semiconductor memory chips 22A.

[0080] In the present embodiment, each first bonding wire 25A is disposed on the -X direction side with respect to the relay component 60. One end of each first bonding wire 25A is bonded to the pad 31SA of the package substrate 21. Each first bonding wire 25A extends from the pad 31SA through the pads 41S of the plurality of first semiconductor memory chips 22A in order. Each first bonding wire 25A is connected to the pad 31SA and is electrically connected to the relay component 60 via the package substrate 21.

[0081] Each second bonding wire 25B electrically connects the pads 41S of a plurality of second semiconductor memory chips 22B and the pads 31SB of the package substrate 21. Each second bonding wire 25B is disposed on the -X direction side with respect to the plurality of second semiconductor memory chips 22B. Each second bonding wire 25B is provided at the end portion on the -X direction side of the plurality of second semiconductor memory chips 22B.

[0082] In this embodiment, each second bonding wire 25B is disposed on the +X direction side with respect to the relay component 60. One end of each second bonding wire 25B is bonded to the pad 31SB of the package substrate 21. Each second bonding wire 25B extends from the pad 31SB through the pads 41S of a plurality of second semiconductor memory chips 22B in sequence. In this embodiment, each second bonding wire 25B extends through between a plurality of first semiconductor memory chips 22A and a plurality of second semiconductor memory chips 22B. Each second bonding wire 25B is connected to the pad 31SB and is electrically connected to the relay component 60 via the package substrate 21.

[0083] In this embodiment, a part of at least some of the plurality of second bonding wires 25B overlaps with at least some of the plurality of first semiconductor memory chips 22A when viewed from the Z direction. For example, a part of all the second bonding wires 25B overlaps with at least some of the plurality of first semiconductor memory chips 22A when viewed from the Z direction.

[0084] <B2. Electrical connection structure related to relay component> Next, the electrical connection structure related to the relay component 60 will be described. FIG. 12 is a cross-sectional view showing an enlarged area surrounded by the F12 line shown in FIG. 11. The plurality of connection terminals 62 of the relay component 60 includes the above-mentioned predetermined number (for example, 12) of connection terminals 62SQ, the above-mentioned predetermined number (for example, 12) of connection terminals 62SA, and the above-mentioned predetermined number (for example, 12) of connection terminals 62SB. In FIG. 12, for convenience of explanation, only one connection terminal 62SQ, one connection terminal 62SA, and one connection terminal 62SB are shown.

[0085] In this embodiment, the wiring pattern 21w of the package substrate 21 includes a plurality of signal lines 21wQ, a plurality of signal lines 21wA, and a plurality of signal lines 21wB. The predetermined number of connection terminals 62SQ are electrically connected to the predetermined number of connection terminals 27S of the NAND package 14' one-to-one via the plurality of signal lines 21wQ of the package substrate 21. The predetermined number of connection terminals 62SA are electrically connected to the plurality of pads 31SA of the package substrate 21 one-to-one via the plurality of signal lines 21wA of the package substrate 21. The predetermined number of connection terminals 62SB are electrically connected to the plurality of pads 31SB of the package substrate 21 one-to-one via the plurality of signal lines 21wB of the package substrate 21.

[0086] In this embodiment, the predetermined number of connection terminals 62SA are arranged closer to the -X direction side than the predetermined number of connection terminals 62SQ. Note that "the predetermined number of connection terminals 62SA are arranged closer to the -X direction side than the predetermined number of connection terminals 62SQ" means that when comparing the predetermined number of connection terminals 62SA and the predetermined number of connection terminals 62SQ, the number of connection terminals 62SA located on the -X direction side is larger than the number of connection terminals 62SQ located on the -X direction side, and it may also include the case where one or a small number of connection terminals 62SA are located on the +X direction side compared to the connection terminals 62SQ.

[0087] In this embodiment, the predetermined number of connection terminals 62SB are arranged closer to the +X direction side than the predetermined number of connection terminals 62SQ. Note that "the predetermined number of connection terminals 62SB are arranged closer to the +X direction side than the predetermined number of connection terminals 62SQ" means that when comparing the predetermined number of connection terminals 62SB and the predetermined number of connection terminals 62SQ, the number of connection terminals 62SB located on the +X direction side is larger than the number of connection terminals 62SQ located on the +X direction side, and it may also include the case where one or a small number of connection terminals 62SB are located on the -X direction side compared to the connection terminals 62SQ.

[0088] In this embodiment, the above-mentioned predetermined number of connection terminals 62SA are arranged closer to the -X direction side than the above-mentioned predetermined number of connection terminals 62SB. Note that "the predetermined number of connection terminals 62SA are arranged closer to the -X direction side than the predetermined number of connection terminals 62SB" means that when comparing the above-mentioned predetermined number of connection terminals 62SA and the above-mentioned predetermined number of connection terminals 62SB, the number of connection terminals 62SA located on the -X direction side is larger than the number of connection terminals 62SB located on the -X direction side, and it may also include the case where one or a small number of connection terminals 62SA are located on the +X direction side compared to the connection terminals 62SB.

[0089] In this embodiment, the relay component 60 includes a branching portion DP. In the branching portion DP, a path P1 that electrically connects a plurality of connection terminals 27S (the above-mentioned predetermined number of connection terminals 27S) included in the connection terminal 27 and a plurality of first bonding wires 25A, and a path P2 that electrically connects a plurality of connection terminals 27S (the above-mentioned predetermined number of connection terminals 27S) included in the connection terminal 27 and a plurality of second bonding wires 25B branch.

[0090] In this embodiment, the branching portion DP includes an interface circuit 60a provided in the component main body 61. In this embodiment, the interface circuit 60a switches between a first state in which the path P1 is connected and the path P2 is blocked, and a second state in which the path P2 is connected and the path P1 is blocked, based on a signal received from the controller 12, for example. In the above-mentioned first state, signals (for example, data signals and timing signals) are transmitted and received between the plurality of first semiconductor memory chips 22A and the controller 12. In the above-mentioned second state, signals (for example, data signals and timing signals) are transmitted and received between the plurality of second semiconductor memory chips 22B and the controller 12. In this embodiment, the above-mentioned first state and the above-mentioned second state realize an electrical connection relationship for two channels. In this embodiment, an electrical connection relationship for two channels is realized between the relay component 60 and a plurality (for example, eight) of semiconductor memory chips 22. On the other hand, between the relay component 60 and the package substrate 21 (that is, between the relay component 60 and the substrate 11), an electrical connection relationship for one channel is realized.

[0091] <B3. Advantages> In this embodiment, the NAND package 14' has a relay component 60 mounted on the package substrate 21. The relay component 60 includes a branch portion DP. According to such a configuration, the branch portion DP can be realized by the relay component 60. As a result, it becomes easier to reduce the size of the NAND package 14' compared to the case where special additional components are provided inside the NAND package 14'.

[0092] In this embodiment, the center C2 of the relay component 60 in the X direction is displaced by 1 mm or more in the X direction with respect to the center C1 of the package substrate 21 in the X direction. According to such a configuration, the distance between the relay component 60 and the controller 12 can be shortened. When the distance between the relay component 60 and the controller 12 can be shortened, it becomes easier to increase the speed of the memory system 1.

[0093] In this embodiment, the relay component 60 is a package component including a plurality of connection terminals 62, and is flip-chip mounted on the first surface 21a of the package substrate 21. According to such a configuration, the branch portion DP can be provided using the relay component 60 that enables flip-chip mounting and has excellent mountability.

[0094] In this embodiment, the plurality of first semiconductor memory chips 22A are stacked on the relay component 60 from the side opposite to the package substrate 21. According to such a configuration, it becomes easier to reduce the size of the NAND package 14' in the X direction compared to the case where the plurality of first semiconductor memory chips 22A are not stacked on the relay component 60 (the case where the plurality of first semiconductor memory chips 22A are stacked on the package substrate 21 at a position different from the relay component 60).

[0095] In this embodiment, a plurality of first bonding wires 25A are arranged on the -X direction side with respect to a plurality (e.g., four) of first semiconductor memory chips 22A. A plurality of second bonding wires 25B are arranged on the -X direction side with respect to a plurality (e.g., four) of second semiconductor memory chips 22B. According to such a configuration, for example, compared with a case where a plurality of first bonding wires 25A are arranged on the +X direction side with respect to a plurality of first semiconductor memory chips 22A and a plurality of second bonding wires 25B are arranged on the +X direction side with respect to a plurality of second semiconductor memory chips 22B, the wiring distance between a plurality (e.g., eight) of semiconductor memory chips 22 and the relay component 60 can be shortened.

[0096] In this embodiment, a plurality of second bonding wires 25B extend between a plurality of first semiconductor memory chips 22A and a plurality of second semiconductor memory chips 22B. According to such a configuration, the distance between a plurality of second semiconductor memory chips 22B and the controller 12 can be shortened, facilitating the speeding up of the memory system 1.

[0097] Some embodiments and modifications have been described above. Note that the embodiments and modifications are not limited to the above-described examples. For example, the "semiconductor memory device" referred to in this application is not limited to the NAND package 14, and may be other types of semiconductor memories such as a NOR-type memory, an MRAM (Magnetoresistive Random Access Memory), or a resistive change-type memory. Further, the "semiconductor memory device" referred to in this application is not limited to a non-volatile semiconductor memory device, and may be a volatile semiconductor memory device such as a DRAM.

[0098] According to at least one embodiment described above, the semiconductor memory device has a plurality of semiconductor memory chips and a plurality of connection terminals. Each of the plurality of semiconductor memory chips has only a plurality of first terminals for one channel composed of a predetermined number of terminals as terminals capable of transferring data signals or timing signals. The plurality of connection terminals include only a plurality of second terminals for one channel composed of the predetermined number of terminals as terminals capable of transferring data signals or timing signals. Thereby, improvement in the electrical characteristics of the memory system can be achieved.

[0099] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0100] 1... Memory system, 11... Substrate (first substrate), 12... Controller, 14, 14´... NAND package (semiconductor memory device), 21... Package substrate (second substrate), 22... Semiconductor memory chip, 22A... First semiconductor memory chip, 22B... Second semiconductor memory chip, 25... Bonding wire, 25A... First bonding wire, 25B... Second bonding wire, 27... Connection terminal, 27S... Predetermined number of connection terminals (second terminals), 31... Pad, 41... Pad, 41S... Predetermined number of pads (first terminals), 60... Relay component, DP... Branch portion.

Claims

1. A first substrate, a controller mounted on the first substrate, a semiconductor memory device mounted on the first substrate, comprising: the semiconductor memory device includes a second substrate including a first surface and a second surface located on the side opposite to the first surface, a sealing member that covers the first surface when viewed from the thickness direction of the second substrate, a plurality of semiconductor memory chips disposed between the first surface and the sealing member, a plurality of bonding wires connecting the first surface and the plurality of semiconductor memory chips, a plurality of connection terminals provided on the second surface and connected to the first substrate, and having: each of the plurality of semiconductor memory chips has only a plurality of first terminals for one channel composed of a predetermined number of terminals as terminals capable of transferring data signals or timing signals, the plurality of connection terminals include only a plurality of second terminals for one channel composed of the predetermined number of terminals as terminals capable of transferring the data signals or the timing signals, a memory system.

2. The plurality of semiconductor memory chips include a plurality of first semiconductor memory chips and a plurality of second semiconductor memory chips, the plurality of bonding wires include a plurality of first bonding wires connected to the plurality of first terminals of each of the plurality of first semiconductor memory chips and a plurality of second bonding wires connected to the plurality of first terminals of each of the plurality of second semiconductor memory chips, the semiconductor memory device includes a branch portion where a path electrically connecting the plurality of second terminals and the plurality of first bonding wires and a path electrically connecting the plurality of second terminals and the plurality of second bonding wires branch, The memory system according to claim 1.

3. The second substrate includes the branch portion, The memory system according to claim 2.

4. The branch portion includes a plurality of pads provided on the first surface, the plurality of first bonding wires are connected to the plurality of pads, the plurality of second bonding wires are connected to the plurality of pads in parallel with the plurality of first bonding wires electrically, The memory system according to claim 3.

5. The semiconductor memory device further includes a relay component mounted on the second substrate, the relay component includes the branch portion, The memory system according to claim 2.

6. The plurality of first bonding wires are connected to the second substrate and electrically connected to the relay component via the second substrate. The plurality of second bonding wires are connected to the second substrate and electrically connected to the relay component via the second substrate. The memory system according to claim 5.

7. When the direction along the first surface is defined as the first direction, The center of the relay component in the first direction is displaced by 1 mm or more in the first direction with respect to the center of the second substrate in the first direction. The memory system according to claim 6.

8. When the direction along the first surface is defined as the first direction, The center of the relay component in the first direction is displaced toward the side closer to the controller with respect to the center of the second substrate in the first direction. The memory system according to claim 6.

9. The relay component is a package component including a plurality of terminals and is flip-chip mounted on the first surface. The plurality of first semiconductor memory chips are stacked on the relay component from the side opposite to the second substrate. The memory system according to any one of claims 5 to 8.

10. The plurality of first semiconductor memory chips are stacked on the relay component from the side opposite to the second substrate. The memory system according to claim 9.

11. The plurality of second bonding wires extend between the plurality of first semiconductor memory chips and the plurality of second semiconductor memory chips. A part of at least some of the plurality of second bonding wires overlaps with at least some of the plurality of first semiconductor memory chips when viewed in the thickness direction of the second substrate. The memory system according to claim 10.

12. When the direction along the first surface is defined as the first direction, The plurality of second terminals include a first number of second terminals arranged on the side closer to the controller and a second number of second terminals arranged on the side farther from the controller with respect to the center of the second substrate in the first direction. The first number is greater than the second number. The memory system according to any one of claims 1 to 8.

13. A second substrate including a first surface and a second surface located on the side opposite to the first surface, A sealing member that covers the first surface when viewed in the thickness direction of the second substrate. A plurality of semiconductor memory chips disposed between the first surface and the sealing member; A plurality of bonding wires connecting the first surface and the plurality of semiconductor memory chips; A plurality of connection terminals provided on the second surface; and having each of the plurality of semiconductor memory chips has only a plurality of first terminals for one channel, which are composed of a predetermined number of terminals, as terminals capable of transferring a data signal or a timing signal; the plurality of connection terminals include only a plurality of second terminals for one channel, which are composed of the predetermined number of terminals, as terminals capable of transferring the data signal or the timing signal; a semiconductor memory device.

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