Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of reducing the size and improving the reliability. The semiconductor storage device of the embodiments includes a via (35A) provided above a substrate, a conductive layer (35B) provided on the via (35A), and a via (35C) provided on the conductive layer (35B). The via (35A), the conductive layer (35B), and the via (35C) are one continuous layer.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2019-168666 (Filing date: September 17, 2019). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments relate to a semiconductor storage device. BACKGROUND

[0004] A semiconductor storage device in which memory cells are arranged in three dimensions is known. SUMMARY

[0005] Embodiments provide a semiconductor storage device that can be reduced in size and improved in reliability.

[0006] A semiconductor storage device of an embodiment has a first contact plug provided above a substrate, a first conductive layer provided on the first contact plug, and a second contact plug provided on the first conductive layer, and the first contact plug, the first conductive layer, and the second contact plug are continuous one layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram showing a circuit configuration of a semiconductor storage device of the first embodiment.

[0008] Figure 2 is a circuit diagram of a block within a memory cell array in the first embodiment.

[0009] Figure 3 is a view showing an example of a planar layout of the semiconductor storage device of the first embodiment.

[0010] Figure 4 is a cross-sectional view along the A-A line in Figure 3 .

[0011] Figure 5 is a cross-sectional view showing another configuration example of the semiconductor storage device of the first embodiment.

[0012] Figure 6 is a cross-sectional view of a memory pillar within a memory cell array in the first embodiment.

[0013] Figure 7 is a plan view of a via and a conductive layer in the semiconductor storage device of the first embodiment.

[0014] Figure 8 is a cross-sectional view along the B-B line in Figure 7 .

[0015] Figure 9 is a cross-sectional view along the C-C line in Figure 7 .

[0016] Figure 10 is a cross-sectional view along the YZ plane of a variation example of the via and the conductive layer in the first embodiment.

[0017] Figure 11 is a cross-sectional view along the YZ plane of another variation example of the via and the conductive layer in the first embodiment.

[0018] Figures 12-21 is a cross-sectional view showing a manufacturing method of the via and the conductive layer in the semiconductor storage device of the first embodiment.

[0019] Figure 22 is a cross-sectional view along the XZ plane of the semiconductor storage device of the second embodiment.

[0020] Figure 23 is a cross-sectional view showing another configuration example of the semiconductor storage device of the second embodiment.

[0021] Figure 24 is a cross-sectional view along the XZ plane of the via and the conductive layer in the semiconductor storage device of the second embodiment.

[0022] Figure 25 is a cross-sectional view along the YZ plane of the via and the conductive layer in the semiconductor storage device of the second embodiment. DETAILED DESCRIPTION

[0023] Embodiments will be described below with reference to the accompanying drawings. In the following description, components having the same function and configuration are denoted with common reference numerals. In addition, each of the embodiments shown below is an example of a device or a method for embodying the technical idea of the embodiments, and the material, shape, configuration, arrangement, and the like of the constituent components are not limited to the following content.

[0024] Here, as a semiconductor storage device, a three-dimensional stacked type NAND (Not And) flash memory in which memory cell transistors are stacked above a semiconductor substrate will be exemplarily described. In this specification, the memory cell transistor will also be referred to as a memory cell.

[0025] 1. First Embodiment

[0026] The following describes the semiconductor storage device of Embodiment 1. In Embodiment 1, a through-hole, a conductive layer (e.g., a bit line), and a through-hole that are sequentially provided on a storage pillar including a storage cell are exemplified. First, the circuit configuration of the semiconductor storage device is described, and then the configuration of the semiconductor storage device is described.

[0027] 1.1 Circuit configuration of semiconductor storage device

[0028] Utilizing Figure 1 The circuit block configuration of the semiconductor storage device of Embodiment 1 is described. Figure 1 is a block diagram that shows the circuit configuration of the semiconductor storage device of Embodiment 1.

[0029] The semiconductor storage device 10 includes a storage cell array 11, an input / output circuit 12, a logic control circuit 13, a ready / busy circuit 14, a register group 15, a sequencer (or control circuit) 16, a voltage generation circuit 17, a driver 18, a row decoder module (RD) 19, a column decoder 20, and a sense amplifier module 21. The register group 15 includes a status register 15A, an address register 15B, and an instruction register 15C.

[0030] The storage cell array 11 includes one or a plurality of blocks BLK0, BLK1, BLK2, …, BLKm (m is an integer of 0 or more). The plurality of blocks BLK each include a plurality of storage cell transistors that establish a correspondence relationship with rows and columns. The storage cell transistors are nonvolatile storage cells that can be electrically rewritten. A plurality of word lines, a plurality of bit lines, a source line, and the like are provided in the storage cell array 11 to control voltages applied to the storage cell transistors. Hereinafter, in the case of being referred to as a block BLK, each of the blocks BLK0 to BLKm is meant. The detailed configuration of the block BLK will be described below.

[0031] The input / output circuit 12 and the logic control circuit 13 are connected to an external device (e.g., a memory controller) (not shown) via a bus. The input / output circuit 12 transmits and receives a signal DQ (e.g., DQ0, DQ1, DQ2, …, DQ7) between the memory controller via the bus.

[0032] The logic control circuit 13 receives an external control signal from the memory controller via the bus. The external control signal includes, for example, a chip enable signal CEn, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protect signal WPn. The "n" attached to the signal name means that the signal is active in a low state.

[0033] The chip enable signal CEn selects the semiconductor storage device (NAND type flash memory) 10, and is asserted when the semiconductor storage device 10 is selected. The command latch enable signal CLE latches a command sent as the signal DQ to the command register 15C. The address latch enable signal ALE latches an address sent as the signal DQ to the address register 15B. The write enable signal WEn saves data sent as the signal DQ to the input / output circuit 12. The read enable signal REn outputs data read from the memory cell array 11 as the signal DQ. The write protect signal WPn is asserted when writing to and erasing from the semiconductor storage device 10 is prohibited.

[0034] The ready / busy circuit 14 generates a ready / busy signal R / Bn in accordance with control from the sequencer 16. The signal R / Bn indicates whether the semiconductor storage device 10 is in a ready state or a busy state. The ready state indicates a state in which a command from a memory controller can be accepted. The busy state indicates a state in which a command from a memory controller cannot be accepted. The memory controller can know whether the semiconductor storage device 10 is in a ready state or a busy state by receiving the signal R / Bn from the semiconductor storage device 10.

[0035] The status register 15A holds state information STS required for the operation of the semiconductor storage device 10, and transfers the state information STS to the input / output circuit 12 based on an instruction from the sequencer 16. The address register 15B holds address information ADD transferred from the input / output circuit 12. The address information ADD includes a column address and a row address. The row address includes, for example, a block address that specifies a block BLK that is an object of an operation, and a page address that specifies a word line that is an object of an operation within the specified block. The command register 15C holds a command CMD transferred from the input / output circuit 12. The command CMD includes, for example, a write command that instructs the sequencer 16 to perform a write operation, and a read command that instructs the sequencer 16 to perform a read operation. The status register 15A, the address register 15B, and the command register 15C include, for example, an SRAM (static random access memory).

[0036] The sequencer 16 receives a command from the command register 15C, and comprehensively controls the semiconductor storage device 10 in accordance with an order based on the command. The sequencer 16 controls the row decoder module 19, the sense amplifier module 21, and the voltage generation circuit 17, and performs a write operation, a read operation, and an erase operation.

[0037] Specifically, the sequencer 16 controls the row decoder module 19, the driver 18, and the sense amplifier module 21 based on a write instruction received from the instruction register 15C to write data to the plurality of memory cell transistors designated by the address information ADD. In addition, the sequencer 16 controls the row decoder module 19, the driver 18, and the sense amplifier module 21 based on a read instruction received from the instruction register 15C to read data from the plurality of memory cell transistors designated by the address information ADD.

[0038] The voltage generation circuit 17 receives a power supply voltage from the outside of the semiconductor storage device 10 and generates a plurality of voltages required for a read operation, a write operation, and an erase operation using the power supply voltage. The voltage generation circuit 17 supplies the generated voltages to the memory cell array 11, the driver 18, the sense amplifier module 21, and the like.

[0039] The driver 18 receives a plurality of voltages from the voltage generation circuit 17. The driver 18 supplies a plurality of voltages selected from among the plurality of voltages supplied by the voltage generation circuit 17 in correspondence with a read operation, a write operation, and an erase operation to the row decoder module 19 via a plurality of signal lines.

[0040] The row decoder module 19 receives a row address from the address register 15B and decodes the row address. The row decoder module 19 selects any one of the blocks BLK and selects a word line within the selected block BLK based on a result of the decoding of the row address. Further, the row decoder module 19 transmits a plurality of voltages supplied by the driver 18 to the selected block BLK.

[0041] The column decoder 20 receives a column address from the address register 15B and decodes the column address. The column decoder 20 selects a bit line based on a result of the decoding of the column address.

[0042] The sense amplifier module 21 senses and amplifies data read out from the memory cell transistors to the bit line at the time of the read operation of the data. Also, the sense amplifier module 21 temporarily holds the read data DAT read out from the memory cell transistors and transmits it to the input / output circuit 12. In addition, the sense amplifier module 21 temporarily holds the write data DAT transmitted from the input / output circuit 12 at the time of the write operation of the data. Further, the sense amplifier module 21 transmits the write data DAT to the bit line.

[0043] Next, the operation of the semiconductor storage device 10 will be described with reference to the flowchart of FIG. 6. Figure 2 The circuit configuration of the memory cell array 11 will be described. As described above, the memory cell array 11 has a plurality of blocks BLK0 to BLKm. Here, the circuit configuration of one block BLK will be described, but the circuit configurations of the other blocks are the same.

[0044] Figure 2is a circuit diagram of one block BLK within the memory cell array 11. The block BLK has, for example, a plurality of string units SU0, SU1, SU2, SU3. Here, as an example, a case where the block BLK has the string units SU0 to SU3 is shown, but the number of string units included in the block BLK can be arbitrarily set. Hereafter, in the case of being referred to as a string unit SU, each of the string units SU0 to SU3 is meant.

[0045] The string units SU0 to SU3 each have a plurality of NAND strings (or memory strings) NS. The number of NAND strings NS included in one string unit SU can be arbitrarily set.

[0046] The NAND string NS includes a plurality of memory cell transistors MT0, MT1, MT2,..., MT7, and selection transistors ST1, ST2. Here, for the sake of simplicity of explanation, a case where the NAND string NS has eight memory cell transistors MT0 to MT7 and two selection transistors ST1, ST2 is shown, but the number of memory cell transistors and selection transistors included in the NAND string NS can be arbitrarily set. Hereafter, in the case of being referred to as a memory cell transistor MT, each of the memory cell transistors MT0 to MT7 is meant.

[0047] The memory cell transistors MT0 to MT7 each have a control gate and a charge storage layer, and nonvolatilely store data. The memory cell transistors MT0 to MT7 are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2.

[0048] The memory cell transistor MT can store one bit of data, or two or more bits of data. The memory cell transistor MT can be of a MONOS (metal-oxide-nitride-oxide-silicon) type using an insulating film as a charge storage layer, or can be of an FG (floating gate) type using a conductive layer as a charge storage layer.

[0049] The gates of the plurality of selection transistors ST1 included in the string unit SU0 are connected to a selection gate line SGD0. Similarly, the gates of the selection transistors ST1 of the respective string units SU1 to SU3 are connected to selection gate lines SGD1 to SGD3, respectively. The selection gate lines SGD0 to SGD3 are independently controlled by the row decoder module 19, respectively.

[0050] The gates of the plurality of selection transistors ST2 included in the string unit SUO are connected to a selection gate line SGS. Similarly, the gates of the selection transistors ST2 of the respective string units SUl to SU3 are connected to selection gate lines SGS, respectively. Further, there is also a case where individual selection gate lines SGS, i.e., selection gate lines SGSO to SGS3, are connected to the gates of the selection transistors ST2 of the string units SUO to SU3 included in the block BLK. The selection transistors STl, ST2 are used for selection of the string units SU in various operations.

[0051] The control gates of the memory cell transistors MTO to MT7 included in the block BLK are connected to word lines WLO to WL7, respectively. The word lines WLO to WL7 are independently controlled by the row decoder module 19, respectively.

[0052] The bit lines BLO to BLi (i is an integer of 0 or more) are connected to the plurality of blocks BLK, respectively, and to one NAND string NS within the string unit SU included in the block BLK. That is, the bit lines BLO to BLi are connected to the drains of the selection transistors STl of the plurality of NAND strings NS located in the same column among the NAND strings NS arranged in a matrix within the block BLK. In addition, the source line SL is connected to the plurality of blocks BLK. That is, the source line SL is connected to the sources of the plurality of selection transistors ST2 included in the block BLK.

[0053] In summary, the string unit SU includes a plurality of NAND strings NS connected to different bit lines BL and connected to the same selection gate line SGD. In addition, the block BLK includes a plurality of string units SU sharing a word line WL. Further, the memory cell array 11 includes a plurality of blocks BLK sharing a bit line BL.

[0054] The block BLK is, for example, a unit of deletion of data. That is, the data held by the memory cell transistors MT included in the same block BLK is deleted at a time. Further, the data can be deleted in units of the string unit SU, and also in units smaller than the string unit SU.

[0055] The plurality of memory cell transistors MT sharing the word line WL within one string unit SU is referred to as a unit component CU. The set of one-bit data stored by the plurality of memory cell transistors MT included in the unit component CU is referred to as a page. The storage capacity of the unit component CU varies depending on the number of bits of the data stored by the memory cell transistors MT. For example, the unit component CU stores one page of data when one-bit data is stored by each memory cell transistor MT, two pages of data when two-bit data is stored, and three pages of data when three-bit data is stored.

[0056] The write operation and the read operation of the cell unit CU are performed in units of pages. In other words, the read and write operations are performed at once with respect to a plurality of memory cell transistors MT connected to one word line WL provided in one string unit SU.

[0057] In addition, the configuration of the memory cell array 11 can be other configurations. The configuration of the memory cell array 11 is described, for example, in U.S. Patent Application No. 12 / 407,403 filed on March 19, 2009, entitled "THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY". In addition, it is described in U.S. Patent Application No. 12 / 406,524 filed on March 18, 2009, entitled "THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY", U.S. Patent Application No. 12 / 679,991 filed on March 25, 2010, entitled "NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME", and U.S. Patent Application No. 12 / 532,030 filed on March 23, 2009, entitled "SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING SAME". These patent applications are incorporated by reference in their entirety into the present application.

[0058] 1.2 Configuration of Semiconductor Storage Device

[0059] Next, an example of the configuration of the semiconductor storage device of the first embodiment will be described. First, the configuration of the semiconductor storage device will be described with reference to FIG. 1. Figure 3 An example of the planar layout of the semiconductor storage device 10 will be described. Figure 3 is a view showing an example of the planar layout of the semiconductor storage device of the first embodiment. It includes Figure 3 In the following views including FIG. 1, two directions parallel to and orthogonal to (or intersecting) each other, the X direction and the Y direction, are set, and a direction orthogonal to (or intersecting) a plane (the XY plane) including the X direction and the Y direction is set as the Z direction. The X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to a direction orthogonal to the semiconductor substrate surface of the semiconductor storage device 10.

[0060] As shown in Figure 3 Fig. 1, a semiconductor memory device 10 is provided with a memory array chip 100 and a peripheral circuit chip 200, for example.

[0061] The memory array chip 100 has a memory cell array 11A, 11B, and a pad region 23A, 22A, 22B, 22C. The memory cell arrays 11A and 11B constitute a memory cell array 11. The peripheral circuit chip 200 is responsible for communication with a memory controller (not shown) provided outside, and has a peripheral circuit 24A, 24B, a row decoder module (RD) 19A, 19B, 19C, and a pad region 23B. The row decoder modules 19A to 19C constitute a row decoder module 19. The peripheral circuit 24A, 24B, and the row decoder modules 19A to 19C control the memory array chip 100.

[0062] The memory array chip 100 and the peripheral circuit chip 200 are formed of different semiconductor substrates, respectively. Electrode pads on the surface of the memory array chip 100 and electrode pads on the surface of the peripheral circuit chip 200 are arranged in a facing manner, and the electrode pads of the memory array chip 100 and the electrode pads of the peripheral circuit chip 200 are bonded. Thus, one semiconductor memory device (semiconductor memory chip) 10 is formed.

[0063] In the memory array chip 100, the memory cell arrays 11A and 11B can perform different actions in parallel. The memory cell arrays 11A and 11B are arranged between the pad regions 22A, 22B, and 22C arranged in the X direction. In detail, the memory cell array 11A is arranged between the pad regions 22A and 22B, and the memory cell array 11B is arranged between the pad regions 22B and 22C.

[0064] The pad regions 22A and 22B are regions for electrically connecting between the memory cell array 11A provided in the memory array chip 100 and the row decoder modules 19A and 19B provided in the peripheral circuit chip 200. The pad regions 22B and 22C are regions for electrically connecting between the memory cell array 11B provided in the memory array chip 100 and the row decoder modules 19B and 19C provided in the peripheral circuit chip 200.

[0065] The pad region 23A is a region in which pads for connecting between the peripheral circuit chip 200 and the memory controller are provided. The pad region 23A extends in the X direction, and is provided adjacent to the memory cell arrays 11A and 11B.

[0066] In the peripheral circuit chip 200, the row decoder modules 19A, 19B, and 19C are disposed so as to overlap or face the pad regions 22A, 22B, and 22C of the memory array chip 100, respectively. For example, the row decoder modules 19A and 19B are electrically connected to the word lines WL provided in the memory cell array 11A, and the row decoder modules 19B and 19C are electrically connected to the word lines WL provided in the memory cell array 11B.

[0067] The peripheral circuit 24A is provided, for example, between the row decoder modules 19A and 19B, and the peripheral circuit 24B is provided, for example, between the row decoder modules 19B and 19C. The peripheral circuit includes, for example, the input / output circuit 12, the logic control circuit 13, the ready / busy circuit 14, the register group 15, the sequencer 16, the voltage generation circuit 17, the driver 18, the column decoder 20, the sense amplifier module 21, and the like.

[0068] The pad region 23B is disposed so as to be adjacent to the peripheral circuits 24A and 24B and overlap the pad region 23A of the memory array chip 100. In the pad region 23B, for example, wirings and the like leading out from the input / output circuits included in the peripheral circuits 24A and 24B are arranged. These wirings are led out to the upper surface of the semiconductor storage device 10 through the via and the pad.

[0069] Next, the cross-sectional configuration of the semiconductor storage device 10 will be described with reference to FIG. 8. Figure 4 The cross-sectional configuration of the semiconductor storage device 10 will be described with reference to FIG. 8. Figure 4 In the cross-sectional views hereinafter, the arrow direction in the Z direction is referred to as the positive direction, and the direction opposite to the arrow direction in the Z direction is referred to as the negative direction. In addition, "up" and "down" in the following description correspond to the directions in the respective drawings. Furthermore, in the cross-sectional views hereinafter, the layer interposed between the conductive layers is omitted. Figure 4 In the cross-sectional view of FIG. 8, the layer interposed between the conductive layers is omitted.

[0070] Figure 4 is a cross-sectional view along the A-A line in FIG. 7, and is a cross-sectional view along the XZ plane of the memory cell array 11A, the pad region 22A, 22B, the peripheral circuit 24A, and the row decoder modules 19A and 19B. Figure 3 is a cross-sectional view along the A-A line in FIG. 7, and is a cross-sectional view along the XZ plane of the memory cell array 11A, the pad region 22A, 22B, the peripheral circuit 24A, and the row decoder modules 19A and 19B.

[0071] As described above, the semiconductor storage device 10 has a configuration in which the memory array chip 100 and the peripheral circuit chip 200 are attached to each other.

[0072] Hereinafter, the cross-sectional configuration in the memory array chip 100 will be described in detail.

[0073] A conductive layer 31 is provided in the negative direction of the Z direction with respect to the semiconductor substrate 30 with the intervening insulating layer. A laminate of a conductive layer 32, a plurality of conductive layers 33, and a conductive layer 34 is provided in the negative direction of the Z direction with respect to the conductive layer 31 with the intervening insulating layer. The conductive layers 31 to 34 extend in the X direction. The conductive layers 31 to 34 have a flat shape along (or parallel to) the XY plane (or the surface of the semiconductor substrate 30).

[0074] The conductive layer 31 functions as a source line SL. The conductive layer 32 functions as a select gate line SGS. The conductive layers 33 function as a plurality of word lines WL0 to WL7, respectively. Further, in the Figure 4 In the figure, two conductive layers 33 are shown, and the remaining conductive layers 33 are omitted. The conductive layer 34 functions as a select gate line SGD. The conductive layers 31 to 34 contain, for example, tungsten (W) or polysilicon. The semiconductor substrate 30 contains, for example, a silicon substrate and an epitaxial layer of silicon.

[0075] A plurality of memory pillars MP of a columnar shape are provided in the laminate including the conductive layers 32 to 34. Each memory pillar MP extends in the Z direction. Each memory pillar MP is configured so as to pass through the conductive layers 32 to 34 in the Z direction (or the laminating direction), reaching the conductive layer 31 from the surface of the conductive layer 34. That is, the memory pillar MP is connected to the source line SL through the select gate line SGD, the plurality of word lines WL0 to WL7, and the select gate line SGS.

[0076] A contact plug CPI is provided in the negative direction of the Z direction with respect to the memory pillar MP, and a conductive layer 35 is provided in the contact plug CPI. A conductive layer 36, a via 37, and a conductive pad 38 are sequentially provided in the negative direction of the Z direction with respect to the conductive layer 35. The conductive layer 35 includes a via (or a contact plug) 35A, a conductive layer 35B, and a via (or a contact plug) 35C. Details of the memory pillar MP and the conductive layer 35 will be described below.

[0077] End portions of each of the conductive layers 32 to 34 extending in the X direction are electrically connected to the via 39 via a contact plug CP2. A conductive layer 40, a via 41, a conductive layer 42, a via 43, and a conductive pad 44 are sequentially provided in the negative direction of the Z direction with respect to the via 39.

[0078] Next, the sectional configuration in the peripheral circuit chip 200 will be described in detail.

[0079] A CMOS (complementary metal oxide semiconductor) circuit CM, including, for example, an n-channel MOS (metal oxide semiconductor) field-effect transistor (hereinafter referred to as an nMOS transistor) and a p-channel MOS field-effect transistor (hereinafter referred to as a pMOS transistor), is disposed on a semiconductor substrate 50. The CMOS circuit CM constitutes peripheral circuits 24A and row decoder modules 19A and 19B that control the operation of multiple memory cells. The semiconductor substrate 50 includes, for example, a silicon substrate and a silicon epitaxial layer.

[0080] like Figure 4 As shown, a source region, a drain region 50A, and a device separation region 50B are disposed on a semiconductor substrate 50. A gate insulating layer 51 is disposed on the semiconductor substrate 50 between the source region 50A and the drain region 50A along the positive Z-direction, and a gate electrode 52 is disposed on the gate insulating layer 51. The nMOS transistor and the pMOS transistor respectively include a source region 50A, a drain region 50A, a semiconductor layer of the semiconductor substrate 50, a gate insulating layer 51, and a gate electrode 52.

[0081] Vias 53A are respectively provided in the source region 50A and the drain region 50A along the positive Z-direction, and conductive layers 54A are respectively provided in the vias 53A. Vias 55A, conductive layers 56A, vias 57A, conductive layers 58A, vias 59A, and conductive pads 60A are sequentially provided in the conductive layers 54A along the positive Z-direction. The conductive pads 60A are disposed on the surface of the peripheral circuit chip 200 in the positive Z-direction.

[0082] Vias 53B are respectively provided in another source region 50A and drain region 50A along the positive Z direction, and conductive layers 54B are respectively provided in the vias 53B. Vias 55B, conductive layers 56B, vias 57B, conductive layers 58B, vias 59B, and conductive pads 60B are sequentially provided in the conductive layers 54B along the positive Z direction. The conductive pads 60B are disposed on the surface of the peripheral circuit chip 200 in the positive Z direction.

[0083] The memory array chip 100 and the peripheral circuit chip 200 are respectively bonded together, for example, with conductive pads including conductive pad 38 and conductive pad 60A, and conductive pad 44 and conductive pad 60B facing each other. Thus, conductive pad 38 and conductive pad 60A are joined and electrically connected. Similarly, conductive pad 44 and conductive pad 60B are joined and electrically connected.

[0084] Next, another structural example of the semiconductor memory device according to the first embodiment will be described. Figure 4In the example shown, a semiconductor memory device 10 in which the memory array chip 100 is attached to the peripheral circuit chip 200 is described as an example, but the application is not limited to this and can also be applied to semiconductor memory devices having other configurations.

[0085] Figure 5 is a cross-sectional view showing another configuration example of the semiconductor memory device of the first embodiment. For example, as shown in Figure 5 , it can also be applied to a semiconductor memory device 10A in which the region 84 in which the memory cells are formed and the region 85 in which the peripheral circuit is formed are provided on one semiconductor substrate 30. In addition, in Figure 5 , the interlayer insulating film between the conductive layers is omitted.

[0086] The cross-sectional configuration of the region 84 in which the memory cells are formed is as follows.

[0087] The plurality of memory pillars MP in which the columnar body is provided on the laminate including the conductive layers 32 to 34 of the semiconductor substrate 30. Each memory pillar MP extends in the Z direction and is disposed so as to penetrate the conductive layers 32 to 34 in the Z direction.

[0088] The contact plug CPI is provided in the positive direction of the Z direction of the memory pillar MP, and the conductive layer 35 is provided in the contact plug CPI. The conductive layer 36, the via 37, and the conductive layer 45 are sequentially provided in the positive direction of the Z direction of the conductive layer 35. Details of the memory pillar MP and the conductive layer 35 will be described below.

[0089] The cross-sectional configuration of the region 85 in which the peripheral circuit is formed is as follows.

[0090] The CMOS circuit CM including, for example, an nMOS transistor and a pMOS transistor is provided in the semiconductor substrate 30. The source region and the drain region 70A and the element isolation region 70B are provided in the semiconductor substrate 30. The gate insulating layer 71 is provided in the positive direction of the Z direction of the semiconductor substrate 30 between the source region 70A and the drain region 70A, and the gate electrode 72 is provided in the gate insulating layer 71. The nMOS transistor and the pMOS transistor each include the source region 70A, the drain region 70A, the semiconductor layer of the semiconductor substrate 30, the gate insulating layer 71, and the gate electrode 72.

[0091] The via 73 is provided in the positive direction of the Z direction of the source region 70A and the drain region 70A, respectively, and the conductive layer 74 is provided in the via 73, respectively. The via 75, the conductive layer 76, the via 77, the via 78, the conductive layer 79, the via 80, the conductive layer 81, the via 82, and the conductive layer 83 are sequentially provided in the positive direction of the Z direction of the conductive layer 74.

[0092] Next, the operation of the semiconductor memory device 10 will be described. Figure 6A cross-sectional configuration of a memory pillar MP (or a NAND string NS) in the memory cell array 11 will be described. The memory pillar MP includes memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2.

[0093] Figure 6 is a cross-sectional view of the memory pillar MP in the memory cell array 11 in the first embodiment. Figure 6 In Figure 4 indicates a state rotated by 180 degrees, and in Figure 5 indicates a state not rotated. Further, in Figure 6 , an interlayer insulating film between the conductive layers is omitted.

[0094] As Figure 6 indicated, the memory cell array 11 includes a semiconductor substrate 30, conductive layers 31 to 34, a memory pillar MP, a contact plug CP1, and a conductive layer 35. The conductive layer 31 is provided above the semiconductor substrate 30. The conductive layer 31 is formed in a flat plate shape parallel to the XY plane, and functions as a source line SL. Further, a main surface of the semiconductor substrate 30 corresponds to the XY plane.

[0095] A plurality of slits SLT along the XZ plane are arranged in the Y direction on the conductive layer 31. A structure (or a laminate) on the conductive layer 31 and between adjacent slits SLT, for example, corresponds to one string unit SU.

[0096] The conductive layer 32, a plurality of conductive layers 33, the conductive layer 34, and the conductive layer 35 are sequentially provided from the lower layer on the conductive layer 31 and between adjacent slits SLT. Adjacent conductive layers in the Z direction among these conductive layers are laminated with an interlayer insulating film interposed therebetween. The conductive layers 32 to 34 are each formed in a flat plate shape parallel to the XY plane. The conductive layer 32 functions as a selection gate line SGS. The plurality of conductive layers 33 sequentially function as word lines WLO to WL7 from the lower layer, respectively. The conductive layer 34 functions as a selection gate line SGD. The conductive layers 32 to 34, for example, include tungsten (W).

[0097] The plurality of memory pillars MP are arranged in a staggered manner, for example, in the X direction and the Y direction. The plurality of memory pillars MP each extend (or penetrate) in the Z direction within the laminate between the slits SLT. Each memory pillar MP is provided through the conductive layers 34, 33, and 32 in a manner reaching the upper surface of the conductive layer 31 from the upper surface of the conductive layer 34. Each memory pillar MP functions as one NAND string NS.

[0098] The memory pillar MP has, for example, a barrier insulating layer 61, a charge storage layer 62, a tunnel insulating layer (also referred to as a tunnel insulating film) 63, and a semiconductor layer 64. Specifically, the barrier insulating layer 61 is provided on the inner wall of a memory hole for forming the memory pillar MP. The charge storage layer 62 is provided on the inner wall of the barrier insulating layer 61. The tunnel insulating layer 63 is provided on the inner wall of the charge storage layer 62. Further, the semiconductor layer 64 is provided on the inner side of the tunnel insulating layer 63. In addition, the memory pillar MP can also be configured to have a core insulating layer provided inside the semiconductor layer 64.

[0099] In this configuration of the memory pillar MP, the portion where the memory pillar MP intersects with the conductive layer 32 functions as the selection transistor ST2. The portions where the memory pillar MP intersects with the conductive layers 33 function as the memory cell transistors MT0 to MT7, respectively. Further, the portion where the memory pillar MP intersects with the conductive layer 34 functions as the selection transistor ST1.

[0100] The semiconductor layer 64 functions as a channel layer of the memory cell transistors MT and the selection transistors ST1 and ST2. The current path of the NAND string NS is formed inside the semiconductor layer 64.

[0101] The charge storage layer 62 has a function of storing the charge injected from the semiconductor layer 64 in the memory cell transistor MT. The charge storage layer 62 contains, for example, a silicon nitride film.

[0102] The tunnel insulating layer 63 functions as a potential barrier when injecting the charge from the semiconductor layer 64 to the charge storage layer 62 or diffusing the charge stored in the charge storage layer 62 to the semiconductor layer 64. The tunnel insulating layer 63 contains, for example, a silicon oxide film.

[0103] The barrier insulating layer 61 prevents the charge stored in the charge storage layer 62 from diffusing to the conductive layer 33 (word line WL). The barrier insulating layer 61 contains, for example, a silicon oxide layer and a silicon nitride layer.

[0104] Above the upper surface of the memory pillar MP, the interlayer insulating film is provided with the conductive layer 35 including the via 35A, the conductive layer 35B, and the via 35C. The conductive layer 35B is a linear wiring layer extending in the Y direction and functions as a bit line BL. A plurality of conductive layers 35 are arranged in the X direction, and the conductive layer 35 is electrically connected to one memory pillar MP corresponding to each string unit SU. Specifically, in each string unit SU, a contact plug CP1 is provided on the semiconductor layer 64 inside each memory pillar MP, and one conductive layer 35 is provided on the contact plug CP1. The conductive layer 35 contains, for example, copper (Cu) or aluminum (Al), tungsten (W). The contact plug CP1 contains a conductive layer, for example, tungsten (W).

[0105] Further, the number of the word lines WL, and the selection gate lines SGD and SGS is not limited to the number described above, and is changed in accordance with the number of the memory cell transistors MT, and the selection transistors ST1 and ST2, respectively. The selection gate line SGS can also include a plurality of conductive layers provided in a plurality of layers, respectively. The selection gate line SGD can also include a plurality of conductive layers provided in a plurality of layers, respectively.

[0106] 1.2.1 Configuration of the conductive layer 35 on the memory pillar

[0107] By using Figures 7-9 , the conductive layer 35 represented by the region BC in Figure 4 , and Figure 5 , an example of the configuration of the conductive layer 35 will be described. Each of the conductive layers 35 is one layer including the via 35A, the conductive layer 35B (or the bit line BL), and the via 35C.

[0108] Figure 7 is a plan view of the via 35A, the conductive layer 35B, and the via 35C in the semiconductor storage device 10 of the first embodiment. Figure 8 is a cross-sectional view along the B-B line in Figure 7 , and represents a cross section of the via 35A, the conductive layer 35B, and the via 35C along the X direction. Figure 9 is a cross-sectional view along the C-C line in Figure 7 , and represents a cross section of the via 35A, the conductive layer 35B, and the via 35C along the Y direction.

[0109] As shown in Figure 7 , Figure 8 , and Figure 9 , a plurality of the conductive layers 35B extend along the Y direction. The conductive layers 35B extending along the Y direction are arranged at a prescribed interval along the X direction. The via 35A and the via 35C are respectively arranged along the Z direction at each of the conductive layers 35B. Each of the vias 35A extends along the Z direction, and is provided below each of the conductive layers 35B, or on the semiconductor substrate 30 (or the contact plug CPI) side of each of the conductive layers 35B. Each of the vias 35C extends along the Z direction, and is provided above each of the conductive layers 35B, or on the conductive layer 36 side of each of the conductive layers 35B.

[0110] The via 35A is continuously formed with the conductive layer 35B. There is no boundary region between the via 35A and the conductive layer 35B. The via 35C is continuously formed with the conductive layer 35B. There is no boundary region between the via 35C and the conductive layer 35B. In other words, the conductive layer 35B has the via 35A protruding downward, and the via 35C protruding upward.

[0111] Hereinafter, by using Figure 8 , and Figure 9The configuration of the via 35A, the conductive layer 35B, and the via 35C will be described in detail.

[0112] The contact plug CP1 is provided in the insulating layer 90. The via 35A is provided in the insulating layer 90 on the contact plug CP1. The conductive layer 35B is arranged at a prescribed interval in the X direction on the via 35A and the insulating layer 90. The insulating layer 91 is arranged between the conductive layers 35B on the insulating layer 90. The insulating layer 92 is provided on the insulating layer 91 and the conductive layer 35B. The via 35C is provided in the insulating layer 92 on the conductive layer 35B. Further, the conductive layer 36 is provided on the via 35C.

[0113] In the X direction, the first width of the conductive layer 35B near the via 35A is greater than the second width of the conductive layer 35B farther from the via 35A than the first width. The via 35A has a cylindrical shape extending in the Z direction, and the first diameter of the via 35A near the conductive layer 35B is greater than the second diameter of the via 35A farther from the conductive layer 35B than the first diameter. The via 35C has a cylindrical shape extending in the Z direction, and the third diameter of the via 35C near the conductive layer 35B is greater than the fourth diameter of the via 35C farther from the conductive layer 35B than the third diameter. In the X direction, the width of the conductive layer 35B is greater than the diameter of the via 35C.

[0114] The via 35A, the conductive layer 35B, and the via 35C are continuously formed between the contact plug CP1 and the conductive layer 36. The via 35A, the conductive layer 35B, and the via 35C are electrically connected and electrically connect between the contact plug CP1 and the conductive layer 36.

[0115] Furthermore, here, the case where the via 35A and the via 35C are arranged in the Z direction will be described. Figure 7 The via 35A and the via 35C are illustrated as being in the shape of an oblate circle or an ellipse having a long diameter in the Y direction in plan view, but are not limited thereto, and the via 35A and the via 35C can also be in the shape of a circle. In addition, in the case where the via 35A and the via 35C are arranged in the Z direction, the via 35A and the via 35C can also be arranged in the Z direction so as to overlap each other. Figure 9 In the case where the via 35A and the via 35C are arranged in the Z direction, the via 35A and the via 35C can also be arranged so as not to overlap each other in the Z direction. Figure 10 The via 35A and the via 35C are illustrated as being in the shape of an oblate circle or an ellipse having a long diameter in the Y direction in plan view, but are not limited thereto, and the via 35A and the via 35C can also be in the shape of a circle. In addition, in the case where the via 35A and the via 35C are arranged in the Z direction, the via 35A and the via 35C can also be arranged in the Z direction so as to overlap each other. Figure 11 The via 35A and the via 35C are illustrated as being in the shape of an oblate circle or an ellipse having a long diameter in the Y direction in plan view, but are not limited thereto, and the via 35A and the via 35C can also be in the shape of a circle. In addition, in the case where the via 35A and the via 35C are arranged in the Z direction, the via 35A and the via 35C can also be arranged in the Z direction so as to overlap each other.

[0116] 1.3 Manufacturing method of semiconductor storage device

[0117] Hereinafter, a manufacturing method of the conductive layer 35 on the storage pillar will be described.

[0118] 1.3.1 Manufacturing method of conductive layer 35

[0119] The manufacturing method of the conductive layer 35 will be described with reference to FIG. 8. Figures 12-21 The manufacturing method of the conductive layer 35 will be described with reference to FIG. 8. Figure 8and Figure 9 The manufacturing method of the conductive layer 35, which includes through-hole 35A, conductive layer 35B and through-hole 35C, will be described. Figures 12-21 A cross-sectional view showing the manufacturing method of the through hole 35A, conductive layer 35B and through hole 35C in the first embodiment. Figures 12-17 , Figure 19 ,and Figure 21 Indicates along Figure 7 The cross-section of the manufacturing process of the conductive layer 35 of the BB wire. Figure 18 and Figure 20 Indicates along Figure 7 The cross-section of the manufacturing process of the conductive layer 35 of the CC line.

[0120] First, such as Figure 12 As shown, a hole 90A for embedding a through-hole 35A is formed within the insulating layer 90 on the contact plug CP1. Specifically, the hole 90A for the through-hole 35A is formed by removing material from the upper surface of the insulating layer 90 to the upper surface of the contact plug CP1 using a reactive ion etching (RIE) method. The insulating layer 90, for example, comprises a silicon oxide layer. The contact plug CP1 comprises a conductive material, such as tungsten (W), aluminum (Al), or titanium (Ti).

[0121] Next, as Figure 13 As shown, a conductive layer 35H is formed within the hole 90A used for the via 35A and on the insulating layer 90. Specifically, the conductive layer 35H is formed within the hole 90A and on the insulating layer 90 by ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or sputtering. The height (or thickness) of the conductive layer 35H formed on the insulating layer 90 is the sum of the height (or thickness) of the conductive layer 35B and the height (or length) of the via 35C. The conductive layer 35H may contain, for example, tungsten or aluminum.

[0122] Next, as Figure 14 As shown, a plurality of conductive layers 35I are formed by patterning the conductive layer 35H. Each conductive layer 35I has a height that is the sum of the height of the conductive layer 35B and the height of the via 35C. Specifically, the conductive layer 35H on the insulating layer 90 is etched using a sidewall processing process or a double patterning technique to form conductive layers 35I arranged at specified intervals along the X direction.

[0123] Next, as Figure 15 As shown, in Figure 14In the illustrated structure, an insulating layer 91 is formed on the insulating layer 90 and the conductive layer 35I. Then, an amorphous silicon layer 93, a carbon layer 94, and an oxide layer 95 are sequentially formed on the insulating layer 91. Next, a resist layer 96 is formed on the oxide layer 95. Specifically, the insulating layer 91 is formed on the insulating layer 90 and the conductive layer 35I using an ALD or CVD method. An amorphous silicon layer 93 is formed on the insulating layer 91 using an ALD or CVD method. Then, a carbon layer 94 and an oxide layer 95 are sequentially formed on the amorphous silicon layer 93. Finally, a patterned resist layer 96 is formed on the oxide layer 95. The carbon layer 94, the oxide layer 95, and the resist layer 96 constitute a multilayer resist structure.

[0124] The carbon layer 94 is, for example, a spin-on carbon (SOC) layer coated on the amorphous silicon layer 93 by spin coating. The oxide layer 95 is, for example, a spin-on glass (SOG) layer coated on the carbon layer 94 by spin coating.

[0125] Next, the RIE method was used to... Figure 15 The structure shown is etched, as follows Figure 16 As shown, an amorphous silicon layer 93A remains only above the conductive layer 35I connected to the contact plug CP1.

[0126] Next, the RIE method was used to... Figure 16 The structure shown is etched, as follows Figure 17 and Figure 18 As shown, the insulating layer 91 in the area where the amorphous silicon layer 93A is not disposed is removed. This exposes the upper portion of the conductive layer 35I, except for the conductive layer 35I connected to the contact plug CP1, from the insulating layer 91. At this time, the amorphous silicon layer 93A and the insulating layer 91 remain above the conductive layer 35I connected to the contact plug CP1.

[0127] Next, the RIE method was used to... Figure 17 and Figure 18 The structure shown is etched, as follows Figure 19 and Figure 20 As shown, the exposed conductive layer 35I is removed from the upper surface of the insulating layer 91 up to the midpoint of the height of the insulating layer 91. This forms the conductive layer 35B and the via 35C.

[0128] Next, the RIE method was used to... Figure 19 and Figure 20 The structure shown is etched, as follows Figure 21 As shown, the insulating layer 91 between conductive layers 35B is removed from the upper surface of conductive layer 35B to the midpoint of the height of conductive layer 35B.

[0129] Next, as Figure 8 andFigure 9 The insulating layer 92 is formed on the insulating layer 91 and the conductive layer 35B by an ALD method or a CVD method. Figure 21 The insulating layer 92 is formed on the insulating layer 91 and the conductive layer 35B by an ALD method or a CVD method.

[0130] The via 35A, the conductive layer 35B, and the via 35C are formed on the contact plug CP1 on the memory pillar MP by the above manufacturing steps.

[0131] 1.4 Effects of the First Embodiment

[0132] According to the first embodiment, it is possible to reduce the size of the semiconductor memory device (or the size of the semiconductor chip). Further, it is possible to improve the reliability of the operation in the semiconductor memory device.

[0133] Hereinafter, the effects of the first embodiment will be described in detail.

[0134] In the first embodiment, the via (or the contact plug) 35A provided above the semiconductor substrate, the conductive layer 35B provided on the via 35A, and the via (or the contact plug) 35C provided on the conductive layer 35B are provided. The via 35A, the conductive layer 35B, and the via 35C are one layer in series. In other words, the via 35A, the conductive layer 35B, and the via 35C are one layer integrally formed, and there is no boundary region between the via 35A and the conductive layer 35B and between the conductive layer 35B and the via 35C. According to this configuration, it is possible to reduce the positional misalignment between the via 35A, the conductive layer 35B, and the via 35C, which occurs when the via 35A, the conductive layer 35B, and the via 35C are separately formed.

[0135] For example, in a semiconductor memory device having a configuration in which the memory array chip 100 and the peripheral circuit chip 200 are attached to each other, there is a case in which the via 35C for connecting from the conductive layer 35B (for example, the bit line BL) to the conductive pad 38 is formed directly above the conductive layer 35B. In this case, the arrangement interval of the conductive layer 35B is fine, and thus a high positional accuracy is required between the conductive layer 35B and the via 35C.

[0136] In the present embodiment, because the via 35A, the conductive layer 35B, and the via 35C are one layer, it is possible to reduce the positional misalignment between the via 35A, the conductive layer 35B, and the via 35C. Thus, it is possible to satisfy the requirement for the high positional accuracy.

[0137] Further, in the configuration design of the semiconductor storage device, the margin of the alignment accuracy is taken into account to determine the size and interval of the conductive layer and the via, thereby determining the size of the semiconductor storage device. According to the present embodiment, since the margin of the alignment accuracy can be reduced, the size and interval of the conductive layer and the via can be reduced, thereby the size of the semiconductor storage device can be reduced.

[0138] That is, the present embodiment has a configuration capable of reducing the margin of the alignment accuracy required for the via 35A, the conductive layer 35B, and the via 35C, and thus, the size and arrangement interval of the via 35A, the conductive layer 35B, and the via 35C can be reduced, and further, the size of the semiconductor storage device can be reduced.

[0139] In addition, since the alignment deviation generated among the via 35A, the conductive layer 35B, and the via 35C can be reduced, the increase in resistance due to the reduction in contact area and the like caused by the alignment deviation among the via 35A, the conductive layer 35B, and the via 35C can be reduced, and thus, the reliability of the operation can be improved.

[0140] Through the above, according to the semiconductor storage device of the first embodiment, the size (or the semiconductor chip size) of the semiconductor storage device can be reduced. Further, the reliability of the operation in the semiconductor storage device can be improved.

[0141] 2. Second Embodiment

[0142] Next, the semiconductor storage device of the second embodiment will be described. In the second embodiment, the via, the wiring layer, and the via sequentially provided on the CMOS circuit CM configuring the peripheral circuit will be exemplified and described. In the second embodiment, mainly the aspects different from the first embodiment will be described.

[0143] 2.1 Configuration of Semiconductor Storage Device

[0144] Next, an example of the configuration of the semiconductor storage device of the second embodiment will be described.

[0145] Figure 22 is a cross-sectional view of the semiconductor storage device of the second embodiment along the XZ plane. Further, in Figure 22 , the interlayer insulating film between the conductive layers is omitted. The semiconductor storage device 10 has the same configuration as the semiconductor storage device shown in Figure 4 , in which the memory array chip 100 and the peripheral circuit chip 200 are bonded.

[0146] Next, the cross-sectional configuration in the memory array chip 100 will be described in detail.

[0147] The conductive layer 31 is provided in the negative direction of the Z direction with respect to the semiconductor substrate 30 with the insulating layer interposed therebetween. The laminated body of the conductive layer 32, the plurality of conductive layers 33, and the conductive layer 34 is laminated in the negative direction of the Z direction with respect to the conductive layer 31 with the insulating layer interposed therebetween. The conductive layers 31 to 34 extend in the X direction. The conductive layers 31 to 34 have a flat plate shape along (or parallel to) the XY plane (or the surface of the semiconductor substrate 30).

[0148] The plurality of memory pillars MP of the columnar body is provided in the laminated body including the conductive layers 32 to 34. The contact plug CPI is provided in each of the memory pillars MP in the negative direction of the Z direction, and the via 47 is provided in the contact plug CPI. The conductive layer 48, the via 49, the conductive layer 36, the via 37, and the conductive pad 38 are sequentially provided in the negative direction of the Z direction with respect to the via 47. The other configurations are the same as those of the semiconductor memory device 10 shown in Figure 4

[0149] Hereinafter, the cross-sectional configuration in the peripheral circuit chip 200 will be described in detail.

[0150] The CMOS circuit CM including, for example, an nMOS transistor and a pMOS transistor is provided in the semiconductor substrate 50. The via 53B is provided in each of the source region 50A and the drain region 50A in the positive direction of the Z direction, and the conductive layer 54B is provided in each of the vias 53B. The via 79A, the conductive layer 79B, and the via 79C are sequentially provided in the positive direction of the Z direction with respect to the conductive layer 54B. The conductive layer 58B, the via 59B, and the conductive pad 60B are sequentially provided in the positive direction of the Z direction with respect to the via 79C. The other configurations are the same as those of the semiconductor memory device 10 shown in Figure 4

[0151] Next, another configuration example of the semiconductor memory device of the second embodiment will be described. In the example shown in Figure 22 the semiconductor memory device 10 in which the memory array chip 100 and the peripheral circuit chip 200 are attached to each other is exemplified, but should not be limited thereto, and can be applied to a semiconductor memory device having other configurations.

[0152] Figure 23 is a cross-sectional view showing another configuration example of the semiconductor memory device of the second embodiment. For example, as Figure 23 shown, it can be applied to the semiconductor memory device 10A in which the region 84 in which the memory cell is formed and the region 85 in which the peripheral circuit is formed are provided on one semiconductor substrate 30. Further, in Figure 23 , the interlayer insulating film between the conductive layers is omitted.

[0153] Hereinafter, the cross-sectional configuration of the region 84 in which the memory cell is formed will be described.

[0154] ​​A contact plug CP1 is provided in the positive direction of the Z direction of the memory pillar MP, and a through-hole 47 is provided in the contact plug CP1. A conductive layer 48, a through-hole 49, a conductive layer 36, a through-hole 37, and a conductive layer 38 are provided in the positive direction of the Z direction of the through-hole 47. The other configurations are the same as those of the semiconductor storage device 10A shown in FIG. 1. Figure 5 The configuration of the semiconductor storage device 10A shown in FIG. 1 is the same as that of the semiconductor storage device 10B.

[0155] Next, the cross-sectional configuration of the region 85 in which the peripheral circuit is formed will be described.

[0156] A CMOS circuit CM including, for example, an nMOS transistor and a pMOS transistor is provided in the semiconductor substrate 30. A through-hole 73 is provided in the positive direction of the Z direction of the source region 70A and the drain region 70A, and a conductive layer 74 is provided in the through-hole 73. A through-hole 75, a conductive layer 76, and a through-hole 77 are provided in the positive direction of the Z direction of the conductive layer 74. A through-hole 86A, a conductive layer 86B, and a through-hole 86C are provided in the positive direction of the Z direction of the through-hole 77. A conductive layer 81, a through-hole 82, and a conductive layer 83 are provided in the positive direction of the Z direction of the through-hole 86C. The other configurations are the same as those of the semiconductor storage device 10A shown in FIG. 1. Figure 5 The configuration of the semiconductor storage device 10A shown in FIG. 1 is the same as that of the semiconductor storage device 10B.

[0157] 2.1.1 Configuration of the conductive layer 86 on the peripheral circuit

[0158] The configuration of the conductive layer 86 in the region LC in the semiconductor storage device 10B shown in FIG. 2 will be described. Figure 24 and Figure 25 The configuration of the conductive layer 86 in the region LC in the semiconductor storage device 10B shown in FIG. 2 will be described. Figure 22 and Figure 23 An example of the configuration of the conductive layer 86 in the region LC in the semiconductor storage device 10B shown in FIG. 2 will be described. Each conductive layer 86 is one layer including a through-hole 86A, a conductive layer 86B, and a through-hole 86C.

[0159] Figure 24 is a cross-sectional view of the conductive layer 86 along the XZ plane in the second embodiment, and shows a cross section of the through-hole 86A, the conductive layer 86B, and the through-hole 86C along the XZ plane. Figure 25 is a cross-sectional view of the conductive layer 86 along the YZ plane, and shows a cross section of the through-hole 86A, the conductive layer 86B, and the through-hole 86C along the YZ plane.

[0160] As shown in Figure 24 and Figure 25As shown, the plurality of conductive layers 86B extend in the Y direction. The conductive layers 86B extending in the Y direction are arranged at specified intervals in the X direction. The via holes 86A and the via holes 86C are respectively arranged below the respective conductive layers 86B in the Z direction. In other words, on the side of the semiconductor substrate 50 or 30 of the respective conductive layers 86B, or on the side of the conductive layer 54B or the contact plug 77. The respective via holes 86C extend in the Z direction and are arranged above the respective conductive layers 86B, in other words, on the side of the conductive layer 58B or the conductive layer 81 of the respective conductive layers 86B.

[0161] The via hole 86A and the conductive layer 86B are continuously formed. There is no boundary region between the via hole 86A and the conductive layer 86B. The via hole 86C and the conductive layer 86B are continuously formed. There is no boundary region between the via hole 86C and the conductive layer 86B. In other words, the conductive layer 86B has a via hole 86A protruding downward and a via hole 86C protruding upward.

[0162] Hereinafter, the configuration of the via hole 86A, the conductive layer 86B, and the via hole 86C will be described in detail using Figure 24 and Figure 25 .

[0163] The conductive layer 54B (or the via hole 77) is provided in the insulating layer 90. The via hole 86A is provided in the insulating layer 90 on the conductive layer 54B. The conductive layer 86B is provided on the via hole 86A and the insulating layer 90. The insulating layer 91 is provided in a region of the insulating layer 90 where the conductive layer 86B is not present. The insulating layer 92 is provided on the insulating layer 91 and the conductive layer 86B. The via hole 86C is provided in the insulating layer 92 on the conductive layer 86B. Further, the conductive layer 58B (or 81) is provided on the via hole 86C.

[0164] In the X direction, the first width of the conductive layer 86B close to the via hole 86A is greater than the second width of the conductive layer 86B farther from the via hole 86A than the first width. The via hole 86A has a columnar shape extending in the Z direction, and the first diameter of the via hole 86A close to the conductive layer 86B is greater than the second diameter of the via hole 86A farther from the conductive layer 86B than the first diameter. The via hole 86C has a columnar shape extending in the Z direction, and the third diameter of the via hole 86C close to the conductive layer 86B is greater than the fourth diameter of the via hole 86C farther from the conductive layer 86B than the third diameter. In the X direction, the width of the conductive layer 86B is greater than the diameter of the via hole 86C.

[0165] The via hole 86A, the conductive layer 86B, and the via hole 86C are continuously formed between the conductive layer 54B (or the via hole 77) and the conductive layer 58B (or 81). The via hole 86A, the conductive layer 86B, and the via hole 86C are electrically connected and electrically connect between the conductive layer 54B and the conductive layer 58B.

[0166] Further, as described in the first embodiment, the through-hole 86A and the through-hole 86C are described as being an oblong or an ellipse having a long diameter in the Y direction, but not limited thereto, and the through-hole 86A and the through-hole 86C can be a circle. In addition, in the first embodiment, the through-hole 86A and the through-hole 86C are described as being arranged in a manner of overlapping in the Z direction, but not limited thereto, and the through-hole 86A and the through-hole 86C can be arranged in a manner of not overlapping in the Z direction. Further, a plurality of through-holes 86C can be arranged on the conductive layer 86B. Figure 25

[0167] 2.2 Manufacturing method of the conductive layer 86

[0168] The manufacturing method of the conductive layer 86 on the peripheral circuit is the same as that described in the first embodiment except for the following aspects.

[0169] The width and the arrangement interval of the through-hole 86A, the conductive layer 86B, and the through-hole 86C in the X direction on the peripheral circuit CM are set to be larger than the width and the arrangement interval of the through-hole 35A, the conductive layer 35B, and the through-hole 35C in the X direction described in the first embodiment in most cases. Therefore, in the second embodiment, the formation of the conductive layer 86B and the through-hole 86C can not use the side wall processing process used in the steps described in the first embodiment. The manufacturing method in the second embodiment is substantially the same as that in the first embodiment except for not using the side wall processing process. Figure 14

[0170] 2.3 Effects of the second embodiment

[0171] According to the second embodiment, as with the first embodiment, it is possible to reduce the size of the semiconductor memory device (or the semiconductor chip size). Further, it is possible to improve the reliability of the operation in the semiconductor memory device. Other effects and the like are the same as those of the first embodiment.

[0172] 3. Other variations and the like

[0173] In the embodiments, the semiconductor memory device 10 in which the memory array chip 100 and the peripheral circuit chip 200 are attached, and the semiconductor memory device 10A in which the region 84 in which the memory cell is formed and the region 85 in which the peripheral circuit is formed are provided on one semiconductor substrate 30 are exemplified and described, but not limited thereto, and can be applied to semiconductor devices having other configurations.

[0174] ​​Further, in the embodiment, a NAND type flash memory is described as an example of the semiconductor storage device, but is not limited to the NAND type flash memory, and can be applied to all other semiconductor memories, and further, can be applied to various storage devices other than the semiconductor memories.

[0175] The present application has been described with several embodiments, but these embodiments are presented as examples, and are not intended to limit the scope of the application. These embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the scope of the application. These embodiments or changes thereof are included in the scope or spirit of the application, and are also included in the scope of the application and equivalents thereof described in the claims.

[0176] [Explanation of symbols]

[0177] 10, 10A semiconductor storage device

[0178] 11, 11A, 11B memory cell array

[0179] 12 input / output circuit

[0180] 13 logic control circuit

[0181] 14 ready / busy circuit

[0182] 15 register group

[0183] 16 sequencer (or control circuit)

[0184] 17 voltage generation circuit

[0185] 18 driver

[0186] 19 row decoder module

[0187] 20 column decoder

[0188] 21 sense amplifier module

[0189] 22A, 22B, 22C lead-out region

[0190] 30 semiconductor substrate

[0191] 31 to 35 conductive layer

[0192] 35A via hole

[0193] 35B conductive layer

[0194] 35C via hole

[0195] 35H, 35I conductive layer

[0196] 36 conductive layer

[0197] 37 via hole

[0198] 38 conductive pad

[0199] 39 via hole

[0200] 40 conductive layer

[0201] 41 via hole

[0202] 42 conductive layer

[0203] 43 via hole

[0204] 44 conductive pad

[0205] 45 conductive layer

[0206] 50 semiconductor substrate

[0207] 50A source region or drain region

[0208] 50B element separation region

[0209] 51 gate insulating layer

[0210] 52 gate electrode

[0211] 53A, 53B via hole

[0212] 54A, 54B conductive layer

[0213] 55A, 55B via hole

[0214] 56A, 56B conductive layer

[0215] 57A, 57B via hole

[0216] 58A, 58B conductive layer

[0217] 59A, 59B via hole

[0218] 60A, 60B conductive pad

[0219] 70A source region or drain region

[0220] 70B element separation region

[0221] 71 gate insulating layer

[0222] 72 gate electrode

[0223] 73 via hole

[0224] 74 conductive layer

[0225] 75 via hole

[0226] 76 conductive layer

[0227] 77 via

[0228] 78 via

[0229] 79 conductive layer

[0230] 80 via

[0231] 81 conductive layer

[0232] 82 via

[0233] 83 conductive layer

[0234] 84, 85 region

[0235] 86 conductive layer

[0236] 86A via

[0237] 86B conductive layer

[0238] 86C via

[0239] 90, 91, 92 insulating layer

[0240] 100 memory array chip

[0241] 200 peripheral circuit chip

[0242] BL, BL0-BLi bit line

[0243] BLK, BLK0-BLKm block

[0244] CM CMOS circuit

[0245] CP1, CP2 contact plug

[0246] MP memory pillar

[0247] MT, MT0-MT7 memory cell transistor

[0248] SGD, SGD0-SGD3 select gate line

[0249] SGS select gate line

[0250] SL source line

[0251] ST1, ST2 select transistor

[0252] SU, SU0-SU3 string unit

[0253] WL, WL0-WL7 word line

Claims

1. A semiconductor memory device comprising: a laminate body in which a plurality of conductive layers are laminated in a first direction; a pillar including a semiconductor layer and extending in the first direction within the laminate body; a charge storage layer provided between the plurality of conductive layers and the semiconductor layer; a first contact plug extending in the first direction and provided above the laminate body and electrically connected to the semiconductor layer; a first conductive layer provided in contact with an upper side of the first contact plug and extending in a second direction intersecting the first direction; and a second contact plug provided in contact with an upper side of the first conductive layer and extending in the first direction, and wherein the first contact plug, the first conductive layer, and the second contact plug are continuous as one layer, the first direction intersects an upper surface of a substrate, the semiconductor memory device further comprises: a plurality of second conductive layers laminated between the substrate and the first contact plug in the first direction; and a pillar penetrating the plurality of second conductive layers in the first direction and electrically connected to the first contact plug, a portion where the plurality of second conductive layers intersect the pillar functions as a memory cell transistor, the first conductive layer is a bit line through which a current from the memory cell transistor flows, and the plurality of second conductive layers are word lines connected to gates of the memory cell transistor.

2. The semiconductor memory device according to claim 1, wherein there is no interface region between the first contact plug and the first conductive layer and between the first conductive layer and the second contact plug.

3. The semiconductor memory device according to claim 1 or 2, wherein in a third direction intersecting the first direction and the second direction, a first width of the first conductive layer near the first contact plug is greater than a second width of the first conductive layer farther from the first contact plug than the first width.

4. The semiconductor memory device according to claim 1 or 2, wherein the first contact plug has a columnar shape extending in the first direction, and a first diameter of the first contact plug near the first conductive layer is greater than a second diameter of the first contact plug farther from the first conductive layer than the first diameter.

5. The semiconductor memory device according to claim 1 or 2, wherein the second contact plug has a columnar shape extending in the first direction, and a third diameter of the second contact plug near the first conductive layer is greater than a fourth diameter of the second contact plug farther from the first conductive layer than the third diameter.

6. The semiconductor memory device according to claim 1 or 2, wherein in a third direction intersecting the first direction and the second direction, a width of the first conductive layer is greater than a diameter of the second contact plug. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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