Semiconductor storage device and method for manufacturing semiconductor storage device

Abstract

To easily form contacts respectively connected to a plurality of conductive layers with a height difference.SOLUTION: A semiconductor storage device of an embodiment comprises: a stopper layer arranged above a part of a stepped part; a plurality of first contacts extending from a height position above a laminate to a position overlapping the stepped part and the laminate in a lamination direction and respectively connected to a portion in which a plurality of first conductive layers on the lower layer side including the lowest conductive layer of the plurality of conductive layers are processed into a stepped shape; and a plurality of second contacts extending from a height position above the laminate to a position overlapping the stepped part in the lamination direction and respectively connected to a portion in which a plurality of second conductive layers on the upper layer side including the uppermost conductive layer of the plurality of conductive layers are processed into a stepped shape. The plurality of first contacts extend in the lamination direction through the stopper layer, whereas the plurality of second contacts extend in the lamination direction without penetrating the stopper layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices such as 3D nonvolatile memories, memory cells are arranged three-dimensionally in a stack of multiple conductive layers stacked one layer at a time and spaced apart from each other. These conductive layers are processed into a stepped shape in some areas of the stack, and contacts are connected to each conductive layer. The challenge is how to form contacts that are connected to multiple conductive layers that belong to different layers of the stack and have different heights. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-138941 [Patent Document 2] Patent Publication No. 2021-27332 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device and a method for manufacturing the semiconductor memory device that can easily form contacts that are connected to a plurality of conductive layers having different heights. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment includes a stacked body in which a plurality of conductive layers are stacked and spaced apart from one another; a staircase portion disposed in a portion of the stacked body and in which the plurality of conductive layers are processed into a staircase shape; a stopper layer disposed above a portion of the staircase portion; a plurality of first contacts extending from a height position above the stacked body and connected to the staircase portion of a plurality of first conductive layers on a lower layer side including a lowest conductive layer among the plurality of conductive layers; and a stopper layer disposed at a position overlapping the staircase portion in the stacked body direction. and a plurality of second contacts extending from a height position above the stack and connected to respective portions of a plurality of second conductive layers on an upper layer side including an uppermost conductive layer among the plurality of conductive layers, the second contacts being processed in a stepped manner, the stopper layer being disposed at least at a position overlapping with the portions of the plurality of first conductive layers being processed in a stepped manner in the stacking direction, the plurality of first contacts extending in the stacking direction through the stopper layer, and the plurality of second contacts extending in the stacking direction without penetrating the stopper layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor memory device according to an embodiment. [Figure 2] 1 is a cross-sectional view showing an example of a configuration of a semiconductor memory device according to an embodiment. [Figure 3] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 4] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8]1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 12] 10 is a cross-sectional view taken along the X direction showing an example of the configuration of a staircase region included in a semiconductor memory device according to a modified example of the embodiment. FIG. [Figure 13] 10A to 10C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to a modified example of the embodiment. [Figure 14] 10A to 10C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to a modified example of the embodiment. [Figure 15] 10A to 10C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to a modified example of the embodiment. [Figure 16] 10A to 10C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to a modified example of the embodiment. [Figure 17] 10A to 10C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to a modified example of the embodiment. [Figure 18] 10A to 10C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to a modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] (Configuration example of semiconductor memory device) 1A and 1B are diagrams illustrating a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, FIG. 1A is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1B is a schematic plan view illustrating the layout of the semiconductor memory device 1.

[0009] However, hatching is omitted in Fig. 1(a) for ease of viewing. Also, Fig. 1(a) shows components that do not necessarily exist on the same cross section, and some upper layer wiring, etc. are omitted.

[0010] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor memory device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0011] As shown in FIG. 1(a), the semiconductor memory device 1 includes, from the bottom of the page, an electrode film EL, a source line SL, one or more select gate lines SGS, a plurality of word lines WL, one or more select gate lines SGD, and a semiconductor substrate SB on which a peripheral circuit CBA is provided.

[0012] A source line SL is disposed on the electrode film EL via an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and electrical conduction is maintained between the source line SL and the electrode film EL via the plugs PG. Although not shown, electrode pads for supplying power and signals from the outside to the semiconductor memory device 1 are provided in the same layer as the electrode film EL. A select gate line SGS, a plurality of word lines WL, and a select gate line SGD are stacked in this order on the source line SL to form a stacked body LM.

[0013] 1(a) and 1(b), a memory region MR is arranged in the center of the word lines WL in the X direction, and staircase regions SR are arranged at both ends of the word lines WL in the X direction. The memory region MR and staircase region SR are divided into multiple regions by multiple plate-like contacts LI that extend in the X direction and penetrate the word lines WL.

[0014] The region disposed between adjacent plate contacts LI in the Y direction and including the memory region MR and the staircase region SR is called a block region BLK. As will be described later, the memory region MR includes multiple memory cells that store data in a non-volatile manner, and the block region BLK serves as a unit for erasing this data.

[0015] Furthermore, a plurality of isolation layers SHE are arranged between adjacent plate contacts LI in the Y direction, penetrating the select gate lines SGD and extending in the X direction. The isolation layers SHE extend in the X direction throughout the entire memory region MR, and reach parts of the staircase regions SR at both ends in the X direction.

[0016] In the memory region MR, a plurality of pillars PL are arranged, penetrating the word lines WL and the select gate lines SGD, SGS in the stacking direction. The lower ends of the pillars PL reach the source lines SL. A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL. This allows the semiconductor memory device 1 to be configured as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0017] In the staircase region SR, the word lines WL and select gate lines SGD, SGS are processed in a staircase shape and terminate in the staircase region SR. As the distance from the memory region MR in the X direction increases, the word lines WL and select gate lines SGD, SGS constituting the terrace portion move from the upper layer to the lower layer, and the height position of the terrace portion decreases toward the source line SL.

[0018] The isolation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the isolation layer SHE penetrates the portions above the multiple word lines WL, dividing these upper portions into the patterns of multiple select gate lines SGD.

[0019] Contacts CC connected to the word lines WL and select gate lines SGD, SGS of each layer are arranged in the terrace portion of each stage formed by multiple word lines WL and select gate lines SGD, SGS. One contact CC is connected to each word line WL and select gate line SGS per layer. One contact CC is connected to each select gate line SGD per layer for each section separated by a separation layer SHE.

[0020] Here, in one block region BLK, the multiple contacts CC are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, multiple contacts CC are arranged, for example, every two block regions BLK.

[0021] 1(b), in the block region BLK at the top of the page, a plurality of contacts CC are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page. Also, in the block regions BLK one block below the above-mentioned block region BLK and two blocks below, a plurality of contacts CC are arranged in the staircase region SR on the right side of the page, among the staircase regions SR at both ends in the X direction. Furthermore, in the block region BLK at the bottom of the page, a plurality of contacts CC are again arranged in the staircase region SR on the left side of the page.

[0022] Therefore, the contacts CC in the staircase regions SR at both ends in the X direction shown in FIG. 1(a) belong to different block regions BLK and are not actually located on the same cross section.

[0023] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL located at the same height as the memory cells.

[0024] The word lines WL, select gate lines SGD, SGS, pillars PL, and contacts CC are covered with an insulating layer 50. The insulating layer 50 also extends around these components.

[0025] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. A peripheral circuit CBA including transistors TR and wiring is arranged on the surface of the semiconductor substrate SB. Various voltages applied to the memory cells from the contacts CC are controlled by the peripheral circuit CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuit CBA controls the electrical operation of the memory cells.

[0026] The peripheral circuit CBA is covered with an insulating layer 40, and by joining this insulating layer 40 with an insulating layer 50 that covers a plurality of word lines WL, etc., a semiconductor memory device 1 is formed that includes a configuration of a plurality of word lines WL, select gate lines SGD, SGS, pillars PL, contacts CC, etc., and the peripheral circuit CBA.

[0027] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0028] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure below the insulating layer 60 and above the insulating layer 53 described below are omitted.

[0029] 2(b) is an enlarged cross-sectional view of a pillar PL at the height of the select gate lines SGD and SGS, and FIG. 2(c) is an enlarged cross-sectional view of a pillar PL at the height of the word line WL.

[0030] Figure 2(d) is a cross-sectional view along the X direction in the staircase region SR of the semiconductor memory device 1. In Figure 2(d), the structure below the insulating layer 60 and above an insulating layer 53, which will be described later, is omitted.

[0031] In this specification, the direction in which the terrace surface of the word line WL of each step in the staircase region SR faces is defined as the upward direction in the semiconductor memory device 1.

[0032] 2(a), the source line SL has a multi-layer structure in which, for example, a lower source line DSLa, an intermediate source line BSL, and an upper source line DSLb are stacked in this order on an insulating layer 60. The intermediate source line BSL is disposed below the memory region MR of the stack LM.

[0033] The lower source line DSLa, the intermediate source line BSL, and the upper source line DSLb are, for example, polysilicon layers, etc. Among them, at least the intermediate source line BSL may be a conductive polysilicon layer or the like in which impurities are diffused.

[0034] The source line SL is connected to the peripheral circuit CBA via the electrode film EL by a through contact (not shown) that extends from the electrode film EL to the peripheral circuit CBA through the insulating layer 50 on the outside of the laminated body LM.

[0035] A laminated body LM is disposed on the source line SL. The laminated body LM includes laminated bodies LMa and LMb in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated one by one.

[0036] The stacked body LMa is disposed above the source line SL. Below the word line WL in the lowest layer of the stacked body LMa, a plurality of select gate lines SGS0 and SGS1 are disposed in this order from the upper layer side of the stacked body LMa, with an insulating layer OL interposed between them. The stacked body LMb is disposed on the stacked body LMa. Above the word line WL in the top layer of the stacked body LMb, a plurality of select gate lines SGD0 and SGD1 are disposed in this order from the upper layer side of the stacked body LMb, with an insulating layer OL interposed between them.

[0037] However, the number of stacked word lines WL and select gate lines SGD, SGS in the stacked body LM is arbitrary. The word lines WL and select gate lines SGD, SGS are, for example, tungsten layers or molybdenum layers. The insulating layer OL is, for example, a silicon oxide layer.

[0038] The upper surface of the laminate LM is covered with an insulating layer 52. The insulating layer 52 is covered with an insulating layer 53. The insulating layers 52 and 53, together with an insulating layer 51 described later, each constitute a part of the insulating layer 50 shown in FIG.

[0039] As described above, the multilayer body LM is divided in the Y direction by the plurality of plate-shaped contacts LI. That is, the plate-shaped contacts LI are aligned in the Y direction and extend in the stacking direction and the X direction of the multilayer body LM.

[0040] In this way, the plate-shaped contact LI extends continuously within the stack LM from one end to the other end in the X direction of the stack LM. The plate-shaped contact LI also penetrates the stack LM and the upper source line DSLb, and reaches the intermediate source line BSL in the memory region MR.

[0041] The plate-shaped contact LI has a tapered shape in which the width in the Y direction decreases from the upper end to the lower end, or a bowing shape in which the width in the Y direction is maximized at a predetermined position between the upper end and the lower end.

[0042] Each of the plate-shaped contacts LI includes an insulating layer 54 and a conductive layer 24. The insulating layer 54 is, for example, a silicon oxide layer, etc. The conductive layer 24 is, for example, a tungsten layer or a conductive polysilicon layer, etc.

[0043] The insulating layer 54 covers the side walls of the plate contact LI facing each other in the Y direction. The conductive layer 24 is filled inside the insulating layer 54 and is electrically connected to the source lines SL including the intermediate source line BSL. The upper end of the conductive layer 24 is connected to the upper wiring via a plug or the like at a position different from that of the cross section of FIG. 2(a). This allows the plate contact LI to function as a source line contact.

[0044] However, instead of the plate-shaped contacts LI, plate-shaped members filled with an insulating layer may penetrate the laminate LM and extend in the X direction, thereby dividing the laminate LM in the Y direction. In this case, the plate-shaped contacts do not function as source line contacts.

[0045] Between the plate contacts LI adjacent in the Y direction, a plurality of isolation layers SHE are arranged, which extend in the X direction and penetrate the upper layer portion of the stacked body LMb. These isolation layers SHE are insulating layers 56, such as silicon oxide layers, which penetrate the select gate lines SGD0 and SGD1 and reach the insulating layer OL immediately below the select gate line SGD1.

[0046] In other words, these separation layers SHE that penetrate the upper part of the laminate LMb extend in the X direction between the plate-shaped contacts LI through the memory region MR and part of the staircase region SR, thereby dividing the upper part of the laminate LMb into the above-mentioned select gate lines SGD0 and SGD1.

[0047] In the memory region MR, a plurality of pillars PL are distributed and arranged, passing through the stacked body LM, the upper source line DSLb, and the intermediate source line BSL to reach the lower source line DSLa.

[0048] The pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0049] The pillar PL has a tapered shape in which the diameter and cross-sectional area decrease from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0050] Each of the multiple pillars PL has a memory layer ME extending in the stacking direction within the stack LM, a channel layer CN penetrating the stack LM and connecting to an intermediate source line BSL, a cap layer CP covering the upper surface of the channel layer CN, and a core layer CR that serves as the core material of the pillar PL.

[0051] 2(b) and 2(c), the memory layer ME has a multilayer structure in which a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN are stacked in this order from the outer periphery of the pillar PL. More specifically, the memory layer ME is arranged on the side surface of the pillar PL except for the depth position of the intermediate source line BSL. The memory layer ME is also arranged on the bottom surface of the pillar PL, which reaches the depth of the lower source line DSLa.

[0052] The channel layer CN penetrates the stacked body LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa. More specifically, the channel layer CN is arranged on the side and bottom surfaces of the pillar PL via the memory layer ME. However, a portion of the channel layer CN contacts the intermediate source line BSL on the side, thereby electrically connecting to the source line SL including the intermediate source line BSL. A core layer CR is filled further inside the channel layer CN.

[0053] Each of the pillars PL has a cap layer CP at its upper end. The cap layer CP is disposed at the upper end of the pillar PL so as to cover at least the upper end of the channel layer CN and is connected to the channel layer CN. The cap layer CP is connected to a bit line BL disposed in the insulating layer 53 via a plug CH disposed in the insulating layer 52. The bit line BL extends above the stacked body LM in the Y direction so as to intersect with the leading direction of the word line WL.

[0054] 2(a), plugs CH are connected only to three of the six pillars PL that penetrate the three separated select gate lines SGD and are electrically connected to the bit lines BL shown in Fig. 2(a). The other pillars PL are connected to other bit lines BL that extend in the Y direction parallel to the bit lines BL shown in Fig. 2(a) at positions different from the cross section shown in Fig. 2(a) via plugs CH not shown in Fig. 2(a).

[0055] The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, and the core layer CR are, for example, silicon oxide layers, etc. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer, etc. The channel layer CN and cap layer CP are, for example, semiconductor layers such as polysilicon layers or amorphous silicon layers.

[0056] As shown in Figure 2(c), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0057] 2(b), select gates STD are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGD0 and SGD1 above the word lines WL, and select gates STS are formed on the side surfaces of the pillars PL in portions facing the select gate lines SGS0 and SGS1 below the word lines WL.

[0058] By applying a predetermined voltage from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD and STS belong can be selected or unselected.

[0059] As shown in Fig. 2(d), the staircase region SR has a staircase portion SP in which multiple word lines WL and select gate lines SGD, SGS are processed in a staircase shape. The staircase portion SP shown in Fig. 2(d) is a part of the staircase region SR divided into multiple block regions BLK, where contacts CC are arranged and which has the function of drawing out the word lines WL, etc.

[0060] The stepped portion SP is covered with an insulating layer 51. The insulating layer 51 reaches, for example, the height position of the uppermost layer of the laminated body LM, and the insulating layers 52 and 53 also cover the upper surface of the insulating layer 51. As described above, the insulating layer 51 also forms part of the insulating layer 50 in FIG.

[0061] In the staircase region SR, the source lines SL include an intermediate insulating layer SCO interposed between the upper source line DSLb and the lower source line DSLa instead of the intermediate source line BSL. The intermediate insulating layer SCO is, for example, a silicon oxide layer.

[0062] Therefore, in the staircase region SR, the plate-shaped contact LI penetrates the insulating layer 51, the stacked body LM, and the upper source line DSLb to reach the intermediate insulating layer SCO.

[0063] Above the portions of the laminated body LMa in the stepped portion SP where the word lines WL and the select gate lines SGS are processed in a stepped shape, a stopper layer STP is disposed via a spacer layer SPC that covers these portions.

[0064] The spacer layer SPC has a plurality of terrace portions and step portions connecting these terrace portions in the stacking direction. These terrace portions and step portions are provided to correspond to, for example, the terrace portions of each insulating layer OL included in the stacked body LMa, and step portions formed by the word lines WL and the insulating layers OL, or the select gate lines SGS and the insulating layers OL, respectively. As a result, the spacer layer SPC is arranged to follow the shapes of the plurality of word lines WL, etc., which are processed in a stepped shape.

[0065] However, the terrace and step portions of the staircase portion SP of the laminate LMa do not necessarily have to correspond one-to-one to the terrace and step portions of the spacer layer SPC. That is, the number of steps of the spacer layer SPC may be fewer than the number of steps of the staircase portion SP of the laminate LMa. Even in this case, the spacer layer SPC is arranged so as to generally follow the shape of the multiple word lines WL, etc., which are processed into a staircase shape. Alternatively, the spacer layer SPC may have a substantially flat shape without any steps.

[0066] The spacer layer SPC is made of the same material as the insulating layer 51, and is, for example, a silicon oxide layer.

[0067] The stopper layer STP is disposed so as to cover the upper surface of the spacer layer SPC. When the spacer layer SPC has a stepped shape, the stopper layer STP also has a stepped shape that follows at least a part of the shape of the plurality of word lines WL, etc., which are processed into a stepped shape. The stopper layer STP is made of a material different from that of the insulating layer 51, such as a tungsten layer. Furthermore, it is preferable that the thickness of the stopper layer STP is greater than the thickness of each of the plurality of word lines WL, etc., and less than twice the thickness of each of these word lines WL, etc.

[0068] Each contact CC of the staircase portion SP passes through the insulating layer 51 and the like and is connected to a word line WL or select gate lines SGD, SGS immediately below an insulating layer OL that constitutes each step of the staircase portion SP.

[0069] Of the multiple contacts CC, the contact CC connected to one of the multiple word lines WL and select gate lines SGS included in the stacked body LMa passes through the stopper layer STP and the spacer layer SPC to reach the word line WL etc. to be connected.

[0070] On the other hand, the stopper layer STP and the spacer layer SPC are not arranged at the positions where the contacts CC connected to any of the word lines WL and the select gate lines SGD included in the stacked body LMb are arranged, and therefore, these contacts CC extend through the insulating layer 51 and reach the word lines, etc. to be connected without penetrating the stopper layer STP and the spacer layer SPC.

[0071] Each contact CC has, for example, a tapered shape in which the diameter and cross-sectional area decrease from the upper end to the lower end, or, for example, a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper end and the lower end.

[0072] The contact CC also has an insulating layer 55 that covers the outer periphery of the contact CC, and a conductive layer 25 such as a tungsten layer or a copper layer that fills the inside of the insulating layer 55.

[0073] The insulating layer 55 is a liner layer for the contacts CC. The insulating layer 55 preferably has a thickness at least 1.5 times, more preferably at least twice, the thickness of each of the word lines WL, for example. This improves the breakdown voltage between the contacts CC that penetrate a conductive stopper layer STP such as a tungsten layer. The conductive layer 25 is a core layer that serves as the core material of the contacts CC, and is connected to upper-layer wiring MX arranged in the insulating layer 53 via a plug V0 arranged in the insulating layer 52. This upper-layer wiring MX is electrically connected to the peripheral circuit CBA (see FIG. 1) described above.

[0074] With this configuration, the word lines WL of each layer and the select gate lines SGD, SGS above and below the word lines WL can be electrically drawn out from one end or the other end in the X direction of the laminated body LM. That is, with the above configuration, a predetermined voltage can be applied to the memory cells MC from the peripheral circuit CBA via the upper layer wiring MX, contacts CC, word lines WL, etc., to operate the memory cells MC as storage elements.

[0075] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Figures 3 to 11. Figures 3 to 11 are diagrams illustrating in order some of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment.

[0076] First, FIG. 3 shows the laminate LMsa, which is the lower layer portion of the laminate LM before the word lines WL are formed, and how various components are formed on the laminate LMsa.

[0077] FIG. 3 is a cross-sectional view along the X direction of the region that will later become the memory region MR and the staircase region SR.

[0078] As shown in FIG. 3(a), a lower source line DSLa, an intermediate sacrificial layer SCN or an intermediate insulating layer SCO, and an upper source line DSLb are formed in this order on a support substrate SS.

[0079] The support substrate SS can be a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, a conductive substrate, etc. The above-mentioned insulating layer 60 (see FIG. 2, etc.) may be formed on the upper surface side of the support substrate SS.

[0080] The intermediate sacrificial layer SCN is formed in a region on the support substrate SS that will later become the memory region MR, and the intermediate insulating layer SCO is formed in a region on the support substrate SS that will later become the staircase region SR. The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, which will later be replaced with a polysilicon layer or the like to become the intermediate source line BSL. As described above, the intermediate insulating layer SCO is, for example, a silicon oxide layer or the like.

[0081] Furthermore, a stacked body LMsa is formed on the upper source line DSLb, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers that will later be replaced with a conductive material to become word lines WL or select gate lines SGS.

[0082] 3(b), the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsa. Such processing can be performed by repeatedly slimming a mask pattern such as a photoresist layer and etching the insulating layers NL and OL of the laminate LMsa.

[0083] That is, a mask pattern is formed on the top surface of the laminate LMsa, and the exposed insulating layers NL and OL are etched away one by one. Then, by processing using oxygen plasma or the like, the edges of the mask pattern are retracted to expose the top surface of the laminate LMsa anew, and the insulating layers NL and OL are further etched away one by one. By repeating this process multiple times, the above-mentioned stepped shape is formed.

[0084] 3(c), an insulating layer 51 is formed to cover the step portion and reach the height of the upper surface of the laminated body LMsa. The insulating layer 51 is also formed in the outer region of the laminated body LMsa.

[0085] As shown in FIG. 3(d), the insulating layer 51 is processed into a stepped shape so as to fit the stepped portions of the insulating layers NL and OL of the laminated body LMsa, thereby forming a spacer layer SPC.

[0086] As described above, the spacer layer SPC may have terrace portions and step portions formed in one-to-one correspondence with the terrace portions and step portions formed by the insulating layers NL and OL of the laminate LMsa, or may have terrace portions and step portions formed in a manner that has fewer steps than the staircase shape formed by the insulating layers NL and OL of the laminate LMsa. The spacer layer SPC may have a substantially flat shape by leaving the insulating layer 51 unprocessed or by processing it to have a substantially flat surface.

[0087] 3(e), a stopper layer STP is formed to cover the upper surface of the spacer layer SPC. The stopper layer STP is preferably formed to a thickness that exceeds the thickness of each of the word lines WL, etc., but is less than twice the thickness of each of the word lines WL, etc.

[0088] Next, FIGS. 4 and 5 show how a laminate LMsb, which is the upper layer portion of the laminate LM before the word lines WL are formed, is formed, and how various components are formed in the laminates LMsa and LMsb.

[0089] 4 and 5 are cross-sectional views along the X direction of the regions that will later become the memory region MR and the staircase region SR, similar to FIG. 3 described above.

[0090] As shown in FIG. 4(a), multiple memory holes MHa are formed in the stack LMsa, extending in the stacking direction. The memory holes MHa are portions that will later become the lower structure of the pillars PL. The multiple memory holes MHa are arranged in an area that will later become the memory region MR, and penetrate the stack LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0091] 4(b), these memory holes MHa are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer. As a result, pillars PLc in which the sacrificial layer 26 is filled in a plurality of memory holes MHa are formed in the region that will later become the memory region MR.

[0092] As shown in Fig. 4(c), a laminate LMsb is formed by covering the laminate LMsa including the stepped portion with multiple insulating layers NL and multiple insulating layers OL stacked one by one. The sacrificial layers NL of the laminate LMsb will later be replaced with conductive layers to become word lines WL or select gate lines SGD.

[0093] In addition, the insulating layers NL and OL are processed to have a stepped shape in a partial region of the laminate LMsb. This processing can be performed by repeating the slimming of a mask pattern such as a photoresist layer and the etching of the insulating layers NL and OL of the laminate LMsb multiple times, similar to the process shown in FIG. 3(b) above.

[0094] At this time, the top step of the staircase portion already formed in the laminate LMsa and the bottom step of the staircase portion formed in the laminate LMsb are brought close together, and these are formed so that they are continuously connected from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb.

[0095] 5(a), an insulating layer 51 is formed to cover the upper surface of the stopper layer STP and the newly formed staircase portion of the laminate LMsb and reach the height of the upper surface of the laminate LMsb. The insulating layer 51 is also formed in the outer regions of the laminates LMsa and LMsb. This forms the insulating layer 51 with the stopper layer STP interposed in a part thereof.

[0096] As shown in FIG. 5(b), multiple memory holes MHb are formed in the stack LMsb, extending in the stacking direction. The memory holes MHb are portions that will later become the upper structure of the pillars PL. The multiple memory holes MHb are arranged in an area that will later become the memory region MR, penetrate the stack LMsb, and each reach the upper end of the pillar PLc formed in the stack LMsa.

[0097] 5(c), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb, thereby opening a memory hole MHa at the bottom of each of the memory holes MHb, and forming a plurality of memory holes MH that penetrate the stacks LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN and reach the lower source line DSLa.

[0098] In addition, if the sacrificial layer 26 filled in the pillars PLc is a CVD-carbon layer or the like, when the mask pattern or the like used in the processing of Figure 5(b) described above is removed by ashing using oxygen plasma or the like, the sacrificial layer 26 can be removed all at once from these pillars PLc as well.

[0099] 6 and 7 show how a pillar PL is formed by forming a multilayer structure in the memory hole MH. Figures 6 and 7 are cross-sectional views along the Y direction of a region that will later become the memory region MR.

[0100] As shown in FIG. 6(a), a plurality of memory holes MH are formed in a region that will later become the memory region MR.

[0101] 6(b), a multilayer insulating layer MEb, a semiconductor layer CNb, and an insulating layer CRb are formed in this order in the memory hole MH, whereby the multilayer insulating layer MEb and the semiconductor layer CNb are disposed on the side surface of the memory hole MH and on the bottom surface where the lower source line DSLa is exposed, and the insulating layer CRb is filled in the center of the memory hole MH.

[0102] The multilayer insulating layer MEb is an insulating layer with a multilayer structure that will later become the memory layer ME. The semiconductor layer CNb is a layer that will later become the channel layer CN. The insulating layer CRb is a silicon oxide layer or the like that will later become the core layer CR.

[0103] The multilayer insulating layer MEb, the semiconductor layer CNb, and the insulating layer CRb are also formed in this order on the upper surface of the laminated body LMsb.

[0104] As shown in Figure 6(c), in the region that will later become the memory region MR, the insulating layer CRb, the semiconductor layer CNb, and the multilayer insulating layer MEb are sequentially etched back to remove them from the top surface of the laminated body LMsb, and a recess DN is formed at the top end of the memory hole MH from which the insulating layer CRb and the semiconductor layer CNb have been removed.

[0105] As a result, the memory layer ME, the channel layer CN, and the core layer CR are formed in the memory hole MH in this order from the outer periphery.

[0106] 7A, in the region that will later become the memory region MR, a semiconductor layer CPb is formed in the recess DN at the upper end of the memory hole MH. The semiconductor layer CPb is a layer that will later become the cap layer CP. The semiconductor layer CPb is also formed on the upper surface of the stacked body LMsb.

[0107] 7(b), in the region that will later become the memory region MR, the semiconductor layer CPb on the top surface of the stacked body LMsb is removed by CMP or the like, and a cap layer CP is formed at the upper end of the memory hole MH. In addition, the insulating layer OL, which is the top layer of the stacked body LMsb that has been thinned by CMP or the like, is added.

[0108] As a result, a pillar PL is formed in which the cap layer CP is buried in the uppermost insulating layer OL. However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and a part of the side surface of the channel layer CN is not exposed from the memory layer ME.

[0109] Next, the formation of the source lines SL and word lines WL will be shown with reference to Figures 8 and 9. Figures 8 and 9 are cross-sectional views along the Y direction of a region that will later become the memory region MR, similar to Figures 6 and 7 described above.

[0110] 8(a), a slit ST is formed that penetrates the stacked bodies LMsb, LMsa and the upper source line DSLb and reaches the intermediate sacrificial layer SCN. Insulating layers 54s are formed on the side walls of the slit ST that face each other in the Y direction.

[0111] The slits ST have a tapered or bowed cross section in the Y direction, and extend in the X direction within the stacks LMsa and LMsb. Therefore, in the staircase region SR (not shown), the lower ends of the slits ST reach the intermediate insulating layer SCO.

[0112] As shown in FIG. 8(b), a removal solution for the intermediate sacrificial layer SCN, such as hot phosphoric acid, is poured through the slit ST whose sidewalls are protected by the insulating layer 54s to remove the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0113] As a result, a gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb. Also, a part of the memory layer ME on the outer periphery of the pillar PL is exposed in the gap layer GPs.

[0114] At this time, since the sidewalls of the slits ST are protected by the insulating layer 54s, the insulating layer NL in the stacks LMsa and LMsb is prevented from being removed as well. In addition, in the staircase region SR (not shown), there is no intermediate sacrificial layer SCN between the lower source line DSLa and the upper source line DSLb, and therefore no gap layer GPs is formed.

[0115] 8(c), a chemical solution is appropriately poured into the gap layer GPs through the slit ST to sequentially remove the block insulating layer BK, charge storage layer CT, and tunnel insulating layer TN (see FIGS. 2(b) and 2(c)) of the memory layer ME exposed in the gap layer GPs. As a result, the memory layer ME is removed from part of the sidewall of the pillar PL, and part of the inner channel layer CN is exposed in the gap layer GPs.

[0116] 8(d), a raw material gas such as amorphous silicon is injected through the slit ST whose sidewalls are protected by the insulating layer 54s, and the gap layer GPs is filled with amorphous silicon, etc. The support substrate SS is also heat-treated to polycrystallize the amorphous silicon filled in the gap layer GPs, thereby forming an intermediate source line BSL containing polysilicon, etc.

[0117] As a result, a part of the channel layer CN of the pillar PL is connected to the source line SL at the side surface via the intermediate source line BSL.

[0118] At this time, in the staircase region SR (not shown), no gap layer GPs is formed between the lower source line DSLa and the upper source line DSLb, and no intermediate source line BSL is formed either.

[0119] As shown in FIG. 9(a), the insulating layer 54s on the sidewall of the slit ST is temporarily removed.

[0120] 9(b), a remover for the insulating layers NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb through the slits ST to remove the insulating layers NL of the laminates LMsa and LMsb, thereby forming laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0121] The stacked bodies LMga and LMgb, each including a plurality of gap layers GP, have a fragile structure. In the region that will later become the memory region MR, a plurality of pillars PL support such fragile stacked bodies LMga and LMgb.

[0122] Such a support structure for the pillars PL prevents the remaining insulating layer OL from bending and the stacked bodies LMga and LMgb from being distorted or collapsing. In addition, in the region that will later become the staircase region SR, the stopper layer STP prevents the insulating layer OL from bending and the stacked bodies LMga and LMgb from being distorted or collapsing.

[0123] 9(c), a source gas of a conductive material such as tungsten or molybdenum is injected into the laminates LMga, LMgb through the slits ST to fill the gap layers GP of the laminates LMga, LMgb with the conductive material to form a plurality of word lines WL, etc. This forms a laminate LM including laminates LMa, LMb in which a plurality of word lines WL, etc. and a plurality of insulating layers OL are alternately stacked one layer at a time.

[0124] The top layer and the second-top conductive layer of the laminated body LMb will be partitioned into a pattern of a plurality of select gate lines SGD by later forming a separation layer SHE that penetrates them.

[0125] As described above, the process of forming the intermediate source lines BSL from the intermediate sacrificial layers SCN and the process of forming the word lines WL from the insulating layers NL are also called a replacement process.

[0126] Thereafter, an insulating layer 54 is formed on the sidewall of the slit ST, and the insulating layer 54 is filled with the conductive layer 24 to form the plate-like contact LI. However, the slit ST may be filled with the insulating layer 54 or the like without forming the conductive layer 24, to form a plate-like member.

[0127] In addition, a trench is formed through one or more conductive layers including the top conductive layer of the laminated body LMb, and an insulating layer 56 is filled in the trench to form a separation layer SHE that divides these conductive layers into the pattern of the select gate line SGD.

[0128] Next, a state in which a plurality of contacts CC are formed in the staircase region SR will be shown with reference to Figures 10 and 11. Figures 10 and 11 are cross-sectional views of the staircase region SR taken along the X direction.

[0129] 10(a), a mask pattern 81 is formed in the staircase region SR, covering the insulating layer 51 and the upper surfaces of the laminate LM. The mask pattern 81 preferably contains the same material as the stopper layer STP described above. If the stopper layer STP is a tungsten layer or the like, the mask pattern 81 can also be a tungsten layer pattern. The mask pattern 81 also has a plurality of openings OPa at positions overlapping with the stepped portions of the word lines WL and the like of the laminate LMa in the stacking direction.

[0130] 10(b), the insulating layer 51 covering the stepped portion SP is etched using the mask pattern 81 to form a plurality of contact holes CLa that penetrate the insulating layer 51 and reach the stopper layer STP. By making the stopper layer STP a layer containing the same type of material as the mask pattern 81, selectivity can be obtained for the stopper layer STP, allowing the stopper layer STP to function as an etch stopper. Furthermore, as described above, by making the thickness of the stopper layer STP greater than the thickness of, for example, the word line WL, it is possible to more reliably prevent the contact holes CLa from penetrating the stopper layer STP.

[0131] 10(c), a plurality of openings OPb are formed in the mask pattern 81 at positions overlapping with the stepped portions of the word lines WL and the like of the laminate LMb in the stacking direction. At this time, the stopper layer STP exposed at the bottoms of the plurality of contact holes CLa is also etched away, so that the plurality of contact holes CLa penetrate the stopper layer STP. At this time, as described above, by setting the thickness of the stopper layer STP to, for example, less than twice the thickness of the word lines WL, the contact holes CLa can more reliably penetrate the stopper layer STP.

[0132] 11(a), the insulating layer 51 covering the stepped portion SP is etched using a mask pattern 81 having a plurality of openings OPb formed therein, to form a plurality of contact holes CLb that penetrate the insulating layer 51 and reach the individual word lines WL, etc. of the laminated body LMb. At this time, the plurality of contact holes CLa also reach the individual word lines WL, etc. of the laminated body LMa.

[0133] 11(b), an insulating layer 55 is formed to cover the sidewalls of the plurality of contact holes CLa, CLb. At this time, the insulating layer 55 can be formed to have a thickness that is, for example, 1.5 times or more the thickness of each of the plurality of word lines WL, etc., and more preferably, 2 times or more the thickness. This makes it possible to maintain the breakdown voltage between the individual contacts CC that extend through the stopper layer STP, which is, for example, a conductive tungsten layer.

[0134] As shown in FIG. 11(c), a conductive material such as tungsten is filled into a plurality of contact holes CLa, CLb having insulating layers 55 formed on their side walls to form a conductive layer 25 that serves as a core layer of the plurality of contact holes CLa, CLb.

[0135] In this way, a plurality of contacts CC are formed in the stepped portion SP.

[0136] Thereafter, an insulating layer 52 is formed on the upper surface of the insulating layer 51 covering the upper surface of the stacked body LM and the staircase region SR, and a plug V0 is formed through the insulating layer 52 to be connected to the contact CC. A plug CH is also formed through the insulating layer 52 to be connected to the pillar PL. Furthermore, an insulating layer 53 is formed on the insulating layer 52, and upper-layer wiring MX and bit lines BL, etc., connected to the plugs V0 and CH are formed. Electrode pads, etc., for electrical conduction with the peripheral circuit CBA are also formed on the upper surface of the insulating layer 53.

[0137] It should be noted that the plugs V0, CH, upper layer wiring MX, bit line BL, etc. may be formed all at once by using, for example, a dual damascene method.

[0138] Furthermore, a peripheral circuit CBA is formed on a semiconductor substrate SB separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. are formed in the insulating layer 40 to draw the peripheral circuit CBA out to the surface of the insulating layer 40, and are connected to electrode pads, etc. formed on the upper surface of the insulating layer 40.

[0139] Next, the support substrate SS and the semiconductor substrate SB are bonded together with their respective insulating layers 50, 40, and the electrode pads in the insulating layers 50, 40 are connected. Thereafter, the support substrate SS is removed to expose the source line SL, and the electrode film EL is connected via the insulating layer 60 in which the plug PG is formed.

[0140] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0141] (Overview) A semiconductor memory device such as a three-dimensional nonvolatile memory is configured such that multiple word lines, etc. are stacked, some of which are formed in a stepped shape, and contacts are connected to these stepped portions, thereby enabling voltage application to the multiple word lines, etc. These contacts are obtained, for example, by forming multiple contact holes collectively that reach the multiple word lines, etc.

[0142] However, due to the large difference in elevation between the word lines belonging to different layers of the stack, some of the contact holes that should reach the word lines on the upper layer may end up penetrating the target word lines.If the contact holes that have passed through the target word lines end up reaching the word lines on the lower layer, these word lines may become conductive via the contacts that will be formed later.

[0143] Therefore, for example, it is conceivable to form contact holes for the lower word lines at a height higher than the word lines, and then form contact holes for the upper word lines, and then perform additional etching to make the contact holes for the lower word lines reach the target word lines. In this case, for example, by adjusting the etching conditions and the aspect ratio of the contact holes, the etching of the contact holes for the lower word lines can be controlled to stop temporarily at a height higher than the target word lines.

[0144] This prevents excessive over-etching of the target word lines when forming contact holes that target the upper word lines. However, precise control is required to adjust the etching conditions and the aspect ratio of the contact holes, and the etching conditions may not have sufficient margin. Furthermore, when the etching is stopped at a height above the target word lines, variations in the depth of the contact holes may occur.

[0145] According to the semiconductor memory device 1 of the embodiment, the stopper layer STP is disposed at least at a position overlapping with a stepped portion of the word lines WL and select gate lines SGS of the laminate LMa in the stacking direction of the laminate LM. Furthermore, the contacts CC connected to the word lines WL, etc. of the laminate LMa extend in the stacking direction of the laminate LM, penetrating the stopper layer STP, while the contacts CC connected to the word lines WL, etc. of the laminate LMb extend in the stacking direction of the laminate LM without penetrating the stopper layer STP. Thus, by disposing the stopper layer STP at the position of the lower contacts CC, it becomes easy to form the contact holes CLa in two stages, and it is possible to prevent the upper contacts CC from penetrating the word lines WL, etc. to be connected.

[0146] According to the semiconductor memory device 1 of the embodiment, the plurality of contacts CC connected to the plurality of word lines WL of the laminated body LMa each have an insulating layer 55 covering the sidewall of the conductive layer 25. This ensures a sufficient breakdown voltage between the plurality of contacts CC even if the stopper layer STP is a conductive layer such as a tungsten layer.

[0147] According to the semiconductor memory device 1 of the embodiment, the thickness of the insulating layer 55 is 1.5 times or more, preferably 2 times or more, the thickness of each of the word lines WL, etc. This more reliably maintains the breakdown voltage between the contacts CC.

[0148] According to the semiconductor memory device 1 of the embodiment, the stopper layer STP is disposed at a position spaced apart from the plate-shaped contact LI in the Y direction. In this manner, since the stopper layer STP is not in contact with the plate-shaped contact LI, it is possible to prevent the electrical characteristics of the plate-shaped contact LI from being affected by the stopper layer STP and being deteriorated.

[0149] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, a plurality of contact holes CLa are formed in the stacking direction of the laminate LM, extending from a height position above the laminate LM to positions overlapping with the staircase portion SP of the laminate LMa and reaching the stopper layer STP, via the mask pattern 81. In this way, etching is temporarily stopped by the stopper layer STP, so that variations in the reach depth of these contact holes CLa can be suppressed.

[0150] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, a plurality of openings OPb are formed at positions that overlap the staircase portion SP of the laminate LMb of the mask pattern 81 in the stacking direction of the laminate LM, and the openings OPb penetrate the stopper layer STP exposed at the bottom surface of a plurality of contact holes CLa that are intended to reach the word lines WL, etc. of the laminate LMa.

[0151] In this way, the opening of the mask pattern 81 for forming the upper contact hole CLb and the removal of the stopper layer STP at the bottom of the lower contact hole CLa are performed simultaneously, thereby reducing the number of steps for forming the contact CC.

[0152] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, a plurality of contact holes CLb are formed via a mask pattern 81 in which a plurality of openings OPb are formed, the contact holes CLb extending in the stacking direction of the laminate LM from a height position above the laminate LM to a position overlapping with the staircase portion SP of the laminate LMb and reaching the staircase-processed portions of the plurality of word lines WL and select gate lines SGD of the laminate LMb, respectively, and the plurality of contact holes CLa are made to reach the staircase-processed portions of the plurality of word lines WL and select gate lines SGS of the laminate LMa, respectively.

[0153] In this way, the formation of the upper contact hole CLb and the additional processing of the lower contact hole CLa are performed simultaneously, thereby reducing the number of steps required to form the contact CC. Furthermore, when additionally etching the lower contact hole CLa, excessive over-etching of the word line WL of the stacked body LMb, which is the target of the upper contact hole CLb, can be prevented.

[0154] Furthermore, since the lower contact holes CLa are stopped above the target word lines WL, etc., there is no need to precisely adjust, for example, the etching conditions and the aspect ratios of these contact holes, and it is also possible to increase the margin of the etching conditions.

[0155] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, a spacer layer SPC is formed that has a plurality of terrace portions and step portions that connect these terrace portions in the stacking direction of the stacks LMsa and LMb, and covers the step portions of the stack LMsa so as to follow at least a portion of the step-like shape of the plurality of insulating layers NL of the stack LMsa.

[0156] In this way, since the stopper layer STP is formed on the stepped spacer layer SPC, the distance between the stopper layer STP and the stepped portion of the laminated body LMsa is prevented from varying. This makes it possible to align the distances of the portions where the multiple contact holes CLa are additionally etched, and to align the amount of over-etching between the lower word lines WL. Therefore, it is also possible to prevent excessive over-etching of the upper word lines WL among the lower word lines WL.

[0157] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, the stopper layer STP is formed to have a thickness greater than the thickness of each of the word lines WL, etc., and less than twice the thickness of each of these word lines WL, etc.

[0158] In this way, by making the thickness of the stopper layer STP greater than the thickness of the word line WL, the etching of the plurality of contact holes CLa can be temporarily stopped by the stopper layer STP without the stopper layer STP penetrating. Also, by making the thickness of the stopper layer STP less than twice the thickness of the word line WL, the stopper layer STP at the bottom of the contact hole CLa can be easily penetrated when forming the opening OPb in the mask pattern 81.

[0159] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, the stopper layer STP is formed to contain the same type of material as the mask pattern 81. This allows the stopper layer STP to be etched with sufficient selectivity to the stopper layer STP.

[0160] In the above-described embodiment, the stopper layer STP is, for example, a tungsten layer. However, the stopper layer STP may be, for example, a tungsten silicon layer, a silicon layer, or a metal oxide layer, as long as it has etching selectivity during etching of the contact hole CLa. The silicon layer may be, for example, an amorphous silicon layer or a polysilicon layer. The metal oxide layer may be, for example, an aluminum oxide (Al2O3) layer.

[0161] (Variation) Next, a semiconductor memory device 2 according to a modification of the embodiment will be described with reference to Figures 12 to 18. The semiconductor memory device 2 according to the modification differs from the embodiment described above in that it includes a stacked body LM2 with a 3-tier structure.

[0162] In the following drawings, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0163] 12 is a cross-sectional view taken along the X direction showing an example of the configuration of a staircase region SR2 included in a semiconductor memory device 2 according to a modified example of the embodiment. In FIG. 12, the structure below an insulating layer 60 and above an insulating layer 53, which will be described later, is omitted.

[0164] 12, the semiconductor memory device 2 of the modified example includes a stacked body LM2 having a 3-tier structure, in which three stacked bodies LMa, LMb, and LMc are stacked. These stacked bodies LMa, LMb, and LMc have a configuration in which multiple word lines WL and multiple insulating layers OL are stacked alternately. Furthermore, these stacked bodies LMa, LMb, and LMc include staircase portions SP2 in which the multiple word lines WL are processed into a staircase shape, in staircase regions SR2, for example, at both ends in the X direction.

[0165] The stacked body LMa is disposed above the source line SL. Below the word line WL in the lowest layer of the stacked body LMa, a plurality of select gate lines SGS0 and SGS1 are disposed in this order from the upper layer side of the stacked body LMa via an insulating layer OL.

[0166] The stacked body LMb is disposed on the stacked body LMa. In the modified example, the stacked body LMb does not include the select gate lines SGD and SGS.

[0167] The stacked body LMc is disposed on the stacked body LMb. Above the word line WL in the uppermost layer of the stacked body LMc, a plurality of select gate lines SGD0 and SGD1 are disposed in this order from the upper layer side of the stacked body LMc, with an insulating layer OL interposed therebetween.

[0168] Furthermore, the semiconductor memory device 2 of the modified example includes a plurality of stopper layers STPa and STPb.

[0169] The stopper layer STPa is arranged above the portions where the word lines WL and the select gate lines SGS in the stacked body LMa of the stepped portion SP2 are processed into a stepped shape, with the spacer layer SPCa therebetween to cover these portions.

[0170] The spacer layer SPCa may have a plurality of terrace portions and step portions corresponding one-to-one to the terrace portions and step portions formed by the word lines WL, the select gate lines SGS, and the insulating layer OL of the laminated body LMa, and may be configured to have fewer steps than the staircase shape formed by the word lines WL, etc. of the laminated body LMa. The spacer layer SPCa may have a substantially flat shape.

[0171] The stopper layer STPb is disposed at a height position above the stopper layer STPa. More specifically, the stopper layer STPb is disposed above the stepped portions of the word lines WL and the select gate lines SGS in the stacked body LMa of the staircase portion SP2 and the stepped portions of the word lines WL in the stacked body LMb of the staircase portion SP2, with the spacer layer SPCb therebetween to cover these portions.

[0172] The spacer layer SPCb may have a plurality of terrace portions and step portions corresponding one-to-one to the terrace portions and step portions formed by the word lines WL, the select gate lines SGS, and the insulating layer OL of the stacked bodies LMa and LMb, and may be configured to have fewer steps than the staircase shape formed by the word lines WL, etc. of the stacked bodies LMa and LMb. The spacer layer SPCb may have a substantially flat shape.

[0173] The spacer layers SPCa and SPCb are made of the same material as the insulating layer 51, such as a silicon oxide layer.

[0174] The stopper layers STPa, STPb are made of a material different from that of the insulating layer 51, such as a tungsten layer. However, the stopper layers STPa, STPb may also be a silicon layer such as a tungsten silicon layer, amorphous silicon, or polysilicon layer, or a metal oxide layer such as an aluminum oxide layer. The thickness of the stopper layers STPa, STPb is preferably greater than the thickness of each of the word lines WL, etc., and less than twice the thickness of each of the word lines WL, etc.

[0175] Of the plurality of contacts CC, the contacts CC connected to the word lines WL and select gate lines SGS of the laminated body LMa respectively penetrate the stopper layer STPa and the spacer layer SPCa to reach the word lines WL etc. to be connected.

[0176] Of the plurality of contacts CC, the contacts CC connected to the word lines WL of the laminated body LMb pass through the stopper layer STPb and the spacer layer SPCb and reach the word lines WL or the like to be connected.

[0177] Of the multiple contacts CC, the contacts CC respectively connected to the word lines WL and select gate lines SGD of the laminate LMc reach the word lines WL, etc. to be connected without penetrating either the stopper layers STPa, STPb or the spacer layers SPCa, SPCb.

[0178] A method for manufacturing the semiconductor memory device 2 of the modified example configured as above will be described below.

[0179] 13 to 18 are diagrams illustrating, in order, some of the steps of a method for manufacturing a semiconductor memory device 2 according to a modified example of the embodiment. 13 to 18 mainly illustrate a method for forming the stepped portion SP2 and contacts CC of the semiconductor memory device 2.

[0180] 13 to 15 show the stacks LMsb and LMsc formed before the word lines WL are formed, and also show how various components are formed in the stacks LMsb and LMsc. Figures 13 to 15 are cross-sectional views along the X direction of the region that will later become the memory region MR and the staircase region SR2.

[0181] In the cross-sectional view shown in Fig. 13(a), a configuration substantially similar to that shown in the cross-sectional view of Fig. 5(a) of the above-described embodiment has already been formed. In Fig. 13(a), a stopper layer STPa and a spacer layer SPCa corresponding to the stopper layer STP and the spacer layer SPC of Fig. 5(a) of the above-described embodiment have already been formed, and these are covered with an insulating layer 51 that reaches the height position of the stacked body LMsb. These configurations shown in Fig. 13(a) can be formed by processes similar to those shown in Figs. 3 and 4 of the above-described embodiment.

[0182] As shown in Figure 13(b), the insulating layer 51 is processed in a stepped shape along the stopper layer STPa above the laminate LMsa and along the stepped portions of the insulating layers NL and OL of the laminate LMsb to form a spacer layer SPCb, and further, a stopper layer STPb covering the upper surface of the spacer layer SPCb is formed.

[0183] As described above, the spacer layer SPCb may have terrace and step portions formed in one-to-one correspondence with the terrace and step portions of the stopper layer STPa above the laminate LMsa and the terrace and step portions formed by the insulating layers NL and OL of the laminate LMsb, or the terrace and step portions may be formed to have fewer steps than the staircase shape of the stopper layer STPa or the staircase shape of the insulating layers NL and OL of the laminate LMsa. The spacer layer SPCb may have a substantially flat shape by leaving the insulating layer 51 unprocessed or by processing it to have a substantially flat surface.

[0184] As shown in FIG. 13(c), a plurality of memory holes MHb are formed in the stacked body LMsb, extending in the stacking direction and reaching the upper ends of the pillars PLc formed in the stacked body LMsa.

[0185] 13(d), these memory holes MHb are filled with a sacrificial layer 26 such as an amorphous silicon layer or a CVD-carbon layer. As a result, in the region that will later become the memory region MR, the sacrificial layer 26 is filled in multiple memory holes MHb, and multiple pillars PLcc are formed in which the lower ends of the above-mentioned pillars PLc are connected.

[0186] 14(a), a laminate LMsc is formed by alternately stacking a plurality of insulating layers NL and a plurality of insulating layers OL, covering the stepped portion of the laminate LMsa and the laminate LMsb including the stepped portion. The sacrificial layers NL of the laminate LMsc will later be replaced with conductive layers to become word lines WL or select gate lines SGD.

[0187] In addition, the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsc. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsc multiple times, similar to the processing shown in FIG. 3(b) of the above-described embodiment.

[0188] At this time, the top step of the staircase portion already formed in the laminate LMsb and the bottom step of the staircase portion formed in the laminate LMsc are brought close to each other, and the staircase shape formed by the insulating layers NL and OL is formed so as to be continuously connected from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsc.

[0189] 14(b), an insulating layer 51 is formed to cover the upper surface of the stopper layer STPb and the newly formed step portion of the laminate LMsc, and to reach the height of the upper surface of the laminate LMsc. The insulating layer 51 is also formed in the outer regions of the laminates LMsa, LMsb, and LMsc. This forms the insulating layer 51 with the stopper layers STPa and STPb interposed in some parts.

[0190] As shown in FIG. 15(a), a plurality of memory holes MHc are formed in the stacked body LMsc, extending in the stacking direction and reaching the upper ends of the pillars PLcc formed in the stacked bodies LMsa and LMsb.

[0191] 15(b), the sacrificial layer 26 is removed from the pillar PLcc at the bottom of the memory hole MHc. As a result, memory holes MHa and MHb are opened at the bottom of the memory holes MHc, respectively, and a plurality of memory holes MH2 are formed that penetrate the stacks LMsc, LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0192] After this, a memory layer ME, a channel layer CN, and a core layer CR extending through the stack LMsc, LMsb, and LMsa are formed in the memory hole MH2, and further the intermediate sacrificial layer SCN of the source line SL is replaced to form a source line SL having an intermediate source line BSL, and multiple pillars PL connected to the source line SL at the side of the channel layer CN are formed.

[0193] Furthermore, the insulating layers NL of the stacked bodies LMsa, LMsb, and LMsc are replaced with conductive material by a replacement process to form stacked bodies LMa, LMb, and LMc having a plurality of word lines WL and select gate lines SGD and SGS.

[0194] Next, how a plurality of contacts CC are formed in the staircase region SR2 will be shown with reference to Figures 16 to 18. Figures 16 to 18 are cross-sectional views of the staircase region SR2 taken along the X direction.

[0195] As shown in Figure 16(a), in the staircase region SR2, a mask pattern 82 is formed that contains, for example, the same type of material as the above-mentioned stopper layers STPa, STPb, and has multiple openings OPa at positions that overlap in the stacking direction with the stepped portions of the word lines WL, etc. of the laminate LMa, and covers the insulating layer 51 and the upper surfaces of the laminate LM2.

[0196] As shown in FIG. 16(b), the insulating layer 51 covering the stepped portion SP2 is etched using a mask pattern 82 to form a plurality of contact holes CLa that penetrate the insulating layer 51 and reach the stopper layer STPb.

[0197] 17(a), a plurality of openings OPb are formed in the mask pattern 82 at positions that overlap with the stepped portions of the word lines WL and the like of the laminate LMb in the stacking direction. At this time, the stopper layer STPb exposed at the bottoms of the plurality of contact holes CLa is also etched away, so that the plurality of contact holes CLa penetrate the stopper layer STPb.

[0198] 17(b), the insulating layer 51 covering the staircase portion SP2 is etched using a mask pattern 82 having a plurality of openings OPb formed therein, to form a plurality of contact holes CLb that penetrate the insulating layer 51 and reach the stopper layer STPb above the staircase portion SP2 of the laminate LMb. At this time, the plurality of contact holes CLa also penetrate the spacer layer SPCb above the staircase portion SP2 of the laminate LMa and reach the stopper layer STPa.

[0199] 18(a), a plurality of openings OPc are formed in the mask pattern 82 at positions that overlap with the stepped portions of the word lines WL and the like of the laminate LMc in the stacking direction. At this time, the stopper layer STPa exposed at the bottoms of the plurality of contact holes CLa and the stopper layer STPb exposed at the bottoms of the plurality of contact holes CLb are also etched away, so that the plurality of contact holes CLa and CLb pass through the stopper layers STPa and STPb, respectively.

[0200] 18(b), the insulating layer 51 covering the stepped portion SP2 is etched using a mask pattern 82 having a plurality of openings OPc formed therein, to form a plurality of contact holes CLc that penetrate the insulating layer 51 and reach the individual word lines WL of the laminated body LMc. At this time, the plurality of contact holes CLa, CLb also reach the individual word lines WL of the laminated bodies LMa, LMb, respectively.

[0201] Thereafter, an insulating layer 55 and a conductive layer 25 are formed in these contact holes CLa, CLb, and CLc, thereby forming a plurality of contacts CC.

[0202] In this manner, the semiconductor memory device 2 of the second modification is manufactured.

[0203] The semiconductor memory device 2 of the modified example includes a stopper layer STPa arranged at a position overlapping the stepped portion of the word lines WL, etc. of the laminate LMa in the stacking direction of the laminate LM2, and a stopper layer STPb arranged at a height position above the stopper layer STPa and at a position overlapping the stepped portion of the word lines WL, etc. of the laminates LMa and LMb in the stacking direction of the laminate LM2. This makes it possible to prevent the contacts CC from penetrating the word lines WL, etc. to be connected, even in a semiconductor memory device 2 having a laminate LM2 with a 3-tier structure, for example.

[0204] According to the manufacturing method of the modified semiconductor memory device 2, a plurality of contact holes CLb are formed at positions overlapping the staircase portion SP2 of the laminate LMb in the stacking direction of the laminate LM2, extending from a height position above the laminate LM2 and reaching the stopper layer STPb via a mask pattern 82 in which a plurality of openings OPb are formed, and the plurality of contact holes CLa are made to reach the stopper layer STPa above the staircase portion SP2 of the laminate LMa.

[0205] In this way, since the etching is temporarily stopped by the stopper layer STPb, it is possible to suppress variations in the heights reached by these contact holes CLb. Also, since the etching is temporarily stopped by the stopper layer STPa, variations in the heights reached by the plurality of contact holes CLa are also suppressed.

[0206] According to the manufacturing method of the modified semiconductor memory device 2, multiple openings OPc are formed at positions that overlap the staircase portion SP2 of the laminate LMc of the mask pattern 82 in the stacking direction of the laminate LM2, and are penetrated through the stopper layer STPa exposed at the bottom surfaces of multiple contact holes CLa and through the stopper layer STPb exposed at the bottom surfaces of multiple contact holes CLb.

[0207] In this way, the opening of the mask pattern 82 for forming the upper contact hole CLc and the removal of the stopper layers STPa, STPb at the bottom of the lower contact holes CLa, CLb are performed simultaneously, thereby reducing the number of steps for forming the contact CC.

[0208] According to the manufacturing method of the semiconductor memory device 2 of the modified example, a plurality of contact holes CLc are formed via a mask pattern 82 in which a plurality of openings OPc are formed, the contact holes CLc extending from a height position above the laminate LM2 at a position where the staircase portion SP2 of the laminate LMc overlaps with the laminate LM2 in the stacking direction and reaching the portions of the laminate LMc where the word lines WL, etc. are processed in a staircase shape, and the contact holes CLa are made to reach the portions of the laminate LMa where the word lines WL, etc. are processed in a staircase shape, and the contact holes CLb are made to reach the portions of the laminate LMb where the word lines WL, etc. are processed in a staircase shape.

[0209] In this way, the formation of the upper contact hole CLc and the additional processing of the lower contact holes CLa and CLb are performed simultaneously, thereby reducing the number of steps required to form the contacts CC. Furthermore, when additionally etching the lower contact holes CLa and CLb, excessive over-etching of the word lines WL of the stacked body LMc, which are the target of the upper contact hole CLc, can be prevented.

[0210] Furthermore, since the lower contact holes CLa and CLb are stopped above the target word lines WL, etc., there is no need to precisely adjust, for example, the etching conditions and the aspect ratios of these contact holes, and the margin of the etching conditions can be increased.

[0211] The semiconductor memory device 2 of the modified example and the manufacturing method thereof also provide the same effects as the above-described embodiment.

[0212] (Other variations) In the above-described embodiment and modified examples, in a method of drawing out a plurality of word lines WL etc. on one side, contacts are arranged alternately in the Y direction for every two block regions BLK in the staircase region SR on one side in the X direction. However, in a method of drawing out word lines WL etc. on one side, it is sufficient to arrange contacts on one side in the X direction within the same block region BLK, and the arrangement order is not limited to the above.

[0213] In addition, in the above-described embodiment and modified examples, the stacks LM and LM2 have a two-tier structure or a three-tier structure. However, the stack configuration may be one-tier, or may be four or more tiers.

[0214] In the above-described embodiment and modified examples, the pillar PL is connected to the source line SL at the side of the channel layer CN, but this is not limiting. For example, the pillar may be configured so that the memory layer at the bottom of the pillar is removed and the lower end of the channel layer is connected to the source line.

[0215] In the above-described embodiment and modified example, the peripheral circuit CBA is arranged above the stack LM, but the peripheral circuit may be arranged below the stack or on the same layer as the stack.

[0216] When the peripheral circuit is disposed below the stack, the source line and the stack can be formed on an insulating layer of a semiconductor substrate having the peripheral circuit covered with the insulating layer, for example. When the peripheral circuit is disposed on the same layer as the stack, the stack can be formed at a different position from the peripheral circuit on the semiconductor substrate on which the peripheral circuit is formed.

[0217] The embodiment of the present invention may be implemented in the following manner.

[0218] (Addendum) a laminate in which a plurality of conductive layers are stacked and spaced apart from one another; a staircase portion disposed in a portion of the laminate, in which the plurality of conductive layers are processed into a staircase shape; a spacer layer including silicon oxide and having a stepped upper surface, the spacer layer being disposed above a portion of the stepped portion; a stopper layer including tungsten and having a stepped upper surface, the stopper layer being disposed above the spacer film; a plurality of first contacts extending from a height position above the laminate at positions overlapping the step portion in the stacking direction of the laminate, and connected to respective portions of a plurality of first conductive layers on a lower layer side including a lowest conductive layer among the plurality of conductive layers, which are processed into a step shape; a plurality of second contacts extending from a height position above the stacked body at positions overlapping with the step portion in the stacking direction and connected to respective portions where a plurality of second conductive layers on an upper layer side including an uppermost conductive layer among the plurality of conductive layers are processed into a step shape; The stopper layer is the plurality of first conductive layers are arranged at least in a position overlapping the stepped portion in the stacking direction, The plurality of first contacts include: extending in the stacking direction through the stopper layer and the spacer layer; The plurality of second contacts include: extending in the stacking direction without penetrating the stopper layer; The thickness of the stopper layer is greater than the individual thickness of the plurality of conductive layers and less than twice the individual thickness of the plurality of conductive layers; Semiconductor memory device.

[0219] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0220] 1, 2...semiconductor memory device, CC...contact, CLa, CLb, CLc...contact hole, LI...plate-shaped contact, LM, LMa, LMb, LMc, LMga, LMgb, LMsa, LMsb, LMsc...stacked body, MC...memory cell, MR...memory region, NL, OL...insulating layer, 51...insulating layer, OPa, OPb, OPc...opening, PL...pillar, SGD, SGS...select gate line, SP, SP2...staircase portion, SR, SR2...staircase region, SPC, SPCa, SPCb...spacer layer, STP, STPa, STPb...stopper layer, WL...word line.

Claims

1. a laminate in which a plurality of conductive layers are stacked and spaced apart from one another; a staircase portion disposed in a portion of the laminate, in which the plurality of conductive layers are processed into a staircase shape; a stopper layer disposed above a portion of the staircase portion; a plurality of first contacts extending from a height position above the stacked body at positions overlapping the step portion in the stacking direction of the stacked body, and connected to respective portions of a plurality of first conductive layers on a lower layer side including a lowest conductive layer among the plurality of conductive layers, which are processed into a step shape; a plurality of second contacts extending from a height position above the stacked body to positions overlapping with the step portion in the stacking direction and connected to respective portions of a plurality of second conductive layers on upper layers including an uppermost conductive layer among the plurality of conductive layers that are processed into a step shape; The stopper layer is the plurality of first conductive layers are arranged at least at positions overlapping the stepped portion in the stacking direction, The plurality of first contacts include: extending through the stopper layer in the stacking direction; The plurality of second contacts include: extending in the stacking direction without penetrating the stopper layer; Semiconductor memory device.

2. the stopper layer is a tungsten layer; 2. The semiconductor memory device according to claim 1.

3. The thickness of the stopper layer is greater than the individual thickness of the plurality of conductive layers and less than twice the individual thickness of the plurality of conductive layers; 3. The semiconductor memory device according to claim 2.

4. The plurality of first contacts include: a conductive core layer; Each of the core layers has an insulating liner layer covering a sidewall thereof.

3. The semiconductor memory device according to claim 2.

5. The thickness of the liner layer is 1.5 times or more the thickness of each of the plurality of conductive layers; 5. The semiconductor memory device according to claim 4.

6. a plurality of third contacts extending from a height position above the stacked body at positions overlapping with the step portion in the stacking direction, and connected to respective stepped portions of a plurality of third conductive layers belonging to a layer between the plurality of first and second conductive layers among the plurality of conductive layers; The stopper layer is a first stopper layer disposed at a position overlapping a portion where the plurality of first conductive layers are processed into a stepped shape in the stacking direction; a second stopper layer disposed at a height position above the first stopper layer and at a position overlapping a portion where the plurality of first and third conductive layers are processed into a stepped shape in the stacking direction, The plurality of first contacts include: extending in the stacking direction through the first and second stopper layers; The plurality of third contacts include: extending in the stacking direction through the second stopper layer; 2. The semiconductor memory device according to claim 1.

7. a first laminate including a plurality of first sacrificial layers stacked at intervals from one another, the plurality of first sacrificial layers being processed into a staircase shape to form a first staircase portion; forming a first stopper layer above the first staircase portion; a second laminate including a plurality of second sacrificial layers stacked on the first laminate at intervals, the second sacrificial layers being processed into a staircase shape to form a second staircase portion on an extension of the first staircase portion; replacing the first and second sacrificial layers with a conductive material to form a plurality of first and second conductive layers, respectively; forming a plurality of first contacts extending from a height position above the first and second stacked bodies at positions overlapping the first step portion and the stacking direction of the first and second stacked bodies and connected to the respective portions of the plurality of first conductive layers processed in a step shape; forming a plurality of second contacts extending from a height position above the first and second stacked bodies at positions overlapping with the second step portion in the stacking direction and connected to the respective stepped portions of the plurality of second conductive layers; forming the plurality of first and second contacts includes: forming a plurality of first contact holes via a mask pattern, the first contact holes extending from a height position above the first and second stacked bodies and reaching the first stopper layer at positions overlapping the first staircase portion and the first and second stacked bodies in a stacking direction; forming a plurality of first openings at positions overlapping the second staircase portion of the mask pattern in the stacking direction, and penetrating the first stopper layer exposed at bottom surfaces of the plurality of first contact holes; forming a plurality of second contact holes, which extend from a height position above the first and second stacked bodies at positions overlapping with the second staircase portion in the stacking direction and reach the portions where the plurality of second conductive layers are processed in a staircase shape, via the mask pattern in which the plurality of first openings are formed, and causing the plurality of first contact holes to reach the portions where the plurality of first conductive layers are processed in a staircase shape, A method for manufacturing a semiconductor memory device.

8. at least one of the first and second stopper layers is formed containing the same type of material as the mask pattern; 8. The method for manufacturing a semiconductor memory device according to claim 7.

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