Semiconductor memory device

Abstract

Provided is a semiconductor storage device that can be appropriately manufactured, which has: a substrate having a first region and a second region arranged in a first direction; a plurality of conductive layers and a plurality of interlayer insulating layers alternately arranged in a second direction intersecting a surface of the substrate, extending in the first direction over the first region and the second region; a semiconductor layer provided in the first region, extending in the second direction, and facing the plurality of conductive layers; a charge accumulation film provided between the plurality of conductive layers and the semiconductor layer; and a first structure provided in the second region, extending in the second direction, and having an outer peripheral surface surrounded by at least a portion of the plurality of conductive layers. The first structure has: a plurality of third regions provided corresponding to at least a portion of the plurality of conductive layers; and a plurality of fourth regions provided corresponding to at least a portion of the plurality of interlayer insulating layers. A width in the first direction of the plurality of third regions is greater than a width in the first direction of the plurality of fourth regions.

Description

[0001] Cross-reference to related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-153514 (filed on September 21, 2021). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Technology

[0004] A semiconductor memory device is known, comprising a substrate, a plurality of gate electrodes stacked in a direction intersecting the surface of the substrate, a semiconductor layer opposite to the plurality of gate electrodes, and a gate insulating layer disposed between the gate electrodes and the semiconductor layer. The gate insulating layer may be, for example, a charge storage layer having insulating properties such as silicon nitride (Si3N4) or a charge storage layer having conductive properties such as a floating gate. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor memory device that can be appropriately manufactured.

[0006] One embodiment of a semiconductor memory device includes: a substrate having a first region and a second region arranged in a first direction; a plurality of conductive layers and a plurality of interlayer insulating layers alternately arranged in a second direction intersecting the surface of the substrate and extending throughout the first region and the second region in the first direction; a semiconductor layer disposed in the first region, extending in the second direction, and opposing the plurality of conductive layers; a charge storage film disposed between the plurality of conductive layers and the semiconductor layer; and a first structure disposed in the second region, extending in the second direction, and having an outer peripheral surface surrounded by at least a portion of the plurality of conductive layers. The first structure includes: a plurality of third regions disposed corresponding to at least a portion of the plurality of conductive layers; and a plurality of fourth regions disposed corresponding to at least a portion of the plurality of interlayer insulating layers. The width of the plurality of third regions in the first direction is greater than the width of the plurality of fourth regions in the first direction. Attached Figure Description

[0007] Figure 1 This is a schematic perspective view of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0009] Figure 3 This is a schematic top view showing a portion of the structure of the semiconductor memory device.

[0010] Figure 4 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0011] Figure 5 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0012] Figure 6 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0013] Figure 7 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0014] Figure 8 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0015] Figure 9 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0016] Figure 10 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0017] Figure 11 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0018] Figure 12 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0019] Figure 13 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0020] Figure 14 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0021] Figure 15 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0022] Figure 16 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0023] Figure 17 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0024] Figure 18 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0025] Figure 19 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0026] Figure 20 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0027] Figure 21 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0028] Figure 22 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0029] Figure 23 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0030] Figure 24 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0031] Figure 25 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0032] Figure 26 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0033] Figure 27 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0034] Figure 28 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0035] Figure 29 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0036] Figure 30 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0037] Figure 31 This is a schematic cross-sectional view used to illustrate the semiconductor memory device involved in the comparative example.

[0038] Figure 32 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device involved in the comparative example.

[0039] Figure 33 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device involved in the comparative example.

[0040] Figure 34 This is a schematic cross-sectional view of a semiconductor memory device involved in other embodiments.

[0041] Figure 35 This is a schematic cross-sectional view of a semiconductor memory device involved in other embodiments. Detailed Implementation

[0042] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and do not limit the present invention. Additionally, the following drawings are schematic, and for ease of explanation, some structural details may be omitted. Also, regarding multiple embodiments, common parts are labeled with the same reference numerals, and sometimes descriptions are omitted.

[0043] Furthermore, when referred to as a "semiconductor memory device" in this specification, it sometimes refers to a memory die, and sometimes to a memory system that includes a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It also sometimes refers to a structure that includes a host computer, such as a smartphone, tablet, or personal computer.

[0044] In addition, when referred to as "control circuit" in this specification, it sometimes refers to peripheral circuits such as sequencers installed on the memory die, sometimes to controller dies or controller chips connected to the memory die, and sometimes to a structure that includes both.

[0045] Furthermore, in this specification, the term "electrically connected" to refer to the first structure and the second structure can mean that the first structure and the second structure are directly connected, or that the first structure is connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0046] In addition, in this specification, the direction parallel to the upper surface of the substrate is called the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and the direction perpendicular to the upper surface of the substrate is called the Z direction.

[0047] In addition, in this specification, the direction along a specified surface is sometimes referred to as the first direction, the direction along the specified surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specified surface is referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0048] Furthermore, in this specification, the terms "upper" and "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when referring to a structure as a lower surface or lower end, it refers to the surface or end of that structure on the substrate side; when referring to it as an upper surface or upper end, it refers to the surface or end of that structure on the opposite side from the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0049] In addition, in this specification, when referring to structures, components, etc., the terms "width," "length," or "thickness" in the specified direction sometimes refer to the width, length, or thickness in a cross-section observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), etc.

[0050] [First Implementation]

[0051] [structure]

[0052] Figure 1 This is a schematic perspective view of the semiconductor memory device according to the first embodiment. Figure 2 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. Furthermore, Figure 2 The YZ cross-section is shown, but when observing cross-sections other than the YZ cross-section along the central axis of semiconductor layer 120 (e.g., the XZ cross-section), the same pattern as the YZ cross-section can also be observed. Figure 2 Same construction. Figure 3 This is a schematic top view showing a portion of the structure of the semiconductor memory device. Figure 4 and Figure 5 This is a schematic cross-sectional view showing a portion of the structure of the semiconductor memory device. Figure 4 The text shows that... Figure 3 The structure shown is a cross-section cut along line A-A′ and viewed in the direction of the arrow. Additionally, in Figure 4 The text shows that... Figure 3 The structure shown is a cross-section cut along line B-B′ and observed in the direction of the arrow. Figure 5 The text shows that... Figure 3 The structure shown is a cross-section cut along line C-C′ and viewed in the direction of the arrow. Furthermore, from... Figure 4 and Figure 5 The insulating layer 125, tunnel insulating film 131, and charge accumulation film 132 described later are omitted.

[0053] like Figure 1As shown, the semiconductor memory device includes a semiconductor substrate 100 and a transistor layer L disposed on the semiconductor substrate 100. TR In transistor layer L TR The wiring layers D0 to D2 are arranged above the wiring layer D2, and the memory cell array layer L is arranged above the wiring layer D2. MCA and in the memory cell array layer L MCA The wiring layer M0 is set above it.

[0054] [Structure of semiconductor substrate 100]

[0055] The semiconductor substrate 100 includes, for example, p-type silicon (Si) containing p-type impurities such as boron (B). An N-type well region containing p-type impurities such as phosphorus (P), a P-type well region containing p-type impurities such as boron (B), a semiconductor substrate region without p-type and p-type well regions, and an insulating region STI are provided on the surface of the semiconductor substrate 100.

[0056] Additionally, a memory hole region R arranged in the X direction is provided on the semiconductor substrate 100. MH and hook-up area R HU .

[0057] [Transistor layer L] TR [Construction]

[0058] transistor layer L TR The semiconductor substrate 100 has multiple insulating layers gi disposed on its upper surface and multiple electrodes gc disposed on the upper surface of these multiple insulating layers gi. Furthermore, each region of the semiconductor substrate 100 and the multiple electrodes gc are respectively connected to a contact electrode CS.

[0059] The N-type well region, P-type well region, and semiconductor substrate region of the semiconductor substrate 100 function as channel regions of multiple transistors Tr that constitute the peripheral circuit of NAND flash memory, and as electrodes of multiple capacitors, respectively.

[0060] Multiple electrodes gc function as the gate electrodes of multiple transistors Tr that constitute the peripheral circuit of NAND flash memory, and as the other electrode of multiple capacitors.

[0061] The contact electrode CS extends in the Z direction and is connected at its lower end to the upper surface of the semiconductor substrate 100 or the electrode gc. An impurity region containing N-type or P-type impurities is provided at the connection portion between the contact electrode CS and the semiconductor substrate 100. The contact electrode CS may, for example, comprise a laminated film containing a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0062] [Construction of wiring layers D0, D1, and D2]

[0063] The wiring layers D0, D1, and D2 contain multiple wiring and transistor layers L TR The structure and memory cell array layer L in MCA At least one of the structures in the wiring is electrically connected. These multiple wirings may include, for example, a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0064] [Memory cell array layer L] MCA memory hole area R MH [Construction in]

[0065] In memory cell array layer L MCA A memory block BLK is provided. An inter-block insulating layer ST, such as silicon oxide (SiO2), is provided on the side of the memory block BLK in the Y direction. The memory block BLK is, for example, as shown below. Figure 3 As shown, it has multiple string units SU arranged in the Y direction. An inter-string unit insulating layer SHE, such as silicon oxide (SiO2), is provided between two adjacent string units SU along the Y direction.

[0066] Memory block BLK, for example Figure 1 As shown, it has a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0067] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may comprise a stack of films containing a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Additionally, the conductive layer 110 may, for example, comprise polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged along the Z direction.

[0068] A portion of the plurality of conductive layers 110 functions as the gate electrode and word line of the memory cell (memory transistor) of the NAND flash memory. A portion of the plurality of conductive layers 110 also functions as the gate electrode and select gate line of the select transistor of the NAND flash memory. Furthermore, a portion of the plurality of conductive layers 110 is composed of… Figure 3 The example shows an inter-string insulation layer SHE that is broken in the Y direction, with each string unit SU as a unit.

[0069] like Figure 1As shown, a conductive layer 112 is disposed below the conductive layer 110. The conductive layer 112 may, for example, contain polysilicon containing impurities such as phosphorus (P) or boron (B). Alternatively, the conductive layer 112 may contain, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. Furthermore, an interlayer insulating layer 101, such as silicon oxide (SiO2), is disposed between the conductive layer 112 and the conductive layer 110. The conductive layer 112 functions as the source line of the NAND flash memory.

[0070] Semiconductor layer 120, for example Figure 3 As shown, the semiconductor layer 120 is arranged in a predetermined pattern in both the X and Y directions. The semiconductor layer 120 functions as a memory cell of the NAND flash memory and as the channel region for the select transistor. The semiconductor layer 120 may contain, for example, polysilicon (Si). The semiconductor layer 120 may contain, for example, polysilicon (Si). Figure 1 As shown, it has a generally cylindrical shape, with an insulating layer 125 such as silicon oxide disposed in the central part. In addition, the outer peripheral surfaces of the semiconductor layer 120 are surrounded by conductive layers 110, which are opposite to the conductive layers 110.

[0071] An impurity region 121 containing N-type impurities such as phosphorus (P) is provided at the upper end of the semiconductor layer 120. The impurity region 121 is connected to the bit line BL via contact electrode Ch and contact electrode Vy.

[0072] The lower end of the semiconductor layer 120 is connected to the conductive layer 112.

[0073] The gate insulating film 130 has a generally cylindrical shape that covers the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 is, for example, as shown in... Figure 2 As shown, a tunnel insulating film 131, a charge storage film 132, and a bulk insulating film 133 are stacked between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the bulk insulating film 133 include, for example, silicon oxide (SiO2). The charge storage film 132 includes, for example, silicon nitride (Si3N4) and other films capable of storing charge. The tunnel insulating film 131, the charge storage film 132, and the bulk insulating film 133 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120, except for the contact portion between the semiconductor layer 120 and the conductive layer 112.

[0074] In addition, Figure 2 An example is shown where the gate insulating film 130 has a charge accumulation film 132 such as silicon nitride. However, the gate insulating film 130 may, for example, have a floating gate such as polysilicon containing N-type or P-type impurities.

[0075] [Memory cell array layer L] MCA The joint area R HU [Construction in]

[0076] like Figure 1 and Figure 3 As shown, the joint area R HU It has multiple contact electrodes CC and multiple support structures HR disposed in the vicinity of these multiple contact electrodes CC.

[0077] exist Figure 1 The figure shows multiple contact electrodes CC arranged in the X direction. These multiple contact electrodes CC extend in the Z direction and are connected at their lower ends to multiple conductive layers 110 at different height positions. The contact electrodes CC may, for example, comprise a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0078] The support structure HR has a generally cylindrical shape extending in the Z direction. In addition, the outer peripheral surface of the support structure HR is surrounded by a conductive layer 110 and an interlayer insulating layer 101, and is in contact with the conductive layer 110 and the interlayer insulating layer 101.

[0079] In addition, such as Figure 4 and Figure 5 As shown, the support structure HR has a generally cylindrical insulating layer 151 and an insulating layer 152 covering the outer peripheral surface of the insulating layer 151. The insulating layer 151 has a plurality of regions 153 and a plurality of regions 154. The plurality of regions 153 are respectively disposed at height positions corresponding to the plurality of conductive layers 110 arranged in the Z direction. The plurality of regions 154 are respectively disposed at height positions corresponding to the plurality of interlayer insulating layers 101 arranged in the Z direction. The plurality of regions 153 and the plurality of regions 154 are arranged alternately in the Z direction. The outer diameter D of region 153 is... 153 The outer diameter D of region 154 is greater than that of region 154. 154 A portion of the upper surface of region 153 is in contact with the lower surface of interlayer insulating layer 101. A portion of the lower surface of region 153 is in contact with the upper surface of interlayer insulating layer 101. The outer peripheral surface of region 153 is in contact with conductive layer 110. The outer peripheral surface of region 154 is in contact with interlayer insulating layer 101.

[0080] In addition, the outer diameter D of region 153 153 For example, it can be specified by the following method. For example, by observing the XY cross-section corresponding to any one of the multiple conductive layers 110 arranged in the Z direction using SEM, TEM, etc. (refer to...) Figure 3 Next, in this XY section, apply a circle along the outer perimeter of region 153. The diameter of this circle can be set as the outer diameter D. 153 .

[0081] Similarly, the outer diameter D154 of region 154 can be specified, for example, by observing the XY cross-section corresponding to any one of the multiple interlayer insulating layers 101 arranged in the Z direction using SEM, TEM, etc. (see reference). Figure 3 Next, in this XY section, apply a circle along the outer perimeter of region 154. The diameter of this circle can be set as the outer diameter D. 154 .

[0082] Furthermore, in this way, the outer diameter D 153 D 154 Under specified conditions, the height positions of the two XY profiles corresponding to regions 153 and 154 are preferably close. For example, the outer diameter D is determined based on the XY profile corresponding to either of the two adjacent conductive layers 110 in the Z direction. 153 When specified, the outer diameter D is preferably determined based on the XY profile corresponding to the interlayer insulating layer 101 disposed between the two conductive layers 110. 154 Regulations are made. However, the outer diameter D can also be determined based on the XY profile corresponding to other height positions. 153 D 154 Regulations shall be established.

[0083] In addition, Figure 4 The example shows the distance D between the central positions of two adjacent support structures HR in the Y direction. HRY Additionally, in Figure 5 This example illustrates the distance D between the center positions of two adjacent support structures HR in the X direction. HRX The amount of protrusion of region 153 relative to region 154 (outer diameter D) 153 With outer diameter D 154 The size of half the difference (which can be adjusted appropriately, for example, compared to the distance D) can be adjusted accordingly. HRY Distance D HRX Or the smaller of them, which is 1 / 16th the size.

[0084] Furthermore, interlayer insulating layer 101 and insulating layers 151, 152 may, for example, contain silicon oxide (SiO2). Additionally, the density of insulating layer 151 may be greater than the density of interlayer insulating layers 101 and 152. Furthermore, the content of hydrogen (H) or other impurities in insulating layer 151 may be less than the content of impurities in interlayer insulating layers 101 and 152. Furthermore, the etching rate for hydrofluoric acid or other solutions may be greater for interlayer insulating layers 101 and 152 than for insulating layer 151. Furthermore, interlayer insulating layers 101 and 151, 152 may be distinguishable using a transmission electron microscope (TEM). Additionally, the boundary lines between interlayer insulating layers 101 and 151, 152 may be distinguishable using a transmission electron microscope.

[0085] [Construction of wiring layer M0]

[0086] For example, Figure 1 As shown, the wiring layer M0 includes multiple wirings. These multiple wirings may include, for example, a laminate of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Furthermore, a portion of the multiple wirings functions as bit lines BL. The bit lines BL are arranged in the X direction and extend in the Y direction. In addition, these multiple bit lines BL are connected to the semiconductor layer 120 via contact electrodes Ch and Vy, respectively.

[0087] [Manufacturing Method]

[0088] Next, refer to Figures 6 to 30 A method for manufacturing a semiconductor memory device according to the first embodiment will be described. Figures 6 to 11 and Figures 16-24 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 4 Corresponding cross-sections. Figure 12 This is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 10 The portion represented by A is shown in enlarged form. Figure 13 This is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 11 The portion represented by A is shown in enlarged form. Figure 14 This is a schematic cross-sectional view used to illustrate other execution methods of the manufacturing method. Figure 11 The portion represented by A is shown in enlarged form. Figure 15 This is a schematic cross-sectional view used to illustrate other execution methods of the manufacturing method, showing the relationship with... Figure 14 The corresponding part. Figures 25-30 This is a schematic cross-sectional view used to illustrate the manufacturing method, showing the relationship with... Figure 4Corresponding cross-sections.

[0089] In the manufacture of the semiconductor memory device according to this embodiment, firstly, a transistor layer L is formed on the semiconductor substrate 100. TR Routing layer D0, routing layer D1 and routing layer D2 ( Figure 1 Additionally, an interlayer insulating layer 101 is formed above the wiring layer D2.

[0090] Next, for example, Figure 6 As shown, a semiconductor layer 112A such as silicon, a sacrificial layer 112B such as silicon nitride, and a semiconductor layer 112C such as silicon are formed. Additionally, multiple interlayer insulating layers 101 and multiple sacrificial layers 110A are formed alternately. Furthermore, an insulating layer 102 is formed. This process is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0091] Next, for example, Figure 7 As shown, multiple memory holes MH are formed at positions corresponding to the multiple semiconductor layers 120. Additionally, multiple vias HRH are formed at positions corresponding to the multiple support structures HR. The memory holes MH and vias HRH are through-holes extending in the Z direction, penetrating the interlayer insulating layer 101 and sacrificial layer 110A, semiconductor layer 112C and sacrificial layer 112B, and exposing the upper surface of semiconductor layer 112A. This process is performed, for example, by a method such as RIE.

[0092] Next, for example, Figure 8 As shown, a mask material 160 is formed on the upper surface of the insulating layer 102. The mask material 160 covers a plurality of memory holes MH and exposes a plurality of via holes HRH.

[0093] Next, for example, Figure 8 As shown, a portion of the sacrificial layer 110A is removed via multiple vias HRH, forming multiple voids 153A. This process is performed, for example, by wet etching.

[0094] Next, for example, Figure 9 As shown, the mask material 160 is removed.

[0095] Next, for example, Figure 10 As shown, an insulating layer 133A, such as silicon nitride, is formed on the upper surface of the insulating layer 102, the inner peripheral surface of the memory hole MH, and the inner peripheral surface of the via hole HRH. This process is performed, for example, by CVD.

[0096] Next, for example, Figure 11As shown, the insulating layer 133A is oxidized. This forms multiple block insulating films 133 in the multiple memory vias MH. Additionally, multiple insulating layers 151 are formed in the multiple vias HRH.

[0097] In addition, for example, Figure 12 As shown, insulating layer 133A ( Figure 10 The thickness of the film can be, for example, the extent to which the voids 153A are not filled. For example, the thickness of the insulating layer 133A can be less than half the thickness of the sacrificial layer 110A.

[0098] Here, as Figure 13 As shown, if the insulating layer 133A is oxidized, the volume of the insulating layer 133A increases. That is, the volume of the block insulating film 133 and the insulating layer 151 is greater than the volume of the insulating layer 133A. Therefore, in this process, due to the increase in volume, the voids 153A can be filled.

[0099] Furthermore, the methods described above are merely illustrative; specific methods can be adjusted accordingly. For example, in reference... Figure 11 In the described process, for example, Figure 14 As shown, gap 153A does not need to be filled. In such cases, for example... Figure 15 As shown, in the process described later, an insulating layer 152 can be formed in the via HRH, thereby filling the void 153A.

[0100] Next, for example, Figure 16 As shown, a mask material 162 is formed on the upper surface of the insulating layer 102. The mask material 162 covers multiple memory holes MH, exposing multiple via holes HRH.

[0101] Next, for example, Figure 16 As shown, an insulating layer 152 is formed in the multiple vias HRH. Figure 16 An example of coating with materials such as polysilazane is shown. However, this process can be performed by CVD or the like. Furthermore, in this process, in the memory hole region R... MH With the joint area R HU Between, a step is formed on the upper surface of the insulating layer 152.

[0102] Next, for example, Figure 17 As shown, in the joint region R HU A mask material 163 is formed on the upper surface of the insulating layer 152.

[0103] Next, for example, Figure 18 As shown, in the memory hole region R MHThe insulating layer 152 is removed to expose the upper surface of the mask material 162. This process is performed, for example, by dry etching or wet etching.

[0104] Next, for example, Figure 19 As shown, remove mask materials 162 and 163.

[0105] Next, for example, Figure 20 As shown, resist 164 is formed. In this process, resist 164 is filled inside the memory hole MH.

[0106] Next, for example, Figure 21 As shown, in the joint region R HU A portion of the insulating layer 152 is removed. This process is performed, for example, by means of a RIE (Reinforcing Interchange). This forms the support structure HR.

[0107] Next, for example, Figure 22 As shown, a portion of the resist 164 is removed, exposing the upper surface of the block insulating film 133.

[0108] Next, for example, Figure 23 As shown, the portion of the insulating layer 152 located above the insulating layer 102 is removed. This process is performed, for example, by CMP (Chemical Mechanical Polishing).

[0109] Next, for example, Figure 24 As shown, a semiconductor layer 120 is formed. In this process, for example, the resist 164 in the memory hole MH is first removed. Next, a reference layer is formed in the memory hole MH. Figure 2 The process described includes a charge storage film 132, a tunnel insulating film 131, a semiconductor layer 120, and an insulating layer 125. This process is performed, for example, by CVD.

[0110] Next, for example, Figure 25 As shown, a trench STA is formed. The trench STA extends in the Z and X directions, and breaks the interlayer insulating layer 101, sacrificial layer 110A, semiconductor layer 112C, and sacrificial layer 112B in the Y direction, exposing the upper surface of semiconductor layer 112A. This process is performed, for example, by a method such as RIE.

[0111] Next, for example, Figure 26 As shown, a portion of the sacrificial layer 112B and the gate insulating film 130 are removed, exposing a portion of the semiconductor layer 120. This process is performed, for example, by a wet etching method.

[0112] Next, for example, Figure 27As shown, a conductive layer 112 is formed. This process is performed, for example, by methods such as epitaxial growth.

[0113] Next, for example, Figure 28 As shown, the sacrificial layer 110A is removed via the slot STA. This forms a hollow structure comprising a plurality of interlayer insulating layers 101 arranged in the Z direction, a structure within a memory via MH supporting these interlayer insulating layers 101 (semiconductor layer 120, gate insulating film 130, and insulating layer 125), and a support structure HR supporting these interlayer insulating layers 101. This process is performed, for example, by a wet etching method.

[0114] Next, for example, Figure 29 As shown, a conductive layer 110B is formed. This process is performed, for example, by a method such as CVD.

[0115] Next, for example, Figure 30 As shown, the portion of the conductive layer 110B that is disposed on the side of the interlayer insulating layer 101 in the Y direction is removed. As a result, a plurality of conductive layers 110 arranged in the Z direction are formed.

[0116] Next, for example, Figure 4 As shown, an inter-block insulating layer ST is formed within the STA groove. This process is performed, for example, by methods such as CVD and RIE.

[0117] Then, the contact electrode CC is formed. Figure 1 ), bit line BL ( Figure 1 By cutting the wafer, the semiconductor memory device according to the first embodiment is formed, through wiring, etc.

[0118] [Comparative Example]

[0119] Figure 31 This is a schematic cross-sectional view used to illustrate the semiconductor memory device involved in the comparative example. The semiconductor memory device involved in the comparative example does not have a support structure HR, but has a support structure HR′. The support structure HR′ does not have an insulating layer 151, but has an insulating layer 151′. See reference... Figure 4 As described above, insulating layer 151 has two regions 153 and 154 with different outer diameters. On the other hand, insulating layer 151' does not have the structure described above. The outer diameter of insulating layer 151' is approximately constant.

[0120] Figure 32 and Figure 33 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device involved in the comparative example. Figure 32 With reference Figure 27 The procedures described correspond to those described. Figure 33With reference Figure 28 The procedures described correspond to those described.

[0121] In the manufacture of the semiconductor memory device involved in the comparative example, the reference procedure is not performed. Figure 8 and Figure 9 The procedures described.

[0122] like Figure 33 As shown, during the manufacture of the semiconductor memory device involved in the comparative example, if multiple sacrificial layers 110A are removed, a hollow structure is formed. This hollow structure includes multiple interlayer insulating layers 101 arranged in the Z direction, a structure within a memory hole MH that supports these multiple interlayer insulating layers 101, and a support structure HR′ that supports these multiple interlayer insulating layers 101.

[0123] Here, the film structure of the structure within the memory hole MH (semiconductor layer 120, gate insulating film 130, and insulating layer 125) differs from the film structure of the support structure HR′. In this case, the amount of thermal shrinkage of the structure within the memory hole MH sometimes differs from the amount of thermal shrinkage of the support structure HR′. Specifically, the amount of thermal shrinkage of the insulating layer 152 is sometimes greater than that of the insulating layer 151. In such a case, if a... Figure 33 In hollow structures like the one shown, the distance between two adjacent interlayer insulating layers 101 in the Z direction sometimes varies depending on the amount of thermal contraction of the structure within the memory hole MH or the supporting structure HR′. Consequently, sometimes the memory hole region R... MH The height position of the upper surface of the structure and the joint area R HU The height positions of the upper surface of the structure are different.

[0124] [Effect]

[0125] During the manufacture of the semiconductor memory device according to the first embodiment, referring to Figure 11 In the described process, an insulating layer 151 is formed. Furthermore, the insulating layer 151 has a plurality of regions 153 arranged in the Z direction. Here, the plurality of regions 153 are embedded in the region near the through-hole HRH in the region between the plurality of interlayer insulating layers 101 arranged in the Z direction. This suppresses the aforementioned variation in the height position of the upper surface. In particular, when the thermal shrinkage of the insulating layer 151 is less than that of the insulating layer 152, the plurality of interlayer insulating layers 101 can be appropriately supported by the plurality of regions 153.

[0126] [Other Implementation Methods]

[0127] The semiconductor memory device according to the first embodiment has been described above. However, the above structure is merely an example, and the specific structure can be adjusted appropriately.

[0128] For example, in Figure 34 The illustrated semiconductor memory device has a support structure HR2 instead of a support structure HR. The support structure HR2 is constructed in essentially the same manner as the support structure HR. However, the support structure HR2 has an insulating layer 251 instead of insulating layers 151 and 152. The insulating layer 251 is constructed in essentially the same manner as insulating layer 151. However, the insulating layer 251 is filled into the via HRH (… Figure 8 )Inside.

[0129] Additionally, for example in Figure 35 The semiconductor memory device illustrated herein has a support structure HR3 instead of a support structure HR. The support structure HR3 is substantially the same as the support structure HR. However, the support structure HR3 replaces insulating layers 151 and 152 and has a plurality of insulating layers 351 arranged in the Z direction and an insulating layer 352 extending in the Z direction. The insulating layer 352 is substantially the same as the insulating layer 152. However, the outer peripheral surface of the insulating layer 352 is in contact with the plurality of insulating layers 351 arranged in the Z direction and the plurality of interlayer insulating layers 101 arranged in the Z direction. The plurality of insulating layers 351 arranged in the Z direction are constructed in the same way as the plurality of regions 153 arranged in the Z direction of the insulating layer 151. For example, in the mask material 160 ( Figure 8 After the sacrificial layer 110A is formed, it is oxidized through an oxidation process to form the insulating layer 351, thereby achieving the structure described above. Additionally, in the mask material 162 ( Figure 16 After the insulation layer 151 is formed, a portion of it is removed, thereby achieving the structure described above.

[0130] Furthermore, in the above example, it is shown that the supporting structures HR1, HR2, and HR3 are located in the joint area R. HU Examples. However, the supporting structures HR2 and HR3 can also be set in the junction area R. HU Areas other than those mentioned above.

[0131] [other]

[0132] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

[0133] Explanation of reference numerals in the attached figures

[0134] 100… Semiconductor substrate, 101… Interlayer insulating layer, 110… Conductive layer, 120… Semiconductor layer, 130… Gate insulating film, 131… Tunnel insulating film, 132… Charge accumulation film, 133… Block insulating film, 151… Insulating layer, 152… Insulating layer, 153… Multiple regions, 154… Region, HR… Support structure.

Claims

1. A semiconductor memory device, wherein, have: The substrate has a first region and a second region arranged in a first direction; Multiple conductive layers and multiple interlayer insulating layers are alternately arranged in a second direction intersecting the surface of the substrate, extending throughout the first region and the second region in the first direction; A semiconductor layer is disposed in the first region, extends in the second direction, and is opposite to the plurality of conductive layers; A charge storage film is disposed between the plurality of conductive layers and the semiconductor layer; as well as The first structure, disposed in the second region and extending in the second direction, has an outer peripheral surface surrounded by at least a portion of the plurality of conductive layers. The first structure has: Multiple third regions are provided, corresponding to at least a portion of the multiple conductive layers; Multiple fourth regions are disposed corresponding to at least a portion of the multiple interlayer insulating layers; and The first insulating layer includes at least one of the plurality of third regions. The width of the plurality of third regions in the first direction is greater than the width of the plurality of fourth regions in the first direction. The first insulating layer has at least one of the following: a density greater than that of at least one of the plurality of interlayer insulating layers, a hydrogen content lower than that of at least one of the plurality of interlayer insulating layers, and an etch rate against the first solution lower than that of at least one of the plurality of interlayer insulating layers.

2. The semiconductor memory device as claimed in claim 1, wherein, It has a second structure disposed in the second region, extending in the second direction, and having an outer peripheral surface surrounded by at least a portion of the plurality of conductive layers. The distance between the central position of the first structure in the first direction and the central position of the second structure in the first direction is defined as the first distance. And if the first protrusion amount is set as half the difference between the width of one of the plurality of third regions in the first direction and the width of one of the plurality of fourth regions in the first direction, The first protrusion is greater than 1 / 16 of the first distance.

3. The semiconductor memory device as claimed in claim 1, wherein, It has a second insulating layer disposed in the second region, extending in the second direction, and having an outer peripheral surface surrounded by the first insulating layer.

4. The semiconductor memory device as claimed in claim 3, wherein, The first insulating layer has at least one of the following: a higher density than the second insulating layer, a lower hydrogen content than the second insulating layer, and a lower etching rate against the second solution than the second insulating layer.

5. The semiconductor memory device according to any one of claims 1 to 4, wherein, It has a contact electrode disposed in the second region, extending in the second direction, and connected to one of the plurality of conductive layers.

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