Semiconductor device

Abstract

To provide a new circuit that is used for a shift register and the like.SOLUTION: A basic configuration includes: a first transistor to fourth transistor; and first wiring to fourth wiring. A power supply potential VDD is supplied to the first wiring; and a power supply potential VSS is supplied to the second wiring. A digital signal having two values is supplied to the third wiring and fourth wiring. This digital signal is at the same potential as the power supply potential VDD when it is at a high level; and the signal is at the same potential as the power supply potential VSS when it is at a low level. There are four combinations of potentials of the third wiring and fourth wiring; and any of the combinations of potentials can turn off the first transistor to fourth transistor. That is, since there is no transistor that is always on, deterioration of transistor characteristics can be suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and also to a display device including the semiconductor device, particularly a semiconductor device. The present invention relates to a liquid crystal display device having the above-mentioned and an electronic device having the liquid crystal display device. [Background technology]

[0002] In recent years, display devices such as liquid crystal display devices and light-emitting devices have become more common due to the increase in large display devices such as liquid crystal televisions. In particular, transistors formed from non-crystalline semiconductors on insulators have been actively developed. The pixel circuit and the driver circuit (hereinafter referred to as the internal circuit) including the shift register circuit are formed by using the transistor. The technology of forming a single integrated circuit (called a semiconductor circuit) contributes greatly to lowering power consumption and costs, and is being actively promoted. The internal circuit formed on the insulator is connected to the insulator via an FPC, etc. It is connected to a controller IC or other external circuit (hereafter referred to as an external circuit) and its operation is It is under control.

[0003] In addition, amorphous semiconductor transistors are used as internal circuits integrally formed on an insulator. A shift register configured as above has been devised (see Patent Document 1).

[0004] However, the characteristics of a non-crystalline semiconductor transistor vary depending on the time it is turned on or the applied voltage. To solve this problem, two transistors were connected in parallel. By connecting the transistors to the power supply and turning them on in sequence, the deterioration of the transistor characteristics can be suppressed. The following has been proposed (see Non-Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-78172 [Non-Patent Document]

[0006] [Non-Patent Document 1] SID ’05 DIGEST P348~P351 [Summary of the Invention] [Problems to be Solved by the Invention]

[0007] In Non-Patent Document 1 above, a detailed driving method is not disclosed. Also, in order to control two transistors connected in parallel one by one, a control circuit with a large circuit scale is required.

[0008] In view of such problems, an object of the present invention is to provide a flip-flop circuit, a shift register, and a semiconductor device including such a shift register, which use a control circuit with a relatively small circuit scale, as well as a display device and an electronic apparatus including the display device.

[0009] Also, an object of the present invention is to provide a flip-flop circuit, a shift register, and a semiconductor device including such a shift register, which use a driving method for suppressing deterioration of transistor characteristics different from the prior art, as well as a display device and an electronic apparatus including the display device. [Means for Solving the Problems]

[0010] One of the semiconductor devices of the present invention includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the gate and the first terminal of the first transistor are electrically connected to the first wiring, and the second terminal of the first transistor is connected to the gate of the fourth transistor, the gate of the second transistor is electrically connected to the second wiring and the first terminal of the second transistor is electrically connected to the fourth wiring, and the second terminal of the second transistor is electrically connected to the gate of the fourth transistor, the gate of the third transistor is electrically connected to the third wiring and the first terminal of the third transistor is electrically connected to the fourth wiring, and the second terminal of the third transistor is electrically connected to the gate of the fourth transistor, the first terminal of the fourth transistor is electrically connected to the fourth wiring and the second terminal of the fourth transistor is electrically connected to the fifth wiring, characterized in that there is a configuration as such.

[0011] The first to fourth transistors may be transistors of the same conductivity type. Also, an amorphous semiconductor may be used for the semiconductor layers of the first to fourth transistors.

[0012] Note that the ratio W / L of the channel width W to the channel length L of the first transistor may be made larger than the ratio W / L of the channel width W to the channel length L of the second transistor.

[0013] Also, the ratio W / L of the channel width W to the channel length L of the first transistor may be made larger than the ratio W / L of the channel width W to the channel length L of the third transistor.

[0014] One of the semiconductor devices of the present invention includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a ​​It has a seventh transistor and an eighth transistor, and the gate of the first transistor is electrically connected to a first wiring, the first terminal of the first transistor is electrically connected to a second wiring , the second terminal of the first transistor is electrically connected to the gate of the second transistor , the gate of the eighth transistor is electrically connected to a fourth wiring, and the first terminal of the eighth transistor is electrically connected to a fifth wiring, and the second terminal of the eighth transistor is electrically connected to the gate of the second transistor , the gate of the sixth transistor is electrically connected to the gate of the second transistor , the first terminal of the sixth transistor is electrically connected to the fifth wiring , and the second terminal of the sixth transistor is electrically connected to the gates of the third transistor and the fourth transistor , the gate and the first terminal of the fifth transistor are electrically connected to the second wiring, and the second terminal of the fifth transistor is electrically connected to the gates of the third transistor and the fourth transistor, the gate of the seventh transistor is electrically connected to a third wiring, the first terminal of the seventh transistor is electrically connected to the fifth wiring , and the second terminal of the seventh transistor is electrically connected to the gates of the third transistor and the fourth transistor, the first terminal of the fourth transistor is electrically connected to the fifth wiring , and the second terminal of the fourth transistor is electrically connected to the gate of the second transistor , the first terminal of the third transistor is electrically connected to the fifth wiring, and the second terminal of the third transistor is electrically connected to a sixth wiring, the first terminal of the second transistor is electrically connected to the third wiring , and the second terminal of the second transistor is electrically connected to the sixth wiring , and it is a configuration characterized in that. electrically connected.

[0015] Note that the first transistor to the eighth transistor may be transistors of the same conductivity type. Further, an amorphous semiconductor may be used for the semiconductor layer of the first transistor to the eighth transistor.

[0016] Note that the ratio W / L of the channel width W to the channel length L of the fifth transistor may be made larger than the ratio W / L of the channel width W to the channel length L of the sixth transistor.

[0017] Note that the ratio W / L of the channel width W to the channel length L of the fifth transistor may be made larger than the ratio W / L of the channel width W to the channel length L of the seventh transistor.

[0018] Further, the semiconductor device of the present invention may be used for a liquid crystal display device.

[0019] One of the liquid crystal display devices of the present invention includes a pixel having a liquid crystal element and a drive circuit. The drive circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gate and the first terminal of the first transistor are electrically connected to a first wiring, the second terminal of the first transistor is electrically connected to the gate of the fourth transistor, the gate of the second transistor is electrically connected to a second wiring, the first terminal of the second transistor is electrically connected to a fourth wiring, the second terminal of the second transistor is electrically connected to the gate of the fourth transistor, the gate of the third transistor is electrically connected to a third wiring, the first terminal of the third transistor is electrically connected to the fourth wiring, the second terminal of the third transistor is electrically connected to the gate of the fourth transistor, the first terminal of the fourth transistor is electrically connected to a fifth wiring, and the second terminal of the fourth transistor is electrically connected to the gate of the fourth transistor. The gate of the third transistor is electrically connected to the third wiring, the first terminal of the third transistor is electrically connected to the fourth wiring, the second terminal of the third transistor is electrically connected to the gate of the fourth transistor, the gate of the fourth transistor is electrically connected to the third wiring, the first terminal of the fourth transistor is electrically connected to the fourth wiring, the second terminal of the fourth transistor is electrically connected to the gate of the fourth transistor, the gate of the fourth transistor is electrically connected to the third wiring, the first terminal of the fourth transistor is electrically connected to the fourth wiring, the second terminal of the fourth transistor is electrically connected to the gate of the fourth transistor, ​​​The first terminal of the transistor is electrically connected to the fourth wiring, and the second terminal of the fourth transistor is electrically connected to the fifth wiring, which is a characteristic configuration.

[0020] The first to fourth transistors may be transistors of the same conductivity type . Further, an amorphous semiconductor may be used for the semiconductor layer of the first to fourth transistors .

[0021] Note that the ratio W / L of the channel width W to the channel length L of the first transistor may be made larger than the ratio W / L of the channel width W to the channel length L of the second transistor .

[0022] Also, the ratio W / L of the channel width W to the channel length L of the first transistor may be made larger than the ratio W / L of the channel width W to the channel length L of the third transistor .

[0023] One of the liquid crystal display devices of the present invention has a pixel having a liquid crystal element and a drive circuit, and the drive circuit has a first transistor, a second transistor, a third transistor, a fourth transistor , a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor . The gate of the first transistor is electrically connected to the first wiring , the first terminal of the first transistor is electrically connected to the second wiring, the second terminal of the first transistor is electrically connected to the gate of the second transistor, the gate of the eighth transistor is electrically connected to the fourth wiring, the first terminal of the eighth transistor is electrically connected to the fifth wiring , the second terminal of the eighth transistor is electrically connected to the gate of the second transistor , and the gate of the sixth transistor is electrically connected to the gate of the second transistor The first terminal of the sixth transistor is electrically connected to the fifth wiring, and the second terminal of the sixth transistor is electrically connected to the gates of the third transistor and the fourth transistor. The gate and the first terminal of the fifth transistor are electrically connected to the second wiring, and the second terminal of the fifth transistor is electrically connected to the gates of the third transistor and the fourth transistor. The gate of the seventh transistor is electrically connected to the third wiring, the first terminal of the seventh transistor is electrically connected to the fifth wiring, and the second terminal of the seventh transistor is electrically connected to the gates of the third transistor and the fourth transistor. The first terminal of the fourth transistor is electrically connected to the fifth wiring, the second terminal of the fourth transistor is electrically connected to the gate of the second transistor, the first terminal of the third transistor is electrically connected to the fifth wiring, the second terminal of the third transistor is electrically connected to the sixth wiring, the first terminal of the second transistor is electrically connected to the third wiring, and the second terminal of the second transistor is electrically connected to the sixth wiring. This is a configuration characterized by the above.

[0024] Note that the first transistor to the eighth transistor may be transistors of the same conductivity type. Also, an amorphous semiconductor may be used for the semiconductor layers of the first transistor to the fourth transistor.

[0025] Note that the ratio W / L of the channel width W to the channel length L of the fifth transistor may be made larger than the ratio W / L of the channel width W to the channel length L of the sixth transistor.

[0026] ​​​​​​​​​​​​​​Incidentally, the ratio W / L of the channel width W to the channel length L of the fifth transistor may be made larger than the ratio W / L of the channel width W to the channel length L of the seventh transistor.

[0027] Note that the switches shown in the present invention can be of various forms. As an example, there are electrical switches, mechanical switches, and the like. That is, any device that can control the flow of current is acceptable, and it is not limited to a specific device, and various devices can be used. For example, a transistor may be used, or a diode (e.g., a PN diode, a PIN diode, a Schottky diode, a transistor connected in diode configuration, etc.) may be used, or a thyristor may be used, or a logic circuit combining them may be used. Therefore, when a transistor is used as the switch, since the transistor operates merely as a switch, the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desirable to have a lower off-current, it is desirable to use a transistor with a polarity that results in a lower off-current. Examples of transistors with a low off-current include those having an LDD region or a multi-gate structure. Also, when the potential of the source terminal of the transistor operating as the switch is close to the low-potential side power supply (Vss, GND, 0V, etc.), an N-channel type is used. Conversely, when the potential of the source terminal is close to the high-potential side power supply (Vdd, etc.), a P-channel type is preferably used. This is because by increasing the absolute value of the gate-source voltage, the switch can operate more easily.

[0028] Note that both N-channel type and P-channel type may be used to form a CMOS type switch. Yes. When using a CMOS switch, either a P-channel or an N-channel switch can conduct current, making it easier to function as a switch. For example, regardless of whether the voltage of the input signal to the switch is high or low, the appropriate voltage can be output. Also, since the voltage amplitude value of the signal for turning the switch on and off can be reduced, the power consumption can also be reduced. When using a transistor as a switch, it has an input terminal (one of the source or drain terminals), an output terminal (the other of the source or drain terminals), and a terminal (gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, there may be no terminal for controlling conduction. Therefore, the number of wiring lines for controlling the terminals can be reduced. In the present invention, "connected" shall include cases where it is electrically connected, cases where it is functionally connected, and cases where it is directly connected. Therefore, in the configuration disclosed by the present invention, it shall also include those other than the predetermined connection relationship. For example, between a certain part and a certain part, one or more elements enabling electrical connection (such as switches, transistors, capacitive elements, inductive elements, resistive elements, diodes, etc.) may be arranged. Also, circuits enabling functional connection (such as logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, potential levels of H signals and L signals, etc.))

[0029] When using a transistor as a switch, it has an input terminal (one of the source or drain terminals), an output terminal (the other of the source or drain terminals), and a terminal (gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, there may be no terminal for controlling conduction. Therefore, the number of wiring lines for controlling the terminals can be reduced. When using a transistor as a switch, it has an input terminal (one of the source or drain terminals), an output terminal (the other of the source or drain terminals), and a terminal (gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, there may be no terminal for controlling conduction. Therefore, the number of wiring lines for controlling the terminals can be reduced. When using a transistor as a switch, it has an input terminal (one of the source or drain terminals), an output terminal (the other of the source or drain terminals), and a terminal (gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, there may be no terminal for controlling conduction. Therefore, the number of wiring lines for controlling the terminals can be reduced. When using a transistor as a switch, it has an input terminal (one of the source or drain terminals), an output terminal (the other of the source or drain terminals), and a terminal (gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, there may be no terminal for controlling conduction. Therefore, the number of wiring lines for controlling the terminals can be reduced. When using a transistor as a switch, it has an input terminal (one of the source or drain terminals), an output terminal (the other of the source or drain terminals), and a terminal (gate terminal) for controlling conduction. On the other hand, when using a diode as a switch, there may be no terminal for controlling conduction. Therefore, the number of wiring lines for controlling the terminals can be reduced.

[0030] In the present invention, "connected" shall include cases where it is electrically connected, cases where it is functionally connected, and cases where it is directly connected. Therefore, in the configuration disclosed by the present invention, it shall also include those other than the predetermined connection relationship. For example, between a certain part and a certain part, one or more elements enabling electrical connection (such as switches, transistors, capacitive elements, inductive elements, resistive elements, diodes, etc.) may be arranged. Also, circuits enabling functional connection (such as logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, potential levels of H signals and L signals, etc.)) In the present invention, "connected" shall include cases where it is electrically connected, cases where it is functionally connected, and cases where it is directly connected. Therefore, in the configuration disclosed by the present invention, it shall also include those other than the predetermined connection relationship. For example, between a certain part and a certain part, one or more elements enabling electrical connection (such as switches, transistors, capacitive elements, inductive elements, resistive elements, diodes, etc.) may be arranged. Also, circuits enabling functional connection (such as logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, potential levels of H signals and L signals, etc.)) In the present invention, "connected" shall include cases where it is electrically connected, cases where it is functionally connected, and cases where it is directly connected. Therefore, in the configuration disclosed by the present invention, it shall also include those other than the predetermined connection relationship. For example, between a certain part and a certain part, one or more elements enabling electrical connection (such as switches, transistors, capacitive elements, inductive elements, resistive elements, diodes, etc.) may be arranged. Also, circuits enabling functional connection (such as logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, potential levels of H signals and L signals, etc.)) In the present invention, "connected" shall include cases where it is electrically connected, cases where it is functionally connected, and cases where it is directly connected. Therefore, in the configuration disclosed by the present invention, it shall also include those other than the predetermined connection relationship. For example, between a certain part and a certain part, one or more elements enabling electrical connection (such as switches, transistors, capacitive elements, inductive elements, resistive elements, diodes, etc.) may be arranged. Also, circuits enabling functional connection (such as logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, potential levels of H signals and L signals, etc.)) In the present invention, "connected" shall include cases where it is electrically connected, cases where it is functionally connected, and cases where it is directly connected. Therefore, in the configuration disclosed by the present invention, it shall also include those other than the predetermined connection relationship. For example, between a certain part and a certain part, one or more elements enabling electrical connection (such as switches, transistors, capacitive elements, inductive elements, resistive elements, diodes, etc.) may be arranged. Also, circuits enabling functional connection (such as logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, potential levels of H signals and L signals, etc.)) In the present invention, "connected" shall include cases where it is electrically connected, cases where it is functionally connected, and cases where it is directly connected. Therefore, in the configuration disclosed by the present invention, it shall also include those other than the predetermined connection relationship. For example, between a certain part and a certain part, one or more elements enabling electrical connection (such as switches, transistors, capacitive elements, inductive elements, resistive elements, diodes, etc.) may be arranged. Also, circuits enabling functional connection (such as logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, potential levels of H signals and L signals, etc.)) In the present invention, "connected" shall include cases where it is electrically connected, cases where it is functionally connected, and cases where it is directly connected. Therefore, in the configuration disclosed by the present invention, it shall also include those other than the predetermined connection relationship. For example, between a certain part and a certain part, one or more elements enabling electrical connection (such as switches, transistors, capacitive elements, inductive elements, resistive elements, diodes, etc.) may be arranged. Also, circuits enabling functional connection (such as logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, potential levels of H signals and L signals, etc.)) In the present invention, "connected" shall include cases where it is electrically connected, cases where it is functionally connected, and cases where it is directly connected. Therefore, in the configuration disclosed by the present invention, it shall also include those other than the predetermined connection relationship. For example, between a certain part and a certain part, one or more elements enabling electrical connection (such as switches, transistors, capacitive elements, inductive elements, resistive elements, diodes, etc.) may be arranged. Also, circuits enabling functional connection (such as logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), and potential level conversion circuits (power supply circuits such as boost circuits and buck circuits, potential levels of H signals and L signals, etc.)) ​​A level shifter circuit that changes a bell, etc.) or a voltage source, a current source, a switching circuit, an amplifier circuit (op Amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc., signal amplitude, current amount, etc. Circuits that can increase the circuit, etc.) or signal generation circuits, memory circuits, control circuits, etc.) may be arranged with one or more in between. Alternatively, it may be directly connected and arranged without sandwiching other elements or other circuits in between. It may be arranged.

[0031] Note that when including only the case where elements or circuits are connected without intervening, it shall be described as being directly connected. Also, when it is described as being electrically connected, it includes the case of being electrically connected (that is, connected with another element sandwiched in between) and the case of being functionally connected (that is, connected with another circuit sandwiched in between) and the case of being directly connected continuously (that is, connected without sandwiching another element or another circuit in between). It shall be included.

[0032] Note that display elements, display devices, light-emitting elements, and light-emitting devices can use various forms or can have various elements. For example, as display elements, display devices, light-emitting elements, and light-emitting devices There are EL elements (organic EL elements, inorganic EL elements, or EL elements containing organic and inorganic substances), electron Emission elements, liquid crystal elements, electronic ink, grating light valves (GLV), plasma dis Play (PDP), digital micromirror devices (DMD), piezoelectric ceramic dis Play, carbon nanotubes, etc., and display media whose contrast changes due to electromagnetic action can be applied. Note that as a display device using an EL element, there is an EL display, and as a display device using an electron emission element, there is a field emission display. (FED) or SED type flat panel displays (SED: Surface-conduct ion Electron-emitter Display), etc., as display devices using liquid crystal elements, there are liquid crystal displays, transmissive liquid crystal displays, transflective liquid crystal dis plays, reflective liquid crystal displays, and as display devices using electronic ink, there is electronic paper. .

[0033] In the present invention, various types of transistors can be applied. Therefore, there is no limitation on the type of applicable transistors. Thus, for example, thin film transistors (TFTs) having an amorphous semiconductor film typified by amorphous silicon or polycrystalline silicon can be applied. By these, it is possible to fabricate even without a high manufacturing temperature, fabricate at low cost, fabricate on a large substrate, fabricate on a transparent substrate, and transmit light through the transistor. Also, transistors formed using a semiconductor substrate or an SOI substrate, MOS transistors, junction transistors, bipolar transistors, etc. can be applied. By these, it is possible to fabricate transistors with little variation, fabricate transistors with high current supply capacity, fabricate transistors with a small size, and configure a circuit with low power consumption. Also, transistors having a compound semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, and further, thin film transistors obtained by thinning them can be applied. By these, it is possible to fabricate even without a high manufacturing temperature, fabricate at room temperature, directly form a transistor on a substrate with low heat resistance, for example, a plastic substrate or a film substrate. Moreover, it is possible to apply transistors manufactured using inkjet or printing methods, etc. This enables manufacturing at room temperature, in a low vacuum state, or on a large substrate. Also, it is possible to manufacture without using a mask (reticle), so the layout of the transistor can be easily changed. In addition, it is possible to apply transistors having organic semiconductors, carbon nanotubes, or other transistors. This enables forming transistors on a substrate that can be bent. Note that the non - single - crystal semiconductor film may contain hydrogen or halogen. Also, the transistor can be formed using various substrates, and the type of substrate is not limited to a specific one. Therefore, for example, as the substrate, a single - crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless - steel substrate, a substrate having a stainless - steel foil, etc. can be used. Also, a transistor can be formed using a certain substrate, and then the transistor can be moved to another substrate and arranged on the other substrate. By using these substrates, it is possible to form a transistor with good characteristics, a transistor with low power consumption, make a device that is not easily broken, or give it heat resistance. Note that the configuration of the transistor can take various forms and is not limited to a specific configuration. For example, a multi - gate structure in which there are two or more gate electrodes may be used. With a multi - gate structure, the channel regions are connected in series, so a plurality of

[0034] channels can be formed. channels can be formed. With a multi - gate structure, the channel regions are connected in series, so a plurality of It has a configuration in which transistors are connected in series. By adopting a multi-gate structure, the off-current can be reduced, the breakdown voltage of the transistor can be improved to enhance reliability, or when operating in the saturation region, even if the drain-source voltage changes, the drain-source current does not change much, enabling flat characteristics. Also, a structure in which gate electrodes are arranged above and below the channel may be used. By adopting a structure in which gate electrodes are arranged above and below the channel, since the channel area increases, the current value can be increased, or the depletion layer can be easily formed to reduce the S value. When gate electrodes are arranged above and below the channel, it has a configuration in which a plurality of transistors are connected in parallel. Also, a structure in which a gate electrode is arranged above the channel may be used, a structure in which a gate electrode is arranged below the channel may be used, a normal stagger structure may be used, an inverse stagger structure may be used, the channel region may be divided into a plurality of regions, may be connected in parallel, or may be connected in series. Also, a source electrode or a drain electrode may overlap with the channel (or a part thereof). By adopting a structure in which a source electrode or a drain electrode overlaps with the channel (or a part thereof), it is possible to prevent charge from accumulating in a part of the channel and making the operation unstable. Also, an LDD region may be provided. By providing an LDD region, the off-current can be reduced, the breakdown voltage of the transistor can be improved to enhance reliability, or when operating in the saturation region, even if the drain-source voltage changes, the drain-source current does not change much, enabling flat characteristics. region, even if the drain-source voltage changes, the drain-source current does not change much, enabling flat characteristics.

[0035] Note that transistors in the present invention can use various types and can be formed using various substrates. Therefore, all of the circuit may be formed on a glass substrate, may be formed on a plastic substrate, may be formed on a single crystal substrate, may be formed on an SOI substrate, or may be formed on any substrate. By forming all of the circuit on the same substrate, the number of components can be reduced to lower the cost, and the number of connection points with circuit components can be reduced to improve the reliability. Alternatively, a part of the circuit may be formed on one substrate and another part of the circuit may be formed on another substrate. That is, all of the circuit does not have to be formed on the same substrate. For example, a part of the circuit is formed on a glass substrate using a transistor, another part of the circuit is formed on a single crystal substrate, and the IC chip is connected by COG (Chip On Glass) and arranged on the glass substrate. Alternatively, the IC chip may be connected to the glass substrate using TAB (Tape Automated Bonding) or a printed circuit board. In this way, by forming a part of the circuit on the same substrate, the number of components can be reduced to lower the cost, and the number of connection points with circuit components can be reduced to improve the reliability. Moreover, in parts where the driving voltage is high or the driving frequency is high, the power consumption will increase. Therefore, if such parts are not formed on the same substrate, it is possible to prevent the power consumption from increasing. Note that in the present invention, one pixel indicates one element capable of controlling brightness. Therefore, as an example, one pixel indicates one color element, and with just one such color element

[0036] ​​​​​​​​​​​​​​​​represents brightness. Therefore, in the case of a color display device, the minimum unit of an image is assumed to be composed of three pixels: an R pixel, a G pixel, and a B pixel. Note that the color elements are not limited to three colors, and more colors can be used, or colors other than RGB can be added. For example, white can be added to form RGBW (W represents white). Also, one or more colors such as yellow, cyan, magenta, emerald green, vermilion, etc. can be added to RGB. Additionally, for at least one of the RGB colors, similar colors can be added. For example, it can be R, G, B1, B2. B1 and B2 are both blue but have slightly different frequencies. By using such color elements, a display closer to the real thing can be achieved, or power consumption can be reduced. As another example, when controlling brightness using multiple regions for one color element, one such region is considered one pixel. Therefore, in the case of performing area gradation, for one color element, there are multiple regions for controlling brightness, and the overall gradation is expressed. However, one such region for controlling brightness is considered one pixel. Therefore, in that case, one color element is composed of multiple pixels. Also, in that case, the size of the region contributing to the display may differ depending on the pixel. Further, in the case of multiple regions for controlling brightness for one color element, that is, in the multiple pixels constituting one color element, the signals supplied to each can be made slightly different to widen the viewing angle. Note that when referring to one pixel (for three colors), it is assumed that three pixels of R, G, and B are considered one pixel. When referring to one pixel (for one color), it is for one color element. In the case of a color display device, the minimum unit of an image is composed of three pixels: an R pixel, a G pixel, and a B pixel. Note that the color elements are not limited to three colors, and more colors can be used, or colors other than RGB can be added. For example, white can be added to form RGBW (W represents white). Also, one or more colors such as yellow, cyan, magenta, emerald green, vermilion, etc. can be added to RGB. Additionally, for at least one of the RGB colors, similar colors can be added. For example, it can be R, G, B1, B2. B1 and B2 are both blue but have slightly different frequencies. By using such color elements, a display closer to the real thing can be achieved, or power consumption can be reduced. As another example, when controlling brightness using multiple regions for one color element, one such region is considered one pixel. Therefore, in the case of performing area gradation, for one color element, there are multiple regions for controlling brightness, and the overall gradation is expressed. However, one such region for controlling brightness is considered one pixel. Therefore, in that case, one color element is composed of multiple pixels. Also, in that case, the size of the region contributing to the display may differ depending on the pixel. Further, in the case of multiple regions for controlling brightness for one color element, that is, in the multiple pixels constituting one color element, the signals supplied to each can be made slightly different to widen the viewing angle. Note that when referring to one pixel (for three colors), it is assumed that three pixels of R, G, and B are considered one pixel. When referring to one pixel (for one color), it is for one color element. Note that when referring to one pixel (for three colors), it is assumed that three pixels of R, G, and B are considered one pixel. When referring to one pixel (for one color), it is for one color element. When referring to one pixel (for one color), it is for one color element. Therefore, when there are a plurality of pixels, they are considered as one pixel.

[0037] In the present invention, the pixels may be arranged (distributed) in a matrix. Here, the pixels being arranged (distributed) in a matrix form means that the pixels are arranged vertically or horizontally. In this case, the number of pixels may be increased or decreased. Therefore, for example, when performing full-color display using three color elements (e.g., RGB), , in stripe arrangement, or in the so-called delta arrangement of three color element dots This also includes the case where the image sensor is arranged in a Bayer pattern. The color elements are not limited to three colors, but may be more than three. For example, RGBW (W is white) or RG B plus one or more colors such as yellow, cyan, magenta, etc. The size of the display area may be different for each pixel. This reduces power consumption. It is possible to reduce the display quality or extend the life of the display element.

[0038] The transistors each include at least a gate, a drain, and a source. A device with three terminals, a channel region between the drain region and the source region, A current can flow through the drain region, the channel region, and the source region. Here, the source and drain vary depending on the transistor structure and operating conditions, so It is difficult to determine which is the source and which is the drain. In this case, the regions that function as source and drain are called source and drain. In that case, for example, they may be written as the first terminal and the second terminal. There is.

[0039] Note that the transistor may be an element having at least three terminals including a base, an emitter, and a collector. Similarly, in this case, the emitter and the collector may be referred to as the first terminal and the second terminal. There is. In some cases, the emitter and the collector may be denoted as the first terminal and the second terminal.

[0040] Note that the gate refers to the whole including a gate electrode and a gate wiring (also referred to as a gate line or a gate signal line, etc.), or a part of them. The gate electrode refers to a conductive film of a part overlapping with a semiconductor forming a channel region or an LDD (Lightly Doped Drain) region, etc. via a gate insulating film. The gate wiring refers to a wiring for connecting between gate electrodes of each pixel or for connecting a gate electrode and another wiring. Note that the gate refers to the whole including a gate electrode and a gate wiring (also referred to as a gate line or a gate signal line, etc.), or a part of them. The gate electrode refers to a conductive film of a part overlapping with a semiconductor forming a channel region or an LDD (Lightly Doped Drain) region, etc. via a gate insulating film. The gate wiring refers to a wiring for connecting between gate electrodes of each pixel or for connecting a gate electrode and another wiring. Note that the gate refers to the whole including a gate electrode and a gate wiring (also referred to as a gate line or a gate signal line, etc.), or a part of them. The gate electrode refers to a conductive film of a part overlapping with a semiconductor forming a channel region or an LDD (Lightly Doped Drain) region, etc. via a gate insulating film. The gate wiring refers to a wiring for connecting between gate electrodes of each pixel or for connecting a gate electrode and another wiring. Note that the gate refers to the whole including a gate electrode and a gate wiring (also referred to as a gate line or a gate signal line, etc.), or a part of them. The gate electrode refers to a conductive film of a part overlapping with a semiconductor forming a channel region or an LDD (Lightly Doped Drain) region, etc. via a gate insulating film. The gate wiring refers to a wiring for connecting between gate electrodes of each pixel or for connecting a gate electrode and another wiring. Note that the gate refers to the whole including a gate electrode and a gate wiring (also referred to as a gate line or a gate signal line, etc.), or a part of them. The gate electrode refers to a conductive film of a part overlapping with a semiconductor forming a channel region or an LDD (Lightly Doped Drain) region, etc. via a gate insulating film. The gate wiring refers to a wiring for connecting between gate electrodes of each pixel or for connecting a gate electrode and another wiring. Note that the gate refers to the whole including a gate electrode and a gate wiring (also referred to as a gate line or a gate signal line, etc.), or a part of them. The gate electrode refers to a conductive film of a part overlapping with a semiconductor forming a channel region or an LDD (Lightly Doped Drain) region, etc. via a gate insulating film. The gate wiring refers to a wiring for connecting between gate electrodes of each pixel or for connecting a gate electrode and another wiring.

[0041] However, there is also a part that functions as both a gate electrode and a gate wiring. Such a region may be called a gate electrode or a gate wiring. That is, there is also a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when there is a channel region overlapping with a gate wiring arranged in an extended manner, that region functions as a gate wiring but also functions as a gate electrode. Therefore, such a region may be called a gate electrode or a gate wiring. However, there is also a part that functions as both a gate electrode and a gate wiring. Such a region may be called a gate electrode or a gate wiring. That is, there is also a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when there is a channel region overlapping with a gate wiring arranged in an extended manner, that region functions as a gate wiring but also functions as a gate electrode. Therefore, such a region may be called a gate electrode or a gate wiring. However, there is also a part that functions as both a gate electrode and a gate wiring. Such a region may be called a gate electrode or a gate wiring. That is, there is also a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when there is a channel region overlapping with a gate wiring arranged in an extended manner, that region functions as a gate wiring but also functions as a gate electrode. Therefore, such a region may be called a gate electrode or a gate wiring. However, there is also a part that functions as both a gate electrode and a gate wiring. Such a region may be called a gate electrode or a gate wiring. That is, there is also a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when there is a channel region overlapping with a gate wiring arranged in an extended manner, that region functions as a gate wiring but also functions as a gate electrode. Therefore, such a region may be called a gate electrode or a gate wiring. However, there is also a part that functions as both a gate electrode and a gate wiring. Such a region may be called a gate electrode or a gate wiring. That is, there is also a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when there is a channel region overlapping with a gate wiring arranged in an extended manner, that region functions as a gate wiring but also functions as a gate electrode. Therefore, such a region may be called a gate electrode or a gate wiring. However, there is also a part that functions as both a gate electrode and a gate wiring. Such a region may be called a gate electrode or a gate wiring. That is, there is also a region where the gate electrode and the gate wiring cannot be clearly distinguished. For example, when there is a channel region overlapping with a gate wiring arranged in an extended manner, that region functions as a gate wiring but also functions as a gate electrode. Therefore, such a region may be called a gate electrode or a gate wiring.

[0042] Also, a region formed of the same material as the gate electrode and connected to the gate electrode may also be called a gate electrode. Similarly, a region formed of the same material as the gate wiring and connected to the gate wiring Also, a region formed of the same material as the gate electrode and connected to the gate electrode may also be called a gate electrode. Similarly, a region formed of the same material as the gate wiring and connected to the gate wiring The area where the gate is connected may also be called the gate wiring. It does not overlap with the region or has a function to connect with another gate electrode. However, due to manufacturing conditions, etc., There are regions formed of materials and connected to gate electrodes and gate wiring. Such a region may also be called a gate electrode or a gate wiring.

[0043] For example, in a multi-gate transistor, the gate electrode of one transistor The gate electrode of the other transistor is connected to the gate electrode of the other transistor by a conductive film made of the same material as the gate electrode. Such a region is often used for connecting the gate electrodes. Since it is a single gate wiring, it can be called a gate wiring. Since it can be considered as a transistor, it can be called a gate electrode. Those that are made of the same material as the gate electrodes and gate wiring and are connected to them are They may be called gate electrodes or gate wiring. For example, the gate electrodes and gate wiring are connected The conductive film of the connected portion may be called a gate electrode or a gate wiring. .

[0044] The gate terminal is a region of the gate electrode or a region electrically connected to the gate electrode. This article refers to a part of the above.

[0045] The source is a combination of a source region, a source electrode, and a source wiring (a source line or a source signal line). The source region refers to the whole or part of the source region. Semiconductors that contain a large amount of P-type impurities (such as boron and gallium) or N-type impurities (such as phosphorus and arsenic). This refers to the conductor region. Therefore, a region containing a small amount of P-type or N-type impurities, also known as the so-called LDD (Lightly Doped Drain) region, is not included in the source region. The source electrode is formed of a material different from the source region and is electrically connected to the source region and is a conductive layer of the arranged part. However, the source electrode may sometimes be called the source electrode including the source region. The source wiring refers to the wiring for connecting between the source electrodes of each pixel or for connecting the source electrode to another wiring. However, there also exists a part that functions as both a source electrode and a source wiring. Such a region may be called a source electrode or a source wiring. That is, there also exists a region where the source electrode and the source wiring cannot be clearly distinguished. For example, when there is a source region overlapping with the extended source wiring, that region functions as a source wiring but also functions as a source electrode. Therefore, such a region may be called a source electrode or a source wiring.

[0046] In addition, a region formed of the same material as the source electrode and connected to the source electrode, or a part connecting the source electrode to the source electrode, may also be called a source electrode. Also, a part overlapping with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected to the source wiring may also be called a source wiring. Such a region, strictly speaking, may have a function of connecting to another source electrode. However, there also exists a part that functions as both a source electrode and a source wiring. Such a region may be called a source electrode or a source wiring. That is, there also exists a region where the source electrode and the source wiring cannot be clearly distinguished. For example, when there is a source region overlapping with the extended source wiring, that region functions as a source wiring but also functions as a source electrode. Therefore, such a region may be called a source electrode or a source wiring. region functions as a source wiring but also functions as a source electrode. Therefore, such a region may be called a source electrode or a source wiring. Therefore, such a region may be called a source electrode or a source wiring.

[0047] Also, a region formed of the same material as the source electrode and connected to the source electrode, or a part connecting the source electrode to the source electrode, may also be called a source electrode. Also, a part overlapping with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected to the source wiring may also be called a source wiring. Such a region, strictly speaking, may have a function of connecting to another source electrode. In addition, a region formed of the same material as the source electrode and connected to the source electrode, or a part connecting the source electrode to the source electrode, may also be called a source electrode. Also, a part overlapping with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected to the source wiring may also be called a source wiring. Such a region, strictly speaking, may have a function of connecting to another source electrode. In addition, a region formed of the same material as the source electrode and connected to the source electrode, or a part connecting the source electrode to the source electrode, may also be called a source electrode. Also, a part overlapping with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected to the source wiring may also be called a source wiring. Such a region, strictly speaking, may have a function of connecting to another source electrode. In addition, a region formed of the same material as the source electrode and connected to the source electrode, or a part connecting the source electrode to the source electrode, may also be called a source electrode. Also, a part overlapping with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected to the source wiring may also be called a source wiring. Such a region, strictly speaking, may have a function of connecting to another source electrode. In addition, a region formed of the same material as the source electrode and connected to the source electrode, or a part connecting the source electrode to the source electrode, may also be called a source electrode. Also, a part overlapping with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected to the source wiring may also be called a source wiring. Such a region, strictly speaking, may have a function of connecting to another source electrode. ​There may be cases where it does not exist. However, due to relationships such as manufacturing conditions, there is a region formed of the same material as the source electrode or source wiring and connected to the source electrode or source wiring. Therefore, such a region may also be referred to as the source electrode or source wiring. Moreover, for example, the conductive film at the portion connecting the source electrode and the source wiring may also be referred to as the source electrode or the source wiring. Note that the source terminal refers to a part of the source region, source electrode, or region electrically connected to the source electrode.

[0048] Also, for example, the conductive film at the portion connecting the source electrode and the source wiring may be called the source electrode or the source wiring. Note that regarding the drain, it is the same as the source.

[0049] In the present invention, a semiconductor device refers to a device having a circuit including semiconductor elements (such as transistors and diodes). It may also refer to all devices that can function by utilizing semiconductor characteristics. Note that a display device refers to a device having display elements (such as liquid crystal elements and light-emitting elements). It may also refer to the display panel main body on which a plurality of pixels including display elements such as liquid crystal elements and EL elements and peripheral drive circuits for driving these pixels are formed on the same substrate. It may also include peripheral drive circuits arranged on the substrate by wire bonding or bumps, so-called chip-on-glass (COG). Furthermore, it may also include those to which a flexible printed circuit (FPC) or a printed wiring board (PWB) is attached (such as ICs, resistance elements, capacitance elements, inductors, and transistors). Furthermore, it may also include optical elements such as polarizing plates and retardation plates.

[0050] Note that regarding the drain, it is the same as the source.

[0051] In the present invention, a semiconductor device refers to a device having a circuit including semiconductor elements (such as transistors and diodes). It may also refer to all devices that can function by utilizing semiconductor characteristics. Also, a display device refers to a device having display elements (such as liquid crystal elements and light-emitting elements). Note that it may also refer to the display panel main body on which a plurality of pixels including display elements such as liquid crystal elements and EL elements and peripheral drive circuits for driving these pixels are formed on the same substrate. It may also include peripheral drive circuits arranged on the substrate by wire bonding or bumps, so-called chip-on-glass (COG). Furthermore, it may also include those to which a flexible printed circuit (FPC) or a printed wiring board (PWB) is attached (such as ICs, resistance elements, capacitance elements, inductors, and transistors). Furthermore, it may also include optical elements such as polarizing plates and retardation plates. Note that a display device refers to a device having display elements (such as liquid crystal elements and light-emitting elements). It may also refer to the display panel main body on which a plurality of pixels including display elements such as liquid crystal elements and EL elements and peripheral drive circuits for driving these pixels are formed on the same substrate. It may also include peripheral drive circuits arranged on the substrate by wire bonding or bumps, so-called chip-on-glass (COG). Furthermore, it may also include those to which a flexible printed circuit (FPC) or a printed wiring board (PWB) is attached (such as ICs, resistance elements, capacitance elements, inductors, and transistors). Furthermore, it may also include optical elements such as polarizing plates and retardation plates.

[0052] Also, a display device refers to a device having display elements (such as liquid crystal elements and light-emitting elements). Note that it may also refer to the display panel main body on which a plurality of pixels including display elements such as liquid crystal elements and EL elements and peripheral drive circuits for driving these pixels are formed on the same substrate. It may also include peripheral drive circuits arranged on the substrate by wire bonding or bumps, so-called chip-on-glass (COG). Furthermore, it may also include those to which a flexible printed circuit (FPC) or a printed wiring board (PWB) is attached (such as ICs, resistance elements, capacitance elements, inductors, and transistors). Furthermore, it may also include optical elements such as polarizing plates and retardation plates. Moreover, for example, the conductive film at the portion connecting the source electrode and the source wiring may be called the source electrode or the source wiring. Note that the source terminal refers to a part of the source region, source electrode, or region electrically connected to the source electrode. In the present invention, a semiconductor device refers to a device having a circuit including semiconductor elements (such as transistors and diodes). It may also refer to all devices that can function by utilizing semiconductor characteristics. Also, a display device refers to a device having display elements (such as liquid crystal elements and light-emitting elements). Note that it may also refer to the display panel main body on which a plurality of pixels including display elements such as liquid crystal elements and EL elements and peripheral drive circuits for driving these pixels are formed on the same substrate. It may also include peripheral drive circuits arranged on the substrate by wire bonding or bumps, so-called chip-on-glass (COG). Furthermore, it may also include those to which a flexible printed circuit (FPC) or a printed wiring board (PWB) is attached (such as ICs, resistance elements, capacitance elements, inductors, and transistors). Furthermore, it may also include optical elements such as polarizing plates and retardation plates. Note that regarding the drain, it is the same as the source. It may include a learning sheet. Further, it may include a backlight unit (such as a light guide plate, a prism sheet , a diffusion sheet, a reflection sheet, and a light source (such as an LED or a cold cathode tube)).

[0053] In addition, a light-emitting device refers to a display device having a self-luminous display element such as an EL element or an element used in an FED. A liquid crystal display device refers to a display device having a liquid crystal element.

[0054] In the present invention, descriptions such as formed on a certain object or formed on ~ are not limited to being directly in contact with a certain object. When not in direct contact, that is, when another object is sandwiched in between, it is also included. Therefore, for example, when layer B is formed on (or on) layer A, it includes the case where layer B is directly formed on layer A and the case where another layer (such as layer C or layer D) is directly formed on layer A and layer B is directly formed on it. Similarly, descriptions such as above ~ are not limited to being directly in contact with a certain object and also include the case where another object is sandwiched in between. Therefore, for example, when layer B is formed above layer A, it includes the case where layer B is directly formed on layer A and the case where another layer (such as layer C or layer D) is directly formed on layer A and layer B is directly formed on it. Regarding descriptions such as below ~ or beneath ~, it is the same and includes both the case of being in direct contact and the case of not being in direct contact. .

Advantages of the Invention

[0055] By using the present invention, a flip-flop using a driving method for suppressing characteristic deterioration of a transistor, a flip-flop circuit, a shift register, a semiconductor device including such a shift register, a display device, and an electronic apparatus including the display device can be provided.

[0056] For example, when the present invention is applied to a shift register, during a non-selection period, since a transistor that supplies a power supply potential to an output terminal is not always in an on state, characteristic deterioration (for example, a shift of a threshold voltage) of the transistor can be suppressed. Therefore, malfunction of the shift register due to characteristic deterioration of the transistor can be suppressed.

[0057] Further, by using the present invention, a flip-flop circuit having a control circuit with a relatively small circuit scale, a shift register, a semiconductor device including such a shift register, and a display device, and an electronic apparatus including the display device can be provided.

Brief Description of the Drawings

[0058]

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Embodiments for Carrying Out the Invention

[0059] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and it will be easily understood by those skilled in the art that the forms and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, it should not be construed as being limited to the content described in this embodiment.

[0060] (First Embodiment) In this embodiment, the basic principle of the present invention will be described with reference to FIG. 1(a).

[0061] FIG. 1(a) is a basic circuit based on the basic principle of the present invention. The basic circuit of FIG. 1(a) includes transistor 101, transistor 102, transistor 103, and transistor 104 and has them.

[0062] The connection relationship of the basic circuit in FIG. 1(a) will be described. The gate of transistor 101 is connected to wiring 105, the first terminal is connected to wiring 105, and the second terminal is connected to the gate of transistor 104. The gate of transistor 102 is connected to wiring 107, the first terminal is connected to wiring 106, and the second terminal is connected to the gate of transistor 104. The gate of transistor 103 is connected to wiring 108, the first terminal is connected to wiring 106 , and the second terminal is connected to the gate of transistor 104. The first terminal of transistor 104 is connected to wiring 106, and the second terminal is connected to wiring 109. Note that the second terminal of transistor 101, the second terminal of transistor 102, the second terminal of transistor 103 and the node between the gate of transistor 104 is defined as node N11.

[0063] Also, transistors 101 to 104 are each of N-channel type.

[0064] Therefore, since the basic circuit of FIG. 1(a) can be entirely composed of N-channel type transistors, the basic circuit of FIG. 1(a) can use amorphous silicon for the semiconductor layer , and the manufacturing process can be simplified. Therefore, the manufacturing cost can be reduced and the yield It is possible to improve [the relevant performance]. Furthermore, it is also possible to fabricate semiconductor devices such as large display panels. Also, for the basic circuit in Fig. 1(a), the manufacturing process can be simplified by using polysilicon or single-crystal silicon in the semiconductor layer.

[0065] In addition, a power supply potential VDD is supplied to wiring 105, and a power supply potential VSS is supplied to wiring 106. Note that the power supply potential VDD is at a higher potential than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to wiring 105 and wiring 106, or other power supply potentials may be supplied.

[0066] Moreover, signals are supplied to wiring 107 and wiring 108 respectively. Note that the signals supplied to wiring 107 and wiring 108 are digital signals with binary values. When this digital signal is an H signal, it has the same potential as the power supply potential VDD (hereinafter also referred to as potential VDD or H level), and when it is an L signal, it has the same potential as the power supply potential VSS (hereinafter also referred to as potential VSS or L level). However, power supply potential VDD, power supply potential VSS, or other power supply potentials may be supplied to wiring 107 and wiring 108 respectively. Moreover, analog signals may be supplied to wiring 107 and wiring 108 respectively.

[0067] Next, the operation of the basic circuit shown in Fig. 1(a) will be described with reference to Fig. 1(b).

[0068] Fig. 1(b) is an example of the timing chart of the basic circuit shown in Fig. 1(a). The timing chart in Fig. 1(b) shows the potential of wiring 107, the potential of wiring 108, and the potential of node N11. ​​​​​​​shows the potential of wiring 109 and the on / off state of transistor 104.

[0069] The timing chart in Fig. 1(b) will be described by dividing it into periods T1 to T4. Also, Fig. 2 (a), Fig. 2(b), Fig. 3(a), and Fig. 3(b) show the operations of the basic circuit in Fig. 1(a) during periods T1, T2, T3, and period T4.

[0070] First, the operation in period T1 will be described with reference to Fig. 2(a). In period T1, an L signal is supplied to wiring 10 7 and an L signal is supplied to wiring 108. Therefore, transistor 10 2 is turned off and transistor 103 is turned off.

[0071] Also, since transistor 101 is diode-connected, the potential at node N11 starts to rise This rise in the potential at node N11 continues until transistor 101 turns off. Transistor 10 1 turns off when the potential at node N11 reaches a value (VDD - Vth101) obtained by subtracting the threshold voltage Vth101 of transistor 101 from the power supply potential VDD. Thus, the potential at node N11 becomes VDD - Vth101. Therefore, transistor 104 turns on and the potential of wiring 109 becomes equal to the power supply potential VSS

[0072] at a certain value.

[0073] Subsequently, the operation in period T2 will be described with reference to Fig. 2(b). In period T2, an H signal is supplied to wiring 1 07 and an L signal is supplied to wiring 108. Therefore, transistor 10 2 turns on and transistor 103 is turned off.

[0074] Also, the potential of node N11 is determined by the operating points of transistor 101 and transistor 102. Note that if the W / L ratio of transistor 102 (where W is the channel width of the channel region and L is the channel length of the channel region) is made sufficiently larger than the W / L ratio of transistor 101, the potential of node N11 will be a value slightly higher than the power supply potential VSS. Accordingly, transistor 104 turns off and wiring 109 becomes in a floating state. The potential of wiring 109 remains equal to the power supply potential VSS in order to maintain the potential during period T1. Next, the operation during period T3 will be described with reference to Fig. 3(a). During period T3, an L signal is supplied to wiring 107 and an H signal is supplied to wiring 108. Accordingly, transistor 102 turns off and transistor 103 turns on. Also, the potential of node N11 is determined by the operating points of transistor 101 and transistor 103. Note that if the W / L ratio of transistor 103 is made sufficiently larger than the W / L ratio of transistor 101, the potential of node N11 will be a value slightly higher than the power supply potential VSS.

[0075] Accordingly, transistor 104 turns off and wiring 109 becomes in a floating state. The potential of wiring 109 remains equal to the power supply potential VSS in order to maintain the potential during period T1 and period T2. Subsequently, the operation during period T4 will be described with reference to Fig. 3(b). During period T4, the potential of wiring 109 remains equal to the power supply potential VSS in order to maintain the potential during period T1, period T2, and period T3.

[0076] Subsequently, the operation during period T3 will be described with reference to Fig. 3(a). During period T3, an L signal is supplied to wiring 107 and an H signal is supplied to wiring 108. Accordingly, transistor 102 turns off and transistor 103 turns on. Also, the potential of node N11 is determined by the operating points of transistor 101 and transistor 103. Note that if the W / L ratio of transistor 103 is made sufficiently larger than the W / L ratio of transistor 101, the potential of node N11 will be a value slightly higher than the power supply potential VSS. Accordingly, transistor 104 turns off and wiring 109 becomes in a floating state. The potential of wiring 109 remains equal to the power supply potential VSS in order to maintain the potential during period T1 and period T2.

[0077] Also, the potential of node N11 is determined by the operating points of transistor 101 and transistor 103. Note that if the W / L ratio of transistor 103 is made sufficiently larger than the W / L ratio of transistor 101, the potential of node N11 will be a value slightly higher than the power supply potential VSS. Accordingly, transistor 104 turns off and wiring 109 becomes in a floating state. The potential of wiring 109 remains equal to the power supply potential VSS in order to maintain the potential during period T1, period T2, and period T3. Subsequently, the operation during period T4 will be described with reference to Fig. 3(b). During period T4, the potential of wiring 109 remains equal to the power supply potential VSS in order to maintain the potential during period T1, period T2, and period T3.

[0078] Accordingly, transistor 104 turns off and wiring 109 becomes in a floating state. The potential of wiring 109 remains equal to the power supply potential VSS in order to maintain the potential during period T1 and period T2. Subsequently, the operation during period T4 will be described with reference to Fig. 3(b). During period T4, the potential of wiring 109 remains equal to the power supply potential VSS in order to maintain the potential during period T1, period T2, and period T3.

[0079] Subsequently, the operation during period T4 will be described with reference to Fig. 3(b). During period T4, The H signal is supplied to 07, and the H signal is supplied to the wiring 108. Therefore, the trans istor 102 is turned on, and the transistor 104 is turned on.

[0080] Also, since the potential of the node N11 is determined by the operating points of the transistors 101, 102, and 1 03, the potential of the node N11 becomes a value slightly higher than the power supply potential VSS.

[0081] Therefore, the transistor 104 is turned off, and the wiring 109 is in a floating state. To maintain the potential of the wiring 109 at the potential during the periods T1, T2, and T3, it remains equal to the power supply potential VSS.

[0082] By the above operation, in the period T1, the basic circuit in Fig. 1(a) supplies the power supply potential VS S to the wiring 109 and makes the potential of the wiring 109 equal to the power supply potential VSS. In the periods T2 to T4, the basic circuit in Fig. 1(a) puts the wiring 109 in a floating state and maintains the potential of the wiring 109 at a value equal to the power supply potential VSS.

[0083] Also, the basic circuit in Fig. 1(a) does not have a transistor that is on in all the periods from T1 to T4. That is, it does not have a transistor that is constantly or almost constantly on. Therefore, the basic circuit in Fig. 1(a) can suppress the characteristic degradation of the transistor and the shift of the threshold voltage due to the characteristic degradation.

[0084] Also, the characteristics of the transistor are likely to deteriorate when the transistor is formed of amorphous silicon. Therefore, the basic circuit in Fig. 1(a) uses amorphous By forming it with silicon, not only can advantages such as reduction of manufacturing cost and improvement of yield be obtained, but also the problem of characteristic degradation of the transistor can be solved.

[0085] Here, the functions of transistors 101 to 104 will be described. Transistor 10 1 has a function as a diode having an input terminal as a first terminal and a gate, and an output terminal as a second terminal. Transistor 102 has a function as a switch that selects whether to connect wiring 106 and node N11 according to the potential of wiring 107. Transistor 103 has a function as a switch that selects whether to connect wiring 106 and node N11 according to the potential of wiring 108. Transistor 104 has a function as a switch that selects whether to connect wiring 106 and wiring 109 according to the potential of node N11.

[0086] Note that transistor 101 may be an element having a resistance component. For example, as shown in Fig. 4(a), a resistance element 401 can be used instead of transistor 101. By using the resistance element 401, the potential of node N11 can be made equal to the power supply potential VDD during period T1. Also, the timing chart of Fig. 4(a) is shown in Fig. 4(b).

[0087] Next, the case where the basic circuit shown in Fig. 1(a) is composed of P-channel type transistors will be described with reference to Fig. 13(a).

[0088] Fig. 13(a) is a basic circuit based on the basic principle of the present invention. The basic circuit of Fig. 13(a) is composed of transistor 1301, transistor 1302, transistor 1303, and transistor It has Sta 1304.

[0089] The connection relationship of the basic circuit in Fig. 13(a) will be described. The gate of transistor 1301 is connected to wiring 1306, the first terminal is connected to wiring 1306, and the second terminal is connected to the gate of transistor 1304. The gate of transistor 1302 is connected to wiring 1307, the first terminal is connected to wiring 1305, and the second terminal is connected to the gate of transistor 1304 The gate of transistor 1303 is connected to wiring 1308, and the first terminal is connected to wiring 1305, and the second terminal is connected to the gate of transistor 1304. The first terminal of transistor 1304 is connected to wiring 1305, and the second terminal is connected to wiring 1309 Note that the node between the second terminal of transistor 1301, the second terminal of transistor 1302, the second terminal of transistor 1303, and the gate of transistor 1304 is node N131.

[0090] Also, transistors 1301 to 1304 are each of P-channel type.

[0091] Therefore, the basic circuit in Fig. 13(a) can all be composed of P-channel type transistors, so no process is required to form an N-channel type transistor. Therefore, the basic circuit in Fig. 13(a) can simplify the manufacturing process, reduce the manufacturing cost, and improve the yield.

[0092] Also, the power supply potential VDD is supplied to wiring 1305, and the power supply potential VSS is supplied to wiring 1306.

[0093] Also, signals are supplied to wiring 1307 and wiring 1308 respectively. Note that the signals supplied to wiring 1307 and wiring 1308 are digital signals each having a binary value.

[0094] Next, the operation of the basic circuit shown in Fig. 13(a) will be described with reference to Fig. 13(b).

[0095] Fig. 13(b) is an example of a timing chart of the basic circuit shown in Fig. 13(a). The timing chart in Fig. 13(b) shows the potential of wiring 1307, the potential of wiring 1308, the potential of node N131, the potential of wiring 1309, and the on / off state of transistor 1304.

[0096] The timing chart in Fig. 13(b) will be described by dividing it into periods T1 to T4. Also, Fig. 14(a), Fig. 14(b), Fig. 15(a), and Fig. 15(b) show the operations of the basic circuit in Fig. 13(a) in periods T1, T2,

[0097] First, the operation in period T1 will be described with reference to Fig. 14(a). In period T1, an H signal is supplied to wiring 1307 and an H signal is supplied to wiring 1308. Therefore, transistor 1302 is turned off and transistor 1303 is turned off.

[0098] Also, since transistor 1301 is diode-connected, the potential of node N131 starts to decrease. This decrease in the potential of node N131 continues until transistor 1301 is turned off. Transistor 1301 turns off when the potential of node N131 reaches the sum (VSS + |Vth1301|) of the power supply potential VSS and the absolute value of the Therefore, the potential of the node N131 becomes VSS+|Vth1301|.

[0099] Therefore, the transistor 1304 is turned on, and the potential of the wiring 1309 becomes the power supply potential VDD. will be equal in value.

[0100] Next, the operation during the period T2 will be described with reference to FIG. An L signal is supplied to the wiring 1307, and an H signal is supplied to the wiring 1308. Transistor 1302 is on and transistor 1303 is off.

[0101] The potential of the node N131 is the operating point of the transistors 1301 and 1302. The W / L ratio of the transistor 1302 (W is the channel area The width of the channel region and L is the channel length of the channel region are set to be much larger than the W / L ratio of the transistor 1301. If you increase the voltage by this amount, the potential of node N131 will be slightly lower than the power supply potential VDD. .

[0102] Therefore, the transistor 1304 is turned off and the wiring 1309 is floating. In order to maintain the potential of the wiring 1309 during the period T1, the power supply potential V It remains equal to DD.

[0103] Next, the operation during the period T3 will be described with reference to FIG. An H signal is supplied to the wiring 1307, and an L signal is supplied to the wiring 1308. The transistor 1302 is turned off and the transistor 1303 is turned on.

[0104] The potential of the node N131 is the operating point of the transistors 1301 and 1303. It is determined by If the W / L ratio of transistor 1303 is made sufficiently larger than the W / L ratio of transistor 1301, the potential of node N131 will be a value slightly lower than the power supply potential VDD.

[0105] Accordingly, transistor 1304 turns off and wiring 1309 becomes floating. The potential of wiring 1309 remains equal to the power supply potential VDD in order to maintain the potential during periods T1 and T2.

[0106] Subsequently, the operation during period T4 will be described with reference to FIG. 15(b). During period T4, an L signal is supplied to wiring 1307 and an L signal is supplied to wiring 1308. Accordingly, transistor 1302 turns on and transistor 1304 is on.

[0107] Also, since the potential of node N131 is determined by the operating points of transistors 1301, 1302, and 1303, the potential of node N131 will be a value slightly lower than the power supply potential VDD.

[0108] Accordingly, transistor 1304 turns off and wiring 1309 becomes floating. The potential of wiring 1309 remains equal to the power supply potential VDD in order to maintain the potential during periods T1, T2, and T3.

[0109] By the above operation, in period T1, the basic circuit in FIG. 13(a) supplies the power supply potential VDD to wiring 1309 and makes the potential of wiring 1309 equal to the power supply potential VDD. In periods T2 to T4, the basic circuit in FIG. 13(a) makes wiring 1309 in a floating state and Maintain the potential of 309 at a value equal to the power supply potential VDD.

[0110] Also, the basic circuit in Fig. 13(a) does not have a transistor that is in the on state during all of periods T1 to T4. That is, it does not have a transistor that is constantly or almost constantly in the on state. Therefore, the basic circuit in Fig. 13(a) can suppress the deterioration of the transistor characteristics and the shift of the threshold voltage due to the deterioration of the characteristics.

[0111] Note that transistors 1301 to 1304 have the same functions as transistors 101 to transistor 104.

[0112] Note that transistor 1301 may be an element having a resistance component. For example, as shown in Fig. 16(a ), a resistance element 1601 can be used in place of transistor 1301. By using the resistance element 1601, the potential of node N131 can be set to a value equal to the power supply potential VSS in period T1. Also, the timing chart of Fig. 16(a) is shown in Fig. 16(b).

[0113] Note that this embodiment can be freely combined with any description of other embodiments in this specification and implemented. Also, any description in this embodiment can be freely combined and implemented .

[0114] (Second Embodiment) In this embodiment, the basic principle of the present invention different from the first embodiment will be described with reference to Fig. 5(a).

[0115] Fig. 5(a) is a basic circuit based on the basic principle of the present invention. The basic circuit in Fig. 5(a) is a transistor It has transistor 501, transistor 502, transistor 503, transistor 504, and transistor 505, transistor 506, and transistor 507.

[0116] The connection relationship of the basic circuit in Fig. 5(a) will be described. The gate of transistor 501 is connected to wiring 508, the first terminal is connected to wiring 508, and the second terminal is connected to the gate of transistor 504. The gate of transistor 502 is connected to wiring 510, and the first end is connected to wiring 509, and the second terminal is connected to the gate of transistor 504. The gate of transistor 503 is connected to wiring 511, the first terminal is connected to wiring 509 , and the second terminal is connected to the gate of transistor 504. Note that the second terminal of transistor 501 , the second terminal of transistor 502, the second terminal of transistor 503, and the gate of transistor 504 are defined as node N51. The first terminal of transistor 504 is connected to wiring 508, and the second terminal is connected to the gate of transistor 507. The gate of transistor 505 is connected to wiring 510, the first terminal is connected to wiring 509, and the second end is connected to the gate of transistor 507. The gate of transistor 506 is connected to wiring 511, the first terminal is connected to wiring 509, and the second terminal is connected to the gate of transistor 507. The first terminal of transistor 507 is connected to wiring 509, and the second terminal is connected to wiring 512. Note that the second terminal of transistor 504, the second terminal of transistor 505 , the second terminal of transistor 506, and the gate of transistor 507 are defined as node N52.

[0117] Also, transistors 501 to 507 are each of N-channel type.

[0118] Therefore, since all the basic circuits in Fig. 5(a) can be composed of N-channel type transistors, the basic circuit in Fig. 5(a) can use amorphous silicon for the semiconductor layer, which enables simplification of the manufacturing process. Thus, reduction of manufacturing cost and improvement of yield can be achieved. Furthermore, it becomes possible to fabricate semiconductor devices such as large display panels. Also, for the basic circuit in Fig. 5(a), simplification of the manufacturing process can be achieved even when using polysilicon or single crystal silicon for the semiconductor layer.

[0119] Also, a power supply potential VDD is supplied to wiring 508, and a power supply potential VSS is supplied to wiring 509. Note that the power supply potential VDD is at a higher potential than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to wiring 508 and wiring 509, or other power supply potentials may be supplied.

[0120] Also, signals are supplied to wiring 510 and wiring 511, respectively. Note that the signals supplied to wiring 510 and wiring 511 are digital signals each having a binary value. This digital signal becomes the same potential as the power supply potential VDD (hereinafter also referred to as potential VDD or H level) when it is an H signal, and becomes the same potential as the power supply potential VSS (hereinafter also referred to as potential VSS or L level) when it is an L signal. However, power supply potential VDD, power supply potential VSS, or other power supply potentials may be supplied to wiring 510 and wiring 511, respectively. Also, analog signals may be supplied to wiring 510 and wiring 511, respectively. ​​​​​​​​​​​​​

[0121] Next, the operation of the basic circuit shown in Fig. 5(a) will be described with reference to Fig. 5(b).

[0122] Fig. 5(b) is an example of a timing chart of the basic circuit shown in Fig. 5(a). Fig. 5( b)'s timing chart shows the potential of wiring 510, the potential of wiring 511, the potential of node N51 , the potential of node N52, the potential of wiring 512, and the on / off state of transistor 507 .

[0123] The timing chart of Fig. 5(b) will be divided into periods T1 to T4 for explanation. Also, Fig. 6 (a), Fig. 6(b), Fig. 7(a), and Fig. 7(b) show the operation of the basic circuit of Fig. 5(a) in periods T1, T2, T3, and period T4.

[0124] First, the operation in period T1 will be described with reference to Fig. 6(a). In period T1, an L signal is supplied to wiring 51 0, and transistors 502 and 505 are off. Also, an L signal is supplied to wiring 511, and transistors 503 and 506 are off.

[0125] Also, since transistor 501 is diode-connected, the potential of node N51 starts to rise . When the potential of node N51 reaches the value (VDD - Vth501) obtained by subtracting the threshold voltage V th501 of transistor 501 from the power supply potential VDD, transistor 501 turns off . Therefore, node N51 becomes a floating state.

[0126] At this time, transistor 504 is on, and the potential of node N52 is also rising. Thus Thus, the potential of the floating node N51 rises together with the potential of node N52 due to the parasitic capacitance between the gate (node N51) and the second terminal (node N52) of transistor 504. This rise in the potential of node N51 continues until the rise in the potential of node N52 stops, and the potential of node N51 becomes equal to or higher than the sum of the power supply potential VDD and the threshold voltage Vt of transistor 504 (VDD + Vth504). That is, the rise in the potential of node N51 continues until the potential of node N52 becomes equal to the power supply potential VDD. The so-called bootstrap operation can make the potential of node N52 equal to the power supply potential VDD. Accordingly, transistor 507 turns on, and the potential of wiring 509 becomes equal to the power supply potential VSS. Here, by making the potential of node N52 equal to the power supply potential VDD, the potential difference between the gate and the source of transistor 507 can be increased. Therefore, transistor 507 can be easily turned on, and the basic circuit can be operated under a wide range of operating conditions. Subsequently, the operation during period T2 will be described with reference to FIG. 6(b). During period T2, an H signal is supplied to wiring 510, and transistors 502 and 505 are on. Also, an L signal is supplied to wiring 511, and transistors 503 and 506 are off. Also, the potential of node N51 is determined by the operating points of transistors 501 and 502. If the W / L ratio of transistor 502 is made sufficiently larger than the W / L ratio of transistor 501, the potential of node N51 is slightly higher than the power supply potential VSS. That is, the potential of node N51 rises until the potential of node N52 becomes equal to the power supply potential VDD. The so-called bootstrap operation can make the potential of node N52 equal to the power supply potential VDD. Accordingly, transistor 507 turns on, and the potential of wiring 509 becomes equal to the power supply potential VSS. Here, by making the potential of node N52 equal to the power supply potential VDD, the potential difference between the gate and the source of transistor 507 can be increased. Therefore, transistor 507 can be easily turned on, and the basic circuit can be operated under a wide range of operating conditions. That is, the potential of node N51 rises until the potential of node N52 becomes equal to the power supply potential VDD. The so-called bootstrap operation can make the potential of node N52 equal to the power supply potential VDD.

[0127] Accordingly, transistor 507 turns on, and the potential of wiring 509 becomes equal to the power supply potential VSS. Here, by making the potential of node N52 equal to the power supply potential VDD, the potential difference between the gate and the source of transistor 507 can be increased. Therefore, transistor 507 can be easily turned on, and the basic circuit can be operated under a wide range of operating conditions. That is, the potential of node N51 rises until the potential of node N52 becomes equal to the power supply potential VDD. The so-called bootstrap operation can make the potential of node N52 equal to the power supply potential VDD. Accordingly, transistor 507 turns on, and the potential of wiring 509 becomes equal to the power supply potential VSS. Here, by making the potential of node N52 equal to the power supply potential VDD, the potential difference between the gate and the source of transistor 507 can be increased. Therefore, transistor 507 can be easily turned on, and the basic circuit can be operated under a wide range of operating conditions. That is, the potential of node N51 rises until the potential of node N52 becomes equal to the power supply potential VDD. The so-called bootstrap operation can make the potential of node N52 equal to the power supply potential VDD. Accordingly, transistor 507 turns on, and the potential of wiring 509 becomes equal to the power supply potential VSS. Here, by making the potential of node N52 equal to the power supply potential VDD, the potential difference between the gate and the source of transistor 507 can be increased. Therefore, transistor 507 can be easily turned on, and the basic circuit can be operated under a wide range of operating conditions.

[0128] Subsequently, the operation during period T2 will be described with reference to FIG. 6(b). During period T2, an H signal is supplied to wiring 510, and transistors 502 and 505 are on. Also, an L signal is supplied to wiring 511, and transistors 503 and 506 are off. That is, the potential of node N51 rises until the potential of node N52 becomes equal to the power supply potential VDD. The so-called bootstrap operation can make the potential of node N52 equal to the power supply potential VDD. Accordingly, transistor 507 turns on, and the potential of wiring 509 becomes equal to the power supply potential VSS. Here, by making the potential of node N52 equal to the power supply potential VDD, the potential difference between the gate and the source of transistor 507 can be increased. Therefore, transistor 507 can be easily turned on, and the basic circuit can be operated under a wide range of operating conditions. That is, the potential of node N51 rises until the potential of node N52 becomes equal to the power supply potential VDD. The so-called bootstrap operation can make the potential of node N52 equal to the power supply potential VDD.

[0129] Also, the potential of node N51 is determined by the operating points of transistors 501 and 502. If the W / L ratio of transistor 502 is made sufficiently larger than the W / L ratio of transistor 501, the potential of node N51 is slightly higher than the power supply potential VSS. That is, the potential of node N51 rises until the potential of node N52 becomes equal to the power supply potential VDD. The so-called bootstrap operation can make the potential of node N52 equal to the power supply potential VDD. Accordingly, transistor 507 turns on, and the potential of wiring 509 becomes equal to the power supply potential VSS. Here, by making the potential of node N52 equal to the power supply potential VDD, the potential difference between the gate and the source of transistor 507 can be increased. Therefore, transistor 507 can be easily turned on, and the basic circuit can be operated under a wide range of operating conditions. becomes the position.

[0130] Therefore, since the transistor 504 is off and the transistor 505 is on, the potential of the node N52 becomes a value equal to the power supply potential VSS. Thus, the transistor 507 is off and the wiring 512 is in a floating state. The potential of the wiring 512 remains at a value equal to the power supply potential VSS in order to maintain the potential during the period T 1.

[0131] Subsequently, the operation during the period T3 will be described with reference to FIG. 7(a). During the period T3, an L signal is supplied to the wiring 5 10, and the transistors 502 and 505 are off . Also, an H signal is supplied to the wiring 511, and the transistors 503 and 506 are on.

[0132] Also, the potential of the node N51 is determined by the operating points of the transistors 501 and 503. If the W / L ratio of the transistor 503 is made sufficiently larger than the W / L ratio of the transistor 501 , then the potential of the node N51 becomes a potential slightly higher than the power supply potential VSS. becomes the position.

[0133] Therefore, since the transistor 504 is off and the transistor 506 is on, the potential of the node N52 becomes a value equal to the power supply potential VSS. Thus, the transistor 507 is off and the wiring 512 is in a floating state. The potential of the wiring 512 remains at a value equal to the power supply potential VSS in order to maintain the potential during the period T 1 and during the period T2.

[0134] Subsequently, the operation during the period T4 will be described with reference to FIG. 7(b). During the period T4, the wiring 5 The H signal is supplied to 10, and the transistors 502 and 505 are on. . Also, the H signal is supplied to the wiring 511, and the transistors 503 and 506 are on.

[0135] Also, since the potential of the node N51 is determined by the operating points of the transistors 501, 502, and transistor 5 03, the potential of the node N51 becomes a potential slightly higher than the power supply potential VSS.

[0136] Therefore, the transistor 504 is off, and since the transistors 505 and 5 06 are on, the potential of the node N52 becomes equal to the power supply potential VSS. Thus , the transistor 507 is off, and the wiring 512 is in a floating state. The potential of the wiring 512 remains equal to the power supply potential VSS in order to maintain the potential during the periods T1, T2, and T3.

[0137] By the above operation, in the period T1, the basic circuit in FIG. 5(a) supplies the power supply potential VS S to the wiring 512 and makes the potential of the wiring 512 equal to the power supply potential VSS. In the periods T2 to T4 , the basic circuit in FIG. 5(a) puts the wiring 512 in a floating state and maintains the potential of the wiring 512 equal to the power supply potential VSS.

[0138] Note that in the period T1, the potential of the node N52 of the basic circuit in FIG. 5(a) can be made equal to the power supply potential VDD . Therefore, the basic circuit in FIG. 5(a) can be operated under a wide range of operating conditions.

[0139] Also, the basic circuit in FIG. 5(a) is in an on state during all of the periods T1 to T4 for the tra ​It does not have a transistor. That is, it does not have a transistor that is constantly or almost constantly in the on state. Therefore, the basic circuit in Fig. 5(a) can suppress the characteristic degradation of the transistor and the shift of the threshold voltage due to the characteristic degradation.

[0140] Also, the characteristics of the transistor are likely to deteriorate when the transistor is formed of amorphous silicon. Therefore, by forming the transistor in the basic circuit of Fig. 5(a) with amorphous silicon, not only can merits such as cost reduction in manufacturing and improvement in yield be obtained, but also the problem of characteristic degradation of the transistor can be solved.

[0141] Here, the functions of transistors 501 to 507 will be described. Transistor 50 1 has a function as a diode having an input terminal as the first terminal and a gate, and an output terminal as the second terminal. Transistor 502 has a function as a switch that selects whether to connect wiring 509 and node N51 according to the potential of wiring 510. Transistor 503 has a function as a switch that selects whether to connect wiring 509 and node N51 according to the potential of wiring 511. Transistor 504 has a function as a switch that selects whether to connect wiring 508 and node N52 according to the potential of node N51. Transistor 505 has a function as a switch that selects whether to connect wiring 509 and node N52 according to the potential of wiring 510. Transistor 506 has a function as a switch that selects whether to connect wiring 509 and node N52 according to the potential of wiring 511. Transistor 507 has a function as a switch that selects whether to connect wiring 509 and node N52 according to the potential of node N52. The potential of It has a function as a switch that selects whether to connect wiring 509 and wiring 512 or not. It has a function.

[0142] Note that transistors 501 to 506 form a 2-input NOR circuit with wiring 510 and wiring 511 as input terminals and node N52 as the output terminal. It forms a 2-input NOR circuit with wiring 510 and wiring 511 as input terminals and node N52 as the output terminal.

[0143] Note that as shown in Fig. 8(a), a capacitor element 801 may be arranged between the gate (node N51) of transistor 504 and the second terminal (node N52). This is because the potential of node N51 and the potential of node N52 increase due to the bootstrap operation, so arranging the capacitor element 801 makes it easier for the basic circuit to perform the bootstrap operation. Note that as shown in Fig. 8(a), a capacitor element 801 may be arranged between the gate (node N51) of transistor 504 and the second terminal (node N52). Since the potential of node N51 and the potential of node N52 increase due to the bootstrap operation, arranging the capacitor element 801 makes it easier for the basic circuit to perform the bootstrap operation. Note that as shown in Fig. 8(a), a capacitor element 801 may be arranged between the gate (node N51) of transistor 504 and the second terminal (node N52). Since the potential of node N51 and the potential of node N52 increase due to the bootstrap operation, arranging the capacitor element 801 makes it easier for the basic circuit to perform the bootstrap operation. Note that as shown in Fig. 8(a), a capacitor element 801 may be arranged between the gate (node N51) of transistor 504 and the second terminal (node N52). Since the potential of node N51 and the potential of node N52 increase due to the bootstrap operation, arranging the capacitor element 801 makes it easier for the basic circuit to perform the bootstrap operation.

[0144] Note that as shown in Fig. 8(b), transistor 503 is not necessarily required. This is because when an H signal is supplied to wiring 510, the potential of node N52 decreases, and transistor 507 may be turned off. Note that as shown in Fig. 8(b), transistor 503 is not necessarily required. Since when an H signal is supplied to wiring 510, the potential of node N52 decreases, transistor 507 may be turned off. Note that as shown in Fig. 8(b), transistor 503 is not necessarily required. Since when an H signal is supplied to wiring 510, the potential of node N52 decreases, transistor 507 may be turned off.

[0145] Next, the case where the basic circuit shown in Fig. 5(a) is composed of P-channel transistors will be described with reference to Fig. 17(a). Next, the case where the basic circuit shown in Fig. 5(a) is composed of P-channel transistors will be described with reference to Fig. 17(a).

[0146] Fig. 17(a) is a basic circuit based on the basic principle of the present invention. The basic circuit of Fig. 17(a) has transistors 1701, 1702, 1703, 1704, 1705, 1706, and 1707. Fig. 17(a) is a basic circuit based on the basic principle of the present invention. The basic circuit of Fig. 17(a) has transistors 1701, 1702, 1703, 1704, 1705, 1706, and 1707. Fig. 17(a) is a basic circuit based on the basic principle of the present invention. The basic circuit of Fig. 17(a) has transistors 1701, 1702, 1703, 1704, 1705, 1706, and 1707. It has transistors 1701, 1702, 1703, 1704, 1705, 1706, and 1707.

[0147] The connection relationship of the basic circuit in Fig. 17(a) will be described. The gate of transistor 1701 is It is connected to wiring 1709, with the first terminal connected to wiring 1709 and the second terminal connected to the gate of transistor 1704. The gate of transistor 1702 is connected to wiring 1710 and continued, with the first terminal connected to wiring 1708 and the second terminal connected to the gate of transistor 1704 . The gate of transistor 1703 is connected to wiring 1711, and the first terminal is connected to wiring 1708 and the second terminal is connected to the gate of transistor 1704 . Note that the node of the second terminal of transistor 1701, the second terminal of transistor 1702, the second terminal of transistor 1703, and the gate of transistor 1704 is defined as node N171 . The first terminal of transistor 1704 is connected to wiring 1709, and the second terminal is connected to the gate of transistor 1707. The gate of transistor 1705 is connected to wiring 1710 and continued, with the first terminal connected to wiring 1708 and the second terminal connected to the gate of transistor 1707 . The gate of transistor 1706 is connected to wiring 1711, and the first terminal is connected to wiring 1708 and the second terminal is connected to the gate of transistor 1707 . The first terminal of transistor 1707 is connected to wiring 1708, and the second terminal is connected to wiring 1712 . Note that the node of the second terminal of transistor 1704, the second terminal of transistor 1705, the second terminal of transistor 1706, and the gate of transistor 1707 is defined as node N172.

[0148] Also, transistors 1701 to 1707 are each of P-channel type.

[0149] Therefore, the basic circuit in Fig. 17(a) is composed of all P-channel type transistors. Therefore, there is no need for a process to form an N-channel transistor. Thus the basic circuit of FIG. 17(a) can simplify the manufacturing process, reduce the manufacturing cost, and improve the yield.

[0150] Also, a power supply potential VDD is supplied to the wiring 1708, and a power supply potential VSS is supplied to the wiring 1709. Note that the power supply potential VDD is higher than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to the wiring 1708 and the wiring 1709, or

[0151] other power supply potentials may be supplied. Also, signals are supplied to the wiring 1710 and the wiring 1711, respectively. Note that the signals supplied to the wiring 1710 and the wiring 1711 are digital signals having binary values, respectively. However, a power supply potential VDD, a power supply potential VSS, or other power supply potentials may be

[0152] Next, the operation of the basic circuit shown in FIG. 17(a) will be described with reference to FIG. 17(b).

[0153] FIG. 17(b) is an example of a timing chart of the basic circuit shown in FIG. 17(a). The timing chart of FIG. 17(b) shows the potential of the wiring 1710, the potential of the wiring 1711, the potential of the node N171, the potential of the node N172, the potential of the wiring 1712, and the on / off of the transistor 1707.

[0154] The timing chart of Fig. 17(b) will be described by dividing it into periods T1 to T4. Also, Fig. 18(a), Fig. 18(b), Fig. 19(a), and Fig. 19(b) show the operations of the basic circuit of Fig. 17(a) in periods T1, T2, period T3, and period T4.

[0155] First, the operation in period T1 will be described with reference to Fig. 18(a). In period T1, an H signal is supplied to wiring 1 710, and transistors 1702 and 1705 are turned off. Also, an H signal is supplied to wiring 1711, and transistors 1703 and transistor 1706 are turned off.

[0156] Moreover, since transistor 1701 is diode-connected, the potential of node N171 begins to decrease. When the potential of node N171 becomes the sum of the power supply potential VSS and the absolute value of the threshold voltage Vth1701 of transistor 1701 (VSS + |Vth1701|), the transistor 1701 turns off. Therefore, node N171 becomes a floating state. At this time, transistor 1704 is on, and the potential of node N172 is also decreasing.

[0157] Therefore, the potential of floating node N171 decreases together with the potential of node N172 due to the parasitic capacitance between the gate (node N171) and the second terminal (node N172) of transistor 17 04. This decrease in the potential of node N171 continues until the decrease in the potential of node N172 stops, and the potential of node N171 becomes a value equal to or less than the value obtained by subtracting the absolute value of the threshold voltage Vth1704 of transistor 17 04 from the power supply potential VSS (VSS - |Vth1704| ). That is, the decrease in the potential of node N171 continues until the potential of node N172 reaches the power supply potential V and the decrease in the potential of node N172 stops. The potential of node N171 decreases until it becomes less than or equal to the value obtained by subtracting the absolute value of the threshold voltage of transistor 1 704 from the power supply potential VSS (VSS - |Vth1704| ). That is, the decrease in the potential of node N171 is accompanied by the decrease in the potential of node N172 until the potential of node N172 reaches the power supply potential V Continue until it becomes equal to SS. By means of the so-called bootstrap operation, the potential of node N172 can be made equal to the power supply potential VSS. Thus, the potential of node N172 can be made equal to the power supply potential VSS.

[0158] Therefore, transistor 1707 turns on and the potential of wiring 1712 becomes equal to the power supply potential VDD. Here, by making the potential of node N172 equal to the power supply potential VSS, the potential difference between the gate and the source of transistor 1707 can be increased. Thus, the potential of node N172 can be made equal to the power supply potential VSS. Therefore, the potential difference between the gate and the source of transistor 1707 can be increased. Thus, transistor 1707 can be made easier to turn on, and the basic circuit can be operated under a wide range of operating conditions. Thus, transistor 1707 can be made easier to turn on, and the basic circuit can be operated under a wide range of operating conditions.

[0159] Subsequently, the operation during period T2 will be described with reference to FIG. 18(b). During period T2, an L signal is supplied to wiring 1710, and transistors 1702 and 1705 are on. Also, an H signal is supplied to wiring 1711, and transistors 1703 and 1706 are off. Also, an L signal is supplied to wiring 1710, and transistors 1702 and 1705 are on. Also, an H signal is supplied to wiring 1711, and transistors 1703 and 1706 are off. Also, an H signal is supplied to wiring 1711, and transistors 1703 and 1706 are off.

[0160] Also, the potential of node N171 is determined by the operating points of transistors 1701 and 1702. If the W / L ratio of transistor 1702 is made sufficiently larger than the W / L ratio of transistor 1701, the potential of node N171 will be a potential slightly lower than the power supply potential VDD. Also, the potential of node N171 is determined by the operating points of transistors 1701 and 1702. If the W / L ratio of transistor 1702 is made sufficiently larger than the W / L ratio of transistor 1701, the potential of node N171 will be a potential slightly lower than the power supply potential VDD. If the W / L ratio of transistor 1702 is made sufficiently larger than the W / L ratio of transistor 1701, the potential of node N171 will be a potential slightly lower than the power supply potential VDD.

[0161] Therefore, transistor 1704 is off and transistor 1705 is on, so the potential of node N172 becomes equal to the power supply potential VDD. Thus, transistor 1707 is off and wiring 1712 is in a floating state. The potential of wiring 1712 remains equal to the potential during period T1 in order to maintain the potential. Therefore, transistor 1704 is off and transistor 1705 is on, so the potential of node N172 becomes equal to the power supply potential VDD. Thus, transistor 1707 is off and wiring 1712 is in a floating state. The potential of wiring 1712 remains equal to the potential during period T1 in order to maintain the potential. The potential of wiring 1712 remains equal to the potential during period T1 in order to maintain the potential.

[0162] Next, the operation in period T3 will be described with reference to FIG. 19(a). In period T3, an H signal is supplied to wiring 1710, and transistors 1702 and 1705 are off while an L signal is supplied to wiring 1711, and transistors 1703 and tran sistor 1706 are on.

[0163] Also, the potential of node N171 is determined by the operating points of transistors 1701 and 1703. If the W / L ratio of transistor 1703 is made sufficiently larger than the W / L ratio of transistor 1701, the potential of node N171 will be slightly lower than the power supply potential VDD.

[0164] Therefore, transistor 1704 is off and transistor 1706 is on, so the potential of node N172 becomes equal to the power supply potential VDD. Thus, transistor 17 07 is off and wiring 1712 is in a floating state. The potential of wiring 1712 remains equal to the power supply potential VDD to maintain the potential during periods T1 and T2.

[0165]

[0166] Next, the operation in period T4 will be described with reference to FIG. 19(b). In period T4, an L signal is supplied to wiring 1710, and transistors 1702 and 1705 are on while an L signal is supplied to wiring 1711, and transistors 1703 and tran sistor 1706 are on.

[0166] Also, the potential of node N171 is determined by transistors 1701, 1702, and tran Since it is determined by the operating point with Sta1703, the potential of node N171 is the power supply potential VDD becomes a potential slightly lower than

[0167] Therefore, transistor 1704 turns off, and since transistors 1705 and 1706 are on, the potential of node N172 becomes equal to the power supply potential VDD . Thus, transistor 1707 turns off, and wiring 1712 becomes in a floating state . The potential of wiring 1712 remains the potential during period T1, period T2, and period T3 , so it remains at the power supply potential VDD

[0168] By the above operation, in period T1, the basic circuit in Fig. 17(a) supplies the power supply potential VDD to wiring 1712 and makes the potential of wiring 1712 equal to the power supply potential VDD. In periods T2 to period 4, the basic circuit in Fig. 17(a) puts wiring 1712 in a floating state and maintains the potential of wiring 1 712 at a value equal to the power supply potential VDD

[0169] Note that in period T1, the potential of node N172 of the basic circuit in Fig. 17(a) can be made equal to the power supply potential VSS . Therefore, the basic circuit in Fig. 17(a) can be operated under a wide range of operating conditions

[0170] Also, the basic circuit in Fig. 17(a) does not have a transistor that is on in all periods from period T1 to period T4 . That is, it does not have a transistor that is constantly or almost constantly on . Therefore, the basic circuit in Fig. 17(a) can suppress the characteristic degradation of the transistor and the shift of the threshold voltage due to the characteristic degradation

[0171] ​Note that transistors 1701 to 1707 have the same functions as transistors 501 to 507.

[0172] Note that transistors 1701 to 1706 form a 2-input NAND circuit with wirings 1710 and 1711 as input terminals and node N172 as the output terminal.

[0173] Note that as shown in Fig. 20(a), a capacitive element 2001 may be disposed between the gate (node N171) of transistor 1704 and the second terminal (node N172). This is because the potential at node N171 and the potential at node N172 are reduced by the bootstrap operation, and disposing the capacitive element 2001 makes it easier for the basic circuit to perform the bootstrap operation.

[0174] Note that as shown in Fig. 20(b), transistor 1703 is not necessarily required. This is because when an L signal is supplied to wiring 1710, the potential at node N172 rises, and transistor 1707 may be turned off.

[0175] Note that this embodiment can be freely combined with any description in other embodiments in this specification. Also, any descriptions in this embodiment can be freely combined and implemented.

[0176] (Third Embodiment) In this embodiment, the basic principle of the present invention different from the first embodiment and the second embodiment will be described with reference to Fig. 9(a).

[0177] FIG. 9(a) shows a basic circuit based on the basic principle of the present invention. The basic circuit of FIG. 9(a) includes transistors 901, 902, 903, and 904 .

[0178] The connection relationship of the basic circuit in FIG. 9(a) will be described. The gate of transistor 901 is connected to the gate of transistor 904, the first terminal is connected to wiring 906, and the second terminal is connected to the gate of transistor 904. The gate of transistor 902 is connected to wiring 907, the first terminal is connected to wiring 905, and the second terminal is connected to the gate of transistor 904. The gate of transistor 903 is connected to wiring 908, the first terminal is connected to wiring 906, and the second terminal is connected to the gate of transistor 904. The first terminal of transistor 904 is connected to wiring 906, and the second terminal is connected to wiring 909 . Note that the node of the second terminal of transistor 901, the gate of transistor 901, the second terminal of transistor 902, the second terminal of transistor 903, and the gate of transistor 904 is defined as node N91 .

[0179] Moreover, transistors 901 to 904 are each of N-channel type

[0180] Therefore, since the basic circuit of FIG. 9(a) can be composed entirely of N-channel type transistors, the basic circuit of FIG. 9(a) can use amorphous silicon for the semiconductor layer , and the manufacturing process can be simplified. Therefore, the manufacturing cost can be reduced and the yield can be improved. Furthermore, semiconductor devices such as large display panels can be fabricated ​​​is also possible. The basic circuit in Fig. 9(a) can simplify the manufacturing process even when polysilicon or single crystal silicon is used in the semiconductor layer.

[0181] Also, a power supply potential VDD is supplied to wiring 905, and a power supply potential VSS is supplied to wiring 906. Note that the power supply potential VDD is higher than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to wiring 905 and wiring 906, or other power supply potentials may be supplied.

[0182] Also, signals are supplied to wiring 907 and wiring 908, respectively. Note that the signals supplied to wiring 9 07 and wiring 908 are digital signals having binary values, respectively. However, a power supply potential VDD, a power supply potential V VSS, and other power supply potentials may be supplied to wiring 907 and wiring 908, respectively. Also, analog signals may be supplied to wiring 907 and wiring 908, respectively.

[0183] Next, the operation of the basic circuit shown in Fig. 9(a) will be described with reference to Fig. 9(b).

[0184] Fig. 9(b) is an example of a timing chart of the basic circuit shown in Fig. 9(a). Fig. 9( b)'s timing chart shows the potential of wiring 907, the potential of wiring 908, the potential of node N91 , the potential of wiring 909, and the on / off state of transistor 904.

[0185] The timing chart in Fig. 9(b) will be described by dividing it into periods T1 to T4. Also, Fig. 1 0(a), Fig. 10(b), Fig. 11(a), and Fig. 11(b) show periods T1, T2, and 9(a) during periods T3 and T4.

[0186] First, the operation during the period T1 will be described with reference to FIG. An L signal is supplied to the wiring 907, and an L signal is supplied to the wiring 908. 9. Transistor 902 is off and transistor 903 is off.

[0187] In addition, since the transistor 901 is diode-connected, the potential of the node N91 decreases. This decrease in the potential of the node N91 continues until the transistor 901 turns off. The potential of the node N91 is equal to the power supply potential VSS and the threshold potential of the transistor 901. When the sum of the absolute value of the threshold voltage Vth901 and the absolute value of the threshold voltage Vth901 becomes (VSS + |Vth901|), the transistor turns off. Therefore, the potential of the node N91 becomes VSS+|Vth901|.

[0188] Therefore, the transistor 904 is turned off, and the potential of the wiring 909 is maintained at the potential of the period T2. In order to maintain the potential, the potential remains equal to the power supply potential VSS. do.

[0189] Next, the operation during the period T2 will be described with reference to FIG. An H signal is supplied to 907, and an L signal is supplied to wiring 908. Transistor 902 is on and transistor 903 is off.

[0190] The potential of the node N91 depends on the operating point of the transistors 901 and 902. It should be noted that the W / L ratio of the transistor 902 is determined by the W / L ratio of the transistor 901. If the potential of node N91 is set to a value slightly lower than the power supply potential VDD, It becomes.

[0191] Therefore, transistor 904 turns on, and the potential of wiring 909 becomes equal to the power supply potential VSS. It becomes a certain value.

[0192] Subsequently, the operation in period T3 will be described with reference to FIG. 11(a). In period T3, an L signal is supplied to wiring 907 and an H signal is supplied to wiring 908. Therefore, transistor 902 turns off and transistor 903 turns on. Also, since transistor 902 is off, the potential of node N91 becomes equal to the power supply potential VSS.

[0193] Also, since transistor 902 is off, the potential of node N91 becomes equal to the power supply potential VSS. It becomes an equal value.

[0194] Therefore, transistor 904 turns off, and wiring 909 becomes a floating state. The potential of wiring 909 remains equal to the power supply potential VSS in order to maintain the potential during periods T1 and T2. The potential of wiring 909 remains equal to the power supply potential VSS. It remains at a value equal to the power supply potential VSS.

[0195] Subsequently, the operation in period T4 will be described with reference to FIG. 11(b). In period T4, an H signal is supplied to wiring 907 and an H signal is supplied to wiring 908. Therefore, transistor 902 turns on and transistor 904 turns on. Also, since the potential of node N91 is determined by the operating points of transistors 901, 902, and 903, the potential of node N91 becomes slightly higher than the power supply potential VSS.

[0196] Also, since the potential of node N91 is determined by the operating points of transistors 901, 902, and 903, the potential of node N91 becomes slightly higher than the power supply potential VSS. It becomes a value slightly higher than the power supply potential VSS.

[0197] Therefore, transistor 904 turns off, and wiring 909 becomes a floating state. ​​​The potential of the wiring 909 is maintained in the periods T1, T2, and T3. Therefore, it remains equal to the power supply potential VSS.

[0198] By the above operation, during the period T2, the basic circuit of FIG. 9(a) applies the power supply potential VS S is supplied to make the potential of the wiring 909 equal to the power supply potential VSS. In the period 1 and the period 2, the basic circuit in FIG. 9A has the wiring 909 in a floating state, and the wiring The potential of the line 909 is maintained at a value equal to the power supply potential VSS.

[0199] In addition, the basic circuit of FIG. 9(a) has a transistor that is on during all of the periods T1 to T4. In other words, it does not have a transistor that is constantly or almost constantly on. Therefore, the basic circuit of FIG. 9(a) does not have a transistor characteristic deterioration and In addition, it is possible to suppress a shift in threshold voltage due to deterioration of characteristics.

[0200] In addition, the characteristics of the transistors are different when the transistors are made of amorphous silicon. Therefore, the basic circuit of Fig. 9(a) uses an amorphous By using silicon, there are benefits such as reduced manufacturing costs and improved yields. Not only this, but also the problem of degradation of transistor characteristics can be solved.

[0201] Here, the functions of the transistors 901 to 904 will be described. 1 is a diode whose second terminal is the input terminal and whose gate is the output terminal, and whose first terminal is the output terminal. The transistor 902 functions as a It functions as a switch to select whether to connect or not connect the transformer to node N91. Distributor 903 functions as a switch that selects whether to connect wiring 906 and node N91 according to the potential of wiring 908. Transistor 904 functions as a switch that selects whether to connect wiring 906 and wiring 909 according to the potential of node N91.

[0202] Note that transistors 901 to 904 constitute a two-input logic circuit with wiring 907 and wiring 908 as input terminals and node N91 as the output terminal.

[0203] Note that transistor 901 may be an element having a resistance component. For example, as shown in FIG. 12(a), resistance element 1201 can be used in place of transistor 901. Also, the timing chart of FIG. 12(a) is shown in FIG. 12(b).

[0204] Next, the case where the basic circuit shown in FIG. 9(a) is configured with P-channel transistors will be described with reference to FIG. 21(a).

[0205] FIG. 21(a) is a basic circuit based on the basic principle of the present invention. The basic circuit of FIG. 21(a) includes transistors 2101, 2102, 2103, and transistor 2104.

[0206] The connection relationship of the basic circuit in FIG. 21(a) will be described. The gate of transistor 2101 is connected to the gate of transistor 2104, the first terminal is connected to wiring 2105, and the second terminal is connected to the gate of transistor 2104. The gate of transistor 2102 is connected to wiring 2107, the first terminal is connected to wiring 2106, and the second terminal is connected to the transistor ​​​​It is connected to the gate of 2104. The gate of transistor 2103 is connected to wiring 2108, the first terminal is connected to wiring 2105, and the second terminal is connected to the gate of transistor 2104. The first terminal of transistor 2104 is connected to wiring 2105, and the second terminal is connected to wiring 2109. Note that the gate of transistor 2101, the second terminal of transistor 2101, the second terminal of transistor 2102, the second terminal of transistor 2103, and the node of the gate of transistor 2104 are defined as node N211.

[0207] Moreover, transistors 2101 to 2104 are each of P-channel type.

[0208] Therefore, since the basic circuit in Fig. 21(a) can be entirely composed of P-channel type transistors, there is no need for a process to form N-channel type transistors. Thus, the basic circuit in Fig. 21(a) can simplify the manufacturing process, reduce the manufacturing cost, and improve the yield.

[0209] Also, the power supply potential VDD is supplied to wiring 2105, and the power supply potential VSS is supplied to wiring 2106. Note that the power supply potential VDD is at a higher potential than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to wiring 2105 and wiring 2106, or other power supply potentials may be supplied.

[0210] Also, signals are respectively supplied to wiring 2107 and wiring 2108. Note that the signals supplied to wiring 2107 and wiring 2108 each have binary values, i.e., digital It is a clock signal. However, the power supply potential VDD , the power supply potential VSS, or another power supply potential may be supplied to the wiring 2107 and the wiring 2108, respectively. Also, an analog signal may be supplied to the wiring 2107 and the wiring 2108, respectively.

[0211] Next, the operation of the basic circuit shown in Fig. 21(a) will be described with reference to Fig. 21(b). .

[0212] Fig. 21(b) is an example of the timing chart of the basic circuit shown in Fig. 21(a). Fig. 2 The timing chart of 1(b) shows the potential of the wiring 2107, the potential of the wiring 2108, the potential of the node N2 11, the potential of the wiring 2109, and the on / off state of the transistor 2104. .

[0213] The timing chart of Fig. 21(b) will be described by dividing it into periods T1 to T4. Also, Fig 22(a), Fig. 22(b), Fig. 23(a), and Fig. 23(b) show the operations of the basic circuit of Fig. 21(a) in periods T1, T2, period T3, and period T4.

[0214] First, the operation in period T1 will be described with reference to Fig. 22(a). In period T1, an H signal is supplied to the wiring 2 107, and an H signal is supplied to the wiring 2108. Therefore, the transistor 2102 is turned off, and the transistor 2103 is turned off.

[0215] Also, since the transistor 2101 is diode-connected, the potential of the node N211 starts to rise. The rise of the potential of this node N211 continues until the transistor 2101 is turned off. The transistor 2101 turns off when the potential of the node N211 reaches the power supply potential VDD from the transistor . When the value obtained by subtracting the absolute value of the threshold potential Vth2101 of 2101 (VDD - |Vth2101|) is reached, it turns off. Therefore, the potential of node N211 becomes VDD - |Vth2101|. Thus, the potential of node N211 becomes VDD - |Vth2101|.

[0216] Therefore, transistor 2104 turns off, and the potential of wiring 2109 remains slightly lower than the power supply potential VDD in order to maintain the potential during period T2. Also, the operation during period T2 will be described next. The operation during period T2 will be described next.

[0217] Subsequently, the operation during period T2 will be described with reference to FIG. 22(b). During period T2, an L signal is supplied to wiring 2107 and an H signal is supplied to wiring 2108. Therefore, transistor 2102 is on and transistor 2103 is off. Subsequently, the operation during period T2 will be described with reference to FIG. 22(b). During period T2, an L signal is supplied to wiring 2107 and an H signal is supplied to wiring 2108. Therefore, transistor 2102 is on and transistor 2103 is off.

[0218] Also, the potential of node N211 is determined by the operating points of transistor 2101 and transistor 2102. If the W / L ratio of transistor 2102 is made sufficiently larger than the W / L ratio of transistor 2101, the potential of node N211 will be slightly higher than the power supply potential VSS. Also, the potential of node N211 is determined by the operating points of transistor 2101 and transistor 2102. If the W / L ratio of transistor 2102 is made sufficiently larger than the W / L ratio of transistor 2101, the potential of node N211 will be slightly higher than the power supply potential VSS. If the W / L ratio of transistor 2102 is made sufficiently larger than the W / L ratio of transistor 2101, the potential of node N211 will be slightly higher than the power supply potential VSS.

[0219] Therefore, transistor 2104 turns on, and the potential of wiring 2109 becomes equal to the power supply potential VDD.

[0220] Subsequently, the operation during period T3 will be described with reference to FIG. 23(a). During period T3, an H signal is supplied to wiring 2107 and an L signal is supplied to wiring 2108. Therefore, transistor 2102 is off and transistor 2103 is on. Subsequently, the operation during period T3 will be described with reference to FIG. 23(a). During period T3, an H signal is supplied to wiring 2107 and an L signal is supplied to wiring 2108. Therefore, transistor 2102 is off and transistor 2103 is on.

[0221] ​​​​​​Also, since the transistor 2102 is off, the potential of the node N211 is equal to the power supply potential VD D.

[0222] Therefore, the transistor 2104 is off and the wiring 2109 is in a floating state. The potential of the wiring 2109 remains at a value equal to the power supply potential VSS in order to maintain the potential during the periods T1 and T2.

[0223] Subsequently, the operation in the period T4 will be described with reference to FIG. 23(b). In the period T4, an L signal is supplied to the wiring 2107 and an L signal is supplied to the wiring 2108. Therefore, the transistor 2102 is on and the transistor 2104 is on.

[0224] Also, since the potential of the node N211 is determined by the operating points of the transistors 2101, 2102, and 2103, the potential of the node N211 is slightly lower than the power supply potential VDD.

[0225] Therefore, the transistor 2104 is off and the wiring 2109 is in a floating state. The potential of the wiring 2109 remains at a value equal to the power supply potential VSS in order to maintain the potential during the periods T1, T2, and T3.

[0226] By the above operations, in the period T2, the basic circuit in FIG. 21(a) supplies the power supply potential VDD to the wiring 2109 and makes the potential of the wiring 2109 equal to the power supply potential VDD. In the periods T1, T3, and T4, the basic circuit in FIG. 21(a) puts the wiring 2109 in a floating state and maintains the potential of the wiring 2109 at a value equal to the power supply potential VDD.

[0227] ​​​​​​Also, the basic circuit in Fig. 21(a) does not have a transistor that is in the on state during all of periods T1 to T4. That is, it does not have a transistor that is constantly or almost constantly in the on state. Therefore, the basic circuit in Fig. 21(a) can suppress the deterioration of the transistor characteristics and the shift of the threshold voltage due to the deterioration of the characteristics.

[0228] Note that transistors 2101 to 2104 have the same functions as transistors 901 to transistor 904.

[0229] Note that transistors 2101 to 2104 form a two-input logic circuit with wirings 2107 and 2108 as input terminals and the output terminal being node N211.

[0230] Note that transistor 2101 may be an element having a resistance component. For example, as shown in Fig. 24(a ), resistance element 2401 can be used instead of transistor 2101. Also, the timing chart of Fig. 24(a) is shown in Fig. 24(b).

[0231] Note that this embodiment can be freely combined with any description in other embodiments in this specification and implemented. Also, any descriptions in this embodiment can be freely combined and implemented as well.

[0232] (Fourth Embodiment) In this embodiment, the basic principle of the present invention different from the first to third embodiments will be described with reference to Fig. 25(a).

[0233] Fig. 25(a) is a basic circuit based on the basic principle of the present invention. The basic circuit in Fig. 25(a) is ​​​​​It has a circuit 2501 and a circuit 2502.

[0234] Note that as the circuit 2501 and the circuit 2502, the basic circuits shown in Fig. 1(a), Fig. 4(a), Fig. 5(a), Fig. 8(a), Fig. 8(b), Fig. 9(a), and Fig. 12(a) can be used. It is possible.

[0235] Therefore, the wiring 2503 and the wiring 2504 correspond to the wiring 107 in Fig. 1(a), the wiring 107 in Fig. 4(a), the wiring 510 in Fig. 5(a), the wiring 510 in Fig. 8(a), the wiring 510 in Fig. 8(b), the wiring 907 in Fig. 9(a), and the wiring 907 in Fig. 12(a).

[0236] Also, the wiring 2505 corresponds to the wiring 108 in Fig. 1(a), the wiring 108 in Fig. 4(a), the wiring 511 in Fig. 5(a), the wiring 511 in Fig. 8(a), the wiring 511 in Fig. 8(b), the wiring 908 in Fig. 9(a), and the wiring 908 in Fig. 12(a).

[0237] Also, the wiring 2506 corresponds to the wiring 109 in Fig. 1(a), the wiring 109 in Fig. 4(a), the wiring 512 in Fig. 5(a), the wiring 512 in Fig. 8(a), the wiring 512 in Fig. 8(b), the wiring 909 in Fig. 9(a), and the wiring 909 in Fig. 12(a).

[0238] Also, since the basic circuit in Fig. 25(a) can all be composed of N-channel type transistors, the basic circuit in Fig. 9(a) can use amorphous silicon for the semiconductor layer, which can simplify the manufacturing process. Therefore, the manufacturing cost can be reduced and the yield can be improved. Furthermore, it becomes possible to fabricate semiconductor devices such as large display panels. Also, the basic circuit in Fig. 25(a) can use polysilicon or single crystal silicon for the semiconductor layer. The use of a computer can also simplify the manufacturing process.

[0239] Also, the wiring to which the power supply potential is supplied is omitted.

[0240] Also, signals are respectively supplied to wiring 2503, wiring 2504, and wiring 2505 Note that the signals supplied to wiring 2503, wiring 2504, and wiring 2505 are digital signals each having a binary value.

[0241] However, the power supply potential VDD, the power supply potential VSS, or another power supply potential may be respectively supplied to wiring 2503, wiring 2504, and wiring 2505. Also, analog signals may be respectively supplied to wiring 2503, wiring

[0242] Next, the operation of the basic circuit shown in Fig. 25(a) will be described with reference to Fig. 25(b). Note that Fig. 25(b) shows the case where the basic circuits shown in Fig. 1(a), Fig. 4(a), Fig. 5(a), Fig. 8(a), and Fig. 8(b) are used as circuits 2501 and 2502.

[0243] Fig. 25(b) is an example of the timing chart of the basic circuit shown in Fig. 25(a). Fig. The timing chart of 25(b) shows the potential of wiring 2503, the potential of wiring 2504, the potential of wiring 2 505, whether the output of circuit 2501 is floating (denoted as OFF) or the power supply potential VSS (denoted as ON), whether the output of circuit 2502 is floating (denoted as OFF) or the power supply potential VSS (denoted as ON), and the potential of wiring 2506.

[0244] The timing chart of Fig. 25(b) will be described by dividing it into periods T1 to T8.

[0245] First, the operation during period T1 will be described. During period T1, an L signal is supplied to wiring 2505 , an L signal is supplied to wiring 2503, and an L signal is supplied to wiring 2504. Circuit 25 01 supplies the power potential VSS to wiring 2506, and circuit 2502 supplies the power potential VSS to wiring 2506. Therefore, the potential of wiring 2506 becomes equal to the power potential VSS .

[0246] Subsequently, the operation during period T2 will be described. During period T2, an L signal is supplied to wiring 2505 , an H signal is supplied to wiring 2503, and an L signal is supplied to wiring 2504. Circuit 2 501 supplies nothing to wiring 2506, and circuit 2502 supplies the power potential VSS to wiring 2506. Therefore, the potential of wiring 2506 becomes equal to the power potential VSS.

[0247] Subsequently, the operation during period T3 will be described. During period T3, an L signal is supplied to wiring 2505 , an L signal is supplied to wiring 2503, and an H signal is supplied to wiring 2504. Circuit 2501 supplies the power potential VSS to wiring 2506, and circuit 2502 supplies nothing to wiring 2506. Therefore, the potential of wiring 2506 becomes equal to the power potential VSS.

[0248] Subsequently, the operation during period T4 will be described. During period T4, an L signal is supplied to wiring 2505 , an H signal is supplied to wiring 2503, and an H signal is supplied to wiring 2504. Circuit 2501 supplies nothing to wiring 2506, and circuit 2502 supplies nothing to wiring 2506. Therefore, the potential of wiring 2506 remains equal to the power potential V SS in order to maintain the potential during period T3.

[0249] Next, the operation during period T5 will be described. During period T5, an H signal is supplied to wiring 2505 and an L signal is supplied to wiring 2503, and an L signal is supplied to wiring 2504. Circuit 2501 supplies nothing to wiring 2506, and circuit 2502 supplies nothing to wiring 2506 . Therefore, the potential of wiring 2506 remains equal to the power supply potential V SS in order to maintain the potential during period T3.

[0250] Next, the operation during period T6 will be described. During period T6, an H signal is supplied to wiring 2505 and an H signal is supplied to wiring 2503, and an L signal is supplied to wiring 2504. Circuit 2501 supplies nothing to wiring 2506, and circuit 2502 supplies nothing to wiring 2506 . Therefore, the potential of wiring 2506 remains equal to the power supply potential V SS in order to maintain the potential during period T3.

[0251] Next, the operation during period T7 will be described. During period T7, an H signal is supplied to wiring 2505 and an L signal is supplied to wiring 2503, and an H signal is supplied to wiring 2504. Circuit 2501 supplies nothing to wiring 2506, and circuit 2502 supplies nothing to wiring 2506 . Therefore, the potential of wiring 2506 remains equal to the power supply potential V SS in order to maintain the potential during period T3.

[0252] Next, the operation during period T8 will be described. During period T8, an H signal is supplied to wiring 2505 and an H signal is supplied to wiring 2503, and an H signal is supplied to wiring 2504. Circuit 2501 supplies nothing to wiring 2506, and circuit 2502 supplies nothing to wiring 2506 . Therefore, the potential of wiring 2506 remains equal to the power supply potential V Remains equal to the value of SS.

[0253] Through the above operations, during period T1, circuit 2501 supplies the power supply potential VSS to wiring 2506, circuit 2502 supplies the power supply potential VSS to wiring 2506, and sets the potential of wiring 2506 to a value equal to the power supply potential VSS. During period T2, circuit 2502 supplies the power supply potential VSS to wiring 2 506 and sets the potential of wiring 2506 to a value equal to the power supply potential VSS. During period T3 circuit 2501 supplies the power supply potential VSS to wiring 2506 and sets the potential of wiring 2506 to the power supply potential VSS. During periods T4 to T8, wiring 2506 is set to a floating state and the potential of wiring 2506 is maintained at a value equal to the power supply potential VSS.

[0254] Also, the basic circuit in Fig. 25(a) does not have a transistor that is in the on state during all of periods T1 to T8. That is, it does not have a transistor that is constantly or constantly in the on state. Therefore, the basic circuit in Fig. 25(a) can suppress the characteristic degradation of the transistor and the shift of the threshold voltage due to the characteristic degradation.

[0255] Also, the characteristics of the transistor are likely to degrade when the transistor is formed of amorphous silicon. Therefore, by forming the basic circuit in Fig. 25(a) with an amorphous silicon transistor, not only can advantages such as reduction of manufacturing cost and improvement of yield be obtained, but also the problem of characteristic degradation of the transistor can be solved.

[0256] Next, the case where the basic circuit shown in Fig. 25(a) is configured with P-channel transistors will be described with reference to Fig. 26(a).

[0257] Figure 26(a) shows a basic circuit based on the basic principle of the present invention. The basic circuit of Figure 26(a) has circuit 2601 and circuit 2602.

[0258] Note that as circuit 2601 and circuit 2602, the basic circuits shown in Figure 13(a), Figure 16(a), Figure 17( a), Figure 20(a), Figure 20(b), Figure 21(a), and Figure 24(a) can be used.

[0259] Therefore, wiring 2603 and wiring 2604 correspond to wiring 1307 in Figure 13(a), wiring 1 307 in Figure 16(a), wiring 1710 in Figure 17(a), wiring 1710 in Figure 20(a), wiring 1710 in Figure 20(b), wiring 2108 in Figure 21(a), and wiring 210 8 in Figure 24(a).

[0260] Also, wiring 2605 corresponds to wiring 1308 in Figure 13(a), wiring 1308 in Figure 16(a), and Figure 17(a)'s wiring 1711, Figure 20(a)'s wiring 1711, Figure 20(b)'s wiring 1711 , wiring 2107 in Figure 21(a), and wiring 2107 in Figure 24(a).

[0261] Also, wiring 2606 corresponds to wiring 1309 in Figure 13(a), wiring 1309 in Figure 16(a), and Figure 17(a)'s wiring 1712, Figure 20(a)'s wiring 1712, Figure 20(b)'s wiring 1712 , wiring 2109 in Figure 21(a), and wiring 2109 in Figure 24(a).

[0262] Therefore, the basic circuit of Figure 26(a) can all be composed of P-channel transistors, so there is no need for a process to form N-channel transistors. Thus The basic circuit in Fig. 26(a) can simplify the manufacturing process, reduce manufacturing costs, and improve the yield.

[0263] Also, the wiring to which the power supply potential is supplied is omitted.

[0264] Moreover, signals are respectively supplied to wiring 2603, wiring 2604, and wiring 2605. Note that the signals supplied to wiring 2603, wiring 2604, and wiring 2605 are digital signals each having a binary value.

[0265] However, power supply potential VDD, power supply potential VSS, or another power supply potential may be respectively supplied to wiring 2603, wiring 2604, and wiring 2605. Also, analog signals may be respectively supplied to wiring 2603, wiring 2604, and wiring 2605.

[0266] Next, the operation of the basic circuit shown in Fig. 26(a) will be described with reference to Fig. 26(b). Note that Fig. 26(b) shows the case where the basic circuits shown in Fig. 13(a), Fig. 16(a), Fig. 17(a), Fig. 20(a), and Fig. 20(b) are used as circuits 2601 and 2602.

[0267] Fig. 26(b) is an example of the timing chart of the basic circuit shown in Fig. 26(a). The timing chart in Fig. 26(b) shows the potential of wiring 2603, the potential of wiring 2604, the potential of wiring 2605, whether the output of circuit 2601 is floating (denoted as OFF) or the power supply potential VSS (denoted as ON), whether the output of circuit 2602 is floating (denoted as OFF) or the power supply potential VSS (denoted as ON), and the potential of wiring 2606.

[0268] The timing chart of Fig. 26(b) will be described by dividing it into periods T1 to T8.

[0269] First, the operation in period T1 will be described. In period T1, an H signal is supplied to wiring 2605, an H signal is supplied to wiring 2603, and an H signal is supplied to wiring 2604. Circuit 2 601 supplies the power supply potential VDD to wiring 2606, and circuit 2602 supplies the power supply potential VDD to wiring 2606. Therefore, the potential of wiring 2606 becomes a value equal to the power supply potential VDD.

[0270] Subsequently, the operation in period T2 will be described. In period T2, an H signal is supplied to wiring 2605, an L signal is supplied to wiring 2603, and an H signal is supplied to wiring 2604. Circuit 2601 supplies nothing to wiring 2606, and circuit 2602 supplies the power supply potential VD D to wiring 2606. Therefore, the potential of wiring 2606 becomes a value equal to the power supply potential VDD.

[0271] Subsequently, the operation in period T3 will be described. In period T3, an H signal is supplied to wiring 2605, an H signal is supplied to wiring 2603, and an L signal is supplied to wiring 2604. Circuit 2601 supplies the power supply potential VDD to wiring 2606, and circuit 2602 supplies nothing to wiring 2606. Therefore, the potential of wiring 2606 becomes a value equal to the power supply potential VDD.

[0272] Subsequently, the operation in period T4 will be described. In period T4, an H signal is supplied to wiring 2605, an L signal is supplied to wiring 2603, and an L signal is supplied to wiring 2604. Circuit 2601 supplies nothing to wiring 2606, and circuit 2602 supplies nothing to wiring 2606. Therefore, the potential of wiring 2606 maintains the potential in period T3 and is the power supply potential V ​​​​​ Remains equal to the value of DD.

[0273] Subsequently, the operation during period T5 will be described. During period T5, an L signal is supplied to wiring 2605 and an H signal is supplied to wiring 2603 and an H signal is supplied to wiring 2604. Circuit 2601 supplies nothing to wiring 2606, and circuit 2602 supplies nothing to wiring 2606 . Therefore, the potential of wiring 2606 remains equal to the power supply potential V DD in order to maintain the potential during period T3.

[0274] Subsequently, the operation during period T6 will be described. During period T6, an L signal is supplied to wiring 2605 and an L signal is supplied to wiring 2603 and an H signal is supplied to wiring 2604. Circuit 2601 supplies nothing to wiring 2606, and circuit 2602 supplies nothing to wiring 2606 . Therefore, the potential of wiring 2606 remains equal to the power supply potential V DD in order to maintain the potential during period T3.

[0275] Subsequently, the operation during period T7 will be described. During period 7, an L signal is supplied to wiring 2605 and an H signal is supplied to wiring 2603 and an L signal is supplied to wiring 2604. Circuit 2 601 supplies nothing to wiring 2606, and circuit 2602 supplies nothing to wiring 2606 . Therefore, the potential of wiring 2606 remains equal to the power supply potential VD D in order to maintain the potential during period T3.

[0276] Subsequently, the operation during period T8 will be described. During period T8, an L signal is supplied to wiring 2605 and an L signal is supplied to wiring 2603 and an L signal is supplied to wiring 2604. Circuit 2601 does not supply anything to wiring 2606, and circuit 2602 does not supply anything to wiring 2606. Therefore, the potential of wiring 2606 remains equal to the power supply potential V DD in order to maintain the potential during period T3.

[0277] By the above operation, in period T1, circuit 2601 supplies the power supply potential VDD to wiring 2606, circuit 2602 supplies the power supply potential VDD to wiring 2606, and the potential of wiring 2606 is set to a value equal to the power supply potential VDD. In period T2, circuit 2602 supplies the power supply potential VDD to wiring 2 606, and the potential of wiring 2606 is set to a value equal to the power supply potential VDD. In period T3 circuit 2601 supplies the power supply potential VDD to wiring 2606, and the potential of wiring 2606 is set to the power supply potential VDD. In periods T4 to T8, wiring 2606 is put in a floating state, and the potential of wiring 2606 is maintained at a value equal to the power supply potential VDD.

[0278] Also, the basic circuit in Fig. 26(a) does not have a transistor that is on in all of periods T1 to T8. That is, it does not have a transistor that is constantly or almost constantly on. Therefore, the basic circuit in Fig. 26(a) can suppress the characteristic degradation of the transistor and the shift of the threshold voltage due to the characteristic degradation.

[0279] Note that this embodiment can be freely combined with any description in other embodiments in this specification. Also, any description in this embodiment can be freely combined and implemented.

[0280] (Fifth Embodiment) In this embodiment, the basic circuit described in the first embodiment is applied to a flip-flop circuit. This case will be described with reference to FIG. 27.

[0281] FIG. 27 is an example of a flip-flop circuit to which the basic circuit of FIG. 1(a) described in the first embodiment is applied. The flip-flop circuit of FIG. 27 includes transistors 2701, 2702, 2703, 2704, 2705, 2706, 2707, and 2708.

[0282] Note that transistor 2705 corresponds to transistor 101 in FIG. 1(a), transistor 2707 corresponds to transistor 103 in FIG. 1(a), and transistor 2706 corresponds to transistor 102 in FIG. 1(a). Also, transistors 2703 and 2704 correspond to transistor 104 in FIG. 1(a).

[0283] The connection relationship of the flip-flop circuit in FIG. 27 will be described. Note that the node connecting the second terminal of transistor 2701, the second terminal of transistor 2708, the gate of transistor 2706, the second terminal of transistor 2704, and the gate of transistor 2702 is defined as node N271. Also, the node connecting the second terminal of transistor 2705, the second terminal of transistor 2706, the second terminal of transistor 2707, the gate of transistor 2703, and the gate of transistor 2704 is defined as node N272.

[0284] The gate of transistor 2701 is connected to wiring 2712, the first terminal is connected to wiring 2709, and the second terminal is connected to node N271. The gate of transistor 2708 is connected to the is connected to line 2713, with its first terminal connected to wiring 2710 and its second terminal connected to node N271 is connected. The gate of transistor 2705 is connected to wiring 2709, its first terminal is connected to wiring 2709, and its second terminal is connected to node N272. The gate of transistor 27 06 is connected to node N271, its first terminal is connected to wiring 2710, and its second terminal is connected to node N272. The gate of transistor 2707 is connected to wiring 2711 and its first terminal is connected to wiring 2710, and its second terminal is connected to node N272. The gate of transistor 2704 is connected to node N272, its first terminal is connected to wiring 2710 continuously, and its second terminal is connected to node N271. The gate of transistor 2703 is connected to node N272, its first terminal is connected to wiring 2710, and its second terminal is connected to wiring 2714 is connected. The gate of transistor 2702 is connected to node N271, its first terminal is connected to wiring 2711, and its second terminal is connected to wiring 2714.

[0285] Also, transistors 2701 to 2708 are each of N-channel type.

[0286] Therefore, since the flip-flop circuit of FIG. 27 can be entirely composed of N-channel type transistors the flip-flop circuit of FIG. 27 can use amorphous silicon in the semiconductor layer and can simplify the manufacturing process. Therefore, the manufacturing cost can be reduced and the yield can be improved. Furthermore, it is also possible to fabricate semiconductor devices such as large display panels. Also, the flip-flop circuit of FIG. 27 can simplify the manufacturing process even when using poly silicon or single crystal silicon in the semiconductor layer.

[0287] Also, a power supply potential VDD is supplied to the wiring 2709, and a power supply potential VSS is supplied to the wiring 2710. Note that the power supply potential VDD is a potential higher than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to the wiring 2709 and the wiring 2710, or other power supply potentials may be supplied.

[0288] Also, signals are respectively supplied to the wiring 2711, the wiring 2712, and the wiring 2713. Note that the signals supplied to the wiring 2711, the wiring 2712, and the wiring 2713 are digital signals each having a binary value. However, a power supply potential VDD, a power supply potential VSS, or other power supply potentials may be respectively supplied to the wiring 2711, the wiring 2712, and the wiring 2713. Also, analog signals may be respectively supplied to the wiring 2711, the wiring 2712, and the wiring 2713.

[0289] Next, the operation of the flip-flop circuit shown in FIG. 27 will be described with reference to FIG. 28. .

[0290] FIG. 28 is an example of a timing chart of the flip-flop circuit shown in FIG. 27. The timing chart in FIG. 28 shows the potential of the wiring 2711, the potential of the wiring 2712, the potential of the node N271 , the potential of the node N272, the potential of the wiring 2714, the on / off relationship of the transistor 2703 and the transistor 2704, and the potential of the wiring 2713.

[0291] The timing chart in FIG. 28 will be described by dividing it into periods T1 to T4. Also, period T3 will be described by dividing it into period T3a and period T3b. Also, FIGS. 29, 30, 31, and FIG. 32. Figures 33 respectively show the operations of the flip-flop circuit in FIG. 27 during period T1, period T2, period T3b, period T4, and period T3a. The periods other than period T1, period T2, and period T3b repeat period T3a and period T4 in sequence.

[0292] First, the operation during period T1 will be described with reference to FIG. 29. During period T1, an L signal is supplied to wiring 2711, an H signal is supplied to wiring 2712, and an L signal is supplied to wiring 2713. Therefore, transistor 2701 turns on, transistor 2708 turns off, and transistor 2707 turns off. At this time, the power supply potential VDD is supplied to node N271 through transistor 2701, and the potential of node N271 rises. Also, transistor 2706 turns on due to the rise in the potential of node N271, and the potential of node N272 decreases. Also, transistors 2703 and 2704 turn off due to the decrease in the potential of node N272.

[0293] Here, the rise in the potential of node N271 continues until transistor 2701 turns off. Transistor 2701 turns off when the potential of node N271 reaches the value (VDD - Vth2701) obtained by subtracting the threshold voltage Vth2701 of transistor 2701 from the power supply potential VDD. Therefore, the potential of node N271 becomes VDD - Vth2701. Also, node N271 becomes a floating state. The potential of node N271 becomes VDD - Vth2701. Also, node N271 becomes a floating state.

[0294] Therefore, transistor 2702 turns on. Also, on wiring 2714, the signal on wiring 2711 is supplied. The power supply potential VDD is supplied to node N271 through transistor 2701, and the potential of node N271 rises. Also, transistor 2706 turns on due to the rise in the potential of node N271, and the potential of node N272 decreases. Also, transistors 2703 and 2704 turn off due to the decrease in the potential of node N272. Here, the rise in the potential of node N271 continues until transistor 2701 turns off. Transistor 2701 turns off when the potential of node N271 reaches the value (VDD - Vth2701) obtained by subtracting the threshold voltage Vth2701 of transistor 2701 from the power supply potential VDD. Therefore, the potential of node N271 becomes VDD - Vth2701. Also, node N271 becomes a floating state. The rise in the potential of node N271 continues until transistor 2701 turns off. Transistor 2701 turns off when the potential of node N271 reaches the value (VDD - Vth2701) obtained by subtracting the threshold voltage Vth2701 of transistor 2701 from the power supply potential VDD.

[0295] Here, the rise in the potential of node N271 continues until transistor 2701 turns off. Transistor 2701 turns off when the potential of node N271 reaches the value (VDD - Vth2701) obtained by subtracting the threshold voltage Vth2701 of transistor 2701 from the power supply potential VDD. Transistor 2701 turns off when the potential of node N271 reaches the value (VDD - Vth2701) obtained by subtracting the threshold voltage Vth2701 of transistor 2701 from the power supply potential VDD. Therefore, the potential of node N271 becomes VDD - Vth2701. Also, node N271 becomes a floating state. Therefore, the potential of node N271 becomes VDD - Vth2701. Also, node N271 becomes a floating state. Node N271 becomes a floating state.

[0296] Therefore, transistor 2702 turns on. Also, on wiring 2714, the signal on wiring 2711 Since the L signal of is supplied, the potential of the wiring 2714 becomes equal to the power supply potential VSS.

[0297] Subsequently, the operation in the period T2 will be described with reference to FIG. 30. In the period T2, an H signal is supplied to the wiring 27 11, an L signal is supplied to the wiring 2712, and an L signal is supplied to the wiring 2713.

[0298] Accordingly, the transistor 2701 turns off, the transistor 2708 remains off, and the transistor 2707 turns on. At this time, the node N271 is in a floating state, and the potential of the node N271 maintains VDD - Vth2701. Also, the potential of the node N 272 remains at the L level because the transistors 2706 and 2707 are on. Therefore, since the node N272 is at the L level, the transistors 2 703 and 2704 remain off.

[0299] Here, the node N271 is in a floating state and maintains the H level. Also, the transistor 2702 remains on because the node N271 maintains the H level. Moreover, since the H signal of the wiring 2711 is supplied to the wiring 2714, the potential of the wiring 2714 is rising. Accordingly, due to the bootstrap operation, the potential of the node N271 becomes equal to or higher than the sum of the power supply potential VDD and the threshold voltage Vth2702 of the transistor 2702 (VDD + Vt h2702), and the potential of the wiring 2714 becomes equal to the power supply potential VDD.

[0300] Subsequently, the operation in the period T3b will be described with reference to FIG. 31. In the period T3b, an L signal is supplied to the wiring 2711, an L signal is supplied to the wiring 2712, and an H signal is supplied to the wiring 2713.​ is supplied.

[0301] Therefore, transistor 2701 remains off, transistor 2708 turns on, and transistor 2707 turns off. At this time, the power supply potential VSS is supplied to node N271 via transistor 27 08, and the potential of node N271 decreases. Also, transistor 27 06 turns off due to the decrease in the potential of node N271, and the potential of node N272 rises. Also, transistors 2703 and 2704 turn on due to the rise in the potential of node N272.

[0302] Also, transistor 2702 turns off due to the decrease in the potential of node N271. Therefore, since the power supply potential VSS is supplied to wiring 2714 via transistor 2703, the potential of wiring 2714 becomes equal to the power supply potential VSS.

[0303] Next, the operation in period T4 will be described with reference to FIG. 32. In period T4, an H signal is supplied to wiring 27 11, an L signal is supplied to wiring 2712, and an L signal is supplied to wiring 2713. is supplied.

[0304] Therefore, transistor 2701 remains off, transistor 2708 turns off, and transistor 2707 turns on. At this time, node N271 becomes floating, and the potential of node N271 maintains the power supply potential VSS. Therefore, transistors 2706 and 2702 turn off. Also, since the power supply potential VSS is supplied to node N272 via transistor 2707, the potential becomes L level. Therefore, transistors 2703 and 2704 turn off. ​

[0305] Therefore, the wiring 2714 becomes in a floating state, and the potential of the wiring 2714 maintains a value equal to the power supply potential VSS.

[0306] Subsequently, the operation in the period T3a will be described with reference to FIG. 33. In the period T3a, an L signal is supplied to the wiring 2711, an L signal is supplied to the wiring 2712, and an L signal is supplied to the wiring 2713 is being supplied.

[0307] Therefore, the transistor 2701 remains off, the transistor 2708 remains off and the transistor 2707 turns off. At this time, the potential of the node N272 rises because the transistor 2707 turns off. Therefore, the transistors 2703 and the transistor 2704 turn on. Also, the power supply potential VSS is supplied to the node N271 via the transistor 2704, and the potential of the node N271 becomes a value equal to the power supply potential VSS. Thus the transistors 2702 and 2706 remain off.

[0308] Also, the power supply potential VSS is supplied to the wiring 2714 via the transistor 2703, and the potential of the wiring 2714 maintains a value equal to the power supply potential VSS.

[0309]

[0310] ​​​​​​​Also, in period T3a, in the flip-flop circuit of FIG. 27, transistors 2703, and transistor 2704 turn on to supply the power supply potential VSS to wiring 2714 and node N27 1. Also, in period T4, the flip-flop circuit of FIG. 27 turns off transistors 2703 and transistor 2704. Therefore, in the flip-flop circuit of FIG. 27, since transistors 2703 and transistor 2704 turn on in sequence, the degradation of the characteristics of transistors 2703 and transistor 2704 can be suppressed, and the potentials of node N271, and wiring 2714 can be stably maintained at a value equal to the power supply potential VSS. Also, the flip-flop circuit of FIG. 27 does not have a transistor that is on in all periods from period T1 to period T4. That is, it does not have a transistor that is constantly or almost constantly on.

[0311] Therefore, the flip-flop circuit of FIG. 27 can suppress the degradation of transistor characteristics and the shift of the threshold voltage due to characteristic degradation. Also, the characteristics of a transistor tend to degrade when the transistor is formed of amorphous silicon. Therefore, by forming the transistors of the flip-flop circuit of FIG. 27 with amorphous silicon, not only merits such as cost reduction in manufacturing and improvement in yield can be obtained, but also the problem of characteristic degradation of the transistors can be solved.

[0312] Here, the functions of transistors 2701 to 2708 will be described. Transistor 2701 connects wiring 2709 and node N271 according to the potential of wiring 2712, or disconnects them.

[0313] Here, the functions of transistors 2701 to 2708 will be described. Transistor 2701 connects or It has a function as a switch for selecting whether to do it or not. Transistor 2702 selects whether to connect wiring 2711 and wiring 2714 according to the potential of node N2 71 and has a function as a switch. Transistor 2703 selects whether to connect wiring 2710 and wiring 2714 according to the potential of node N272 and has a function as a switch. Transistor 2704 selects whether to connect wiring 2710 and node N 271 according to the potential of node N272 and has a function as a switch. Transistor 2705 has a function as a diode with the input terminal as the first terminal and the gate, and the output terminal as the second terminal . Transistor 2706 selects whether to connect wiring 2710 and node N272 according to the potential of node N271 and has a function as a switch. Transistor 2707 selects whether to connect wiring 2710 and node N 272 according to the potential of wiring 2711 and has a function as a switch. Transistor 2708 selects whether to connect wiring 2710 and node N271 according to the potential of wiring 2713 and has a function as a switch. Note that transistors 2705, 2706, and 2707 constitute a 2-input NOR circuit 2715 with node N271 and wiring 2711 as input terminals and node N272 as the output terminal .

[0314] Note that transistor 2705 may be an element having a resistance component. For example, as shown in FIG. 34 , a resistance element 3401 can be used instead of transistor 2705. Resistance

[0315] By using the resistor 3401, the potential at the node N272 can be set to a value equal to the power supply potential VDD. This is possible.

[0316] As shown in FIG. 35, a capacitor 3501 may be disposed between the gate of the transistor 2702 (node N271) and the second terminal (wiring 2714). This is because, during the period T2, the potential at the node N271 and the potential of the wiring 2714 are raised by the bootstrap operation. Therefore, by disposing the capacitor 3501, the flip-flop circuit becomes more likely to perform the bootstrap operation. This is why.

[0317] Note that the transistor 2701 only needs to make the node N271 floating and set the potential of the node N271 to the H level during the period T1. Therefore, even if the first terminal of the transistor 27 01 is connected to the wiring 2712, the node N271 can be made floating and the potential of the node N271 can be set to the H level.

[0318] Next, the case where the flip-flop circuit shown in FIG. 27 is composed of P-channel transistors will be described with reference to FIG. 44.

[0319] FIG. 44 is an example of a flip-flop circuit to which the basic circuit of FIG. 13(a) described in the first embodiment is applied. The flip-flop circuit of FIG. 44 includes transistors 4401, tra nsistors 4402, transistors 4403, transistors 4404, transistors 440 5, transistors 4406, transistors 4407, and transistors 4408. It has. That's it.

[0320] Note that the transistor 4405 is the transistor 1301 in FIG. 13(a), and the transistor 44 07 corresponds to transistor 1302 in Fig. 13(a), and transistor 4406 corresponds to transistor 1303 in Fig. 13(a), respectively. Also, transistor 4403 and transistor 4404 correspond to transistor 1304 in Fig. 13(a).

[0321] The connection relationship of the flip-flop circuit in Fig. 44 will be described. Note that the node of the second terminal of transistor 440 1, the second terminal of transistor 4408, the gate of transistor 4406, and the second terminal of transistor 4404 and the gate of transistor 4402 is designated as node N441 . Also, the node of the second terminal of transistor 4405, the second terminal of transistor 4406, the second terminal of transistor 4407, the gate of transistor 4403, and the gate of transistor 4404 is designated as node N442 . The gate of transistor 4401 is connected to wiring 4412, the first terminal is connected to wiring 4409 , and the second terminal is connected to node N441. The gate of transistor 4408 is connected to wiring

[0322] 4413, the first terminal is connected to wiring 4410, and the second terminal is connected to node N441 . The gate of transistor 4405 is connected to wiring 4409, the first terminal is connected to wiring 4409, and the second terminal is connected to node N442. The gate of transistor 44 06 is connected to node N441, the first terminal is connected to wiring 4410, and the second terminal is connected to node N442. The gate of transistor 4407 is connected to wiring 4411 , the first terminal is connected to wiring 4410, and the second terminal is connected to node N442 . The gate of transistor 4404 is connected to node N442, the first terminal is connected to wiring 4410 , and the second terminal is connected to node N442. ​Continuing, the second terminal is connected to node N441. The gate of transistor 4403 is connected to node N442, the first terminal is connected to wiring 4410, and the second terminal is connected to wiring 4414. The gate of transistor 4402 is connected to node N441, the first terminal is connected to wiring 4411, and the second terminal is connected to wiring 4414.

[0323] Also, transistors 4401 to 4408 are each of P-channel type.

[0324] Therefore, the flip-flop circuit in FIG. 44 can be entirely composed of P-channel type transistors, eliminating the need for a process to form N-channel type transistors. Therefore, the flip-flop circuit in FIG. 44 can simplify the manufacturing process, reducing manufacturing costs and improving yield.

[0325] Also, the power supply potential VDD is supplied to wiring 4410, and the power supply potential VSS is supplied to wiring 4409. Note that the power supply potential VDD is at a higher potential than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to wiring 4409 and wiring 4410, or other power supply potentials may be supplied.

[0326] Also, signals are respectively supplied to wiring 4411, wiring 4412, and wiring 4413. Note that the signals supplied to wiring 4411, wiring 4412, and wiring 4413 are digital signals each having a binary value. However, power supply potential VDD, power supply potential VSS, or other power supply potentials may be respectively supplied to wiring 4411, It may also be provided. Further, analog signals may be supplied to the wiring 4411, the wiring 4412, and the wiring 4413, respectively.

[0327] Next, the operation of the flip-flop circuit shown in FIG. 44 will be described with reference to FIG. 45. .

[0328] FIG. 45 is an example of a timing chart of the flip-flop circuit shown in FIG. 44. The timing chart of FIG. 45 shows the potential of the wiring 4411, the potential of the wiring 4412, the potential of the node N441, the potential of the node N442, the potential of the wiring 4414, the on / off relationship of the transistors 4403 and 4404, and the potential of the wiring 4413. The timing chart of FIG. 44 will be described by dividing it into periods T1 to T4. Further, the period T3 will be described by dividing it into a period T3a and a period T3b.

[0329] Note that the periods other than the period T1, the period T2, and the period T3b repeat the period T3a and the period T4 in this order.

[0330]

[0331] First, the operation in the period T1 will be described. In the period T1, an H signal is supplied to the wiring 4411, an L signal is supplied to the wiring 4412, and an H signal is supplied to the wiring 4413. Accordingly, the transistor 4401 is turned on, the transistor 4408 is turned off, and the transistor 4407 is turned off. At this time, the power supply potential VSS is supplied to the node N441 through the transistor 4401, and the potential of the node N441 decreases. Further, the transistor 4406 is turned on due to the decrease in the potential of the node N441, and the potential of the node N442 increases.

[0332] ​​​​​​​​​​。Also, the transistors 4403 and 4404 are turned off by the increase in the potential of the node N442. Thereby.

[0333] Here, the decrease in the potential of the node N441 continues until the transistor 4401 is turned off. The transistor 4401 is turned off when the potential of the node N441 reaches the sum of the power supply potential VSS and the absolute value of the threshold voltage Vth4401 of the transistor 4401 (VSS + |Vth4401|). Therefore, the potential of the node N441 becomes VSS + |Vth4401|. Also, the node N441 becomes in a floating state. Therefore, the transistor 4402 is turned on. Also, since the H signal of the wiring 4411 is supplied to the wiring 4414, the potential of the wiring 4414 becomes equal to the power supply potential VDD.

[0334] Subsequently, the operation in the period T2 will be described. In the period T2, an L signal is supplied to the wiring 4411, an H signal is supplied to the wiring 4412, and an H signal is supplied to the wiring 4413. Therefore, the transistor 4401 is turned off, the transistor 4408 remains off, and the transistor 4407 is turned on. At this time, the node N441 is in a floating state, and the potential of the node N441 maintains VSS + |Vth4401|. Also,

[0335] Since the potential of the node N442 is at the H level because the transistors 4406 and 4407 are turned on, the transistors 4403 and 4404 remain off. Here, the potential of the node N442 is at the H level, so the transistors 4403 and 4404 remain off.

[0336] Therefore, the transistor 4401 is turned off, the transistor 4408 remains off, and the transistor 4407 is turned on. At this time, the node N441 is in a floating state, and the potential of the node N441 maintains VSS + |Vth4401|. Also, the potential of the node N442 remains at the H level because the transistors 4406 and 4407 are turned on. Thus, since the node N442 is at the H level, the transistors 4403 and 4404 remain off. state, and the potential of the node N441 maintains VSS + |Vth4401|. Also, the potential of the node N442 remains at the H level because the transistors 4406 and 4407 are turned on. Therefore, since the node N442 is at the H level, the transistors 4403 and 4404 remain off. Here, the potential of the node N442 is at the H level, so the transistors 4403 and 4404 remain off. Therefore, the transistors 4403 and 4404 remain off.

[0337] Here, node N441 is in a floating state and maintains the L level. Also, the transistor 4402 remains on because node N441 maintains the L level. Also, since the L signal of wiring 4411 is supplied to wiring 4414, the potential of wiring 4414 is decreasing. Therefore, due to the bootstrap operation, the potential of node N441 becomes a value obtained by subtracting the absolute value of the threshold voltage Vth4402 of transistor 4402 from the power supply (VSS - |Vth4402|) or less, and the potential of wiring 4414 becomes equal to the power supply potential VSS at the threshold value.

[0338] Subsequently, the operation during period T3b will be described. During period T3b, an H signal is supplied to wiring 4411, an H signal is supplied to wiring 4412, and an L signal is supplied to wiring 4413.

[0339] Therefore, transistor 4401 remains off, transistor 4408 turns on, and transistor 4407 turns off. At this time, the power supply potential VDD is supplied to node N441 via transistor 44 08, and the potential of node N441 rises. Also, transistor 4406 turns off due to the rise in the potential of node N441, and the potential of node N442 decreases. Also, transistors 4403 and 4404 turn on due to the decrease in the potential of node N442. Also, transistor 4402 turns off due to the rise in the potential of node N441. Therefore, since the power supply potential VDD is supplied to wiring 4414 via transistor 4403, the potential of wiring 4414 becomes equal to the power supply potential VDD.

[0340] Also, transistor 4402 turns off due to the rise in the potential of node N441. Therefore, since the power supply potential VDD is supplied to wiring 4414 via transistor 4403, the potential of wiring 4414 becomes equal to the power supply potential VDD.

[0341] Next, the operation in period T4 will be described. In period T4, an L signal is supplied to wiring 4411 and an H signal is supplied to wiring 4412, and an H signal is supplied to wiring 4413.

[0342] Therefore, transistor 4401 remains off, transistor 4408 turns off and transistor 4407 turns on. At this time, node N441 becomes floating and the potential of node N441 maintains the power supply potential VDD. Therefore, transistors 4406 and transistor 4402 turn off. Also, since the potential of node N442 is supplied with the power supply potential VDD via transistor 4407, it becomes the H level. Therefore, transistors 4403 and transistor 4404 turn off.

[0343] Therefore, wiring 4414 becomes floating and the potential of wiring 4414 maintains a value equal to the power supply potential VDD.

[0344] Next, the operation in period T3a will be described. In period T3a, an H signal is supplied to wiring 4411 and an H signal is supplied to wiring 4412, and an H signal is supplied to wiring 4413.

[0345] Therefore, transistor 4401 remains off, transistor 4408 remains off and transistor 4407 turns off. At this time, the potential of node N442 decreases because transistor 4407 turns off. Therefore, transistors 4403 and transistor 4404 turn on. Also, the power supply potential VDD is supplied to node N441 via transistor 4404, and the potential of node N441 becomes a value equal to the power supply potential VDD. Thus, ​​​Thus, transistor 4402 and transistor 4406 remain off.

[0346] Also, power supply potential VDD is supplied to wiring 4414 via transistor 4403, and the potential of wiring 4414 maintains a value equal to power supply potential VDD.

[0347] By the above operations, in period T1, the flip-flop circuit in FIG. 44 sets node N441 to the floating state while remaining at the L level. In period T2, the flip-flop circuit in FIG. 44 can, by bootstrap operation, lower the potential of node N441 to VSS - |Vth4402| or lower and make the potential of wiring 4414 equal to power supply potential VSS.

[0348] Also, in period T3a, the flip-flop circuit in FIG. 44 turns on transistor 4403 and transistor 4404 to supply power supply potential VDD to wiring 4414 and node N44 1. Also, in period T4, the flip-flop circuit in FIG. 44 turns off transistor 4403 and transistor 4404. Therefore, in the flip-flop circuit in FIG. 44, since transistor 4403 and transistor 4404 turn on in sequence, deterioration of the characteristics of transistor 4403 and transistor 4404 can be suppressed, and the potentials of node N441 and wiring 4414 can be stably maintained at a value equal to power supply potential VDD.

[0349] Also, the flip-flop circuit in FIG. 44 does not have a transistor that is on in all periods from period T1 to period T4. That is, it does not have a transistor that is constantly or almost constantly on. Therefore, the flip-flop circuit in FIG. 44 has Deterioration and shift of the threshold voltage due to characteristic deterioration can be suppressed.

[0350] Note that transistors 4401 to 4408 have the same functions as transistors 2701 to transistors 2708.

[0351] Note that transistors 4405, 4406, and 4407 form a 2-input NAND circuit 4415 with node N441 and wiring 4411 as input terminals and node N442 as the output terminal.

[0352] Note that transistor 4405 may be an element having a resistance component. For example, as shown in FIG. 46, a resistance element 4601 can be used instead of transistor 4405. By using the resistance element 4601, a value equal to the power supply potential VSS can be set at the potential of node N442.

[0353] Note that, as shown in FIG. 47, a capacitance element 4701 may be arranged between the gate (node N441) of transistor 4402 and the second terminal (wiring 4414). This is because, during period T2, the potential of node N441 and the potential of wiring 4414 are raised by bootstrap operation. Therefore, by arranging the capacitance element 4701, the flip-flop circuit can easily perform bootstrap operation.

[0354] Note that during period T1, transistor 4401 only needs to make node N441 in a floating state and be able to set the potential of node N441 to the L level. Therefore, even if the first terminal of transistor 4401 is connected to wiring 4412, node N441 can be made in a floating state.The potential of node N441 can be set to the L level.

[0355] In addition, this embodiment can be freely combined with any description of other embodiments in this specification. It can be implemented. Also, any descriptions in this embodiment can be freely combined and implemented. It can be done.

[0356] (Sixth Embodiment) In this embodiment, the case where the basic circuit described in the second embodiment is applied to a flip - flop circuit will be described with reference to FIG. 36. Referring to FIG. 36, the case where the basic circuit of FIG. 5(a) described in the second embodiment is applied to a flip - flop circuit will be described.

[0357] FIG. 36 is an example of a flip - flop circuit to which the basic circuit of FIG. 5(a) described in the second embodiment is applied. The flip - flop circuit of FIG. 36 includes transistors 3600, 3601, 3602, 3603, 3604, transistors 3605, 3606, 3607, 3608, 3609, and transistor 3610.

[0358] Note that transistor 3605 corresponds to transistor 501 in FIG. 5(a), transistor 3607 corresponds to transistor 502 in FIG. 5(a), transistor 3606 corresponds to transistor 503 in FIG. 5(a), transistor 3608 corresponds to transistor 504 in FIG. 5(a), transistor 3610 corresponds to transistor 505 in FIG. 5(a), and transistor 3609 corresponds to transistor 506 in FIG. 5(a). Also, transistors 3603 and 3604 correspond to transistor 507 in FIG. 5(a).

[0359] The connection relationship of the flip - flop circuit in FIG. 36 will be described. Note that transistor 360​​​​​​​​ The node of the second terminal of 1, the second terminal of transistor 3600, the gate of transistor 3606, and the second terminal of transistor 3604 and the gate of transistor 3602 is defined as node N361. Also, the node of the second terminal of transistor 3605, the second terminal of transistor 3606, the second terminal of transistor 3607, and the gate of transistor 3608 is defined as node N362. Also, the node of the second terminal of transistor 3609, the second terminal of transistor 3608, the second terminal of transistor 3610, the gate of transistor 3603, and the gate of transistor 3604 is defined as node N363. The gate of transistor 3601 is connected to wiring 3614, the first terminal is connected to wiring 3611, and the second terminal is connected to node N361. The gate of transistor 3600 is connected to wiring 3615, the first terminal is connected to wiring 3612, and the second terminal is connected to node N361. The gate of transistor 3606 is connected to node N361, the first terminal is connected to wiring 3612, and the second terminal is connected to node N362. The gate of transistor 3605 is connected to wiring 3611, the first terminal is connected to wiring 3611, and the second terminal is connected to node N362. The gate of transistor 3607 is connected to wiring 3613, the first terminal is connected to wiring 3612, and the second terminal is connected to node N362. The gate of transistor 3608 is connected to node N362, the first terminal is connected to wiring 3611, and the second terminal is connected to node N363. The gate of transistor 3609 is connected to node N361, the first terminal is connected to wiring 3612, and the second terminal is connected to node N363.

[0360] The gate of transistor 3601 is connected to wiring 3614, the first terminal is connected to wiring 3611, and the second terminal is connected to node N361. The gate of transistor 3600 is connected to wiring 3615, the first terminal is connected to wiring 3612, and the second terminal is connected to node N361. The gate of transistor 3606 is connected to node N361, the first terminal is connected to wiring 3612, and the second terminal is connected to node N362. The gate of transistor 3605 is connected to wiring 3611, the first terminal is connected to wiring 3611, and the second terminal is connected to node N362. The gate of transistor 3607 is connected to wiring 3613, the first terminal is connected to wiring 3612, and the second terminal is connected to node N362. The gate of transistor 3608 is connected to node N362, the first terminal is connected to wiring 3611, and the second terminal is connected to node N363. The gate of transistor 3609 is connected to node N361, the first terminal is connected to wiring 3612, and the second terminal is connected to node N363. The gate of transistor 3601 is connected to wiring 3614, the first terminal is connected to wiring 3611, and the second terminal is connected to node N361. The gate of transistor 3600 is connected to wiring 3615, the first terminal is connected to wiring 3612, and the second terminal is connected to node N361. The gate of transistor 3606 is connected to node N361, the first terminal is connected to wiring 3612, and the second terminal is connected to node N362. The gate of transistor 3605 is connected to wiring 3611, the first terminal is connected to wiring 3611, and the second terminal is connected to node N362. is connected. The gate of transistor 3610 is connected to wiring 3613, and the first terminal is connected to wiring 3612, and the second terminal is connected to node N363. Transistor 36 04 has its gate connected to node N363, its first terminal connected to wiring 3612, and its second terminal connected to node N361. The gate of transistor 3603 is connected to node N363 and its first terminal is connected to wiring 3612, and its second terminal is connected to wiring 3616. The gate of transistor 3602 is connected to node N361, its first terminal is connected to wiring 3613 and its second terminal is connected to wiring 3616.

[0361] Also, transistors 3600 to 3610 are each of N-channel type.

[0362] Therefore, since all the flip-flop circuits in FIG. 36 can be composed of N-channel type transistors, the flip-flop circuit in FIG. 36 can use an amorphous silicon in the semiconductor layer and can simplify the manufacturing process. Therefore, manufacturing cost can be reduced and yield can be improved. Furthermore, it becomes possible to fabricate semiconductor devices such as large display panels. Also, the flip-flop circuit in FIG. 36 can simplify the manufacturing process even when using polysilicon or single-crystalline silicon in the semiconductor layer.

[0363] Also, a power supply potential VDD is supplied to wiring 3611, and a power supply potential VSS is supplied to wiring 3612. Note that the power supply potential VDD is at a higher potential than the power supply potential VSS. However digital signals, analog signals, etc. may be supplied to wiring 3611 and wiring 3612, or other power supply potentials may be supplied.

[0364] Also, signals are supplied to wiring 3613, wiring 3614, and wiring 3615, respectively. Note that the signals supplied to wiring 3613, wiring 3614, and wiring 3615 are digital signals each having a binary value. However, power supply potential VDD, power supply potential VSS, or other power supply potential may be supplied to wiring 3613, wiring 3614, and wiring 3615, respectively. Also, analog signals may be supplied to wiring 3613, wiring 3614, and wiring 3615, respectively.

[0365] Next, the operation of the flip-flop circuit shown in FIG. 36 will be described with reference to FIG. 37. .

[0366] FIG. 37 is an example of a timing chart of the flip-flop circuit shown in FIG. 36. The timing chart of FIG. 37 shows the potential of wiring 3613, the potential of wiring 3614, the potential of node N361, the potential of node N362, node N363, the potential of wiring 3616, and the on / off relationship of transistors 3603 and 3604, and the potential of wiring 3615.

[0367] The timing chart of FIG. 37 will be described by dividing it into periods T1 to T4. Also, period T3 will be described by dividing it into period T3a and period T3b.

[0368] Note that the periods other than period T1, period T2, and period T3b repeat period T3a and period T4 in order.

[0369] First, the operation in period T1 will be described. In period T1, an L signal is supplied to wiring 3613, an H signal is supplied to wiring 3614, and an L signal is supplied to wiring 3615. ​​​​​​​​​

[0370] Therefore, transistor 3601 turns on, transistor 3600 turns off, and transistors 3607 and 3610 turn off. At this time, node N36 1 is supplied with the power supply potential VDD via transistor 3601, and the potential of node N361 rises. Also, transistors 3606 and 3609 turn on due to the rising potential of node N361 , and the potentials of nodes N362 and N363 decrease. Also, transistor 3608 turns off due to the decreasing potential of node N362. Also, transistors 3603 and 3604 turn off due to the decreasing potential of node N363.

[0371] Here, the rising of the potential of node N361 continues until transistor 3601 turns off. Transistor 3601 turns off when the potential of node N361 reaches a value (VDD - Vth3601) obtained by subtracting the threshold voltage Vth3601 of transistor 3601 from the power supply potential VDD. Therefore, the potential of node N361 becomes VDD - Vth3601. Also, node N36 1 becomes a floating state.

[0372] Therefore, transistor 3602 turns on. Also, since the L signal of wiring 3613 is supplied to wiring 3616, the potential of wiring 3616 becomes equal to the power supply potential VSS .

[0373] Subsequently, the operation in period T2 will be described. In period T2, an H signal is supplied to wiring 3613, an L signal is supplied to wiring 3614, and an L signal is supplied to wiring 3615.

[0374] ​​Therefore, transistor 3601 turns off, and transistor 3600 remains off while transistors 3607 and 3610 turn on. At this time, node N361 is in a floating state, and the potential of node N361 is VDD - Vth3601 being maintained. Also, the potential of node N362 remains at the L level because transistors 3606 and transistor 3607 are on. Further, the potential of node N363 remains at the L level because transistors 3609 and 3610 are on. Thus, since node N363 is at the L level, transistors 3603 and 3604 remain off.

[0375] Here, node N361 is in a floating state and maintains the H level. Also, transistor 3602 remains on because node N361 maintains the H level . Also, since the H signal of wiring 3613 is supplied to wiring 3616, the potential of wiring 3616 is rising. Therefore, due to the bootstrap operation, the potential of node N361 becomes equal to or higher than the sum of the power supply potential VDD and the threshold voltage Vth3602 of transistor 3602 (VD D + Vth3602), and the potential of wiring 3616 becomes equal to the power supply potential VDD .

[0376] Subsequently, the operation during period T3b will be described. During period T3b, an L signal is supplied to wiring 3613, an L signal is supplied to wiring 3614, and an H signal is supplied to wiring 3615.

[0377] Therefore, transistor 3601 remains off, and transistor 3600 turns on Then, transistor 3607 and transistor 3610 turn off. At this time, the power supply potential VSS is supplied to node N361 via transistor 3600, and the potential of node N361 decreases. Also, transistor 3606 and transistor 3607 turn off due to the decrease in the potential of node N361. Therefore, the potentials of node N362 and node N363 rise by the bootstrap operation. The potential of node N362 rises to be equal to or higher than the sum of the power supply potential VDD and the threshold voltage Vth3608 of transistor 3608 (VDD + Vth3608). The potential of node N363 rises to the power supply potential VDD. Therefore, transistor 3603 and transistor 3604 turn on due to the rise in

[0378] the potential of node N363. Also, transistor 3602 turns off due to the decrease in the potential of node N361. Therefore, since the power supply potential VSS is supplied to wiring 3616 via

[0379] transistor 3603, the potential of wiring 3616 becomes equal to the power supply potential VSS.

[0380] Subsequently, the operation in period T4 will be described. In period T4, an H signal is supplied to wiring 3613, an L signal is supplied to wiring 3614, and an L signal is supplied to wiring 3615. Therefore, transistor 3601 remains off, transistor 3600 turns off, and 9 remains off. Also, since the potential of node N362 is supplied with the power supply potential VSS via transistor 3607, it becomes the L level. Therefore, transistor 3608 turns off. Also, since the potential of node N363 is supplied with the power supply potential VSS via transistor 3610, it becomes the L level. Therefore, transistors 3603 and 3604 turn off. Accordingly, wiring 3616 becomes a floating state, and the potential of wiring 3616 maintains a value equal to the power supply potential VSS. Subsequently, the operation in period T3a will be described. In period T3a, an L signal is supplied to wiring 3613, an L signal is supplied to wiring 3614, and an L signal is supplied to wiring 3615. Therefore, transistor 3601 remains off, transistor 3600 remains off, and transistors 3607 and 3610 turn off. At this time, node N361 is in a floating state, and the potential of node N361 remains at the L level. Therefore, transistors 3602, 3606, and 3609 remain off. Also, the potential of node N362 and the potential of node N363 increase due to the bootstrap operation. The potential of node N362 increases to be equal to or higher than the sum (VDD + Vth3608) of the power supply potential VDD and the threshold voltage Vth3608 of transistor 3608. The potential of node N363 increases to the power supply potential VDD. Therefore, transistors 3603 and 3604 turn on due to the increase in the potential of node N363.

[0381]

[0382]

[0383]

[0384] ​​​​​​​​​​​​​​​ Therefore, the power supply potential VSS is supplied to the wiring 3616 via the transistor 3603, so that the potential of the wiring 3616 maintains a value equal to the power supply potential VSS.

[0385] By the above operation, in the period T1, the flip-flop circuit in FIG. 36 sets the node N361 to the floating state while remaining at the H level. In the period T2, the flip-flop circuit in FIG. 36 can raise the potential of the node N361 to VDD + Vth3602 or higher by the bootstrap operation and set the potential of the wiring 3616 to a value equal to the power supply potential VDD.

[0386] Also, in the period T3a, in the flip-flop circuit in FIG. 36, the transistors 3603, and 3604 are turned on to supply the power supply potential VSS to the wiring 3616 and the node N36 1. Further, in the period T4, the flip-flop circuit in FIG. 36 turns off the transistors 3603 and 3604. Therefore, in the flip-flop circuit in FIG. 36, since the transistors 3603 and 3604 are turned on in sequence, the degradation of the characteristics of the transistors 3603 and 3604 can be suppressed, and the potentials of the node N361, and the wiring 3616 can be stably maintained at a value equal to the power supply potential VSS.

[0387] Also, the flip-flop circuit in FIG. 36 can set the potential of the node N 363 to a value equal to the power supply potential VDD in the periods T3a and T3b. Therefore, even if the characteristics of the transistors 3603 and 3604 deteriorate, the flip-flop circuit in FIG. 36 can be operated under a wide range of operating conditions.

[0388] ​In addition, the flip-flop circuit of FIG. 36 is in an on state during all of periods T1 to T4. There is no transistor that is in an on state constantly or almost constantly. That is, there is no transistor that is in an on state constantly or almost constantly. Therefore, the flip-flop circuit of FIG. 36 can suppress degradation of transistor characteristics and shift of the threshold voltage due to characteristic degradation.

[0389] In addition, transistor characteristics are likely to degrade when the transistor is formed of amorphous silicon. Therefore, by forming the transistors of the flip-flop circuit of FIG. 36 of amorphous silicon, not only can merits such as reduction of manufacturing cost and improvement of yield be obtained, but also the problem of transistor characteristic degradation can be solved.

[0390] Here, the functions of transistors 3600 to 3610 will be described. Transistor 3600 has a function as a switch that selects whether to connect wiring 3612 and node N361 according to the potential of wiring 3615. Transistor 3601 has a function as a switch that selects whether to connect wiring 36 14 and node N361 according to the potential of wiring 3614. Transistor 3602 has a function as a switch that selects whether to connect wiring 3613 and wiring 3616 according to the potential of node N361. Transistor 3603 has a function as a switch that selects whether to connect wiring 3612 and wiring 3 616 according to the potential of node N363. Transistor 3604 has a function as a switch that selects whether to connect wiring 3612 and node N361 according to the potential of node N363. Transistor 3605 has a function as a switch that selects whether to connect wiring 3612 and node N361 according to the potential of node N363. Transistor 3605 has an input terminal has a function as a diode with the first terminal and the gate, and the output terminal as the second terminal. The transistor 3606 has a function as a switch that selects whether to connect the wiring 3612 and the node N 362 according to the potential of the node N361. The transistor 3607 has a function as a switch that selects whether to connect the wiring 3612 and the node N362 according to the potential of the wiring 3613. The transistor 3608 has a function as a switch that selects whether to connect the wiring 3611 and the node N3 62 according to the potential of the node N362. The transistor 3609 has a function as a switch that selects whether to connect the wiring 3612 and the node N363 according to the potential of the node N361. The transistor 3609 has a function as a switch that selects whether to connect the wiring 3612 and the node N363 according to the potential of the node N361. The transistor 3610 has a function as a switch that selects whether to connect the wiring 3612 and the node N 363 according to the potential of the wiring 3613. The transistor 3610 has a function as a switch that selects whether to connect the wiring 3612 and the node N

[0391] Note that the transistors 3605, 3606, 3607, 3608, 3609, and 3610 constitute a 2-input NOR circuit 3617 with the node N36 1 and the wiring 3613 as input terminals and the node N363 as the output terminal. 1 and the wiring 3613 as input terminals and the node N363 as the output terminal. is configured.

[0392] Note that, as shown in FIG. 38, a capacitive element 3801 may be disposed between the gate (node N362) of the transistor 3608 and the second terminal (node N363). This is because the potentials of the node N362 and the node N363 are raised by the bootstrapping operation during the period T3a and the period T3b. Therefore, by disposing the capacitive element 3801, the glitch can be reduced. This is because the flip-flop circuit is more likely to perform a bootstrap operation.

[0393] Note that, as shown in FIG. 39, the transistor 3607 is not necessarily required.

[0394] Note that, as shown in FIG. 40, a capacitive element 4111 may be disposed between the gate (node N361) of the transistor 3602 and the second terminal (wiring 3616). This is because, during the period T2, the potential of the node N361 and the potential of the wiring 3616 are raised by the bootstrap operation, and thus, by disposing the capacitive element 4111, the flip-flop circuit becomes more likely to perform a bootstrap operation. This is because the flip-flop circuit is more likely to perform a bootstrap operation.

[0395] Note that the transistor 3601 only needs to put the node N361 in a floating state and raise the potential of the node N361 to the H level during the period T1. Therefore, even if the first terminal of the transistor 36 01 is connected to the wiring 3614, the node N361 can be put in a floating state and the potential of the node N361 can be raised to the H level.

[0396] Next, a flip-flop circuit configured with P-channel transistors as shown in FIG. 36 will be described with reference to FIG. 48. Refer to FIG. 48 for the description.

[0397] FIG. 48 is an example of a flip-flop circuit to which the basic circuit of FIG. 17(a) described in the second embodiment is applied. The flip-flop circuit of FIG. 48 includes transistors 4800, tra nsistors 4801, transistors 4802, transistors 4803, transistors 480 4, transistors 4805, transistors 4806, transistors 4807, transistors 480 8, transistors 4809, and transistors 4810. has transistors 4808, transistors 4809, and transistors 4810.

[0398] Note that transistor 4805 corresponds to transistor 1701 in Fig. 17(a), transistor 48 07 corresponds to transistor 1702 in Fig. 17(a), transistor 4806 corresponds to the t ransistor 1703 in Fig. 17(a), transistor 4808 corresponds to transistor 1704 in Fig. 17(a), t ransistor 4810 corresponds to transistor 1705 in Fig. 17(a), and transistor 4809 corresponds to t he transistor 1706 in Fig. 17(a), respectively. Also, transistor 4803 , and transistor 4804 correspond to transistor 1707 in Fig. 17(a).

[0399] The connection relationship of the flip-flop circuit in Fig. 48 will be described. Note that the second terminal of transistor 480 1, the second terminal of transistor 4800, the gate of transistor 4806, and the t he second terminal of transistor 4804, and the gate of transistor 4802 are connected at a node called node N481 . Also, the second terminal of transistor 4805, the second terminal of transistor 4806, and the t he second terminal of transistor 4807, and the gate of transistor 4808 are connected at a node called node N482 . Also, the second terminal of transistor 4809, the second terminal of transistor 4808, and the t he second terminal of transistor 4810, the gate of transistor 4803, and the gate of transistor 4804 are connected at a node called node N483 .

[0400] The gate of transistor 4801 is connected to wiring 4814, the first terminal is connected to wiring 4811 , and the second terminal is connected to node N481. The gate of transistor 4800 is connected to the w iring 4815, the first terminal is connected to wiring 4812, and the second terminal is connected to node N481 and is connected. The gate of transistor 4806 is connected to node N481, and the first terminal is connected to wiring 4812, and the second terminal is connected to node N482. Transistor 48 05 has its gate connected to wiring 4811, its first terminal connected to wiring 4811, and its second terminal connected to node N482. The gate of transistor 4807 is connected to wiring 4813 and its first terminal is connected to wiring 4812, and its second terminal is connected to node N482. The gate of transistor 4808 is connected to node N482, its first terminal is connected to wiring 4811 and its second terminal is connected to node 483. The gate of transistor 4809 is connected to node N481, its first terminal is connected to wiring 4812, and its second terminal is connected to node N483 continuously. The gate of transistor 4810 is connected to wiring 4813, its first terminal is connected to wiring 4812, and its second terminal is connected to node N483. The gate of transistor 480 4 is connected to node N483, its first terminal is connected to wiring 4812, and its second terminal is connected to node N481. The gate of transistor 4803 is connected to node N483 and its first terminal is connected to wiring 4812, and its second terminal is connected to wiring 4816. The gate of transistor 4802 is connected to node N481, its first terminal is connected to wiring 4813 and its second terminal is connected to wiring 4816.

[0401] Also, transistors 4800 to 4810 are each of P-channel type.

[0402] Therefore, since the flip-flop circuit of FIG. 48 can be entirely composed of P-channel type transistors, no process for forming N-channel type transistors is required. Therefore, the flip-flop circuit in FIG. 48 can simplify the manufacturing process, reduce manufacturing costs, and improve the yield.

[0403] Also, the power supply potential VDD is supplied to the wiring 4812, and the power supply potential VSS is supplied to the wiring 4811. Note that the power supply potential VDD is higher than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to the wiring 4811 and the wiring 4812, or other power supply potentials may be supplied.

[0404] Signals are also supplied to the wiring 4813, the wiring 4814, and the wiring 4815, respectively. Note that the signals supplied to the wiring 4813, the wiring 4814, and the wiring 4815 are digital signals having binary values, respectively. However, the power supply potential VDD, the power supply potential VSS, or other power supply potentials may be supplied to the wiring 4813, the wiring 4814, and the wiring 4815, respectively. Also, analog signals may be supplied to the wiring 4813, the wiring 4814, and the wiring 4815, respectively.

[0405] Next, the operation of the flip-flop circuit shown in FIG. 48 will be described with reference to FIG. 49.

[0406] FIG. 49 is an example of a timing chart of the flip-flop circuit shown in FIG. 48. The timing chart of FIG. 49 shows the potential of the wiring 4813, the potential of the wiring 4814, the potential of the node N481, the potential of the node N482, the node N483, the potential of the wiring 4816, the on / off relationship of the transistors 4803 and 4804, and the potential of the wiring 4815.

[0407] The timing chart of FIG. 48 will be described by dividing it into periods T1 to T4. Also, period T3 will be described by dividing it into period T3a and period T3b.

[0408] Note that, except for periods T1, T2, and T3b, periods T3a and T4 are repeated in sequence.

[0409] First, the operation in period T1 will be described. In period T1, an H signal is supplied to wiring 4813, an L signal is supplied to wiring 4814, and an H signal is supplied to wiring 4815.

[0410] Therefore, transistor 4801 turns on, transistor 4800 turns off, and transistors 4807 and 4810 turn off. At this time, the power supply potential VSS is supplied to node N48 1 via transistor 4801, and the potential of node N481 decreases. Also, transistors 4806 and 4809 turn on due to the decrease in the potential of node N481, and the potentials of nodes N482 and N483 increase. Also, transistor 4808 turns off due to the increase in the potential of node N482. Also, transistors 4803 and 4804 turn off due to the increase in the potential of node N483.

[0411] Here, the decrease in the potential of node N481 continues until transistor 4801 turns off. Transistor 4801 turns off when the potential of node N481 becomes the sum (VSS + |Vth4801|) of the power supply potential VSS and the absolute value of the threshold voltage Vth4801 of transistor 4801. Therefore, the potential of node N481 becomes VSS + |Vth4801|. Also, node N481 becomes a floating state.

[0412] ​​ Therefore, the transistor 4802 is turned on. Also, since the H signal of the wiring 4813 is supplied to the wiring 4816, the potential of the wiring 4816 becomes equal to the power supply potential VDD. .

[0413] Subsequently, the operation in the period T2 will be described. In the period T2, an L signal is supplied to the wiring 4813, an H signal is supplied to the wiring 4814, and an H signal is supplied to the wiring 4815.

[0414] Therefore, the transistor 4801 is turned off, the transistor 4800 remains off, and the transistors 4807 and 4810 are turned on. At this time, the node N481 is in a floating state, and the potential of the node N481 maintains VSS + |Vth4801|. Also, since the transistors 4806 and 4807 are turned on, the potential of the node N482 remains at the H level. Further, since the transistors 4809 and 4810 are turned on, the potential of the node N483 remains at the H level. Thus, since the node N483 is at the H level, the transistors 4803 and 4804 remain off.

[0415] Here, the node N481 is in a floating state and maintains the L level. Also, since the node N481 maintains the L level, the transistor 4802 remains on. Also, since the L signal of the wiring 4813 is supplied to the wiring 4816, the potential of the wiring 4816 is decreasing. Therefore, by the bootstrap operation, the potential of the node N481 is from the power supply potential VSS to the absolute value of the threshold voltage Vth4802 of the transistor 4802. ​​​​​​​​​​​​​The drawn value (VSS - |Vth4802|) or less, and the potential of the wiring 4816 becomes equal to the power supply potential V SS.

[0416] Subsequently, the operation in the period T3b will be described. In the period T3b, an H signal is supplied to the wiring 4813 and an H signal is supplied to the wiring 4814, and an L signal is supplied to the wiring 4815.

[0417] Therefore, the transistor 4801 remains off, the transistor 4800 turns on , and the transistors 4807 and 4810 turn off. At this time, the power supply potential VDD is supplied to the node N 481 through the transistor 4800, and the potential of the node N481 rises. Also, the transistors 4806 and 4809 turn off due to the rise in the potential of the node N481 . Therefore, the potentials of the nodes N482 and N483 decrease by the bootstrap operation. The potential of the node N482 is the value obtained by subtracting the absolute value of the threshold voltage Vth4808 of the transistor 4808 from the power supply potential VSS (VSS - |Vth4808|) or less. The potential of the node N483 decreases to the power supply potential VSS . Therefore, the transistors 4803 and 4804 turn on due to the decrease in the potential of the node N48 3.

[0418] Also, the transistor 4802 turns off due to the rise in the potential of the node N481. Therefore , since the power supply potential VDD is supplied to the wiring 4816 through the transistor 4803 , the potential of the wiring 4816 becomes equal to the power supply potential VDD.

[0419] Subsequently, the operation in the period T4 will be described. In the period T4, an L signal is supplied to the wiring 4813 ​The H signal is supplied to wiring 4814, and the H signal is supplied to wiring 4815.

[0420] Therefore, transistor 4801 remains off, and transistor 4800 turns off. Then, transistors 4807 and 4810 turn on. At this time, node N481 is in a floating state, and the potential of node N481 maintains the power supply potential VDD. Therefore, transistors 4802, 4806, and transistor 480 9 remain off. Also, since the potential of node N482 is supplied with the power supply potential VDD via transistor 4807, it becomes the H level. Thus, transistor 4808 turns off. Also, since the potential of node N483 is supplied with the power supply potential VDD via transistor 4810, it becomes the H level. Thus, transistors 4803 and 4804 turn off.

[0421] Therefore, wiring 4816 becomes a floating state, and the potential of wiring 4816 maintains a value equal to the power supply potential VDD.

[0422] Subsequently, the operation in period T3a will be described. In period T3a, an H signal is supplied to wiring 4813, an H signal is supplied to wiring 4814, and an H signal is supplied to wiring 4815.

[0423] Therefore, transistor 4801 remains off, transistor 4800 remains off, and transistors 4807 and 4810 turn off. At this time , node N481 is in a floating state, and the potential of node N481 remains at the H level. Therefore, transistors 4802, 4806, and transistor 48 09 remains off. Also, the potential of node N482 and the potential of node N483 decrease due to the bootstrapping operation. The potential of node N482 decreases to a value equal to or less than the value obtained by subtracting the absolute value of the threshold voltage Vth4808 of transistor 4808 from the power supply potential VSS (VSS - |Vth 4808|). The potential of node N483 decreases to the power supply potential VSS. Therefore, transistors 4803 and 4804 turn on due to the decrease in the potential of node N483. Accordingly, since the power supply potential VDD is supplied to wiring 4816 via transistor 4803, the potential of wiring 4816 maintains a value equal to the power supply potential VDD. Through the above operations, in period T1, the flip - flop circuit in FIG. 48 sets node N481 to the

[0424] floating state while keeping it at the L level. In period T2, the flip - flop circuit in FIG. 48 can reduce the potential of node N481 to VSS - |Vth480 2| or less and make the potential of wiring 4816 equal to the power supply potential VSS by means of the bootstrapping operation.

[0425] In period T3a, the flip - flop circuit in FIG. 48 supplies the power supply potential VDD to wiring 4816 and node N48 1 as transistors 4803 and 4804 turn on. In period T4, the flip - flop circuit in FIG. 48 turns off transistors 4803 and 4804. Therefore, since transistors 4803 and 4804 of the flip - flop circuit in FIG. 48 turn on in sequence, the characteristic degradation of transistors 4803 and 4804 can be suppressed, and node N481, The potential of node N481 is reduced to VSS - |Vth480 2| or less, and the potential of wiring 4816 can be made equal to the power supply potential VSS.

[0426] Also, in period T3a, the flip - flop circuit in FIG. 48 supplies the power supply potential VDD to wiring 4816 and node N48 1 as transistors 4803 and 4804 turn on. In period T4, the flip - flop circuit in FIG. 48 turns off transistors 4803 and 4804. Therefore, since transistors 4803 and 4804 of the flip - flop circuit in FIG. 48 turn on in sequence, the characteristic degradation of transistors 4803 and 4804 can be suppressed, and node N481, 1 as transistors 4803 and 4804 turn on. In period T4, the flip - flop circuit in FIG. 48 turns off transistors 4803 and 4804. Therefore, since transistors 4803 and 4804 of the flip - flop circuit in FIG. 48 turn on in sequence, the characteristic degradation of transistors 4803 and 4804 can be suppressed, and node N481, 1 as transistors 4803 and 4804 turn on. In period T4, the flip - flop circuit in FIG. 48 turns off transistors 4803 and 4804. Therefore, since transistors 4803 and 4804 of the flip - flop circuit in FIG. 48 turn on in sequence, the characteristic degradation of transistors 4803 and 4804 can be suppressed, and node N481, 1 as transistors 4803 and 4804 turn on. In period T4, the flip - flop circuit in FIG. 48 turns off transistors 4803 and 4804. Therefore, since transistors 4803 and 4804 of the flip - flop circuit in FIG. 48 turn on in sequence, the characteristic degradation of transistors 4803 and 4804 can be suppressed, and node N481, 1 as transistors 4803 and 4804 turn on. In period T4, the flip - flop circuit in FIG. 48 turns off transistors 4803 and 4804. Therefore, since transistors 4803 and 4804 of the flip - flop circuit in FIG. 48 turn on in sequence, the characteristic degradation of transistors 4803 and 4804 can be suppressed, and node N481, The potential of the wiring 4816 can be stably maintained at a value equal to the power supply potential VDD.

[0427] Also, the flip-flop circuit in FIG. 48 can set the potential of the node N 483 to a value equal to the power supply potential VSS during the period T3a and the period T3b. Therefore, even if the characteristics of the transistors 4803 and 4804 deteriorate, the flip-flop circuit in FIG. 48 can operate under a wide range of operating conditions.

[0428] In addition, the flip-flop circuit in FIG. 48 does not have a transistor that is in the on state during all of the periods T1 to T4. That is, it does not have a transistor that is constantly or almost constantly in the on state. Therefore, the flip-flop circuit in FIG. 48 can suppress the deterioration of the transistor characteristics and the shift of the threshold voltage due to the characteristic deterioration.

[0429] Note that the transistors 4800 to 4810 have the same functions as the transistors 3600 to 3610.

[0430] Note that the transistors 4805, 4806, 4807, 4808, 4809, and 4810 form a 2-input NAND circuit 4817 with the node N48 1 and the wiring 4813 as input terminals and the node N483 as the output terminal.

[0431] Note that, as shown in FIG. 50, a capacitive element 5001 may be disposed between the gate (node N482) of the transistor 4808 and the second terminal (node N483). This is because during the period T3a and the period T3b, the potential of the node N482 and the potential of the node N483 are Boo ​ By the bootstrap operation, in order to reduce it, by arranging the capacitive element 5001, the flip flop circuit becomes more likely to perform the bootstrap operation.

[0432] Note that, as shown in FIG. 51, the transistor 4807 is not necessarily required.

[0433] Note that, as shown in FIG. 52, a capacitive element 5201 may be arranged between the gate (node N481) of the transistor 4802 and the second terminal (wiring 4816). This is because, during the period T2, the potential of node N481 and the potential of wiring 4816 are to be raised by the bootstrap operation. Therefore, by arranging the capacitive element 5201, the flip-flop circuit becomes more likely to perform the bootstrap operation.

[0434] Note that the transistor 4801 only needs to make node N481 in a floating state during the period T1 and be able to set the potential of node N481 to the L level. Therefore, even if the first terminal of the transistor 48 01 is connected to the wiring 4814, node N481 can be made in a floating state and the potential of node N481 can be set to the L level.

[0435] Note that this embodiment can be freely combined with any description of other embodiments in this specification and implemented. Also, any descriptions in this embodiment can be freely combined and implemented .

[0436] (Seventh Embodiment) In this embodiment, the case where the basic circuit described in the fourth embodiment is applied to a flip-flop circuit will be described with reference to FIG. 56.

[0437] FIG. 56 shows a flip-flop circuit to which the basic circuit of FIG. 25(a) described in the fourth embodiment is applied. The flip-flop circuit of FIG. 56 includes transistor 5601, transistor 5602, transistor 5603, transistor 5604, transistor 5605 , transistor 5606, transistor 5607, circuit 5608, and circuit 5609.

[0438] Note that as the circuits 5608 and 5609, the NOR circuit 2715 of FIG. 27 and the NOR circuit 3617 of FIG. 36 can be used.

[0439] The connection relationship of the flip-flop circuit of FIG. 56 will be described. Note that the second terminal of transistor 560 1, the second terminal of transistor 5607, the second terminal of transistor 5605, and the second terminal of transistor 560 6 and the gate of transistor 5602 are defined as node N561. Also, the node between the gate of transistor 5604 and the gate of transistor 5606 is defined as node N562. Also, the node between the gate of transistor 5603 and the gate of transistor 5605 is defined as node N563.

[0440] The gate of transistor 5601 is connected to wiring 5614, the first terminal is connected to wiring 5610, and the second terminal is connected to node N561. The gate of transistor 5607 is connected to wiring 5615, the first terminal is connected to wiring 5611, and the second terminal is connected to node N561. The two input terminals of circuit 5608 are respectively connected to node N561 and wiring 5612, and the output terminal is connected to node N562. The two input terminals of circuit 5609 are respectively connected to node N561 and wiring 5613, and the output terminal is connected to node N563. ​ It is. The gate of transistor 5606 is connected to node N562, and the first terminal is connected to wiring 5611, and the second terminal is connected to node N561. The gate of transistor 5605 is connected to node N563, the first terminal is connected to wiring 5611, and the second terminal is connected to node N561. The gate of transistor 5604 is connected to node N562 , the first terminal is connected to wiring 5611, and the second terminal is connected to wiring 5616. The gate of tra nsistor 5603 is connected to node N563, the first terminal is connected to wiring 5611 , and the second terminal is connected to wiring 5616. The gate of transistor 5602 is connected to node N 561, the first terminal is connected to wiring 5613, and the second terminal is connected to wiring 5616 .

[0441] Also, transistors 5601 to 5607 are each of N-channel type. Also, the transistors included in circuit 5608 and circuit 5609 are also each of N-channel type .

[0442] Therefore, since all the flip-flop circuits in FIG. 56 can be composed of N-channel type transistors , the flip-flop circuit in FIG. 56 can use an amorphous silicon con in the semiconductor layer, and the manufacturing process can be simplified. Therefore, the manufacturing cost can be reduced and the yield can be improved. Furthermore, it is also possible to fabricate a semiconductor device such as a large display panel. Also, the flip-flop circuit in FIG. 56 can simplify the manufacturing process even when using polysilicon or single-crystalline silicon in the semiconductor layer.

[0443] Also, a power supply potential VDD is supplied to wiring 5610, and a power supply potential VSS is supplied to wiring 5611. Note that the power supply potential VDD is at a higher potential than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to wiring 5610 and wiring 5611, or other power supply potentials may be supplied.

[0444] Also, signals are respectively supplied to wiring 5612, wiring 5613, wiring 5614, and wiring 5615. Note that the signals supplied to wiring 5612, wiring 5613, wiring 5614, and wiring 56 15 are digital signals each having a binary value. However, power supply potential V DD, power supply potential VSS, or other power supply potentials may be respectively supplied to wiring 5612, wiring 5613, wiring 5614, and wiring 5615. Also, analog signals may be respectively supplied to wiring 5612, wiring 5613, wiring 5614, and wiring 5615.

[0445] Next, the operation of the flip-flop circuit shown in FIG. 56 will be described with reference to FIG. 57.

[0446] FIG. 57 is an example of a timing chart of the flip-flop circuit shown in FIG. 56. The timing chart of FIG. 57 shows the potential of wiring 5612, the potential of wiring 5613, the potential of wiring 5614, the potential of node N561, the potential of node N562, the potential of node N563, the potential of wiring 5616, the on / off relationship of transistor 5604 and transistor 5606, the on / off relationship of transistor 5603 and transistor 5605, and the potential of wiring 5615.

[0447] ​​​​​​​​​The timing chart of FIG. 57 will be described by dividing it into periods T1 to T4. Also, period T3 will be described by dividing it into period T3a and period T3b.

[0448] Note that for periods other than period T1, period T2, and period T3b, period T3a and period T4 are repeated in order. are repeated.

[0449] First, the operation in period T1 will be described. In period T1, an H signal is supplied to wiring 5612, an L signal is supplied to wiring 5613, an H signal is supplied to wiring 5614, and an L signal is supplied to wiring 5615. is supplied.

[0450] Accordingly, transistor 5601 turns on and transistor 5607 turns off. At this time, the potential of node N561 rises because the power supply potential VDD is supplied through transistor 5601. Therefore, circuit 5608 outputs an L signal to node N562, and transistors 5604 and 5606 turn off. Also, circuit 5609 outputs an L signal to node N563, and transistors 5603 and 5605 turn off. to node N563, and transistors 5603 and 5605 turn off.

[0451] Note that the rise in the potential of node N561 continues until transistor 5601 turns off. Transistor 5601 turns off when the potential of node N561 reaches the value (VDD - Vth5601) obtained by subtracting the threshold voltage Vth5601 of transistor 5601 from the power supply potential VDD. from the power supply potential VDD. from the power supply potential VDD. Accordingly, the potential of node N561 becomes VDD - Vth5601, and node N561 enters a floating state. becomes VDD - Vth5601, and node N561 enters a floating state.

[0452] Accordingly, transistor 5602 turns on. Transistor 5602 is connected to wiring 5616. Since the L signal of wiring 5613 is supplied through, the potential of wiring 5616 becomes the power supply potential VSS and becomes equal to the value of.

[0453] Subsequently, the operation in period T2 will be described. In period T2, an L signal is supplied to wiring 5612 and an H signal is supplied to wiring 5613, an L signal is supplied to wiring 5614, and an L signal is supplied to wiring 561 5.

[0454] Therefore, transistor 5601 turns off and transistor 5607 remains off At this time, the potential of node N561 maintains VDD - Vth5601. Thus circuit 5608 outputs an L signal to node N562, and transistors 5604 and tran sistor 5606 remain off. Also, circuit 5609 outputs an L signal to node N563 and transistors 5603 and transistor 5605 remain off.

[0455] Since an H signal is supplied to wiring 5613, the potential of wiring 5616 starts to rise. Therefore, the potential of node N561 becomes, by the bootstrap operation, the sum of the power supply potential VDD and the threshold voltage Vth5602 of transistor 5602 (VDD + Vth5602) or more. Thus, the potential of wiring 5616 rises to a value equal to the power supply potential VDD.

[0456] Subsequently, the operation in period T3b will be described. In period T3b, an H signal is supplied to wiring 5612 and an L signal is supplied to wiring 5613, an L signal is supplied to wiring 5614, and an H signal is supplied to wiring 5 615.

[0457] Therefore, transistor 5601 turns off and transistor 5607 turns on. Since the power supply potential VSS is supplied to node N561 via transistor 5607, the potential of node N561 decreases. Therefore, circuit 5608 outputs an L signal to node N562, and transistors 5604 and 5606 remain off. Also, circuit 560 9 outputs an H signal to node N563, and transistors 5603 and 5605 turn on.

[0458] Note that since node N561 reaches the L level, transistor 5602 turns off. Since the power supply potential VSS is supplied to wiring 56 16 via transistor 5603, the potential of wiring 5616 remains equal to the power supply potential VSS.

[0459] Next, the operation during period T4 will be described. During period T4, an L signal is supplied to wiring 5612 , an H signal is supplied to wiring 5613, an L signal is supplied to wiring 5614, and an L signal is supplied to wiring 561 5.

[0460] Therefore, transistor 5601 remains off and transistor 5607 turns off. The potential of node N561 maintains the L level. Thus, circuit 5608 outputs an H signal to node N562, and transistors 5604 and 5606 turn on. Also, circuit 5609 outputs an L signal to node N563, and transistors 5603 and trans istor 5605 turn off.

[0461] Note that since node N561 maintains the L level, transistor 5602 turns off. Since the power supply potential VSS is supplied to wiring 5616 via transistor 5604, the potential of wiring 56 16 remains equal to the power supply potential VSS.

[0462] Next, the operation during period T3a will be described. During period T3a, an H signal is applied to wiring 5612, an L signal is applied to wiring 5613, an L signal is applied to wiring 5614, and an H signal is applied to wiring 5 615.

[0463] Accordingly, transistor 5601 turns off and transistor 5607 turns on. The potential of node N561 maintains the L level. Thus, circuit 5608 outputs an L signal to node N5 62, and transistors 5604 and 5606 turn off. Also, circuit 5609 outputs an H signal to node N563, and transistors 5603 and 5605 turn on.

[0464] Note that since node N561 maintains the L level, transistor 5602 turns off. Since the power supply potential VSS is supplied to wiring 5616 via transistor 5603, the potential of wiring 56 16 remains equal to the power supply potential VSS.

[0465] By the above operations, during period T1, the flip-flop circuit in FIG. 56 sets node N561 to the floating state while maintaining the H level. During period T2, the flip-flop circuit in FIG. 56 can raise the potential of node N561 to VDD + Vth5602 or higher and set the potential of wiring 5616 equal to the power supply potential VDD by means of the bootstrap operation.

[0466] Also, during period T3a, transistor 5603 turns on and supplies the power supply potential VSS to wiring 5616. Also, during period T4, transistor 5604 turns on and supplies the power supply potential VSS to wiring 56 16. Accordingly, the flip-flop circuit in FIG. 56, during the period During period T3a and period T4, it is possible to always supply the power supply potential VSS to the wiring 5616. It can be done.

[0467] Also, during period T3b, the transistor 5605 is turned on to supply the power supply potential VSS to the node N561. Also, during period T4, the transistor 5606 is turned on to supply the power supply potential VSS to the node N5 61. Therefore, the flip-flop circuit in FIG. 56 can always supply the power supply potential VSS to the node N561 during period T3b and period T4. It can be done. It can be done.

[0468] Also, the flip-flop circuit in FIG. 56 does not have a transistor that is in the on state during all of periods T1 to T4. That is, it does not have a transistor that is in a steady or almost steady on state. Therefore, the flip-flop circuit in FIG. 56 can suppress the deterioration of the transistor characteristics and the shift of the threshold voltage due to the characteristic deterioration. Also, the characteristics of the transistor are likely to deteriorate when the transistor is formed of amorphous silicon. Therefore, the flip-flop circuit in FIG. 56 can obtain merits such as reduction of manufacturing cost and improvement of yield by forming the transistor of amorphous silicon, and can also solve the problem of characteristic deterioration of the transistor.

[0469] Here, the functions of the transistors 5601 to 5607 will be described. The transistor 5601 has a function as a switch that selects whether to connect the wiring 5610 and the node N561 according to the potential of the wiring 5614. The transistor 5602 is connected to the node N5 lit can be obtained, and the problem of characteristic deterioration of the transistor can also be solved. lit can be obtained, and the problem of characteristic deterioration of the transistor can also be solved.

[0470] Here, the functions of the transistors 5601 to 5607 will be described. The transistor 5601 has a function as a switch that selects whether to connect the wiring 5610 and the node N561 according to the potential of the wiring 5614. The transistor 5602 is connected to the node N5 5610 and the node N561 according to the potential of the wiring 5611. The transistor 5603 is connected to the node N5 According to the potential of 61, a switch that selects whether to connect wiring 5613 and wiring 5616 has a function. Transistor 5603 has a function as a switch that selects whether to connect wiring 5611 and wiring 5616 according to the potential of node N563. According to the potential of node N563, transistor 5603 has a function as a switch that selects whether to connect wiring 5611 and wiring 5616. According to the potential of node N563, transistor 5603 has a function as a switch that selects whether to connect wiring 5611 and wiring 5616. Transistor 5604 has a function as a switch that selects whether to connect wiring 5611 and wiring 5616 according to the potential of node N562. Transistor 5604 has a function as a switch that selects whether to connect wiring 5611 and wiring 5616 according to the potential of node N562. Transistor 5605 has a function as a switch that selects whether to connect wiring 5611 and node N561 according to the potential of node N563. Transistor 5605 has a function as a switch that selects whether to connect wiring 5611 and node N561 according to the potential of node N563. Transistor 5606 has a function as a switch that selects whether to connect wiring 5611 and node N561 according to the potential of node N562. Transistor 5606 has a function as a switch that selects whether to connect wiring 5611 and node N561 according to the potential of node N562. Transistor 5607 has a function as a switch that selects whether to connect wiring 5611 and node N561 according to the potential of wiring 5615. Transistor 5607 has a function as a switch that selects whether to connect wiring 5611 and node N561 according to the potential of wiring 5615.

[0471] Next, the case where the basic circuit shown in FIG. 56 is configured with P-channel transistors will be described with reference to FIG. 58. Next, the case where the basic circuit shown in FIG. 56 is configured with P-channel transistors will be described with reference to FIG. 58.

[0472] FIG. 58 is an example of a flip-flop circuit to which the basic circuit of FIG. 26(a) described in the fourth embodiment is applied. The flip-flop circuit of FIG. 58 includes transistors 5801, transistors 5802, transistors 5803, transistors 5804, transistors 5805, transistors 5806, transistors 5807, circuit 5808, and circuit 5809. FIG. 58 is an example of a flip-flop circuit to which the basic circuit of FIG. 26(a) described in the fourth embodiment is applied. The flip-flop circuit of FIG. 58 includes transistors 5801, transistors 5802, transistors 5803, transistors 5804, transistors 5805, transistors 5806, transistors 5807, circuit 5808, and circuit 5809. FIG. 58 is an example of a flip-flop circuit to which the basic circuit of FIG. 26(a) described in the fourth embodiment is applied. The flip-flop circuit of FIG. 58 includes transistors 5801, transistors 5802, transistors 5803, transistors 5804, transistors 5805, transistors 5806, transistors 5807, circuit 5808, and circuit 5809. FIG. 58 is an example of a flip-flop circuit to which the basic circuit of FIG. 26(a) described in the fourth embodiment is applied. The flip-flop circuit of FIG. 58 includes transistors 5801, transistors 5802, transistors 5803, transistors 5804, transistors 5805, transistors 5806, transistors 5807, circuit 5808, and circuit 5809. FIG. 58 is an example of a flip-flop circuit to which the basic circuit of FIG. 26(a) described in the fourth embodiment is applied. The flip-flop circuit of FIG. 58 includes transistors 5801, transistors 5802, transistors 5803, transistors 5804, transistors 5805, transistors 5806, transistors 5807, circuit 5808, and circuit 5809.

[0473] Note that as circuit 5808 and circuit 5809, the NAND circuit 4415 of FIG. 44, FIG. 48 The NAND circuit 4817 can be used.

[0474] The connection relationship of the flip-flop circuit in FIG. 58 will be described. Note that the second terminal of transistor 580 1, the second terminal of transistor 5807, the second terminal of transistor 5805, and the second terminal of transistor 5806 and the gate of transistor 5802 are defined as node N581. Also, the node between the gate of transistor 5804 and the gate of transistor 5806 is defined as node N582. Also, the node between the gate of transistor 5803 and the gate of transistor 5805 is defined as node N583.

[0475] The gate of transistor 5801 is connected to wiring 5814, the first terminal is connected to wiring 5810, and the second terminal is connected to node N581. The gate of transistor 5807 is connected to wiring 5815, the first terminal is connected to wiring 5811, and the second terminal is connected to node N581. The two input terminals of circuit 5808 are respectively connected to node N581 and wiring 5812, and the output terminal is connected to node N582. The two input terminals of circuit 5809 are respectively connected to node N581 and wiring 5813, and the output terminal is connected to node N583. The gate of transistor 5806 is connected to node N582, the first terminal is connected to wiring 5811, and the second terminal is connected to node N581. The gate of transistor 5805 is connected to node N583, the first terminal is connected to wiring 5811, and the second terminal is connected to node N581. The gate of transistor 5804 is connected to node N582, the first terminal is connected to wiring 5811, and the second terminal is connected to wiring 5816. The transistor The gate of transistor 5803 is connected to node N583, the first terminal is connected to wiring 5811, and the second terminal is connected to wiring 5816. The gate of transistor 5802 is connected to node N 581, the first terminal is connected to wiring 5813, and the second terminal is connected to wiring 5816.

[0476] Also, transistors 5801 to 5807 are each of P-channel type. Also, the transistors included in circuit 5808 and circuit 5809 are each of P-channel type as well.

[0477] Therefore, all of the flip-flop circuits in FIG. 58 can be composed of P-channel type transistors, so that there is no need for a process for forming N-channel type transistors. Therefore, the flip-flop circuit in FIG. 58 can simplify the manufacturing process, and can reduce the manufacturing cost and improve the yield.

[0478] Also, the power supply potential VDD is supplied to wiring 5811, and the power supply potential VSS is supplied to wiring 5810. Note that the power supply potential VDD is at a higher potential than the power supply potential VSS. However, digital signals, analog signals, etc. may be supplied to wiring 5810 and wiring 5811, or other power supply potentials may be supplied.

[0479] Also, signals are supplied to wiring 5812, wiring 5813, wiring 5814, and wiring 5815, respectively. Note that the signals supplied to wiring 5812, wiring 5813, wiring 5814, and wiring 58 15 are digital signals each having a binary value. However, power supply potentials V may be supplied to wiring 5812, wiring 5813, wiring 5814, and wiring 5815, respectively. DD, VSS, or other signals may be supplied.​​​ DD, the power supply potential VSS, or another power supply potential may be supplied. Also, for wiring 5812 , wiring 5813, wiring 5814, and wiring 5815, analog signals may be supplied respectively thereto.

[0480] Next, the operation of the flip-flop circuit shown in FIG. 58 will be described with reference to FIG. 59 .

[0481] FIG. 59 is an example of a timing chart of the flip-flop circuit shown in FIG. 58. In FIG 59's timing chart, the potential of wiring 5812, the potential of wiring 5813, wiring 5814 's potential, the potential of node N581, the potential of node N582, the potential of node N583, wiring 5816 's potential, the on / off relationship of transistor 5804 and transistor 5806, the trans istor 5803 and the on / off relationship of transistor 5805, and the potential of wiring 5815 are shown.

[0482] The timing chart of FIG. 59 will be described by dividing it into periods T1 to T4. Also, period T3 will be described by dividing it into period T3a and period T3b.

[0483] Note that the periods other than period T1, period T2, and period T3b repeat period T3a and period T4 in order .

[0484] First, the operation in period T1 will be described. In period T1, an L signal is supplied to wiring 5812 , an H signal is supplied to wiring 5813, an L signal is supplied to wiring 5814, and an H signal is supplied to wiring 5815 .

[0485] Therefore, transistor 5801 turns on and transistor 5807 turns off. At this time, the potential of the node N581 is supplied with the power supply potential VSS via the transistor 5801. Therefore, the circuit 5808 outputs a H signal to the node N582, and the The transistor 5804 and the transistor 5806 are turned off. An output is sent to node N583, and transistors 5803 and 5805 are turned off.

[0486] The potential of the node N581 continues to decrease until the transistor 5801 is turned off. The transistor 5801 is connected to the power supply potential VSS. When the absolute value of the low-level voltage Vth5801 is reached (VSS+|Vth5801|), the Therefore, the potential of node N581 is VSS+|Vth5801|, and node N5 81 will be floating.

[0487] Therefore, the transistor 5802 is turned on. Since the H signal of the wiring 5813 is supplied through the will be equal to

[0488] Next, the operation in the period T2 will be described. In the period T2, an H signal is supplied to the wiring 5812. An L signal is supplied to the wiring 5813, an H signal is supplied to the wiring 5814, and An H signal is supplied to 5.

[0489] Therefore, transistor 5801 turns off and transistor 5807 remains off. At this time, the potential of the node N581 is maintained at VSS+|Vth5801|. Therefore, the circuit 5808 outputs an H signal to the node N582, and the transistor 5804 and Transistor 5806 remains off. Circuit 5809 also supplies a H signal to node N583. output, and transistor 5803 and transistor 5805 remain off.

[0490] Note that since an L signal is supplied to the wiring 5813, the potential of the wiring 5816 starts to decrease. Therefore, the potential of node N581 is raised from the power supply potential VSS by the bootstrap operation. The value obtained by subtracting the absolute value of the threshold voltage Vth5802 of the transistor 5802 from the Therefore, the potential of the wiring 5816 is equal to the power supply potential VSS. The value decreases to a low level.

[0491] Next, the operation during the period T3b will be described. During the period T3b, an L signal is applied to the wiring 5812. A high-level signal is supplied to the wiring 5813, a high-level signal is supplied to the wiring 5814, and a low-level signal is supplied to the wiring 5815. The L signal is supplied to 815.

[0492] Thus, transistor 5801 is turned off and transistor 5807 is turned on. Since the power supply potential VDD is supplied to the node N581 through the transistor 5807, The potential of N581 rises. Therefore, the circuit 5808 outputs an H signal to the node N582, The transistor 5804 and the transistor 5806 remain off. 9 outputs an L signal to the node N583, and the transistors 5803 and 5805 will be turned on.

[0493] Since the node N581 becomes H level, the transistor 5802 is turned off. Since the power supply potential VDD is supplied to the wiring 5816 through the transistor 5803, The potential of this becomes equal to the power supply potential VDD.

[0494] Next, the operation during period T4 will be described. During period T4, an H signal is supplied to wiring 5812 an L signal is supplied to wiring 5813, an H signal is supplied to wiring 5814, and wiring 581 5 has an H signal supplied thereto.

[0495] Therefore, transistor 5801 remains off, and transistor 5807 turns off. The potential of node N581 maintains the H level. Thus, circuit 5808 outputs an L signal to node N582, and transistors 5804 and 5806 turn on. Also, circuit 5809 outputs an H signal to node N583, and transistors 5803 and 580 5 turn off.

[0496] Note that since node N581 maintains the H level, transistor 5802 turns off. Since power supply potential VDD is supplied to wiring 5816 via transistor 5804, the potential of wiring 58 16 remains at a value equal to the power supply potential VDD.

[0497] Next, the operation during period T3a will be described. During period T3a, an L signal is supplied to wiring 5812 an H signal is supplied to wiring 5813, an H signal is supplied to wiring 5814, and wiring 5 815 has an H signal supplied thereto.

[0498] Therefore, transistor 5801 turns off, and transistor 5807 turns off. The potential of node N581 maintains the H level. Thus, circuit 5808 outputs an H signal to node N5 82, and transistors 5804 and 5806 turn off. Also, circuit 5809 outputs an L signal to node N583, and transistors 5803 and 580 Terminal 5805 is turned on.

[0499] Note that in order for node N581 to maintain the H level, transistor 5802 is turned off. Wiring Since power supply potential VDD is supplied to wiring 5816 via transistor 5803, the potential of wiring 58 16 remains at a value equal to the power supply potential VDD.

[0500] By the above operation, in period T1, the flip-flop circuit in FIG. 58 sets node N581 to the floating state while maintaining the L level. In period T2, the flip-flop in FIG. 58 circuit can, by the bootstrap operation, lower the potential of node N581 to VSS - |Vth580 2| or less and make the potential of wiring 5816 equal to the power supply potential VSS.

[0501] Also, in period T3a, transistor 5803 turns on to supply power supply potential VDD to wiring 5816. Also, in period T4, transistor 5804 turns on to supply power supply potential VDD to wiring 5816. Therefore, the flip-flop circuit in FIG. 58 can always supply power supply potential VDD to wiring 5816 during period T3a and period T4.

[0502] Also, in period T3b, transistor 5805 turns on to supply power supply potential VDD to node N581. Also, in period T4, transistor 5806 turns on to supply power supply potential VDD to node N581. Therefore, the flip-flop circuit in FIG. 58 can always supply power supply potential VDD to node N581 during period T3b and period T4.

[0503] Also, the flip-flop circuit in FIG. 58 is in the on state during all of periods T1 to T4.​​ There is no certain transistor. That is, there is no transistor that is constantly or almost constantly in the on state. Therefore, the flip circuit in FIG. 58 can suppress the deterioration of the transistor characteristics and the shift of the threshold voltage due to the characteristic deterioration.

[0504] Note that transistors 5801 to 5807 have the same functions as transistors 5601 to 5607.

[0505] Note that this embodiment can be freely combined with any description of other embodiments in this specification and implemented. Also, any descriptions in this embodiment can be freely combined and implemented .

[0506] (Eighth Embodiment) In this embodiment, a shift register to which the flip-flop circuits described in the fifth and sixth embodiments are applied will be described with reference to FIG. 60.

[0507] FIG. 60 is an example of a shift register to which the flip-flop circuits described in the fifth and sixth embodiments are applied. In the shift register of FIG. 60, a plurality of flip-flop circuits 6001 are arranged.

[0508] Note that the flip-flop circuit 6001 is the same as that shown in the fifth and sixth embodiments .

[0509] Note that in FIG. 60, the flip-flop circuit 6001(n - 1) at the n - 1 stage, the flip-flop circuit 6001(n) at the nth stage, and the flip-flop circuit 6001( at the n + 1 stage It shows (n + 1). Note that n is an even number. Note that the flip-flop circuits in the even-numbered stages The input terminal IN601 of 6001 is connected to the wiring 6005, and the input terminal IN60 1 of the odd-numbered stage is connected to the wiring 6004.

[0510] Note that the input terminal IN601 is connected to the wiring 2711 in FIG. 27, the wiring 3613 in FIG. 36, and the wiring 4411 in FIG. 44, and the wiring 4813 in FIG. 48, respectively. The input terminal IN602 is connected to the wiring 2712 in FIG. 27, the wiring 3614 in FIG. 36, the wiring 4412 in FIG. 44, and the wiring 4814 in FIG. 48, respectively. The input terminal IN603 is connected to the wiring 2713 in FIG. 27, the wiring 3615 in FIG. 36, the wiring 4413 in FIG. 44, and the wiring 4815 in FIG. 48, respectively connected. The input terminal IN604 is connected to the wiring 2709 in FIG. 27, the wiring 3611 in FIG. 36, the wiring 4410 in FIG. 44, and the wiring 4812 in FIG. 48, respectively. The input terminal I N605 is connected to the wiring 2710 in FIG. 27, the wiring 3612 in FIG. 36, the wiring 4409 in FIG. 44, and the wiring 4811 in FIG. 48, respectively. The output terminal OUT606 is connected to the wiring 27 14 in FIG. 27, the wiring 3616 in FIG. 36, the wiring 4414 in FIG. 44, and the wiring 4816 in FIG. 48, respectively.

[0511] Also, the power supply potential VDD is supplied to the wiring 6002, and the power supply potential VSS is supplied to the wiring 6003. Note that the power supply potential VDD is a potential higher than the power supply potential VSS. However the wiring 6002 and the wiring 6003 may be supplied with digital signals, analog signals, etc., or other power supply potentials may be supplied.

[0512] In addition, signals are respectively supplied to wiring 6004, wiring 6005, and wiring 6006. Note that the signals supplied to wiring 6004, wiring 6005, and wiring 6006 are digital signals each having a binary value. However, power supply potential VDD, power supply potential VSS, or other power supply potential may be respectively supplied to wiring 6004, wiring 6005, and wiring 6006. In addition, analog signals may be respectively supplied to wiring 6004, wiring 6005, and wiring 6006. Note that the output signal of the flip - flop circuit 6001 at the n - 2 stage is supplied to wiring 6006.

[0513]

[0514] Next, the operation of the shift register shown in FIG. 60 will be described with reference to the timing chart of FIG. 61.

[0515] FIG. 61 is an example of the timing chart of the shift register shown in FIG. 60. The timing chart of FIG. 61 shows the potential of wiring 6004, the potential of wiring 6005, the potential of output terminal OUT606(n - 2), the potential of output terminal OUT606(n - 1), the potential of output terminal OUT606(n), and the potential of output terminal OUT606(n + 1).

[0516] Note that the timing chart of FIG. 61 shows the case where the flip - flop circuit 6001 is composed of N - channel transistors. When the flip - flop circuit 6001 is composed of P - channel transistors, the H level and the L level may be inverted respectively.

[0517] Note that the timing chart of FIG. 61 will be described by dividing it into periods T1 to T8.

[0518] First, the operation in period T1 will be described. In period T1, the flip-flop circuit 60 01(n - 1) performs the operation in period T1 in the fifth and sixth embodiments. The flip-flop circuit 6001(n) performs the operation in period T4 in the fifth and sixth embodiments. The flip-flop circuit 6001(n + 1) performs the operation in period T3a in the fifth and sixth embodiments.

[0519] Subsequently, the operation in period T2 will be described. In period T2, the flip-flop circuit 6 001(n - 1) performs the operation in period T2 in the fifth and sixth embodiments. The flip-flop circuit 6001(n) performs the operation in period T1 in the fifth and sixth embodiments. The flip-flop circuit 6001(n + 1) performs the operation in period T4 in the fifth and sixth embodiments.

[0520] Therefore, an H signal is output from the output terminal OUT606 of the flip-flop circuit 6001(n - 1).

[0521] Subsequently, the operation in period T3 will be described. In period T3, the flip-flop circuit 6 001(n - 1) performs the operation in period T3b in the fifth and sixth embodiments. The flip-flop circuit 6001(n) performs the operation in period T2 in the fifth and sixth embodiments. The flip-flop circuit 6001(n + 1) performs the operation in period T1 in the fifth and sixth embodiments.

[0522] Therefore, an H signal is output from the output terminal OUT606 of the flip-flop circuit 6001(n). is output.

[0523] Next, the operation in period T4 will be described. In period T4, the flip-flop circuit 6 001(n - 1) performs the operation in period T4 in the fifth and sixth embodiments. The flip-flop circuit 6001(n) performs the operation in period T3b in the fifth and sixth embodiments. The flip-flop circuit 6001(n + 1) performs the operation in period T2 in the fifth and sixth embodiments.

[0524] Therefore, an H signal is output from the output terminal OUT606 of the flip-flop circuit 6001(n + 1).

[0525] Next, the operation in period T5 will be described. In period T5, the flip-flop circuit 6 001(n - 1) performs the operation in period T3a in the fifth and sixth embodiments. The flip-flop circuit 6001(n) performs the operation in period T4 in the fifth and sixth embodiments. The flip-flop circuit 6001(n + 1) performs the operation in period T3b in the fifth and sixth embodiments.

[0526] Next, the operation in period T6 will be described. In period T6, the flip-flop circuit 6 001(n - 1) performs the operation in period T4 in the fifth and sixth embodiments. The flip-flop circuit 6001(n) performs the operation in period T3a in the fifth and sixth embodiments. The flip-flop circuit 6001(n + 1) performs the operation in period T4 in the fifth and sixth embodiments.

[0527] Next, the operation in period T7 will be described. In period T7, the flip-flop circuit 6 001(n - 1) performs the operation in period T3a in the fifth and sixth embodiments. The flip-flop circuit 6001(n) performs the operation in period T4 in the fifth and sixth embodiments. The flip-flop circuit 6001(n + 1) performs the operation in period T3a in the fifth embodiment and the sixth embodiment.

[0528] Next, the operation in period T8 will be described. In period T8, the flip-flop circuit 6 001(n - 1) performs the operation in period T4 in the fifth and sixth embodiments. The flip-flop circuit 6001(n) performs the operation in period T3a in the fifth and sixth embodiments. The flip-flop circuit 6001(n + 1) performs the operation in period T4 in the fifth embodiment and the sixth embodiment.

[0529] As described above, the shift register shown in FIG. 60 can use all N-channel type or P-channel type transistors by using the flip-flop circuits shown in the fifth and sixth embodiments. Moreover, since it can be composed of all N-channel type transistors, the shift register shown in FIG. 60 can use amorphous silicon in the semiconductor layer, and the manufacturing process can be simplified. Therefore, it is possible to reduce the manufacturing cost and improve the yield. Furthermore, it is also possible to fabricate a large display panel. Also, by using the shift register shown in FIG. 60, the transistors of amorphous silicon, whose characteristics are likely to deteriorate,

[0530] can be made. ​​​​​​Even by using studs, the lifespan of the semiconductor device can be extended.

[0531] The characteristics of the transistor are liable to deteriorate when the transistor is formed of amorphous silicon. Therefore, by forming the transistors of the shift register of FIG. 60 of amorphous silicon, not only can advantages such as reduction of manufacturing cost and improvement of yield be obtained, but also the problem of characteristic deterioration of the transistors can be solved.

[0532] Note that this embodiment can be freely combined with any description of other embodiments in this specification and implemented. Also, any descriptions in this embodiment can be freely combined and implemented.

[0533] (Ninth Embodiment) In this embodiment, a source driver to which the shift register described in the eighth embodiment is applied will be described with reference to FIG. 62.

[0534] The circuit shown in FIG. 62 is an example of a circuit configuration to which the shift register shown in the eighth embodiment is applied.

[0535] The circuit shown in FIG. 62 has a shift register 6501 and a plurality of switches 6503. Also, the shift register 6501 has a plurality of output terminals OUT.

[0536] Also, FIG. 62 shows the switches 6503, loads 6504, and output terminals OUT in the first stage, second stage, third stage, and nth stage, respectively. Also, n is a natural number of 2 or more.

[0537] Also, the shift register 6501 is the same as that described in the eighth embodiment.

[0538] As shown in the circuit of FIG. 62, wiring 6502 is connected to load 6504 via switch 6503. Also, switch 6503 is controlled by shift register 6501.

[0539] Also, a transmission signal is supplied to wiring 6502. The transmission signal may be a current or a voltage.

[0540] Although not shown, a plurality of control signals and various power supply potentials are supplied to shift register 6501.

[0541] Next, the operation of the circuit shown in FIG. 62 will be described.

[0542] Shift register 6501 sequentially outputs an H signal or an L signal from the output terminal OUT(1) of the first stage. At the same time, switch 6503 is turned on sequentially from the first stage. Then, the transmission signal is supplied to load 6504 via switch 6503 sequentially from the first stage.

[0543] When an H signal is sequentially output from the output terminal OUT(1) of the first stage, an N-channel type transistor is used as switch 6503. When an L signal is sequentially output from the output terminal OUT(1) of the first stage, a P-channel type transistor is used as switch 6503.

[0544] Also, the circuit of FIG. 62 can supply different voltages or currents to a plurality of loads 6504 by changing the transmission signal at each timing of turning on and off switch 6503.

[0545] Here, the functions of shift register 6501 and switch 6503 will be described.​​​​​​​​​​

[0546] First, the shift register 6501 has a function of outputting a signal for selecting whether to turn on or off the switch 6503. Also, the shift register 6501 is the same as that shown in the eighth embodiment. First, the shift register 6501 has a function of outputting a signal for selecting whether to turn on or off the switch 6503. Also, the shift register 6501 is the same as that shown in the eighth embodiment. is the same as that shown in the eighth embodiment.

[0547] Also, the switch 6503 has a function of selecting whether to connect the wiring 6502 and the load 6504. has a function of selecting whether to connect the wiring 6502 and the load 6504.

[0548] As described above, the circuit shown in FIG. 62 can be configured with only N-channel type or only P-channel type for all transistors by using the shift register of the eighth embodiment. As described above, the circuit shown in FIG. 62 can be configured with only N-channel type or only P-channel type for all transistors by using the shift register of the eighth embodiment. type only.

[0549] Note that the circuit in FIG. 62 controls the on / off of one switch by one output signal of the shift register. However, the on / off of a plurality of switches may be controlled by one output signal of the shift register. Therefore, with reference to FIG. 63, the configuration when controlling the on / off of three switches by one output signal of the shift register will be described. Note that the circuit in FIG. 62 controls the on / off of one switch by one output signal of the shift register. However, the on / off of a plurality of switches may be controlled by one output signal of the shift register. Therefore, with reference to FIG. 63, the configuration when controlling the on / off of three switches by one output signal of the shift register will be described. switches may be controlled. Therefore, with reference to FIG. 63, the configuration when controlling the on / off of three switches by one output signal of the shift register will be described. switches by one output signal of the shift register will be described with reference to FIG. 63. will be described.

[0550] The circuit shown in FIG. 63 has a shift register 6601 and a plurality of switch groups 6605. Also, the shift register 6601 has a plurality of output terminals OUT. Also, the switch group 6605 has three switches. Also, the load group 6606 has three loads. The circuit shown in FIG. 63 has a shift register 6601 and a plurality of switch groups 6605. Also, the shift register 6601 has a plurality of output terminals OUT. Also, the switch group 6605 has three switches. Also, the load group 6606 has three loads. switch group 6605 has three switches. Also, the load group 6606 has three loads. has three loads.

[0551] Also, in FIG. 63, the switch group 6605, the load The load group 6606 and the output terminal OUT are respectively shown. Also, n is a natural number of 2 or more. 。

[0552] Also, the shift register 6601 is the same as that described in the eighth embodiment.

[0553] As shown in the circuit of FIG. 63, the wiring 6602, the wiring 6603, and the wiring 6604 are respectively connected to three loads of the load group 6606 through three switches of the switch group 6605. 。 Also, the three switches of the switch group 6605 are controlled by the shift register 6601. 。

[0554] Also, the transmission signal 1 is supplied to the wiring 6602, the transmission signal 2 is supplied to the wiring 6603, and the transmission signal 3 is supplied to the wiring 6604. Also, the transmission signal 1, the transmission signal 2, and the transmission signal 3 may be current or voltage. 。 。

[0555] Although not shown, a plurality of control signals and various power supply potentials are supplied to the shift register 6601. 。

[0556] Next, the operation of the circuit shown in FIG. 63 will be described.

[0557] The shift register 6601 sequentially outputs an H signal or an L signal from the output terminal OUT(1) of the first stage. At the same time, the three switches of the switch group 6605 are turned on in order from the first stage at the same timing. Then, the transmission signal 1, the transmission signal 2, and the transmission signal 3 are respectively supplied to the loads of the load group 6606 through the switch group 6605 in order from the first stage. 。 。 。 。

[0558] When an H signal is sequentially output from the output terminal OUT(1) of the first stage of the shift register 6601, an N-channel type transistor is used as the switch included in the switch group 6605. When an L signal is sequentially output from the output terminal OUT(1) of the first stage of the shift register 6601, a P-channel type transistor is used as the switch included in the switch group 6605. Also, in the circuit of FIG. 63, each time the timing of the on / off switching of the switches included in the switch group 6605 changes, the transmission signal 1, the transmission signal 2, and the transmission signal 3 are each changed. By doing so, different voltages or currents can be supplied to the loads included in the load group 6606.

[0559] Here, the functions of the shift register 6601 and the switch group 6605 will be described. First, the shift register 6601 has a function of outputting a signal for selecting whether to turn on or off the switches included in the switch group 6605 simultaneously. Also, the shift register 6601 is the same as that shown in the eighth embodiment.

[0560]

[0561]

[0562] Also, the switch group 6605 has a function of selecting whether to connect the wirings 6602, 6603, and 6604 and the load group 6606 to each other or not.

[0563] As described above, in the circuit shown in FIG. 63, the on / off of a plurality of switches can be controlled by one output signal of the shift register 6601. Also, as already described, by using the shift register of the eighth embodiment, all transistors can be of only the N-channel type, or ​​​​​​​​​​It can be configured with only P-channel types.

[0564] Here, a configuration in which the shift register shown in the eighth embodiment, which is different from FIGS. 62 and 63, is applied will be described with reference to FIG. 64. It will be described with reference to FIG. 64.

[0565] The circuit shown in FIG. 64 has a shift register 6701 and a plurality of switch groups 6705. The shift register 6701 has three output terminals OUT. Also, the switch group 6705 has three switches. Also, the load group 6706 has three loads. The switch group 6705 has three switches. Also, the load group 6706 has three loads. has.

[0566] Also, FIG. 64 shows the switch group 6705 and the load group 6706 in the first stage, second stage, and third stage. shown.

[0567] The shift register 6701 is the same as that described in the eighth embodiment.

[0568] As shown in the circuit of FIG. 64, a plurality of wirings 6707 are connected to the three loads of the load group 6706 through the three switches of the switch group 6705. Also, the three switches of the switch group 6705 are respectively controlled by the shift register 6701. The three switches of the switch group 6705 are respectively controlled by the shift register 6701. The three switches of the switch group 6705 are respectively controlled by the shift register 6701. controlled.

[0569] Also, an output signal from the first-stage output terminal OUT(1) of the shift register 6701 is supplied to the wiring 6702. An output signal from the second-stage output terminal OUT(2) of the shift register 6701 is supplied to the wiring 6703. An output signal from the third-stage output terminal OUT(3) of the shift register 6701 is supplied to the wiring 6704. An output signal from the second-stage output terminal OUT(2) of the shift register 6701 is supplied to the wiring 6703. An output signal from the second-stage output terminal OUT(2) of the shift register 6701 is supplied to the wiring 6703. An output signal from the third-stage output terminal OUT(3) of the shift register 6701 is supplied to the wiring 6704.

[0570] Also, a transmission signal 1 is supplied to the wiring 6707(1) of the first stage, a transmission signal 2 is supplied to the wiring 6707( 2) of the second stage, and a transmission signal 3 is supplied to the wiring 6707(3) of the third stage. Also, the transmission signal 1, the transmission signal 2, and the transmission signal 3 may be currents or voltages.

[0571] Although not shown in the figure, a plurality of control signals and various power supply potentials are supplied to the shift register 6701.

[0572] Next, the operation of the circuit shown in FIG. 64 will be described.

[0573] The shift register 6701 sequentially outputs an H signal or an L signal from the output terminal OUT(1) of the first stage. At the same time, the switches included in the switch group 6705 are sequentially turned on one by one. Therefore, one transmission signal is sequentially supplied to the loads included in the load group 6706.

[0574] When an H signal is sequentially output from the output terminal OUT(1) of the first stage of the shift register 6701, an N-channel type transistor is used as the switch included in the switch group 6705. When an L signal is sequentially output from the output terminal OUT(1) of the first stage of the shift register 6701, a P-channel type transistor is used as the switch included in the switch group 6705.

[0575] Also, the circuit in FIG. 64 can supply different voltages or currents to the loads included in the load group 6706 by changing each transmission signal at the timing of the on / off switching of the switches included in the switch group 6705.

[0576] ​​​​In this way, the circuit shown in Figure 64 can supply one transmission signal to multiple loads. In Figure 64, three switches are used in each switch group. Because a switch is used, the number of transmitted signals can be reduced by a factor of three.

[0577] As already mentioned, by using the shift register of the eighth embodiment, All transistors can be made up of only N-channel or only P-channel types. do.

[0578] This embodiment may be freely combined with any of the other embodiments described in this specification. In addition, any of the descriptions in this embodiment can be freely combined and implemented. It is possible.

[0579] (Tenth embodiment) In this embodiment, the layout diagram of the flip-flop circuit described in the third embodiment will be This will be described with reference to FIG.

[0580] FIG. 65 is a layout diagram of the flip-flop circuit shown in FIG. The layout diagram of the flip-flop circuit shows a polycrystalline semiconductor as the semiconductor layer of the transistor. In FIG. 65, the semiconductor layer 6 801, a gate electrode layer 6802, and a wiring layer 6803 are formed. do.

[0581] In the layout diagram of the flip-flop circuit in FIG. The sensor 2708 is located in the sensor area.

[0582] In the layout diagram of the flip-flop circuit shown in FIG. 65, the transistor 2705 has a dual gate structure.

[0583] Also, a wiring 2709 is arranged between each transistor and the wirings 2711a and 2711b. This is because the signals supplied to the wirings 2711a and 2711b become noise and affect the operation of each transistor. Therefore, since the wiring 2709 is arranged between each transistor and the wirings 2711a and 2711b, the wiring 2709 can suppress this noise.

[0584] Next, the layout diagram of the flip-flop circuit shown in FIG. 66 shows the case where an amorphous semiconductor (amorphous silicon) is used.

[0585] Also, a wiring 2709 is arranged between each transistor and the wirings 2711a and 2711b. This is because the signals supplied to the wirings 2711a and 2711b become noise and affect the operation of each transistor. Therefore, since the wiring 2709 is arranged between each transistor and the wirings 2711a and 2711b, the wiring 2709 can suppress this noise.

[0586] Note that this embodiment can be freely combined with any description of other embodiments in this specification. Also, any description in this embodiment can be freely combined and implemented.

[0587] (Embodiment 11) ​​​​​​​In the 11th embodiment, an example of a panel in which a plurality of pixels are formed will be described with reference to FIG. 75. As shown in FIG. 75(A), panel 191 has a pixel portion 591 composed of a plurality of pixels 590 arranged in a matrix. The pixel portion 591 can be configured in an active matrix system in which switching elements such as thin film transistors are arranged for each pixel 590. As a display medium of the pixel 590, a light emitting element such as an electroluminescence element may be provided, or a liquid crystal element may be provided.

[0588] As shown in FIG. 75(B), a drive circuit for driving the pixel portion 591 may be provided on the same substrate as the substrate on which the pixel portion 591 is formed. In FIG. 75(B), the same parts as those in FIG. 75(A) are denoted by the same reference numerals and the description thereof is omitted. In FIG. 75(B), a source driver 593 and a gate driver 594 are shown as the drive circuit. Note that the present invention is not limited to this, and in addition to the source driver 593 and the gate driver 594, a further drive circuit may be provided. The drive circuit may be formed on a separate substrate and mounted on the substrate on which the pixel portion 591 is formed. For example, the pixel portion 591 is formed on a glass substrate using a thin film transistor, and the drive circuit is formed using a single crystal substrate and its IC chip is connected to the glass substrate by COG (Chip On Glass). Alternatively, the IC chip may be connected to the glass substrate by TAB (Tape Automated Bonding), or may be connected to the glass substrate using a printed circuit board. Further, the drive circuit may be formed using a thin film transistor formed in the same process as the thin film transistor included in the pixel 590 on the same substrate as the substrate on which the pixel portion 591 is formed.

[0589] ​ The channel formation region of the thin film transistor may be formed of a polycrystalline semiconductor or an amorphous semiconductor.

[0590] Note that this embodiment can be freely combined with any description of other embodiments in this specification and implemented. Also, any descriptions in this embodiment can be freely combined and implemented .

[0591] (Embodiment 12) FIG. 76(A) shows a configuration example of the pixel portion 591 shown in FIGS. 75(A) and 75(B) (hereinafter referred to as the first pixel configuration). The pixel portion 591 includes a plurality of source signal lines S1 to Sp (p is a natural number), a plurality of scanning lines G1 to Gq (q is a natural number) provided so as to intersect the plurality of source signal lines S1 to Sp, and pixels 690 provided at each intersection of the source signal lines S1 to Sp and the scanning lines G1 to Gq.

[0592] The configuration of the pixel 690 in FIG. 76(A) is shown in FIG. 76(B). In FIG. 76(B), a pixel 690 formed at the intersection of one Sx (x is a natural number less than or equal to p) of the plurality of source signal lines S1 to Sp and one Gy (y is a natural number less than or equal to q) of the plurality of scanning lines G1 to Gq is shown. The pixel 690 includes a first transistor 691, a second transistor 692, a capacitor element 693, and a light-emitting element 694. In this embodiment, an example using a light-emitting element 694 having a pair of electrodes and emitting light when a current flows between the pair of electrodes is shown. Also, as the capacitor element 693, the parasitic capacitance of the second transistor 692 or the like may be positively utilized. The first transistor 691 and the second transistor 692 are n-channel It may be either a channel-type transistor or a p-channel type transistor. Pixel 6 As the transistor constituting 90 of the pixels, a thin film transistor can be used.

[0593] The gate of the first transistor 691 is connected to the scanning line Gy, and one of the source and drain of the first transistor 691 is connected to the source signal line Sx, and the other is connected to the gate of the second transistor 692 and one electrode of the capacitive element 693. The other electrode of the capacitive element 693 is connected to the terminal 695 to which the potential V3 is applied. One of the source and drain of the second transistor 692 is connected to one electrode of the light emitting element 694, and the other is connected to the terminal 696 to which the potential V2 is applied. The other electrode of the light emitting element 694 is connected to the terminal 697 to which the potential V1 is applied.

[0594] The display method of the pixel portion 591 shown in FIGS. 76(A) and 76(B) will be described.

[0595] One of the plurality of scanning lines G1 to Gq is selected, and image signals are input to all of the plurality of source signal lines S1 to Sp while the selected scanning line is selected. In this way, image signals are input to the pixels of one row of the pixel portion 591. The plurality of scanning lines G1 to Gq are sequentially selected and the same operation is performed to input image signals to all the pixels 690 of the pixel portion 591.

[0596] The operation of the pixel 690 in which one of the plurality of scanning lines G1 to Gq, Gy, is selected and an image signal is input from one of the plurality of source signal lines S1 to S p, Sx, will be described. When the scanning line Gy is selected, the first transistor 691 is turned on. The on state of the transistor means that the source and drain are in a conductive state, and the off state of the transistor means that when the scanning line Gy is selected, the first transistor 691 becomes on. The on state of the transistor means that the source and drain are in a conductive state, and the off state of the transistor means that the source and drain are in a non-conductive state. It is assumed that the source and the drain are in a non-conductive state. When the first transistor 691 is turned on, the image signal input to the source signal line Sx passes through the first transistor 6 91 and is input to the gate of the second transistor 692. The second transistor 69 2 selects an on state or an off state according to the input image signal. When the on state of the second transistor 692 is selected, the drain current of the second transistor 692 flows into the light-emitting element 694, and the light-emitting element 694 emits light.

[0597] The potential V2 and the potential V3 are kept such that the potential difference is always constant when the second transistor 692 is turned on. The potential V2 and the potential V3 may be the same potential. When the potential V2 and the potential V3 are the same potential, the terminal 695 and the terminal 696 may be connected to the same wiring. The potential V1 and the potential V2 are set to have a predetermined potential difference when the light emission of the light-emitting element 694 is selected. In this way, a current is passed through the light-emitting element 694 to cause the light-emitting element 694 to emit light. emit light.

[0598] Note that the wiring and electrodes are one or more elements selected from the group consisting of aluminum (Al), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (Ag), copper (Cu), magnesium (Mg ), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), and oxygen (O), and are composed of one or more elements selected from the group consisting of silicon (Si), phosphorus (P), boron (B), arsenic (As), gallium (Ga), indium (In), tin (Sn), and oxygen (O). Or a compound or alloy material composed of one or more elements selected from a group (for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), zinc oxide (ZnO), aluminum neodymium (Al-Nd ), magnesium silver (Mg-Ag), etc.), or a combination of these compounds substances, etc.). Or a compound of these with silicon (silicide) (for example, aluminum silicon, molybdenum silicon, nickel silicide, etc.), or a compound of these with nitrogen (for example, titanium nitride, tantalum nitride, molybdenum nitride, etc.). Note that silicon (Si) may contain a large amount of n-type impurities (such as phosphorus) or p-type impurities (such as boron). By containing these impurities, the conductivity is improved, or it behaves similarly to a normal conductor, making it easier to use as wiring or electrodes. Note that silicon may be single crystal, polycrystalline (polysilicon), or amorphous (amorphous silicon). By using single crystal silicon or polycrystalline silicon, the resistance can be reduced. By using amorphous silicon, it can be made in a simple manufacturing process. Note that aluminum and silver have high conductivity, so signal delay can be reduced and they are easy to etch, so they are easy to pattern and can be microfabricated. Note that copper has high conductivity, so signal delay can be reduced. Note that molybdenum can be manufactured without problems such as the material deteriorating when in contact with oxide semiconductors such as ITO and IZO, or silicon, and is easy to pattern and etch and has high heat resistance, so it is desirable. Note that titanium is an oxide semiconductor such as ITO and IZO and can be manufactured without problems such as the material deteriorating when in contact with oxide semiconductors such as ITO and IZO, or silicon, and is easy to pattern and etch and has high heat resistance, so it is desirable. Note that titanium is an oxide semiconductor such as ITO and IZO Even when in contact with silicon, it can be manufactured without problems such as material defects, and moreover, it is desirable because of its high heat resistance. Tungsten is desirable because of its high heat resistance . Neodymium is desirable because of its high heat resistance. In particular, when forming an alloy with aluminum , the heat resistance is improved and it becomes difficult for aluminum to cause hillock, so it is desirable. Silicon can be formed simultaneously with the semiconductor layer of the transistor, and it is desirable because of its high heat resistance. Indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), zinc oxide (Zn O), and silicon (Si) are desirable because they have light transmittance and can be used for parts that transmit light . For example, they can be used as pixel electrodes or common electrodes .

[0599] Note that the wiring and electrodes may be formed as a single layer or may have a multilayer structure. By forming a single-layer structure, the manufacturing process can be simplified, the number of process days can be reduced, and the cost can be reduced. Also, by forming a multilayer structure, the merits of each material can be utilized, the demerits can be reduced, and wiring and electrodes with good performance can be formed. For example, by including a material with low resistance (such as aluminum) in the multilayer structure, the resistance of the wiring can be reduced. Also, if a material with high heat resistance is included, for example, by forming a laminated structure in which a material with weak heat resistance but having other merits is sandwiched between materials with high heat resistance, the heat resistance of the entire wiring and electrodes can be increased. For example, a layer containing aluminum is sandwiched between layers containing molybdenum or titanium in such a form. It is desirable to form a laminated structure. Also, in a case where there is a portion that directly contacts wirings, electrodes, etc. made of another material, they may have an adverse effect on each other. For example, when one material enters into the other material, it may change the properties and fail to achieve the original purpose, or problems may occur during manufacturing and it may not be possible to manufacture normally. In such a case, the problem can be solved by sandwiching or covering a certain layer with another layer. For example, when it is desired to bring indium tin oxide (ITO) into contact with aluminum, it is desirable to sandwich titanium or molybdenum in between. Also, when it is desired to bring silicon into contact with aluminum, it is desirable to sandwich titanium or molybdenum in between.

[0600] Note that this embodiment can be freely combined with any description of other embodiments in this specification and implemented. Also, any descriptions in this embodiment can be freely combined and implemented .

[0601] (Embodiment 13) FIG. 77(A) shows a configuration example of the pixel portion 591 shown in FIGS. 75(A) and 75(B). FIG. 77(A) shows an example different from the first pixel configuration shown in the 12th embodiment (hereinafter referred to as the second pixel configuration). The pixel portion 591 includes a plurality of source signal lines S1 to Sp (p is a natural number), a plurality of scanning lines G1 to Gq (q is a natural number) and a plurality of scanning lines R1 to Rq provided so as to intersect with the plurality of source signal lines S1 to Sp, and pixels 790 provided at each intersection of the source signal lines S1 to Sp, the scanning lines G1 to Gq, and the scanning lines R1 to Rq.

[0602] The configuration of pixel 790 in FIG. 77(A) is shown in FIG. 77(B). In FIG. 77(B), one of the plurality of source signal lines S1 to Sp, Sx (x is a natural number less than or equal to p), one of the plurality of scan lines G1 to Gq, Gy (y is a natural number less than or equal to q), and one of the plurality of scan lines R1 to Rq, Ry, and the pixel 790 formed at the intersection is shown. In the pixel having the configuration shown in FIG. 77(B), the same parts as those in FIG. 76(B) are denoted by the same reference numerals, and the description thereof is omitted. In FIG. 77(B), the pixel 690 shown in FIG. 76(B) is different in that it has a third transistor 791. The third transistor 791 may be an n-channel transistor or a p-channel transistor. As the transistor constituting the pixel 790, a thin film transistor can be used.

[0603] The gate of the third transistor 791 is connected to the scan line Ry, and one of the source and drain of the third transistor 791 is connected to the gate of the second transistor 692 and one of the electrodes of the capacitor element 693, and the other is connected to a terminal 792 to which a potential V4 is applied.

[0604] The display method of the pixel portion 591 shown in FIGS. 77(A) and 77(B) will be described.

[0605] The method of causing the light emitting element 694 to emit light is the same as the method described in the twelfth embodiment. In the pixels having the configurations shown in FIGS. 77(A) and 77(B), by having the scan line Ry and the third transistor 791, regardless of the image signal input from the source signal line Sx, the light emitting element 694 of the pixel 790 can be made non-emissive. The time for the light emitting element 694 of the pixel 790 to emit light is set by the signal input to the scan line Ry. It is possible to set a light emission period shorter than the period during which all the scanning lines G1 to Gq are sequentially selected. Thus, when performing display in the time-division gradation method, a short sub-frame period can be set, and high gradation can be expressed. It is possible to set a light emission period shorter than the period during which all the scanning lines G1 to Gq are sequentially selected. Thus, when performing display in the time-division gradation method, a short sub-frame period can be set, and high gradation can be expressed. It is possible to set a light emission period shorter than the period during which all the scanning lines G1 to Gq are sequentially selected. Thus, when performing display in the time-division gradation method, a short sub-frame period can be set, and high gradation can be expressed.

[0606] The potential V4 may be set such that the second transistor 692 is turned off when the third transistor 791 is turned on. For example, when the third transistor 791 is turned on, the potential V4 can be set to the same potential as the potential V3. By setting the potential V3 and the potential V4 to the same potential, the charge held in the capacitive element 693 is discharged, and the voltage between the source and the gate of the second transistor 692 is set to zero, so that the second transistor 692 can be turned off. When the potential V3 and the potential V4 are set to the same potential, the terminal 695 and the terminal 792 may be connected to the same wiring. The potential V4 may be set such that the second transistor 692 is turned off when the third transistor 791 is turned on. For example, when the third transistor 791 is turned on, the potential V4 can be set to the same potential as the potential V3. By setting the potential V3 and the potential V4 to the same potential, the charge held in the capacitive element 693 is discharged, and the voltage between the source and the gate of the second transistor 692 is set to zero, so that the second transistor 692 can be turned off. When the potential V3 and the potential V4 are set to the same potential, the terminal 695 and the terminal 792 may be connected to the same wiring. The potential V4 may be set such that the second transistor 692 is turned off when the third transistor 791 is turned on. For example, when the third transistor 791 is turned on, the potential V4 can be set to the same potential as the potential V3. By setting the potential V3 and the potential V4 to the same potential, the charge held in the capacitive element 693 is discharged, and the voltage between the source and the gate of the second transistor 692 is set to zero, so that the second transistor 692 can be turned off. When the potential V3 and the potential V4 are set to the same potential, the terminal 695 and the terminal 792 may be connected to the same wiring. The potential V4 may be set such that the second transistor 692 is turned off when the third transistor 791 is turned on. For example, when the third transistor 791 is turned on, the potential V4 can be set to the same potential as the potential V3. By setting the potential V3 and the potential V4 to the same potential, the charge held in the capacitive element 693 is discharged, and the voltage between the source and the gate of the second transistor 692 is set to zero, so that the second transistor 692 can be turned off. When the potential V3 and the potential V4 are set to the same pote...

Claims

1. having first to fourth transistors and a circuit, one of the source or drain of the first transistor is electrically connected to an output signal line, the other of the source or drain of the first transistor is electrically connected to a clock signal line, one of the source or drain of the second transistor is electrically connected to the output signal line, the other of the source or drain of the second transistor is electrically connected to a power supply line, one of the source or drain of the third transistor is electrically connected to the gate of the first transistor, the other of the source or drain of the third transistor is electrically connected to a first signal line, the gate of the third transistor is electrically connected to the first signal line, one of the source or drain of the fourth transistor is electrically connected to the gate of the first transistor, the other of the source or drain of the fourth transistor is electrically connected to the power supply line, the gate of the third transistor is electrically connected to a second signal line, the input terminal of the circuit is electrically connected to the clock signal line, a semiconductor device in which the output terminal of the circuit is electrically connected to the gate of the second transistor.

2. having first to fourth transistors and a circuit, one of the source or drain of the first transistor is electrically connected to an output signal line, the other of the source or drain of the first transistor is electrically connected to a clock signal line, one of the source or drain of the second transistor is electrically connected to the output signal line, the other of the source or drain of the second transistor is electrically connected to a power supply line, one of the source or drain of the third transistor is electrically connected to the gate of the first transistor, the other of the source or drain of the third transistor is electrically connected to a first signal line, the gate of the third transistor is electrically connected to the first signal line, one of the source or drain of the fourth transistor is electrically connected to the gate of the first transistor, the other of the source or drain of the fourth transistor is electrically connected to the power supply line, the gate of the third transistor is electrically connected to a second signal line, The first input terminal of the circuit is electrically connected to the clock signal line, The second input terminal of the circuit is electrically connected to the gate of the first transistor, A semiconductor device in which the output terminal of the circuit is electrically connected to the gate of the second transistor.

3. In claim 1 or claim 2, The circuit has a fifth transistor, The gate of the fifth transistor is electrically connected to the clock signal line, A semiconductor device in which one of the source or drain of the fifth transistor is electrically connected to the gate of the second transistor.

Images