Chip component

Abstract

To increase the resistance against external force.SOLUTION: A chip component includes a substrate 20, a first insulating layer 30 formed on the substrate 20, first to fifth capacitors formed in the first insulating layer 30, a second insulating layer 40 formed on the first insulating layer 30, a first coil LA and a second coil formed in the second insulating layer 40 and electrically connected to the first to fifth capacitors, an external electrode 110 electrically connected to at least any of the first to fifth capacitors among the first to fifth capacitors, the first coil LA, and the second coil, and a sealing resin 120 that covers the second insulating layer 40 and a side surface of the external electrode 110 and exposes an upper surface of the external electrode 110.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] The present disclosure relates to chip components.

Background Art

[0002] Patent Document 1 discloses a chip component including an LC circuit including a capacitor and an inductor.

Prior Art Document

Patent Document

[0003]

Patent Document 1

[0004] [Summary] By the way, in chip components, resistance to external forces may be required.

[0005] A chip component according to an aspect of the present disclosure includes a substrate, a first insulating layer formed on the substrate, a capacitor formed in the first insulating layer, a second insulating layer formed on the first insulating layer, a coil formed in the second insulating layer and electrically connected to the capacitor, an external electrode electrically connected to at least the capacitor of the capacitor and the coil, and a sealing resin that covers the second insulating layer and covers a side surface of the external electrode and exposes an upper surface of the external electrode.

Brief Description of the Drawings

[0006]

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[0007] [Detailed Description] Hereinafter, some embodiments of the chip component in the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn at a certain scale. Also, for ease of understanding, the hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0008] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is merely for illustrative purposes and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] As used herein, the expression "at least one" means "one or more" of the desired options. As an example, as used herein, the expression "at least one" means "only one option" or "both of the two options" if the number of options is two. As another example, as used herein, the expression "at least one" means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] As used herein, "the dimension of A (depth, width, length) is equal to the dimension of B (depth, width, length)" or "the dimension of A (depth, width, length) and the dimension of B (depth, width, length) are equal to each other" includes a relationship in which the difference between the dimension of A (depth, width, length) and the dimension of B (depth, width, length) is within 10% of the dimension of A (depth, width, length), for example.

[0011] <Embodiment> [Schematic Configuration of Chip Component] Referring to FIGS. 1 and 2, the schematic configuration of a chip component 10 according to an embodiment will be described. FIG. 1 shows the electrical configuration of the chip component 10. FIG. 2 schematically shows the overall configuration of the chip component 10.

[0012] (Circuit Configuration) As shown in FIG. 1, the chip component 10 includes first to third external terminals 11 to 13 as a plurality of external terminals and an LC circuit 14.

[0013] The first external terminal 11 and the second external terminal 12 constitute input / output terminals. More specifically, the first external terminal 11 and the second external terminal 12 are configured as input terminals for transmitting an input signal to the LC circuit 14 or output terminals for transmitting an output signal from the LC circuit 14 to the outside. When the first external terminal 11 is configured as an input terminal, the second external terminal 12 is configured as an output terminal. When the first external terminal 11 is configured as an output terminal, the second external terminal 12 is configured as an input terminal. The third external terminal 13 constitutes a reference terminal. More specifically, the third external terminal 13 is configured to transmit a reference voltage (for example, a ground voltage) to the LC circuit 14.

[0014] The LC circuit 14 includes a ladder filter circuit constituted by a first coil LA, a second coil LB, and first to fifth capacitors CA to CE. More specifically, the LC circuit 14 includes an elliptic filter circuit. The elliptic filter circuit is, for example, a ladder elliptic low-pass filter circuit.

[0015] The first coil LA is electrically connected to the first external terminal 11. The second coil LB is electrically connected to the second external terminal 12. The first coil LA and the second coil LB are electrically connected to each other.

[0016] The first capacitor CA is electrically connected to the first external terminal 11 and the third external terminal 13. The second capacitor CB is connected in parallel to the first coil LA. The third capacitor CC is electrically connected to the node N between the first coil LA and the second coil LB. The fourth capacitor CD is connected in parallel to the second coil LB. The fifth capacitor CE is electrically connected to the second external terminal 12 and the third external terminal 13.

[0017] Thus, the elliptic filter circuit includes an L-type filter circuit and a π-type filter circuit from the first external terminal 11 to the second external terminal 12. The L-type filter circuit includes the first capacitor CA, the second capacitor CB, and the first coil LA. The π-type filter circuit includes the third to fifth capacitors CC to CE and the second coil LB.

[0018] Also, the elliptic filter circuit includes an L-type filter circuit and a π-type filter circuit from the second external terminal 12 to the first external terminal 11. The L-type filter circuit includes the fourth capacitor CD, the fifth capacitor CE, and the second coil LB. The π-type filter circuit includes the first to third capacitors CA to CC and the first coil LA.

[0019] Also, the elliptic filter circuit includes the first capacitor CA, a T-type filter circuit, and the fifth capacitor CE from the first external terminal 11 to the second external terminal 12. The T-type filter circuit includes the second to fourth capacitors CB to CD, the first coil LA, and the second coil LB.

[0020] Note that the LC circuit 14 is not limited to the ladder filter circuit and can be arbitrarily changed. That is, the number of coils and the number of capacitors in the LC circuit 14 can be arbitrarily changed respectively. Each of the coil and the capacitor may have one or more.

[0021] (Schematic overall configuration of chip components) As shown in FIG. 2, the chip component 10 includes a substrate 20, a first insulating layer 30, a second insulating layer 40, and a third insulating layer 50. The first insulating layer 30 is formed on the substrate 20. In one example, the first insulating layer 30 is laminated on the substrate 20. The third insulating layer 50 is laminated on the first insulating layer 30. The second insulating layer 40 is formed on the first insulating layer 30. In one example, the second insulating layer 40 is laminated on the third insulating layer 50. Note that in FIG. 2, in order to show the first to fifth capacitors CA to CE, the thickness of the first insulating layer 30 is shown thick. Therefore, the relationship between the thicknesses of the first insulating layer 30, the second insulating layer 40, and the third insulating layer 50 in FIG. 2 is different from the actual relationship between the thicknesses of the first insulating layer 30, the second insulating layer 40, and the third insulating layer 50.

[0022] The first to fifth capacitors CA to CE are provided in the first insulating layer 30. Each of the first to fifth capacitors CA to CE includes a first electrode CA1 to CE1 and a second electrode CA2 to CE2 that are arranged to face each other in the thickness direction of the first insulating layer 30.

[0023] The second electrode CA2 of the first capacitor CA is electrically connected to the first electrode CB1 of the second capacitor CB. The second electrode CB2 of the second capacitor CB is electrically connected to the second electrode CC2 of the third capacitor CC. The second electrode CC2 of the third capacitor CC is electrically connected to the second electrode CD2 of the fourth capacitor CD. The first electrode CD1 of the fourth capacitor CD is electrically connected to the second electrode CE2 of the fifth capacitor CE. The first electrode CC1 of the third capacitor CC is electrically connected to the first electrode CA1 of the first capacitor CA and the first electrode CE1 of the fifth capacitor CE.

[0024] The first coil LA and the second coil LB are provided in the second insulating layer 40. The first coil LA is formed in a spiral shape in a plan view. The second coil LB is formed in a spiral shape in a plan view. The first coil LA includes a first end 71A and a second end 72A. The second coil LB includes a first end 71B and a second end 72B. The second end 72A of the first coil LA and the second end 72B of the second coil LB are electrically connected to each other.

[0025] The first to third external terminals 11 to 13 are provided on the second insulating layer 40. The first to third external terminals 11 to 13 are arranged spaced apart from each other on the second insulating layer 40. The first external terminal 11 is electrically connected to the first coil LA, the first capacitor CA, and the second capacitor CB. The second external terminal 12 is electrically connected to the second coil LB, the fourth capacitor CD, and the fifth capacitor CE. The third external terminal 13 is electrically connected to the first capacitor CA, the third capacitor CC, and the fifth capacitor CE.

[0026] The chip component 10 includes a first connection electrode 80, second connection electrodes 90A, 90B, and third connection electrodes 100A, 100B. The first connection electrode 80 electrically connects the second end 72A of the first coil LA and the second end 72B of the second coil LB to the second electrode CC2 of the third capacitor CC.

[0027] The second connection electrode 90A electrically connects the first external terminal 11, the second electrode CA2 of the first capacitor CA, the first end 71A of the first coil LA, and the first electrode CB1 of the second capacitor CB. The second connection electrode 90B electrically connects the second external terminal 12, the second electrode CE2 of the fifth capacitor CE, the first end 71B of the second coil LB, and the first electrode CD1 of the fourth capacitor CD.

[0028] The third connection electrode 100A electrically connects the third external terminal 13, the first electrode CA1 of the first capacitor CA, and the first electrode CC1 of the third capacitor CC. The third connection electrode 100B electrically connects the third external terminal 13, the first electrode CC1 of the third capacitor CC, and the first electrode CE1 of the fifth capacitor CE.

[0029] (Specific configuration of chip component) With reference to FIGS. 3 to 5, an example of the overall configuration of the chip component 10 will be described. FIG. 3 schematically shows a perspective structure of the chip component 10. FIG. 4 schematically shows an exploded perspective structure of the chip component 10. In FIG. 4, for ease of understanding of the drawing, the encapsulating resin 120 described later is omitted. FIG. 5 schematically shows a cross-sectional structure of the chip component 10 cut along the line F5-F5 of FIG. 3. In the present disclosure, the term "plan view" means viewing the chip component 10 or a component of the chip component 10 in the Z direction of the XYZ axes orthogonal to each other in FIG. 1.

[0030] In the following description, in the Z direction, the direction from the substrate 20 toward the external electrode 110 described later is defined as "upward", and the direction from the external electrode 110 toward the substrate 20 is defined as "downward". For this reason, in the components of the chip component 10, the "upper surface" is the surface facing upward, and the "lower surface" is the surface facing downward. Also, in the components of the chip component 10, the "side surface" is the surface intersecting the Z direction. Also, the X direction is an example of the "first direction".

[0031] As shown in FIGS. 3 and 4, the chip component 10 includes an encapsulating resin 120. The encapsulating resin 120 surrounds the third insulating layer 50 and the second insulating layer 40. The chip component 10 is formed in a rectangular parallelepiped shape in which the Z direction is the thickness direction, the X direction is the length direction, and the Y direction is the width direction. In this embodiment, the dimension of the chip component 10 in the Z direction is 0.4 mm or more and 1.2 mm or less, the dimension of the chip component 10 in the X direction is 1.0 mm or more and 1.2 mm or less, and the dimension of the chip component 10 in the Y direction is 0.5 mm or more and 0.6 mm or less. Note that each dimension of the chip component 10 can be arbitrarily changed.

[0032] The chip component 10 includes external electrodes 110 exposed in the Z direction from the encapsulating resin 120. In one example, the external electrodes 110 are provided on the second insulating layer 40. The external electrodes 110 include a first external electrode 111, a second external electrode 112, and a third external electrode 113 arranged at intervals from each other in the X direction. The first external electrode 111 and the second external electrode 112 are disposed at both ends in the X direction of the chip component 10. The third external electrode 113 is disposed between the first external electrode 111 and the second external electrode 112 in the X direction. The first external electrode 111 constitutes the first external terminal 11 (see FIG. 2), the second external electrode 112 constitutes the second external terminal 12 (see FIG. 2), and the third external electrode 113 constitutes the third external terminal 13 (see FIG. 2).

[0033] The first to third external electrodes 111 to 113 are formed in a rectangular flat plate shape with the Z direction as the thickness direction. In one example, the first external electrode 111 and the second external electrode 112 have the same size as each other. The third external electrode 113 has a size larger than that of the first external electrode 111 and the second external electrode 112. In one example, the dimension of the third external electrode 113 in the X direction is larger than the dimension of the first external electrode 111 (the second external electrode 112) in the X direction. The dimension of the third external electrode 113 in the Y direction is larger than the dimension of the first external electrode 111 (the second external electrode 112) in the Y direction.

[0034] In one example, the first to third external electrodes 111 to 113 are constituted by pillars made of Cu or a Cu alloy. A bonding layer 115 is provided on the upper surfaces of the first to third external electrodes 111 to 113. The thickness of the first to third external electrodes 111 to 113 is, for example, about 20 μm. The bonding layer 115 may include, for example, a solder electrode. The thickness of the solder electrode is, for example, about 25 μm. Also, the bonding layer 115 may include, for example, a NiPdAu layer. The thickness of the NiPdAu layer is, for example, about 7 μm.

[0035] In one example, the sum of the thickness of the first external electrode 111 and the thickness of the bonding layer 115 is 25 μm or more and 70 μm or less. In another example, the thickness of the portion of the first external electrode 111 and the bonding layer 115 that protrudes in the Z direction from the encapsulating resin 120 is 5 μm or more and 50 μm or less. Note that each of the sum of the thickness of the second external electrode 112 and the thickness of the bonding layer 115, and the sum of the thickness of the third external electrode 113 and the thickness of the bonding layer 115 is 25 μm or more and 70 μm or less. In another example, the thickness of the portion of the second external electrode 112 and the bonding layer 115 that protrudes in the Z direction from the encapsulating resin 120 is 5 μm or more and 50 μm or less. In another example, the thickness of the portion of the third external electrode 113 and the bonding layer 115 that protrudes in the Z direction from the encapsulating resin 120 is 5 μm or more and 50 μm or less.

[0036] The substrate 20 is formed in a rectangular parallelepiped shape. The substrate 20 includes a first substrate surface 21, a second substrate surface 22 facing the opposite side of the first substrate surface 21, and first to fourth substrate side surfaces 23 to 26 connecting the first substrate surface 21 and the second substrate surface 22.

[0037] The first substrate surface 21 and the second substrate surface 22 are formed in a rectangular shape in which the X direction is the longitudinal direction and the Y direction is the short-side direction in plan view. The first substrate side surface 23 and the second substrate side surface 24 constitute both end faces of the substrate 20 in the X direction, and the third substrate side surface 25 and the fourth substrate side surface 26 constitute both end faces of the substrate 20 in the Y direction.

[0038] For the substrate 20, for example, a semiconductor substrate is used. In one example, the substrate 20 is a silicon (Si) substrate. Therefore, the chip component 10 can also be referred to as a semiconductor device.

[0039] The thickness of the substrate 20 may be 50 μm or more and 500 μm or less. The thickness of the substrate 20 may be 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, or 400 μm or more and 500 μm or less. In one example, the thickness of the substrate 20 is 50 μm or more and 150 μm or less. Here, the thickness of the substrate 20 can be defined by the distance in the Z direction between the first substrate surface 21 and the second substrate surface 22.

[0040] As shown in FIG. 4, the first insulating layer 30 includes a portion formed over the entire surface of the first substrate surface 21 of the substrate 20. The first insulating layer 30 is composed of, for example, an inorganic insulating layer. Examples of the inorganic insulating layer include silicon oxide (SiO2) and silicon nitride (SiN). The first insulating layer 30 is composed of a laminated structure of a plurality of insulating films.

[0041] The first insulating layer 30 is formed in a thin film shape with the Z direction as the thickness direction. The first insulating layer 30 includes a first upper surface 30S and a first lower surface 30R facing opposite sides in the Z direction, and first to fourth side surfaces 30A to 30D connecting the first upper surface 30S and the first lower surface 30R. The first upper surface 30S faces the same side as the first substrate surface 21 of the substrate 20, and the first lower surface 30R faces the same side as the second substrate surface 22 of the substrate 20. The first lower surface 30R is in contact with the first substrate surface 21. The first side surface 30A and the second side surface 30B constitute both end faces of the first insulating layer 30 in the X direction, and the third side surface 30C and the fourth side surface 30D constitute both end faces of the first insulating layer 30 in the Y direction. The first side surface 30A faces the same side as the first substrate side surface 23 of the substrate 20, and the second side surface 30B faces the same side as the second substrate side surface 24 of the substrate 20. The third side surface 30C faces the same side as the third substrate side surface 25 of the substrate 20, and the fourth side surface 30D faces the same side as the fourth substrate side surface 26 of the substrate 20.

[0042] The first insulating layer 30 includes first to third insulating films 31 to 33 (see FIG. 8) laminated in the Z direction. The first insulating film 31 is in contact with the first substrate surface 21 of the substrate 20. The second insulating film 32 is laminated on the first insulating film 31. The third insulating film 33 is laminated on the second insulating film 32. In this embodiment, the first insulating film 31 is formed of a silicon oxide film. Both the second insulating film 32 and the third insulating film 33 are formed of a silicon nitride film. That is, the relative dielectric constants of both the second insulating film 32 and the third insulating film 33 are larger than the relative dielectric constant of the first insulating film 31. In particular, the second insulating film 32 is formed as a dielectric layer of the first to fifth capacitors CA to CE (see FIG. 2). Therefore, the second insulating film 32 is preferably an insulating film having a high relative dielectric constant. That is, the second insulating film 32 is preferably formed of a silicon nitride film.

[0043] Note that the constituent materials of the first to third insulating films 31 to 33 can be arbitrarily changed. In one example, the first insulating film 31 may be formed of a silicon nitride film. In one example, each of the second insulating film 32 and the third insulating film 33 may be formed of a silicon oxide film. Also, the number of laminated insulating films of the first insulating layer 30 can be arbitrarily changed within a range in which the first to fifth capacitors CA to CE can be formed.

[0044] The thickness of the first insulating layer 30 is less than the thickness of the substrate 20. The thickness of the first insulating layer 30 is thinner than the thicknesses of the first to third external electrodes 111 to 113. The thickness of the first insulating layer 30 may be 0.3 μm or more and 12 μm or less. The thickness of the first insulating layer 30 may be 0.3 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, 8 μm or more and 10 μm or less, or 10 μm or more and 12 μm or less. In one example, the thickness of the first insulating layer 30 may be 0.6 μm or more and 6 μm or less. The thickness of each of the first to third insulating films 31 to 33 may be 0.1 μm or more and 4 μm or less. In one example, the thickness of each of the first to third insulating films 31 to 33 may be 0.1 μm or more and 4 μm or less. In one example, the thickness of each of the first to third insulating films 31 to 33 may be 0.2 μm or more and 2 μm or less. In one example, the thicknesses of the first to third insulating films 31 to 33 may be the same as each other or different from each other. Here, the thickness of the first insulating layer 30 can be defined by the distance in the Z direction between the first upper surface 30S and the first lower surface 30R. The thickness of the first insulating film 31 can be defined by the distance in the Z direction between the upper surface and the lower surface of the first insulating film 31. The thickness of the second insulating film 32 can be defined by the distance in the Z direction between the upper surface and the lower surface of the second insulating film 32. The thickness of the third insulating film 33 can be defined by the distance in the Z direction between the upper surface and the lower surface of the third insulating film 33.

[0045] In the first to fifth capacitors CA to CE provided in the first insulating layer 30, first electrodes CA1 to CE1 (see FIG. 2) are formed on the first insulating film 31, and second electrodes CA2 to CE2 (see FIG. 2) are formed on the second insulating film 32. The second insulating film 32 covers the first electrodes CA1 to CE1. The third insulating film 33 covers the second electrodes CA2 to CE2.

[0046] The third insulating layer 50 is formed in a thin film shape with the Z direction as the thickness direction. The third insulating layer 50 is constituted by, for example, an organic insulating layer. The third insulating layer 50 is constituted by, for example, polyimide (PI). The third insulating layer 50 is interposed between the first insulating layer 30 and the second insulating layer 40 in the Z direction and is configured to be in contact with both the first insulating layer 30 and the second insulating layer 40. The third insulating layer 50 includes a third lower surface 50R (see FIG. 15) in contact with the third insulating film 33 of the first insulating layer 30 and a third upper surface 50S in contact with the second insulating layer 40. The third lower surface 50R is formed in an uneven shape according to the shape of the third insulating film 33 of the first insulating layer 30. On the other hand, the third upper surface 50S is formed by a plane orthogonal to the Z direction.

[0047] The thickness of the third insulating layer 50 is greater than the thickness of the first insulating layer 30. On the other hand, the thickness of the third insulating layer 50 is less than the thickness of the substrate 20. In one example, the thickness of the third insulating layer 50 is less than the thicknesses of the first to third external electrodes 111 to 113. In one example, the thickness of the third insulating layer 50 may be 2 μm or more and 20 μm or less. In this embodiment, the thickness of the first insulating layer 30 is about 1.2 μm, and the thickness of the third insulating layer 50 is about 4 μm. Here, the thickness of the third insulating layer 50 can be defined by the distance in the Z direction between the third upper surface 50S and the third lower surface 50R. Note that the thickness of the third insulating layer 50 can be arbitrarily changed. In one example, the thickness of the third insulating layer 50 may be less than the thickness of the first insulating layer 30. In another example, the thickness of the third insulating layer 50 may be equal to the thickness of the first insulating layer 30.

[0048] The third upper surface 50S of the third insulating layer 50 is constituted by a rougher surface than the third lower surface 50R. In one example, the third upper surface 50S is constituted by a surface roughened by an ashing process. That is, the surface roughness of the third upper surface 50S is greater than the surface roughness of the third lower surface 50R. In one example, the arithmetic surface roughness (Ra) of the third upper surface 50S is greater than the arithmetic surface roughness of the third lower surface 50R. In one example, the ashing process is performed over the entire surface of the third upper surface 50S.

[0049] The third insulating layer 50 is formed in a rectangular shape that is slightly smaller than the substrate 20 in a plan view. Therefore, the outer peripheral edge of the third insulating layer 50 is disposed at a position spaced apart from the first to fourth substrate side surfaces 23 to 26 of the substrate 20 in a plan view.

[0050] The second insulating layer 40 is formed in a flat plate shape with the Z direction as the thickness direction. The second insulating layer 40 is composed of an organic insulating layer. Examples of the organic insulating layer include a photosensitive resin layer and a thermosetting resin layer. Examples of the photosensitive resin layer include a photosensitive insulating film such as an epoxy resin and a photosensitive polyimide. The second insulating layer 40 is formed in a rectangular parallelepiped shape with the Z direction as the thickness direction. The second insulating layer 40 is formed in a rectangular shape in which the X direction is the longitudinal direction and the Y direction is the short side direction in a plan view. In one example, in a plan view, the second insulating layer 40 is formed in a rectangular shape that is slightly smaller than the substrate 20. The second insulating layer 40 includes a second upper surface 40S and a second lower surface 40R facing opposite sides in the Z direction, and first to fourth side surfaces 40A to 40D connecting the second upper surface 40S and the second lower surface 40R. The second upper surface 40S faces the same side as the first substrate surface 21, and the second lower surface 40R faces the same side as the second substrate surface 22. The second insulating layer 40 is in contact with the third upper surface 50S of the third insulating layer 50 on the second lower surface 40R. The first to fourth side surfaces 40A to 40D are formed, for example, flush with the side surfaces of the third insulating layer 50. The first side surface 40A faces the same side as the first side surface 30A of the first insulating layer 30, and the second side surface 40B faces the same side as the second side surface 30B of the first insulating layer 30. The third side surface 40C faces the same side as the third side surface 30C of the first insulating layer 30, and the fourth side surface 40D faces the same side as the fourth side surface 30D of the first insulating layer 30.

[0051] The second insulating layer 40 includes first to third insulating films 41 to 43 laminated in the Z direction. The first insulating film 41 is disposed closer to the substrate 20 in the Z direction. In one example, the first insulating film 41 is in contact with the third upper surface 50S of the third insulating layer 50. The second insulating film 42 is laminated on the first insulating film 41. The third insulating film 43 is laminated on the second insulating film 42. The first insulating film 41 constitutes the second lower surface 40R of the second insulating layer 40. The third insulating film 43 constitutes the second upper surface 40S of the second insulating layer 40. The first coil LA and the second coil LB (both see FIG. 5) are provided in the second insulating film 42. The first to third external electrodes 111 to 113 are provided on the third insulating film 43. In this embodiment, the first to third insulating films 41 to 43 are made of an epoxy resin as an example of a photosensitive resin layer.

[0052] Note that the constituent materials of the first to third insulating films 41 to 43 can be arbitrarily changed. In one example, at least one of the first to third insulating films 41 to 43 may be made of a photosensitive polyimide. Also, the number of laminated insulating films of the second insulating layer 40 can be arbitrarily changed within a range where the first coil LA and the second coil LB can be formed.

[0053] The thickness of the second insulating layer 40 is thicker than the thickness of the first insulating layer 30. The thickness of the second insulating layer 40 is thicker than the thickness of the third insulating layer 50. In one example, the thickness of the second insulating layer 40 is thicker than the thickness of the first to third external electrodes 111 to 113. The thickness of the second insulating layer 40 may be thicker than, for example, the thickness of the substrate 20. The thickness of the second insulating layer 40 may be 30 μm or more and 600 μm or less. The thickness of the second insulating layer 40 may be 30 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, or 400 μm or more and 500 μm or less. In one example, the thickness of the second insulating layer 40 may be 60 μm or more and 210 μm. Here, the thickness of the second insulating layer 40 can be defined by the distance in the Z direction between the second upper surface 40S and the second lower surface 40R.

[0054] The thickness of each of the first to third insulating films 41 to 43 may be 10 μm or more and 200 μm or less. In one example, the thickness of each of the first to third insulating films 41 to 43 may be 20 μm or more and 70 μm or less. In one example, the thicknesses of the first to third insulating films 41 to 43 are equal to each other. Note that the thicknesses of the first to third insulating films 41 to 43 may be different from each other, or the thickness of one insulating film may be different from the thicknesses of the other two insulating films. The thickness of the second insulating film 42 provided with the first coil LA and the second coil LB may be greater than the thickness of the first insulating layer 30. Also, the thickness of each of the first to third insulating films 41 to 43 may be greater than the thickness of the first insulating layer 30.

[0055] [Detailed Configuration of Capacitor] With reference to FIGS. 6 to 11, an example of the detailed configuration of the first to fifth capacitors CA to CE will be described.

[0056] FIG. 6 shows a schematic plan structure showing an example of the electrode structure on the first insulating film 31 of the first insulating layer 30. FIG. 7 shows a schematic plan structure showing an example of the electrode structure on the second insulating film 32 of the first insulating layer 30. FIG. 8 schematically shows a cross-sectional structure obtained by cutting the first insulating layer 30 along the line F8-F8 in FIG. 7. FIG. 9 schematically shows a cross-sectional structure obtained by cutting the first insulating layer 30 along the line F9-F9 in FIG. 7. FIG. 10 schematically shows a cross-sectional structure obtained by cutting the first insulating layer 30 along the line F10-F10 in FIG. 7. FIG. 11 schematically shows a cross-sectional structure obtained by cutting the first insulating layer 30 along the line F11-F11 in FIG. 7.

[0057] As shown in FIGS. 6 and 7, the first to fifth capacitors CA to CE are arranged to be separated from each other in a direction orthogonal to the Z direction. The first capacitor CA and the second capacitor CB are arranged closer to the first side surface 30A than the center in the X direction of the first insulating layer 30 in a plan view. The first capacitor CA and the second capacitor CB are arranged to be separated from each other in the Y direction. When viewed from the Y direction, the first capacitor CA and the second capacitor CB are arranged at positions overlapping each other. The fourth capacitor CD and the fifth capacitor CE are arranged closer to the second side surface 30B than the center in the X direction of the first insulating layer 30 in a plan view. The fourth capacitor CD and the fifth capacitor CE are arranged to be separated from each other in the Y direction. When viewed from the Y direction, the fourth capacitor CD and the fifth capacitor CE are arranged at positions overlapping each other. The fourth capacitor CD is adjacent to the first capacitor CA in the X direction. The fifth capacitor CE is adjacent to the second capacitor CB in the X direction. The third capacitor CC is arranged at the center in the X direction of the first insulating layer 30 in a plan view. A part of the third capacitor CC is arranged between the first capacitor CA and the second capacitor CB in the Y direction. The remaining part of the third capacitor CC is arranged between the fourth capacitor CD and the fifth capacitor CE in the Y direction.

[0058] As shown in FIG. 6, the first electrodes CA1 to CE1 of the first to fifth capacitors CA to CE are provided on the first insulating film 31. As shown in FIG. 7, the second electrodes CA2 to CE2 of the first to fifth capacitors CA to CE are provided on the second insulating film 32. As shown in FIGS. 8 to 11, the second insulating film 32 is interposed between the first electrodes CA1 to CE1 and the second electrodes CA2 to CE2 in the Z direction. Therefore, the second insulating film 32 constitutes the dielectric layer of the first to fifth capacitors CA to CE. Hereinafter, the detailed configurations of the second electrodes CA2 to CE2 and the first electrodes CA1 to CE1 will be described.

[0059] As shown in FIG. 6, on the first insulating film 31, a first wiring 61 that constitutes the first electrodes CA1, CC1, CE1, a second wiring 62 that constitutes the first electrode CB1, and a third wiring 63 that constitutes the first electrode CD1 are provided. The first to third wirings 61 to 63 are configured as a metal layer (wiring layer). The thickness of each of the first to third wirings 61 to 63 may be 0.1 μm or more and 5 μm or less. The thickness of each of the first to third wirings 61 to 63 may be 0.1 μm or more and 0.3 μm or less, 0.3 μm or more and 0.6 μm or less, 0.6 μm or more and 0.9 μm or less, 0.9 μm or more and 1.2 μm or less, 1.2 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, or 4 μm or more and 5 μm or less. In one example, the thickness of each of the first to third wirings 61 to 63 may be less than 1 μm. In one example, the thickness of each of the first to third wirings 61 to 63 may be 0.2 μm or more and 0.8 μm or less.

[0060] Each of the first to third wirings 61 to 63 includes a laminated structure of an aluminum (Al) layer and a titanium nitride (TiN) layer. The Al layer may include at least one of a pure Al layer (an Al layer composed of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer. The TiN layer is formed over the entire upper surface of the Al layer. The thickness of the TiN layer is thinner than the thickness of the Al layer.

[0061] The first wiring 61 includes a first electrode portion 61A that constitutes the first electrode CA1, a second electrode portion 61B that constitutes the first electrode CC1, and a third electrode portion 61C that constitutes the first electrode CE1. The first wiring 61 includes a shape that is point-symmetrical with respect to the center of the first insulating layer 30 in a plan view. Here, the center of the first insulating layer 30 is the center in the X direction and the center in the Y direction of the first insulating layer 30 in a plan view.

[0062] The first electrode portion 61A is disposed closer to the first side surface 30A of the first insulating layer 30 in the X direction. In one example, the first electrode portion 61A extends along the first side surface 30A and the fourth side surface 30D in a plan view.

[0063] The first electrode portion 61A includes a first portion 61AA extending in the X direction at a position adjacent to the third side surface 30C in the Y direction, and a second portion 61AB extending in the Y direction while meandering at a position adjacent to the first side surface 30A in the X direction. The width dimension WA1 of the first portion 61AA is larger than the width dimension WA2 of the second portion 61AB. The second portion 61AB includes a portion extending in the X direction after meandering.

[0064] The second electrode portion 61B is disposed at the center of the first insulating layer 30 in the X direction. The second wiring 62 is rectangular in a plan view, with the X direction being the short side direction and the Y direction being the long side direction. The width dimension WB of the second electrode portion 61B is larger than the width dimension WA1 of the first portion 61AA.

[0065] The third electrode portion 61C is disposed closer to the second side surface 30B of the first insulating layer 30 in the X direction. In one example, the third electrode portion 61C extends along the second side surface 30B and the fourth side surface 30D in a plan view. The third electrode portion 61C has a point-symmetrical relationship with the first electrode portion 61A. For this reason, the third electrode portion 61C includes a first portion 61CA and a second portion 61CB, similar to the first electrode portion 61A. The first portion 61CA has a point-symmetrical relationship with the first portion 61AA of the first electrode portion 61A, and the second portion 61CB has a point-symmetrical relationship with the second portion 61AB of the first electrode portion 61A. For this reason, the width dimension WC1 of the first portion 61CA is equal to the width dimension WA1 of the first portion 61AA of the first electrode portion 61A. The width dimension WC2 of the second portion 61CB is equal to the width dimension WA2 of the second portion 61AB of the first electrode portion 61A.

[0066] The second wiring 62 is disposed closer to the first side surface 30A of the first insulating layer 30 in the X direction. The second wiring 62 is disposed closer to the fourth side surface 30D of the first insulating layer 30 than the first electrode portion 61A of the first wiring 61 in the Y direction.

[0067] The second wiring 62 includes a first portion 62A extending in the X direction and a second portion 62B extending from the intermediate portion of the first portion 62A in the X direction toward the fourth side surface 30D. The second portion 62B is formed in an L shape in a plan view. The second portion 62B is disposed at a position adjacent to the second portion 61AB of the first electrode portion 61A of the first wiring 61 in a plan view.

[0068] The width dimension WD of the first portion 62A is larger than the width dimension WA1 of the first portion 61AA of the first electrode portion 61A. The width dimension WE of the second portion 62B is larger than the width dimension WB of the second portion 61AB of the first electrode portion 61A.

[0069] The third wiring 63 is disposed closer to the second side surface 30B of the first insulating layer 30 in the X direction. The third wiring 63 is disposed closer to the fourth side surface 30D of the first insulating layer 30 than the third electrode portion 61C of the first wiring 61 in the Y direction. The third wiring 63 has a point-symmetrical relationship with the second wiring 62. Therefore, the third wiring 63 includes a first portion 63A and a second portion 63B in the same manner as the second wiring 62. The first portion 63A has a point-symmetrical relationship with the first portion 62A of the second wiring 62, and the second portion 63B has a point-symmetrical relationship with the second portion 62B of the second wiring 62. Therefore, the width dimension WF of the first portion 63A is equal to the width dimension WD of the first portion 62A of the second wiring 62. The width dimension WG of the second portion 63B is equal to the width dimension WE of the second portion 62B of the second wiring 62.

[0070] As shown in FIG. 7, on the second insulating film 32, a fourth wiring 64 constituting the second electrode CA2, a fifth wiring 65 constituting the second electrode CB2, a sixth wiring 66 constituting the second electrode CC2, a seventh wiring 67 constituting the second electrode CD2, and an eighth wiring 68 constituting the second electrode CE2 are provided. The fourth to eighth wirings 64 to 68 are configured as a metal layer (wiring layer). In one example, the fourth to eighth wirings 64 to 68 are made of the same material as the first to third wirings 61 to 63. In one example, the thicknesses of the fourth to eighth wirings 64 to 68 are equal to each other. In one example, the thicknesses of the fourth to eighth wirings 64 to 68 are thinner than the thicknesses of the first to third wirings 61 to 63.

[0071] Note that the materials constituting the fourth to eighth wirings 64 to 68 can be arbitrarily changed. The materials constituting the fourth to eighth wirings 64 to 68 may be different from the materials constituting the first to third wirings 61 to 63. Also, the thicknesses of the fourth to eighth wirings 64 to 68 can be arbitrarily changed. In one example, the thicknesses of the fourth to eighth wirings 64 to 68 may be equal to the thicknesses of the first to third wirings 61 to 63. In one example, the thicknesses of the fourth to eighth wirings 64 to 68 may be greater than the thicknesses of the first to third wirings 61 to 63.

[0072] As shown in FIGS. 7 and 8, the fourth wiring 64 is disposed to face the first electrode portion 61A of the first wiring 61 in the Z direction. The fourth wiring 64 includes a first opposing portion 64A that faces a first portion 61AA of the first electrode portion 61A and a second opposing portion 64B that faces a second portion 61AB of the first electrode portion 61A. The length of the first opposing portion 64A in the X direction is shorter than the length of the first portion 61AA of the first electrode portion 61A in the X direction. The second opposing portion 64B faces the entire surface of the second portion 61AB of the first electrode portion 61A. In this way, the first capacitor CA is formed by the fourth wiring 64, the first electrode portion 61A, and the second insulating film 32 interposed between the fourth wiring 64 and the first electrode portion 61A.

[0073] As shown in FIGS. 7 and 10, the fifth wiring 65 is disposed to face the second wiring 62 in the Z direction. The fifth wiring 65 includes a first opposing portion 65A that faces a first portion 62A of the second wiring 62 and a second opposing portion 65B that faces a second portion 62B of the second wiring 62. The first opposing portion 65A faces the entire surface of the first portion 62A of the second wiring 62. In plan view, the second portion 62B of the second wiring 62 includes a portion protruding from the second opposing portion 65B. The area of the second opposing portion 65B is smaller than the area of the second portion 62B of the second wiring 62. In this way, the second capacitor CB is formed by the fifth wiring 65, the second wiring 62, and the second insulating film 32 interposed between the fifth wiring 65 and the second wiring 62.

[0074] As shown in FIGS. 7 and 9, the sixth wiring 66 is disposed to face the second electrode portion 61B of the first wiring 61 in the Z direction. The sixth wiring 66 is formed in a rectangular shape in which the X direction is the short side direction and the Y direction is the long side direction in plan view. The sixth wiring 66 faces the entire surface of the second electrode portion 61B. In this way, the third capacitor CC is constituted by the sixth wiring 66, the second electrode portion 61B, and the second insulating film 32 interposed between the sixth wiring 66 and the second electrode portion 61B.

[0075] As shown in FIGS. 7 and 8, the seventh wiring 67 is disposed to face the third wiring 63 in the Z direction. The seventh wiring 67 includes a first facing portion 67A facing the first portion 63A of the third wiring 63 and a second facing portion 67B facing the second portion 63B of the third wiring 63. In plan view, the second portion 63B of the third wiring 63 includes a portion protruding from the second facing portion 67B. The area of the second facing portion 67B is smaller than the area of the second portion 63B of the third wiring 63. In this way, the fourth capacitor CD is constituted by the seventh wiring 67, the third wiring 63, and the second insulating film 32 interposed between the seventh wiring 67 and the third wiring 63.

[0076] As shown in FIGS. 7 and 10, the eighth wiring 68 is disposed to face the third electrode portion 61C of the first wiring 61 in the Z direction. The eighth wiring 68 includes a first facing portion 68A facing the first portion 61CA of the third electrode portion 61C and a second facing portion 68B facing the second portion 61CB of the third electrode portion 61C. The length of the first facing portion 68A in the X direction is shorter than the length of the first portion 61CA of the third electrode portion 61C in the X direction. The second facing portion 68B faces the entire surface of the second portion 61CB of the third electrode portion 61C. In this way, the fifth capacitor CE is constituted by the eighth wiring 68, the third electrode portion 61C, and the second insulating film 32 interposed between the eighth wiring 68 and the third electrode portion 61C.

[0077] As shown in FIGS. 7 to 10, the capacitances of the first to fifth capacitors CA to CE are proportional to the facing areas of the wirings in the Z direction. Here, the facing area means the area of the region where the wirings overlap in plan view.

[0078] The facing area between the fourth wiring 64 and the first electrode portion 61A of the first wiring 61 is smaller than the facing area between the sixth wiring 66 and the second electrode portion 61B of the first wiring 61. The facing area between the fourth wiring 64 and the first electrode portion 61A of the first wiring 61 is equal to the facing area between the eighth wiring 68 and the third electrode portion 61C of the first wiring 61. The facing area between the fourth wiring 64 and the first electrode portion 61A of the first wiring 61 is larger than the facing area between the fifth wiring 65 and the second wiring 62. The facing area between the fourth wiring 64 and the first electrode portion 61A of the first wiring 61 is larger than the facing area between the seventh wiring 67 and the third wiring 63. The facing area between the fifth wiring 65 and the second wiring 62 is equal to the facing area between the seventh wiring 67 and the third wiring 63.

[0079] Therefore, the capacitance of the first capacitor CA is smaller than the capacitance of the third capacitor CC. The capacitance of the first capacitor CA is larger than the capacitance of the second capacitor CB. The capacitance of the first capacitor CA is larger than the capacitance of the fourth capacitor CD. The capacitance of the first capacitor CA is equal to the capacitance of the fifth capacitor CE. The capacitance of the second capacitor CB is equal to the capacitance of the fourth capacitor CD.

[0080] (Connection structure of capacitors) With reference to FIGS. 7 to 11, the connection structure of the first to fifth capacitors CA to CE will be described.

[0081] As shown in FIG. 7, the chip component 10 includes first to fourth intermediate wirings 131 to 134 and first to fourth vias 135 to 138. As shown in FIGS. 8 to 11, each of the first to fourth intermediate wirings 131 to 134 is provided on the second insulating film 32 of the first insulating layer 30. Each of the first to fourth vias 135 to 138 penetrates the second insulating film 32 in the Z direction. Each of the first to fourth intermediate wirings 131 to 134 is composed of a material containing at least one of, for example, Cu and Al. In one example, each of the first to fourth intermediate wirings 131 to 134 is composed of the same material as, for example, the fourth to eighth wirings 64 to 68. The first to fourth vias 135 to 138 are composed of a material containing at least one of, for example, Ti, tungsten (W), Al, and Cu.

[0082] As shown in FIGS. 7 and 8, the first intermediate wiring 131 faces the first electrode portion 61A of the first wiring 61. The first intermediate wiring 131 is disposed at a position adjacent in the X direction to the first facing portion 64A of the fourth wiring 64 and adjacent in the Y direction to the fifth wiring 65. The first intermediate wiring 131 is connected to the first wiring 61 by the first via 135. The first intermediate wiring 131 is connected to the third connection electrode 100A.

[0083] As shown in FIGS. 7 and 11, the second intermediate wiring 132 faces the tip of the second portion 62B of the second wiring 62. The second intermediate wiring 132 is disposed at a position adjacent in the X direction to the tip of the second facing portion 65B of the fifth wiring 65. The second intermediate wiring 132 is connected to the second wiring 62 by the second via 136. The second intermediate wiring 132 is connected to the second connection electrode 90A.

[0084] As shown in FIGS. 7 and 9, the third intermediate wiring 133 faces the tip of the second portion 63B of the third wiring 63. The third intermediate wiring 133 is disposed at a position adjacent in the X direction to the tip of the second facing portion 67B of the seventh wiring 67. The third intermediate wiring 133 is connected to the third wiring 63 by the third via 137. The third intermediate wiring 133 is connected to the second connection portion 80B of the first connection electrode 80.

[0085] As shown in FIGS. 7 and 10, the fourth intermediate wiring 134 faces the third electrode portion 61C of the first wiring 61. The fourth intermediate wiring 134 is disposed between the first facing portion 68A of the eighth wiring 68 and the first facing portion 65A of the fifth wiring 65 in the X direction. The fourth intermediate wiring 134 is connected to the first wiring 61 by the fourth via 138. Therefore, the fourth intermediate wiring 134 has the same potential as the first intermediate wiring 131. The fourth intermediate wiring 134 is connected to the third connection electrode 100B.

[0086] [Detailed Configuration of Coil] Referring to FIGS. 12 and 13, an example of the detailed configuration of the first coil LA and the second coil LB will be described. FIG. 12 shows a schematic plan structure of rewiring layers 82, 84, 87, 92, 95, 102, 106, which will be described later, on the first insulating film 41 of the second insulating layer 40. FIG. 13 shows a schematic plan structure of the first coil LA and the second coil LB on the second insulating film 42 of the second insulating layer 40, a part of the first connection electrode 80, a part of the second connection electrodes 90A and 90B, and a part of the third connection electrodes 100A and 100B, which will be described later.

[0087] As shown in FIG. 13, the first coil LA and the second coil LB are arranged at the same position in the Y direction and separated from each other in the X direction. The first coil LA is arranged closer to the first side surface 40A with respect to the center of the second insulating layer 40 in a plan view. The second coil LB is arranged closer to the second side surface 40B with respect to the center of the second insulating layer 40 in a plan view. The first coil LA and the second coil LB are arranged at the same position in the Z direction. In one example, the first coil LA and the second coil LB are arranged on the first insulating film 41 (see FIG. 12) of the second insulating layer 40.

[0088] The first coil LA includes a spiral winding portion 73A, a first end portion 71A that constitutes the inner end portion of the winding portion 73A, and a second end portion 72A that constitutes the outer end portion of the winding portion 73A in a plan view. Both the first end portion 71A and the second end portion 72A extend along the Y direction in a plan view. The first coil LA includes an inner region 74A that is inner than the winding portion 73A. The inner region 74A is mainly constituted by the second insulating film 42.

[0089] The second coil LB includes a spiral winding portion 73B in a plan view, a first end portion 71B constituting the inner end portion of the winding portion 73B, and a second end portion 72B constituting the outer end portion of the winding portion 73B. In one example, the winding direction of the winding portion 73B and the winding direction of the winding portion 73A are opposite to each other. Both the first end portion 71B and the second end portion 72B extend along the Y direction in a plan view. The second coil LB includes an inner region 74B that is inward of the winding portion 73B. The inner region 74B is mainly constituted by the second insulating film 42.

[0090] As shown in FIGS. 12 and 13, the first end portion 71A of the first coil LA is connected to the second connection electrode 90A. The first end portion 71B of the second coil LB is connected to the second connection electrode 90B. The second end portion 72A of the first coil LA and the second end portion 72B of the second coil LB are electrically connected by the first connection electrode 80.

[0091] The first coil LA and the second coil LB are provided so as to penetrate the second insulating film 42 of the second insulating layer 40 in the Z direction. In one example, the thickness of the winding portion 73A of the first coil LA and the thickness of the winding portion 73B of the second coil LB are equal to the thickness of the second insulating film 42. For this reason, the thickness of the winding portion 73A of the first coil LA and the thickness of the winding portion 73B of the second coil LB are thicker than the thickness of the first insulating layer 30. Also, the thickness of the winding portion 73A of the first coil LA and the thickness of the winding portion 73B of the second coil LB are thicker than the thickness of the third insulating layer 50.

[0092] [Detailed Configuration of Connection Electrodes] With reference to FIGS. 12 to 18, an example of the detailed configuration of the first connection electrode 80, the second connection electrodes 90A and 90B, and the third connection electrodes 100A and 100B will be described.

[0093] FIG. 14 schematically shows a planar structure of a third insulating film 43 of the second insulating layer 40. FIG. 15 schematically shows a cross-sectional structure obtained by cutting the chip component 10 along the line F15-F15 in FIG. 14. FIG. 16 schematically shows a cross-sectional structure obtained by cutting the chip component 10 along the line F16-F16 in FIG. 14. FIG. 17 schematically shows a cross-sectional structure obtained by cutting the chip component 10 along the line F17-F17 in FIG. 14. FIG. 18 schematically shows a cross-sectional structure obtained by cutting the chip component 10 along the line F18-F18 in FIG. 14. For the first insulating layer 30, the first to eighth wirings 61 to 68, and the first to fifth capacitors CA to CE, refer to the first insulating layer 30, the first to eighth wirings 61 to 68, and the first to fifth capacitors CA to CE in FIGS. 6 to 11.

[0094] (First connection electrode) As shown in FIG. 13, the first connection electrode 80 includes first to third connection portions 80A to 80C. The first connection portion 80A electrically connects the sixth wiring 66 of the third capacitor CC, the second end portion 72A of the first coil LA, and the second end portion 72B of the second coil LB to each other. The second connection portion 80B electrically connects the fifth wiring 65 of the second capacitor CB and the sixth wiring 66 of the third capacitor CC. The third connection portion 80C electrically connects the seventh wiring 67 of the fourth capacitor CD and the sixth wiring 66 of the third capacitor CC.

[0095] As shown in FIG. 16, the first connection electrode 80 is provided on both the first insulating layer 30 and the second insulating layer 40. In one example, the first connection electrode 80 is provided across the first insulating layer 30, the third insulating layer 50, and the second insulating layer 40. More specifically, the first connection portion 80A penetrates the third insulating film 33 of the first insulating layer 30, the third insulating layer 50, and the first insulating film 41 of the second insulating layer 40 in the Z direction. The first connection portion 80A includes one or more (two in this embodiment) first vias 81 and a first rewiring layer 82.

[0096] As shown in FIG. 13, the two first vias 81 are arranged at positions adjacent to each other in the X direction between the second end portion 72A of the first coil LA and the second end portion 72B of the second coil LB. The two first vias 81 are arranged so as to be displaced from each other in the Y direction. Each first via 81 is formed in an oval shape extending in the Y direction in plan view.

[0097] As shown in FIG. 16, the first via 81 penetrates the third insulating film 33 of the first insulating layer 30, the third insulating layer 50, and the first insulating film 41 of the second insulating layer 40 in the Z direction. The first via 81 is connected to the sixth wiring 66 of the third capacitor CC. The first via 81 includes a first portion 81A penetrating the first insulating film 41 and a second portion 81B penetrating the third insulating layer 50 and the third insulating film 33. The dimension of the second portion 81B in the X direction is smaller than the dimension of the first portion 81A in the X direction. Also, as shown in FIG. 18, the dimension of the second portion 81B in the Y direction is smaller than the dimension of the first portion 81A in the Y direction.

[0098] The first portion 81A is joined to the first rewiring layer 82. The second portion 81B is joined to the sixth wiring 66 of the third capacitor CC. Therefore, the joining area between the second portion 81B and the sixth wiring 66 is smaller than the joining area between the first portion 81A and the first rewiring layer 82.

[0099] As shown in FIG. 16, the first rewiring layer 82 is provided on the first insulating film 41 of the second insulating layer 40. More specifically, the first rewiring layer 82 is in contact with the upper surface 42S of the second insulating film 42. The thickness of the first rewiring layer 82 is thinner than the thickness of the second insulating film 42. The first rewiring layer 82 is arranged between the winding portions 73A of the first coil LA and the winding portions 73B of the second coil LB in the X direction in plan view. The first rewiring layer 82 is formed in a rectangular shape in plan view. In one example, the thickness of the first rewiring layer 82 is about 8 μm.

[0100] As shown in FIG. 13, the second end portion 72A of the first coil LA and the second end portion 72B of the second coil LB are provided on the first rewiring layer 82. The second end portion 72A of the first coil LA is provided at an end closer to the first coil LA among both end portions in the X direction of the first rewiring layer 82 in a plan view. The second end portion 72A extends along the Y direction. The length of the second end portion 72A in the Y direction is longer than the length of the first portion 81A of the first via 81 in the Y direction. The second end portion 72B of the second coil LB is provided at an end closer to the second coil LB among both end portions in the X direction of the first rewiring layer 82 in a plan view. The second end portion 72B extends along the Y direction. The length of the second end portion 72B in the Y direction is longer than the length of the first portion 81A of the first via 81 in the Y direction. In one example, the length of the second end portion 72B in the Y direction is equal to the length of the second end portion 72A of the first coil LA in the Y direction.

[0101] Note that each of the length of the second end portion 72A of the first coil LA and the length of the second end portion 72B of the second coil LB in the Y direction can be arbitrarily changed. In one example, the length of the second end portion 72B in the Y direction may be longer or shorter than the length of the second end portion 72A of the first coil LA in the Y direction.

[0102] As shown in FIG. 16, the thickness of the second end portion 72A of the first coil LA is thinner than the thickness of the wound portion 73A of the first coil LA by the thickness of the first rewiring layer 82. The sum of the thickness of the second end portion 72A and the thickness of the first rewiring layer 82 is equal to the thickness of the second insulating film 42 of the second insulating layer 40. The thickness of the second end portion 72A of the first coil LA is thicker than the thickness of the first insulating layer 30. Also, the thickness of the second end portion 72A of the first coil LA is thicker than the thickness of the third insulating layer 50.

[0103] The thickness of the second end portion 72B of the second coil LB is thinner than the thickness of the winding portion 73B of the second coil LB by the thickness of the first rewiring layer 82. The sum of the thickness of the second end portion 72B and the thickness of the first rewiring layer 82 is equal to the thickness of the second insulating film 42 of the second insulating layer 40. For this reason, the thickness of the second end portion 72B is equal to the thickness of the second end portion 72A of the first coil LA. The thickness of the second end portion 72A of the first coil LA and the thickness of the second end portion 72B of the second coil LB are thicker than the thickness of the first insulating layer 30. Also, the thickness of the second end portion 72A of the first coil LA and the thickness of the second end portion 72B of the second coil LB are thicker than the thickness of the third insulating layer 50. In one example, both the thickness of the second end portion 72B of the second coil LB and the thickness of the second end portion 72A of the first coil LA are about 22 μm.

[0104] As shown in FIG. 18, the second connection portion 80B penetrates the third insulating film 33 of the first insulating layer 30, the third insulating layer 50, and the first insulating film 41 and the second insulating film 42 of the second insulating layer 40 in the Z direction. As shown in FIGS. 12 and 13, the second connection portion 80B is disposed closer to the third side surface 40C of the second insulating layer 40 than the first connection portion 80A. The second connection portion 80B includes a second via 83, a second rewiring layer 84, and a first connection layer 85.

[0105] As shown in FIG. 18, the second via 83 penetrates the third insulating film 33 of the first insulating layer 30, the third insulating layer 50, and the first insulating film 41 of the second insulating layer 40 in the Z direction. The second via 83 is connected to the fifth wiring 65 of the second capacitor CB. The second via 83 is formed in an oval shape extending in the Y direction in plan view. The second via 83 includes a first portion 83A that penetrates the first insulating film 41 and a second portion 83B that penetrates the third insulating layer 50 and the third insulating film 33 (see FIG. 8). The dimension of the second portion 83B in the X direction is smaller than the dimension of the first portion 83A in the X direction. Also, the dimension of the second portion 83B in the Y direction is smaller than the dimension of the first portion 83A in the Y direction.

[0106] The first part 83A is joined to the second rewiring layer 84. The second part 83B is joined to the fifth wiring 65 of the second capacitor CB. Therefore, the joining area between the second part 83B and the fifth wiring 65 is smaller than the joining area between the first part 83A and the second rewiring layer 84.

[0107] As shown in FIGS. 12 and 13, the second rewiring layer 84 is disposed closer to the third side surface 40C of the second insulating layer 40 than the first rewiring layer 82. Also, the second rewiring layer 84 is disposed at a position overlapping the first rewiring layer 82 when viewed from the Y direction. The second rewiring layer 84 is formed in a substantially rectangular shape in which the Y direction is the longitudinal direction and the X direction is the short side direction. As shown in FIG. 13, the second rewiring layer 84 includes a notch formed so as to avoid the winding portion 73A of the first coil LA. The thickness of the second rewiring layer 84 is equal to, for example, the thickness of the first rewiring layer 82.

[0108] The first connection layer 85 connects the first rewiring layer 82 and the second rewiring layer 84. The first connection layer 85 extends in the Y direction in plan view. The first connection layer 85 is disposed closer to the first rewiring layer 82 than the second via 83 in plan view. The first connection layer 85 is disposed closer to the second coil LB than the second via 83 in plan view. Also, the first connection layer 85 is disposed closer to the second rewiring layer 84 than the first via 81 of the first connection portion 80A in plan view. The first connection layer 85 is disposed at the same position as the first via 81 in the X direction.

[0109] As shown in FIG. 18, the first connection layer 85 includes a first connection end portion 85A, a second connection end portion 85B, and an intermediate portion 85C. The first connection end portion 85A is a portion of the first connection layer 85 provided on the first rewiring layer 82. The first connection end portion 85A is in contact with the upper surface of the first rewiring layer 82. The second connection end portion 85B is a portion of the first connection layer 85 provided on the second rewiring layer 84. The second connection end portion 85B is in contact with the upper surface of the second rewiring layer 84. The intermediate portion 85C is a portion of the first connection layer 85 between the first rewiring layer 82 and the second rewiring layer 84 in the X direction. The intermediate portion 85C is provided on the second insulating film 42 of the second insulating layer 40. The intermediate portion 85C is in contact with the upper surface 42S of the second insulating film 42. In one example, the thickness of the intermediate portion 85C is equal to the thickness of the second insulating film 42. The thickness of the intermediate portion 85C is greater than the thicknesses of the first connection end portion 85A and the second connection end portion 85B. The first connection end portion 85A is thinner than the intermediate portion 85C by the thickness of the first rewiring layer 82. The second connection end portion 85B is thinner than the intermediate portion 85C by the thickness of the second rewiring layer 84. When the thickness of the first rewiring layer 82 is equal to the thickness of the second rewiring layer 84, the thickness of the first connection end portion 85A is equal to the thickness of the second connection end portion 85B.

[0110] In one example, the thickness of the intermediate portion 85C is about 30 μm. In one example, the thicknesses of both the first connection end portion 85A and the second connection end portion 85B are about 22 μm. In one example, the thickness of the second rewiring layer 84 is about 8 μm.

[0111] As shown in FIG. 13, the third connection portion 80C is disposed closer to the fourth side surface 40D of the second insulating layer 40 than the first connection portion 80A. The third connection portion 80C includes a third via 86, a third rewiring layer 87, and a second connection layer 88. In one example, the third via 86, the third rewiring layer 87, and the second connection layer 88 are in a point-symmetrical relationship with the second via 83, the second rewiring layer 84, and the first connection layer 85 of the second connection portion 80B with respect to the center of the second insulating layer 40. Although not shown, the third connection portion 80C, similar to the second connection portion 80B, penetrates the third insulating film 33 of the first insulating layer 30, the third insulating layer 50, and the first insulating film 41 and the second insulating film 42 of the second insulating layer 40 in the Z direction.

[0112] The third via 86 is connected to the seventh wiring 67 of the fourth capacitor CD. The third via 86 is connected to the third rewiring layer 87. The third via 86 is oval in shape extending in the Y direction in plan view. The configuration of the third via 86 is the same as that of the second via 83. The third rewiring layer 87 has a shape that is point-symmetrical to the second rewiring layer 84 in plan view. The second connection layer 88 connects the first rewiring layer 82 and the third rewiring layer 87. The configuration of the second connection layer 88 is the same as that of the first connection layer 85. The second connection layer 88 is arranged at a position different from that of the two first vias 81 in plan view.

[0113] Although not shown, the thickness of the third via 86 is, for example, equal to the thickness of the second via 83. The thickness of the third rewiring layer 87 is, for example, equal to the thickness of the first rewiring layer 82. The thickness of the second connection layer 88 is, for example, equal to the thickness of the first connection layer 85.

[0114] (Second connection electrode) As shown in FIGS. 12 to 15, the second connection electrodes 90A and 90B are arranged spaced apart from each other in the X direction. The second connection electrodes 90A and 90B are dispersedly arranged on both sides in the X direction of the third capacitor CC. The second connection electrode 90A is arranged closer to the first side surface 40A of the second insulating layer 40 than the third capacitor CC in the X direction. The second connection electrode 90B is arranged closer to the second side surface 40B of the second insulating layer 40 than the third capacitor CC in the X direction.

[0115] The second connection electrode 90A includes two first vias 91A and 91B, a rewiring layer 92, and a second via 93. The first vias 91A and 91B, the rewiring layer 92, and the second via 93 are made of a material containing, for example, Cu. In one example, the first vias 91A and 91B, the rewiring layer 92, and the second via 93 are made of the same material as each other.

[0116] As shown in FIGS. 12 and 13, the first via 91A is connected to the fourth wiring 64 of the first capacitor CA. The first via 91B is electrically connected to the second wiring 62 of the second capacitor CB. More specifically, the first via 91B is connected to the second intermediate wiring 132 (see FIG. 7). As described above, the second intermediate wiring 132 is connected to the second wiring 62 by the second via 136.

[0117] The first vias 91A and 91B are arranged at the same position in the X direction and separated from each other in the Y direction. Each of the first vias 91A and 91B is formed in an oval shape extending in the Y direction in plan view. As shown in FIG. 13, the first vias 91A and 91B are arranged at positions different from the first end portion 71A of the first coil LA in plan view. The first vias 91A and 91B are arranged in the inner region 74A of the first coil LA.

[0118] As shown in FIG. 15, the first via 91A includes a first portion 91AA that penetrates the first insulating film 41 of the second insulating layer 40, and a second portion 91AB that penetrates the third insulating film 33 of the third insulating layer 50 and the first insulating layer 30.

[0119] The first portion 91AA is joined to the rewiring layer 92. The second portion 91AB is joined to the fourth wiring 64 of the first capacitor CA. The dimension of the second portion 91AB in the X direction is smaller than the dimension of the first portion 91AA in the X direction. Although not shown, the dimension of the second portion 91AB in the Y direction is smaller than the dimension of the first portion 91AA in the X direction. Therefore, the joining area between the second portion 91AB and the fourth wiring 64 is smaller than the joining area between the first portion 91AA and the rewiring layer 92.

[0120] As shown in FIGS. 13 and 14, the rewiring layer 92 includes a portion disposed in the inner region 74A of the first coil LA. The rewiring layer 92 is formed in a rectangular shape in plan view. As shown in FIG. 15, the rewiring layer 92 is provided on the second insulating film 42 of the second insulating layer 40. In one example, the rewiring layer 92 is in contact with the upper surface 42S of the second insulating film 42.

[0121] As shown in FIG. 13, the first end portion 71A of the first coil LA is provided on the rewiring layer 92. The first end portion 71A is disposed at an end portion closer to the first side surface 40A of the second insulating layer 40 among both end portions of the rewiring layer 92 in the X direction. As shown in FIG. 14, the first vias 91A and 91B are disposed at an end portion closer to the second coil LB among both end portions of the rewiring layer 92 in the X direction.

[0122] As shown in FIG. 13, the first end portion 71A extends along the Y direction. The length of the first end portion 71A in the Y direction is longer than the length of each of the first vias 91A and 91B in the Y direction. In one example, the width dimension of the first end portion 71A is equal to the width dimension of the first portion 91AA of the first vias 91A and 91B. Here, the width dimension of the first end portion 71A is the dimension of the first end portion 71A in the X direction. The width dimension of the first portion 91AA of the first vias 91A and 91B is the dimension of the first portion 91AA in the X direction.

[0123] Thus, the bonding area between the first end portion 71A and the rewiring layer 92 is larger than the bonding area between the first portion 91AA (see FIG. 15) of the first via 91A and the rewiring layer 92. Also, the bonding area between the first end portion 71A and the rewiring layer 92 is larger than the bonding area between the first portion of the first via 91B and the rewiring layer 92. That is, the bonding area between the first end portion 71A and the rewiring layer 92 is larger than the bonding area between the first via 91A and the fourth wiring 64. Also, the bonding area between the first end portion 71A and the rewiring layer 92 is larger than the bonding area between the first via 91B and the second intermediate wiring 132.

[0124] As shown in FIG. 15, the thickness of the first end portion 71A of the first coil LA is thinner than the thickness of the winding portion 73A of the first coil LA by the thickness of the rewiring layer 92. The sum of the thickness of the first end portion 71A and the thickness of the rewiring layer 92 is equal to the thickness of the second insulating film 42. The thickness of the first end portion 71A of the first coil LA is thicker than the thickness of the first insulating layer 30. The thickness of the first end portion 71A of the first coil LA is thicker than the thickness of the third insulating layer 50.

[0125] The second via 93 is provided on the first end portion 71A of the first coil LA. That is, the second via 93 is disposed at a position overlapping the first end portion 71A in a plan view. The second via 93 penetrates the third insulating film 43 of the second insulating layer 40 in the Z direction. The second via 93 is in contact with the first external electrode 111. The dimension of the second via 93 in the X direction is larger than the dimension of the first end portion 71A of the first coil LA in the X direction.

[0126] Note that the dimension of the second via 93 in the X direction can be arbitrarily changed. In one example, the dimension of the second via 93 in the X direction may be equal to or less than the dimension of the first end portion 71A of the first coil LA in the X direction.

[0127] The thickness relationship of each component of the second connection electrode 90A is as follows. That is, the thickness (dimension in the Z direction) of the first vias 91A and 91B is thicker than the thickness of the first end portion 71A of the first coil LA. The thickness of the first vias 91A and 91B is thicker than the thickness of the winding portion 73A of the first coil LA. In other words, the thickness of the first vias 91A and 91B is thicker than the thickness of the second insulating film 42. Also, the thickness of the first vias 91A and 91B is thicker than the thickness of the second via 93. The rewiring layer 92 is thinner than the thicknesses of the first vias 91A and 91B and the second via 93.

[0128] The first external electrode 111 connected to the second via 93 is provided on the third insulating film 43 of the second insulating layer 40. The first external electrode 111 is in contact with the upper surface of the third insulating film 43. As shown in FIG. 14, the first external electrode 111 is arranged so as to overlap with the first end portion 71A of the first coil LA and a portion of the winding portion 73A closer to the first side surface 40A of the second insulating layer 40 in a plan view. A part of the first external electrode 111 is arranged at a position overlapping with the inner region 74A of the first coil LA in a plan view. On the other hand, as shown in FIG. 15, the first external electrode 111 is arranged closer to the first side surface 40A than the first vias 91A and 91B in a plan view. In one example, the thickness of the first external electrode 111 is thinner than the thickness of the winding portion 73A of the first coil LA. In one example, the thickness of the first external electrode 111 is thinner than the thickness of the first end portion 71A of the first coil LA. In one example, the thickness of the first external electrode 111 is thicker than the thickness of the rewiring layer 92. In one example, the thickness of the rewiring layer 92 is about 8 μm. In one example, the thickness of the winding portion 73A of the first coil LA is about 30 μm. In one example, the thickness of the first end portion 71A of the first coil LA is about 22 μm. In one example, the thickness of the first external electrode 111 is about 20 μm.

[0129] As shown in FIGS. 12, 13, 14, and 17, the second connection electrode 90B includes two first vias 94A and 94B, a rewiring layer 95, and a second via 96. The first vias 94A and 94B, the rewiring layer 95, and the second via 96 are made of a material containing, for example, Cu. In one example, the first vias 94A and 94B, the rewiring layer 95, and the second via 96 are made of the same material as each other.

[0130] The first via 94A is connected to the eighth wiring 68 (see FIG. 7) of the fifth capacitor CE. The first via 94B is connected to the seventh wiring 67 (see FIG. 7) of the fourth capacitor CD. The configuration of the first vias 94A and 94B is the same as that of the first vias 91A and 91B (see FIG. 15) of the second connection electrode 90A. In one example, as shown in FIG. 17, the first via 94B includes a first portion 94BA and a second portion 94BB. The first portion 94BA has the same configuration as the first portion 91AA (see FIG. 15) of the first via 91A. The second portion 94BB has the same configuration as the second portion 91AB (see FIG. 15) of the first via 91A. Therefore, the bonding area between the first via 94A and the eighth wiring 68 is smaller than the bonding area between the first via 94A and the rewiring layer 95. The bonding area between the first via 94B and the seventh wiring 67 is smaller than the bonding area between the first via 94B and the rewiring layer 95.

[0131] As shown in FIGS. 13 and 14, the rewiring layer 95 has the same size and the same shape as the rewiring layer 92 of the second connection electrode 90A in plan view. On the rewiring layer 95, a first end portion 71B of the second coil LB is provided. The first end portion 71B has the same size and the same shape as the first end portion 71A of the first coil LA. The first end portion 71B is point-symmetric to the first end portion 71A with respect to the center of the second insulating layer 40.

[0132] The first vias 94A and 94B and the first end portion 71B of the second coil LB are arranged at different positions from each other in plan view. The first vias 94A and 94B are arranged closer to the first coil LA than the first end portion 71B. In other words, the first vias 94A and 94B are arranged in the inner region 74B of the second coil LB. The first vias 94A and 94B are arranged at the end portion closer to the first coil LA among both end portions in the X direction of the rewiring layer 95. The first end portion 71B is arranged at the end portion closer to the second side surface 40B of the second insulating layer 40 among both end portions in the X direction of the rewiring layer 95. Also, the bonding area between the first end portion 71B and the rewiring layer 95 is larger than the bonding area between the first via 94A and the rewiring layer 95. The bonding area between the first end portion 71B and the rewiring layer 95 is larger than the bonding area between the first via 94B and the rewiring layer 95.

[0133] The second via 96 is provided on the first end portion 71B of the second coil LB. The second via 96 is in contact with both the first end portion 71B and the second external electrode 112 by penetrating the third insulating film 43 of the second insulating layer 40 in the Z direction. The shape and size of the second via 96 are the same as those of the second via 93 of the second connection electrode 90A.

[0134] The thickness relationship of each component of the second connection electrode 90B is the same as that of each component of the second connection electrode 90A. Also, the thickness (dimension in the Z direction) of the first vias 94A and 94B is equal to the thickness of the first vias 91A and 91B (see FIG. 15) of the second connection electrode 90A. The thickness of the rewiring layer 95 is equal to the thickness of the rewiring layer 92 of the second connection electrode 90A. The thickness (dimension in the Z direction) of the second via 96 is equal to the thickness of the second via 93 of the second connection electrode 90A.

[0135] (Third connection electrode) As shown in FIGS. 13, 14, and 18, the third connection electrodes 100A and 100B connect the first wiring 61 that electrically connects the first capacitor CA and the third capacitor CC and the third external electrode 113.

[0136] The third connection electrode 100A includes a first via 101, a rewiring layer 102, a connection layer 103, and a second via 104. The first via 101 penetrates the third insulating film 33 of the first insulating layer 30, the third insulating layer 50, and the first insulating film 41 of the second insulating layer 40 in the Z direction. The first via 101 electrically connects the rewiring layer 102 and the first wiring 61. The first via 101 is formed in an oval shape extending in the X direction in plan view. The first via 101 includes a first portion 101A and a second portion 101B.

[0137] The first portion 101A penetrates the first insulating film 41 of the second insulating layer 40 in the Z direction. The first portion 101A is joined to the rewiring layer 102. The second portion 101B penetrates both the third insulating layer 50 and the third insulating film 33 of the first insulating layer 30. The second portion 101B is joined to the first intermediate wiring 131 (see FIG. 7).

[0138] The dimension of the second part 101B in the X direction is smaller than the dimension of the first part 101A in the X direction. Although not shown, the dimension of the second part 101B in the Y direction is smaller than the dimension of the first part 101A in the X direction. Therefore, the bonding area between the second part 101B and the first intermediate wiring 131 is smaller than the bonding area between the first part 101A and the rewiring layer 102.

[0139] As shown in FIG. 13, the rewiring layer 102 extends in the Y direction in a plan view. The rewiring layer 102 includes a wide portion having a large dimension in the X direction and a narrow portion having a small dimension in the X direction in a plan view. The wide portion is disposed closer to the third side surface 40C of the second insulating layer 40 than the narrow portion. The second part 101B of the first via 101 is bonded to the wide portion of the rewiring layer 102.

[0140] As shown in FIG. 18, the rewiring layer 102 is provided on the second insulating film 42 of the second insulating layer 40. The rewiring layer 102 is in contact with the upper surface 42S of the second insulating film 42. The thickness of the rewiring layer 102 is thinner than the thickness of the second insulating film 42. A connection layer 103 is provided on the rewiring layer 102.

[0141] As shown in FIG. 13, the connection layer 103 is provided in the narrow portion of the rewiring layer 102. That is, the connection layer 103 is disposed at a position different from that of the first via 101 in a plan view. The connection layer 103 extends in the Y direction. And the connection layer 103 includes a portion protruding from the rewiring layer 102 in the Y direction. In one example, the length dimension (dimension in the Y direction) of the rewiring layer 102 is longer than the length dimension (dimension in the X direction) of the first via 101.

[0142] As shown in FIG. 18, the thickness of the overlapping portion of the connection layer 103 provided on the rewiring layer 102 is thinner than the thickness of the protruding portion of the connection layer 103 protruding from the rewiring layer 102. The sum of the thickness of the overlapping portion of the connection layer 103 and the thickness of the rewiring layer 102 is equal to the thickness of the second insulating film 42. The thickness of the protruding portion of the connection layer 103 is equal to the thickness of the second insulating film 42. Thus, the connection layer 103 penetrates the second insulating film 42 in the Z direction.

[0143] As shown in FIGS. 14 and 18, a second via 104 is provided on the connection layer 103. The second via 104 is in contact with the connection layer 103 and the third external electrode 113. As shown in FIG. 18, the dimension of the second via 104 in the Y direction is larger than the dimension of the connection layer 103 in the Y direction.

[0144] The thickness relationship of each component of the third connection electrode 100A is as follows. That is, the thickness (dimension in the Z direction) of the first via 101 is thicker than the thickness of the rewiring layer 102. The thickness of the first via 101 is thicker than the thickness of the protruding portion of the connection layer 103. In other words, the thickness of the first via 101 is thicker than the thickness of the second insulating film 42. Also, the thickness of the first via 101 is thicker than the thickness of the second via 104. The rewiring layer 102 is thinner than the thicknesses of the first via 101 and the second via 104. The rewiring layer 102 is thinner than the thickness of the overlapping portion of the connection layer 103. In one example, the thickness of the rewiring layer 102 is about 8 μm. In one example, the portion of the connection layer 103 provided on the rewiring layer 102 is about 22 μm. The thickness of the portion of the connection layer 103 provided on the second insulating film 42, in other words, the thickness of the portion of the connection layer 103 protruding from the rewiring layer 102 is about 30 μm.

[0145] The third connection electrode 100B includes a first via 105, a rewiring layer 106, a connection layer 107, and a second via 108. The arrangement modes of the first via 105, the rewiring layer 106, the connection layer 107, and the second via 108 are in a point-symmetric relationship with the arrangement modes of the first via 101, the rewiring layer 102, the connection layer 103, and the second via 104 with respect to the center of the second insulating layer 40. In one example, the shapes and sizes of the first via 105, the rewiring layer 106, the connection layer 107, and the second via 108 are the same as the shapes and sizes of the first via 101, the rewiring layer 102, the connection layer 103, and the second via 104.

[0146] The first via 105 penetrates the third insulating film 33 of the first insulating layer 30, the third insulating layer 50, and the first insulating film 41 of the second insulating layer 40 in the Z direction. The first via 101 electrically connects the rewiring layer 102 and the first wiring 61.

[0147] The rewiring layer 106 is provided on the second insulating film 42. A connection layer 107 is provided on the rewiring layer 106. And a second via 108 is provided on the connection layer 107. The second via 108 is in contact with the connection layer 107 and the third external electrode 113. As described above, the third connection electrodes 100A and 100B electrically connect the third external electrode 113 and the first wiring 61.

[0148] [Detailed Configuration of the Second Insulating Layer and Encapsulation Resin] With reference to FIGS. 17, 19, and 20, the detailed configuration of the second insulating layer 40 and the detailed configuration of the encapsulation resin 120 will be described. FIG. 19 shows a schematic planar structure in a state where the encapsulation resin 120 is omitted from the chip component 10. FIG. 20 schematically shows a cross-sectional structure obtained by cutting the chip component 10 along the line F20-F20 in FIG. 19.

[0149] As shown in FIGS. 19 and 20, the second insulating layer 40 includes a recessed portion 44. The recessed portion 44 is provided at a position different from the first to third external electrodes 111 to 113 in plan view. More specifically, it can be said that the recessed portion 44 is formed between the first external electrode 111 and the third external electrode 113 in the X direction and between the third external electrode 113 and the second external electrode 112 in the X direction. Hereinafter, for convenience, the recessed portion 44 formed between the first external electrode 111 and the third external electrode 113 in the X direction is referred to as "first recessed portion 44A", and the recessed portion 44 formed between the third external electrode 113 and the second external electrode 112 in the X direction is referred to as "second recessed portion 44B".

[0150] The first recessed portion 44A is formed so as to surround the first external electrode 111 from the second side surfaces 40B to 40D sides of the second insulating layer 40 in plan view. That is, the first recessed portion 44A is formed in a substantially U shape that opens toward the first side surface 40A of the second insulating layer 40 in plan view.

[0151] The second recessed portion 44B is formed so as to surround the second external electrode 112 from the sides of the first side surface 40A, the third side surface 40C, and the fourth side surface 40D of the second insulating layer 40 in a plan view. That is, the second recessed portion 44B is formed in a substantially U shape that opens toward the second side surface 40B of the second insulating layer 40 in a plan view.

[0152] The first recessed portion 44A and the second recessed portion 44B are provided on both sides in the X direction of the third external electrode 113. In a plan view, the first recessed portion 44A and the second recessed portion 44B are provided at positions adjacent to the third external electrode 113 in the X direction.

[0153] As shown in FIG. 20, both the first recessed portion 44A and the second recessed portion 44B are configured by removing the third insulating film 43 from the second insulating layer 40. That is, both the first recessed portion 44A and the second recessed portion 44B penetrate the third insulating film 43 in the Z direction. Thereby, the bottom surfaces of the first recessed portion 44A and the second recessed portion 44B are constituted by the upper surface 42S of the second insulating film 42. In this embodiment, the third insulating film 43 is separated into a plurality of mounting portions by the first recessed portion 44A and the second recessed portion 44B. Specifically, the third insulating film 43 of the second insulating layer 40 includes a first mounting portion 43A where the first external electrode 111 is provided, a second mounting portion 43B where the second external electrode 112 is provided, and a third mounting portion 43C where the third external electrode 113 is provided. The first to third mounting portions 43A to 43C are arranged at intervals in the X direction.

[0154] The first mounting portion 43A is provided at an end portion near the first side surface 40A of the second insulating layer 40 in a plan view. The dimension of the first mounting portion 43A in the Y direction is smaller than the dimension of the second insulating layer 40 in the Y direction. The first recessed portion 44A is provided on both sides in the Y direction of the first mounting portion 43A.

[0155] As shown in FIG. 19, the first mounting portion 43A is formed in a rectangular shape in which the Y direction is the longitudinal direction and the X direction is the short side direction in plan view. The first mounting portion 43A includes first to fourth side surfaces 43AA to 43AD. The first side surface 43AA and the second side surface 43AB constitute both end surfaces of the first mounting portion 43A in the X direction. The first side surface 43AA constitutes a part of the first side surface 40A of the second insulating layer 40 in the Z direction. The second side surface 43AB constitutes a part of the first recess 44A. The third side surface 43AC and the fourth side surface 43AD constitute both end surfaces of the first mounting portion 43A in the Y direction. Both the third side surface 43AC and the fourth side surface 43AD constitute a part of the first recess 44A. The third side surface 43AC faces the same side as the third side surface 40C of the second insulating layer 40, and the fourth side surface 43AD faces the same side as the fourth side surface 40D of the second insulating layer 40.

[0156] The first external electrode 111 is formed on the upper surface 43AS of the first mounting portion 43A. In plan view, the first external electrode 111 is slightly smaller than the upper surface 43AS of the first mounting portion 43A. More specifically, the side surface 111A of the first external electrode 111 includes a first side surface 111AA and a second side surface 111AB that constitute both end surfaces of the first external electrode 111 in the X direction, and a third side surface 111AC and a fourth side surface 111AD that constitute both end surfaces of the first external electrode 111 in the Y direction. The first side surface 111AA is disposed closer to the first side surface 40A of the second insulating layer 40 than the second side surface 111AB. The third side surface 111AC is disposed closer to the third side surface 40C of the second insulating layer 40 than the fourth side surface 111AD. In plan view, the first side surface 111AA of the first external electrode 111 is disposed closer to the second side surface 43AB than the first side surface 43AA of the first mounting portion 43A. The second side surface 111AB of the first external electrode 111 is disposed closer to the first side surface 43AA than the second side surface 43AB of the first mounting portion 43A. The third side surface 111AC of the first external electrode 111 is disposed closer to the fourth side surface 43AD than the third side surface 43AC of the first mounting portion 43A. The fourth side surface 111AD of the first external electrode 111 is disposed closer to the third side surface 43AC than the fourth side surface 43AD of the first mounting portion 43A. For this reason, the outer peripheral portion of the upper surface 43AS of the first mounting portion 43A is exposed from the first external electrode 111.

[0157] The second mounting portion 43B is provided at an end portion near the second side surface 40B of the second insulating layer 40 in a plan view. The dimension of the second mounting portion 43B in the Y direction is smaller than the dimension of the second insulating layer 40 in the Y direction. Second recessed portions 44B are provided on both sides of the second mounting portion 43B in the Y direction.

[0158] The second mounting portion 43B is formed in a rectangular shape in which the Y direction is the longitudinal direction and the X direction is the short side direction in a plan view. The second mounting portion 43B includes first to fourth side surfaces 43BA to 43BD. The first side surface 43BA and the second side surface 43BB constitute both end surfaces of the second mounting portion 43B in the X direction. The second side surface 43BB constitutes a part of the second insulating layer 40 in the Z direction of the second side surface 40B. The first side surface 43BA constitutes a part of the second recessed portion 44B. The third side surface 43BC and the fourth side surface 43BD constitute both end surfaces of the second mounting portion 43B in the Y direction. Both the third side surface 43BC and the fourth side surface 43BD constitute a part of the second recessed portion 44B. The third side surface 43BC faces the same side as the third side surface 40C of the second insulating layer 40, and the fourth side surface 43BD faces the same side as the fourth side surface 40D of the second insulating layer 40.

[0159] The second external electrode 112 is formed on the upper surface 43BS of the second mounting portion 43B. In a plan view, the second external electrode 112 is slightly smaller than the upper surface 43BS of the second mounting portion 43B. More specifically, the side surface 112A of the second external electrode 112 includes a first side surface 112AA and a second side surface 112AB that constitute both end surfaces of the second external electrode 112 in the X direction, and a third side surface 112AC and a fourth side surface 112AD that constitute both end surfaces of the second external electrode 112 in the Y direction. The second side surface 112AB is disposed closer to the second side surface 40B of the second insulating layer 40 than the first side surface 112AA. The third side surface 112AC is disposed closer to the third side surface 40C of the second insulating layer 40 than the fourth side surface 112AD. In a plan view, the first side surface 112AA of the second external electrode 112 is disposed closer to the second side surface 43BB than the first side surface 43BA of the second mounting portion 43B. The second side surface 112AB of the second external electrode 112 is disposed closer to the first side surface 43BA than the second side surface 43BB of the second mounting portion 43B. The third side surface 112AC of the second external electrode 112 is disposed closer to the fourth side surface 43BD than the third side surface 43BC of the second mounting portion 43B. The fourth side surface 112AD of the second external electrode 112 is disposed closer to the third side surface 43BC than the fourth side surface 43BD of the second mounting portion 43B. Therefore, the outer peripheral portion of the upper surface 43BS of the second mounting portion 43B is exposed from the second external electrode 112.

[0160] The third mounting portion 43C is provided at the center in the X direction of the second insulating layer 40 in a plan view. The dimension of the third mounting portion 43C in the Y direction is equal to the dimension of the second insulating layer 40 in the Y direction. Therefore, both the first recessed portion 44A and the second recessed portion 44B are not provided on both sides of the third mounting portion 43C in the Y direction.

[0161] The third mounting portion 43C is formed in a rectangular shape in which the Y direction is the longitudinal direction and the X direction is the short side direction in plan view. The third mounting portion 43C includes first to fourth side surfaces 43CA to 43CD. The first side surface 43CA and the second side surface 43CB constitute both end surfaces of the third mounting portion 43C in the X direction. The first side surface 43CA faces the second side surface 43AB of the first mounting portion 43A in the X direction. The first side surface 43CA constitutes a part of the first recessed portion 44A. The second side surface 43CB faces the first side surface 43BA of the second mounting portion 43B in the X direction. The second side surface 43CB constitutes a part of the second recessed portion 44B. The third side surface 43CC and the fourth side surface 43CD constitute both end surfaces of the third mounting portion 43C in the Y direction. The third side surface 43CC constitutes a part of the third side surface 40C of the second insulating layer 40. The fourth side surface 43CD constitutes a part of the fourth side surface 40D of the second insulating layer 40.

[0162] The third external electrode 113 is formed on the upper surface 43CS of the third mounting portion 43C. In plan view, the third external electrode 113 is slightly smaller than the upper surface 43CS of the third mounting portion 43C. More specifically, the side surface 113A of the third external electrode 113 includes a first side surface 113AA and a second side surface 113AB that constitute both end faces of the third external electrode 113 in the X direction, and a third side surface 113AC and a fourth side surface 113AD that constitute both end faces of the third external electrode 113 in the Y direction. The first side surface 113AA is disposed closer to the first external electrode 111 than the second side surface 113AB. The first side surface 113AA faces the second side surface 111AB of the first external electrode 111 in the X direction. The second side surface 113AB faces the first side surface 112AA of the second external electrode 112 in the X direction. The third side surface 113AC is disposed closer to the third side surface 40C of the second insulating layer 40 than the fourth side surface 113AD. In plan view, the first side surface 113AA of the third external electrode 113 is disposed closer to the second side surface 43CB than the first side surface 43CA of the third mounting portion 43C. The second side surface 113AB of the third external electrode 113 is disposed closer to the first side surface 43CA than the second side surface 43CB of the third mounting portion 43C. The third side surface 113AC of the third external electrode 113 is disposed closer to the fourth side surface 43CD than the third side surface 43CC of the third mounting portion 43C. The fourth side surface 113AD of the third external electrode 113 is disposed closer to the third side surface 43CC than the fourth side surface 43CD of the third mounting portion 43C. For this reason, the outer peripheral portion of the upper surface 43CS of the third mounting portion 43C is exposed from the third external electrode 113.

[0163] The encapsulation resin 120 covers the second upper surface 40S of the second insulating layer 40 (the upper surface of the third insulating film 43) and the side surfaces 111A to 113A of the first to third external electrodes 111 to 113. In one example, the encapsulation resin 120 covers the upper surfaces 43AS to 43CS of the first to third mounting portions 43A to 43C and the side surfaces 111A to 113A of the first to third external electrodes 111 to 113. In this embodiment, the encapsulation resin 120 covers the entire side surfaces 111A to 113A of the first to third external electrodes 111 to 113. The encapsulation resin 120 enters both the first recess 44A and the second recess 44B. Therefore, a part of the encapsulation resin 120 is in contact with the upper surface 42S of the second insulating film 42.

[0164] More specifically, the encapsulation resin 120 covers the side surface 111A of the first external electrode 111 from the X direction and the Y direction. In this embodiment, the encapsulation resin 120 covers all of the first to fourth side surfaces 111AA to 111AD of the first external electrode 111. Also, the encapsulation resin 120 covers the side surface 112A of the second external electrode 112 from the X direction and the Y direction. In this embodiment, the encapsulation resin 120 covers all of the first to fourth side surfaces 112AA to 112AD of the second external electrode 112. Also, the encapsulation resin 120 covers the side surface 113A of the third external electrode 113 from the X direction and the Y direction. In this embodiment, the encapsulation resin 120 covers all of the first to fourth side surfaces 113AA to 113AD of the third external electrode 113.

[0165] As shown in FIG. 20, the upper surfaces 111S of the first external electrode 111, the upper surfaces 112S of the second external electrode 112, and the upper surfaces 113S of the third external electrode 113 are each exposed from the encapsulation resin 120. In one example, the upper surfaces 111S to 113S of the first to third external electrodes 111 to 113 are flush with the upper surface 120S of the encapsulation resin 120. The bonding layer 115 is formed on the upper surfaces 111S to 113S of the first to third external electrodes 111 to 113 exposed from the encapsulation resin 120.

[0166] By entering the sealing resin 120 into the first recessed portion 44A, it covers the second to fourth side surfaces 43AB to 43AD of the first mounting portion 43A and the first side surface 43CA of the third mounting portion 43C. Also, by entering the sealing resin 120 into the second recessed portion 44B, it covers the first side surface 43BA, the third side surface 43BC, and the fourth side surface 43BD of the second mounting portion 43B and the second side surface 43CB of the third mounting portion 43C. Further, the sealing resin 120 covers the portion of the upper surface 43AS of the first mounting portion 43A that is exposed from the first external electrode 111, the portion of the upper surface 43BS of the second mounting portion 43B that is exposed from the second external electrode 112, and the portion of the upper surface 43CS of the third mounting portion 43C that is exposed from the third external electrode 113.

[0167] The sealing resin 120 covers the first to fourth side surfaces 40A to 40D (see FIG. 19) of the second insulating layer 40. More specifically, as shown in FIG. 17, the first to third insulating films 41 to 43 of the second insulating layer 40 have steps at the first to fourth side surfaces 40A to 40D. A first step 45A is formed between the first insulating film 41 and the second insulating film 42 at the first to fourth side surfaces 40A to 40D. A second step 45B is formed between the second insulating film 42 and the third insulating film 43 at the first to fourth side surfaces 40A to 40D. Therefore, the sealing resin 120 is in contact with the upper surface 41S of the first insulating film 41 at the outer peripheral edge of the first insulating film 41. The sealing resin 120 is in contact with the upper surface 42S of the second insulating film 42 at the outer peripheral edge of the second insulating film 42.

[0168] As shown in FIG. 17, the sealing resin 120 covers the side surface of the third insulating layer 50. In one example, the sealing resin 120 covers the entire side surface of the third insulating layer 50. Also, the sealing resin 120 covers the side surfaces of the first insulating layer 30 corresponding to the second insulating film 32 and the third insulating film 33 among the first to fourth side surfaces 30A to 30D. The sealing resin 120 is in contact with the upper surface of the first insulating film 31 of the first insulating layer 30.

[0169] As shown in FIG. 19, the sealing resin 120 includes first to fourth side cover portions 121 to 124 that cover first to fourth side surfaces 40A to 40D of the second insulating layer 40. Here, the first to fourth side cover portions 121 to 124 are an example of the "side cover portion".

[0170] As shown in FIG. 15, the first side cover portion 121 covers the first side surface 40A of the second insulating layer 40, the side surface of the third insulating layer 50 that faces the same side as the first side surface 40A, and the side surface of the first side surface 30A of the first insulating layer 30 that corresponds to the second insulating film 32 and the third insulating film 33.

[0171] As shown in FIG. 17, the second side cover portion 122 covers the second side surface 40B of the second insulating layer 40, the side surface of the third insulating layer 50 that faces the same side as the second side surface 40B, and the side surface of the second side surface 30B of the first insulating layer 30 that corresponds to the second insulating film 32 and the third insulating film 33.

[0172] Although not shown, the third side cover portion 123 covers the third side surface 40C of the second insulating layer 40, the side surface of the third insulating layer 50 that faces the same side as the third side surface 40C, and the side surface of the third side surface 30C of the first insulating layer 30 that corresponds to the second insulating film 32 and the third insulating film 33.

[0173] Although not shown, the fourth side cover portion 124 covers the fourth side surface 40D of the second insulating layer 40, the side surface of the third insulating layer 50 that faces the same side as the fourth side surface 40D, and the side surface of the fourth side surface 30D of the first insulating layer 30 that corresponds to the second insulating film 32 and the third insulating film 33. The first to fourth side cover portions 121 to 124 are integrated.

[0174] As shown in FIG. 19, the first side cover portion 121 covers the first side surface 43AA of the first placement portion 43A of the third insulating film 43 among the first side surface 40A of the second insulating layer 40. Therefore, the sealing resin 120 covers the first to fourth side surfaces 43AA to 43AD of the first placement portion 43A. The second side cover portion 122 covers the second side surface 43BB of the second placement portion 43B of the third insulating film 43 among the second side surface 40B of the second insulating layer 40. Therefore, the sealing resin 120 covers the first to fourth side surfaces 43BA to 43BD of the second placement portion 43B. The third side cover portion 123 covers the third side surface 43CC of the third placement portion 43C of the third insulating film 43 among the third side surface 40C of the second insulating layer 40. The fourth side cover portion 124 covers the fourth side surface 43CD of the third placement portion 43C of the third insulating film 43 among the fourth side surface 40D of the second insulating layer 40. Therefore, the sealing resin 120 covers the first to fourth side surfaces 43CA to 43CD of the third placement portion 43C. Thus, since the first to fourth side cover portions 121 to 124 cover the peripheries of the first to third placement portions 43A to 43C, the first to fourth side cover portions 121 to 124 are arranged outward of the first to third external electrodes 111 to 113 in a plan view. More specifically, the first side cover portion 121 is arranged on the side opposite to the third external electrode 113 with respect to the first external electrode 111 in the X direction in a plan view. The second side cover portion 122 is arranged on the side opposite to the third external electrode 113 with respect to the second external electrode 112 in the X direction in a plan view.

[0175] [Manufacturing Method of Chip Component] With reference to FIGS. 21 to 44, an example of the manufacturing process of the chip component 10 will be described. FIGS. 21 to 44 schematically show the cross-sectional structure in the manufacturing process of the chip component 10. The cross-sectional positions of FIGS. 21 to 44 are the same as the cross-sectional position of FIG. 20. Therefore, in FIGS. 21 to 44, the first to fifth capacitors CA to CE, a part of the first connection electrode 80, and the third connection electrodes 100A and 100B are not shown. Refer to FIGS. 6 to 11 for the first to fifth capacitors CA to CE. Refer to FIGS. 13 to 18 for a part of the first connection electrode 80 and the third connection electrodes 100A and 100B.

[0176] The manufacturing method of the chip component 10 mainly includes a step of preparing a substrate 820, a step of forming a first insulating layer 830 on the substrate 820, a step of forming first to fifth capacitors CA to CE in the first insulating layer 830, a step of forming a third insulating layer 850 on the first insulating layer 830, a step of forming a second insulating layer 840, a step of forming a first coil LA and a second coil LB in the second insulating layer 840, a step of forming connection wirings, a step of forming connection electrodes, a step of forming first to third external electrodes 111 to 113, a step of forming a sealing resin 920, a step of forming a plating layer, and a step of singulating.

[0177] FIG. 21 shows a step of preparing a substrate 820 and a part of a step of forming a first insulating layer 830 on the substrate 820. FIG. 21 schematically shows a cross-sectional structure of the substrate 820. The substrate 820 is formed in a flat plate shape with the Z direction as the thickness direction. The substrate 820 includes, for example, a plurality of substrates 20 (see FIG. 20). The substrate 820 includes a first substrate surface 821 and a second substrate surface 822 facing opposite sides in the Z direction. The substrate 820 is constituted by, for example, a semiconductor wafer. In one example, the substrate 820 is constituted by a Si wafer.

[0178] Subsequently, in the step of forming the first insulating layer 830 on the substrate 820, a first insulating film 831 is formed on the first substrate surface 821 of the substrate 820. The first insulating film 831 is constituted by, for example, a silicon oxide film. In this case, the first insulating film 831 is formed by, for example, a thermal oxidation method. Note that the first insulating film 831 may be constituted by a silicon nitride film. In this case, the first insulating film 831 is formed by, for example, a CVD (Chemical Vapor Deposition) method.

[0179] FIG. 22 shows a step of forming the first insulating layer 830, a step of forming first to fifth capacitors CA to CE, a part of a step of forming connection wirings, and a part of a step of forming connection electrodes. FIG. 22 shows a part of the first capacitor CA, the third capacitor CC, and the fourth capacitor CD among the first to fifth capacitors CA to CE.

[0180] In the step of forming the first to fifth capacitors CA to CE, the first to third wirings 61 to 63 are formed on the first insulating film 831. The first to third wirings 61 to 63 have a laminated structure including an Al layer and a TiN layer laminated in this order from the side of the first insulating film 831. The Al layer and the TiN layer are formed using, for example, at least one of a sputtering method and a vapor deposition method.

[0181] Subsequently, in the step of forming the first insulating layer 830, the second insulating film 832 is formed. The second insulating film 832 is formed so as to cover the upper surface of the first insulating film 831 and the first to third wirings 61 to 63. The second insulating film 832 is constituted by, for example, a silicon nitride film. In this case, the second insulating film 832 is formed by a CVD method.

[0182] Subsequently, in the step of forming the connection wiring, through holes are formed in the region of the second insulating film 832 where the connection wiring is to be formed. Then, the first to fourth vias 135 to 138 are formed by embedding a conductive material in the through holes. The first to fourth vias 135 to 138 may be formed of Ti or W. Note that the first to fourth vias 135 to 138 may have a laminated structure including an Al layer and a TiN layer, similar to the first to third wirings 61 to 63.

[0183] Subsequently, in the step of forming the first to fifth capacitors CA to CE, the fourth to eighth wirings 64 to 68 are formed on the second insulating film 832. The fourth to eighth wirings 64 to 68 have a laminated structure including an Al layer and a TiN layer laminated in this order from the side of the second insulating film 832. The Al layer and the TiN layer are formed using, for example, at least one of a sputtering method and a vapor deposition method.

[0184] Also, in the step of forming the connection wiring, the first to fourth intermediate wirings 131 to 134 are formed in the region on the second insulating film 832 where the connection wiring is to be formed. The first to fourth intermediate wirings 131 to 134 have a laminated structure including an Al layer and a TiN layer laminated in this order from the side of the second insulating film 832. The Al layer and the TiN layer are formed using, for example, at least one of a sputtering method and a vapor deposition method. The first to fourth intermediate wirings 131 to 134 may be formed in a process common to the fourth to eighth wirings 64 to 68.

[0185] Subsequently, in the step of forming the first insulating layer 830, the third insulating film 833 is formed. The third insulating film 833 is formed so as to cover the upper surface of the second insulating film 832, the fourth to eighth wirings 64 to 68, and the first to fourth intermediate wirings 131 to 134. The third insulating film 833 is constituted by, for example, a silicon nitride film. In this case, the third insulating film 833 is formed by a CVD method. Openings are formed in the region of the third insulating film 833 that covers the first to fourth intermediate wirings 131 to 134 so as to expose a part of each of the first to fourth intermediate wirings 131 to 134. The openings may be formed by etching the third insulating film 833, or may be formed when the third insulating film 833 is formed.

[0186] The step of forming the connection electrodes includes a step of forming the first connection electrode 80, a step of forming the second connection electrodes 90A and 90B, and a step of forming the third connection electrodes 100A and 100B. First, through holes are formed in the region of the third insulating film 833 where the first connection electrode 80, the second connection electrodes 90A and 90B, and the third connection electrodes 100A and 100B are to be formed. Through the through holes, a part of each of the first to fourth intermediate wirings 131 to 134 and a part of each of the fourth to eighth wirings 64 to 68 are exposed. Subsequently, a conductive material is embedded in each through hole. The conductive material is constituted by, for example, a material containing Cu. Thereby, a part of each of the first via 81, the second via 83, and the third via 86 of the first connection electrode 80, a part of the first vias 91A, 91B, 94A, and 94B of the second connection electrodes 90A and 90B, and a part of the first vias 101 and 105 of the third connection electrodes 100A and 100B are formed.

[0187] Figures 23 and 24 show the process of forming the third insulating layer 850. Figure 24 shows an enlarged view of a part of the surface layer portion of the third insulating layer 850 in Figure 23. As shown in Figure 23, in the process of forming the third insulating layer 850, the third insulating layer 850 is formed on the first insulating layer 830. The third insulating layer 850 is in contact with the first insulating layer 830. The third insulating layer 850 includes a third upper surface 850S and a third lower surface 850R facing the side opposite to the third upper surface 850S. The third lower surface 850R is in contact with the first insulating layer 830. The third insulating layer 850 is composed of, for example, polyimide. The third insulating layer 850 is formed to be thicker than the first insulating layer 830. The third insulating layer 850 is formed by, for example, applying liquid polyimide on the first insulating layer 830. Then, the applied liquid polyimide is thermally cured to form the third insulating layer 850. Note that the third insulating layer 850 may be formed by, for example, attaching a sheet-like polyimide on the first insulating layer 830.

[0188] Subsequently, as shown in Figure 24, an ashing process is performed on the third upper surface 850S of the third insulating layer 850. As a result, the third upper surface 850S is formed to be rougher than the third lower surface 850R (see Figure 23) of the third insulating layer 850.

[0189] Figure 25 shows a part of the process of forming the connection electrodes. The process of forming the connection electrodes includes the process of forming the first connection electrode 80, the second connection electrodes 90A, 90B, and the third connection electrodes 100A, 100B (see Figure 14).

[0190] In the step of forming the connection electrodes, first, through holes are formed in the region of the third insulating layer 850 where the first connection electrode 80, the second connection electrodes 90A and 90B, and the third connection electrodes 100A and 100B are to be formed. Through the through holes, a part of each of the first via 81, the second via 83, and the third via 86 of the first connection electrode 80, a part of each of the first vias 91A, 91B, 94A, and 94B of the second connection electrodes 90A and 90B, and a part of each of the first vias 101 and 105 of the third connection electrodes 100A and 100B are exposed. Subsequently, a conductive material is embedded in each through hole. The conductive material is composed of, for example, a material containing Cu. Thereby, a part of each of the first via 81, the second via 83, and the third via 86 of the first connection electrode 80, a part of each of the first vias 91A, 91B, 94A, and 94B of the second connection electrodes 90A and 90B, and a part of each of the first vias 101 and 105 of the third connection electrodes 100A and 100B are formed.

[0191] FIG. 26 shows a part of the step of forming the second insulating layer 840 and a part of the step of forming the connection electrodes. In the step of forming the second insulating layer 840, first, the first insulating film 841 is formed on the third insulating layer 850. The first insulating film 841 is in contact with the third upper surface 850S of the third insulating layer 850. That is, the second insulating layer 840 is formed so as to be in contact with the third insulating layer 850. The first insulating film 841 is composed of an organic insulating film. The organic insulating film contains, for example, an epoxy resin. In one example, the first insulating film 841 is formed by adhering a dry film resist composed of an epoxy resin onto the third insulating layer 850. Subsequently, after exposing the pattern to the first insulating film 841 and then developing it, a plurality of through holes 841A are formed in the first insulating film 841. Each through hole 841A exposes a part of each of the first via 81, the second via 83, and the third via 86 of the first connection electrode 80, a part of each of the first vias 91A, 91B, 94A, and 94B of the second connection electrodes 90A and 90B, a part of each of the first vias 101 and 105 of the third connection electrodes 100A and 100B, and the third insulating layer 850 around them. That is, each through hole 841A is formed to form these vias 81, 83, 86, 91A, 91B, 94A, 94B, 101, and 105.

[0192] Subsequently, in the step of forming the connection electrodes, for example, a metal layer 930 is formed by at least one of a sputtering method and a vapor deposition method. The metal layer 930 is formed on the third upper surface 850S of the third insulating layer 850, on the upper surface and side surfaces of the first insulating film 841, and on the side surfaces constituting the respective through holes 841A. The metal layer 930 is made of a material containing, for example, Cu.

[0193] Figs. 27 to 29 show the step of forming the connection electrodes. As shown in Fig. 27, in the step of forming the connection electrodes, first, a resist 940 is formed on the metal layer 930. The resist 940 is formed, for example, by coating on the metal layer 930. Then, after exposing a pattern on the resist 940, the resist 940 is removed in the regions where the first connection electrode 80, the second connection electrodes 90A and 90B, and the third connection electrodes 100A and 100B are formed by developing. In the removed regions of the resist 940, the metal layer 930 is exposed.

[0194] Subsequently, as shown in Fig. 28, in the step of forming the connection electrodes, a conductive material is filled in the regions of the resist 940 where the metal layer 930 is exposed. In this step, for example, by an electroplating method using the metal layer 930 as a seed layer, a conductive material is formed in the regions of the resist 940 where the metal layer 930 is exposed. The conductive material is, for example, a material containing Cu. Thereby, the first vias 81, 83, and 86 of the first connection electrode 80, the first vias 91A, 91B, 94A, and 94B of the second connection electrodes 90A and 90B, and the first vias 101 and 105 of the third connection electrodes 100A and 100B are formed. In this step, further, the first rewiring layers 82, 84, and 87 of the first connection electrode 80, the rewiring layers 92 and 95 of the second connection electrodes 90A and 90B, and the rewiring layers 102 and 106 of the third connection electrodes 100A and 100B are formed. These rewiring layers 82, 84, 87, 92, 95, 102 contain the metal layer 930.

[0195] Subsequently, as shown in FIG. 29, the resist 940 is removed. As a result, the metal layer 930 is exposed. The metal layer 930 is exposed in a region different from the rewiring layers 82, 92, 95, 102. Subsequently, the exposed metal layer 930 is removed by etching.

[0196] FIG. 30 shows a part of the process of forming the second insulating layer 840. In the process of forming the second insulating layer 840, first, a second insulating film 842 is formed on the first insulating film 841. The second insulating film 842 is composed of an organic insulating film. The organic insulating film contains, for example, an epoxy resin. In one example, the second insulating film 842 is formed by attaching a dry film resist composed of an epoxy resin onto the first insulating film 841. Subsequently, after exposing the pattern to the second insulating film 842 and then developing it, a plurality of through holes 842A are formed in the second insulating film 842. Each through hole 842A exposes the first coil LA, the second coil LB, the first connection layer 85 and the second connection layer 88 of the first connection electrode 80, the connection layers 103, 107 of the third connection electrodes 100A, 100B, and the first insulating film 841 around them. That is, each through hole 842A is formed to form the first coil LA, the second coil LB, and the connection layers 85, 88, 103, 107.

[0197] FIGS. 31 to 34 show the process of forming the connection electrodes and the process of forming the first coil LA and the second coil LB. As shown in FIG. 31, in the process of forming the connection electrodes and the process of forming the first coil LA and the second coil LB, a metal layer 950 is formed by at least one of, for example, sputtering and vapor deposition. The metal layer 950 is formed on the upper surface of the first insulating film 841, the upper surface and the side surfaces of the second insulating film 842, and the side surfaces constituting each through hole 842A. The metal layer 950 is composed of a material containing, for example, Cu.

[0198] Subsequently, as shown in FIG. 32, a resist 960 is formed on the metal layer 950. The resist 960 is formed, for example, by coating it on the metal layer 950. Then, after exposing a pattern on the resist 960 and developing it, the resist 960 is removed in the regions where the first connection electrode 80, the second connection electrodes 90A and 90B, and the third connection electrodes 100A and 100B, and the first coil LA and the second coil LB are formed. The metal layer 950 is exposed in the removed regions of the resist 960.

[0199] Subsequently, as shown in FIG. 33, the regions of the resist 960 where the metal layer 950 is exposed are filled with a conductive material. More specifically, each through-hole 842A is filled with a conductive material. In this process, for example, a conductive material is formed in the regions where the metal layer 950 is exposed from the resist 960 by an electroplating method using the metal layer 950 as a seed layer. The conductive material is, for example, a material containing Cu. After each through-hole 842A is filled with the conductive material, the resist 960 is peeled off.

[0200] Subsequently, as shown in FIG. 34, the metal layer 950 is removed, for example, by etching. The regions of the metal layer 950 that are exposed due to the peeling of the resist 960 are removed. In addition, the portions of the conductive material filled in the through-holes 842A that protrude above the upper surface of the second insulating film 842 are also removed. Thereby, the first coil LA, the second coil LB, the first connection layer 85 and the second connection layer 88 of the first connection electrode 80, and the connection layers 103 and 107 of the third connection electrodes 100A and 100B are formed. The first end portion 71A of the first coil LA is formed to be at a position different from that of the first vias 91A and 91B in a plan view. The first end portion 71B of the second coil LB is formed to be at a position different from that of the first vias 94A and 94B in a plan view.

[0201] FIG. 35 shows the process of forming the second insulating layer 840. In the step of forming the second insulating layer 840, first, a third insulating film 843 is formed on the second insulating film 842. The third insulating film 843 is composed of an organic insulating film. The organic insulating film contains, for example, an epoxy resin. In one example, the third insulating film 843 is formed by attaching a dry film resist composed of an epoxy resin onto the second insulating film 842. Subsequently, after exposing a pattern to the third insulating film 843 and then developing it, a recessed portion 844 and a plurality of through holes 843A are formed in the third insulating film 843. Each through hole 843A is formed to form the second vias 93 and 96 of the second connection electrodes 90A and 90B and the second vias 104 and 108 of the third connection electrodes 100A and 100B.

[0202] Figs. 36 to 39 show the step of forming connection electrodes and the step of forming the first to third external electrodes 111 to 113. As shown in Fig. 36, in the step of forming connection electrodes and the step of forming the first to third external electrodes 111 to 113, a metal layer 970 is formed by at least one of, for example, sputtering and vapor deposition. The metal layer 970 is formed on the upper surface of the second insulating film 842, the upper surface and side surfaces of the third insulating film 843, and the side surfaces constituting each through hole 843A and recessed portion 844. The metal layer 970 is composed of a material containing, for example, Cu.

[0203] Subsequently, as shown in Fig. 37, a resist 980 is formed on the metal layer 970. The resist 980 is formed by, for example, coating it on the metal layer 970. Then, after exposing a pattern to the resist 980 and then developing it, the resist 980 is removed in the regions where the second connection electrodes 90A and 90B, the third connection electrodes 100A and 100B, and the first to third external electrodes 111 to 113 are formed. The metal layer 970 is exposed in the removed regions of the resist 980.

[0204] Subsequently, as shown in FIG. 38, the exposed regions of the metal layer 970 in the resist 980 are filled with a conductive material. In this process, for example, a conductive material is formed in the regions where the metal layer 970 is exposed from the resist 980 by an electroplating method using the metal layer 950 as a seed layer. The conductive material is, for example, a material containing Cu.

[0205] Subsequently, as shown in FIG. 39, the resist 980 is peeled off. As a result, portions of the metal layer 970 different from the first to third external electrodes 111 to 113 are exposed. Then, the metal layer 970 is removed, for example, by etching. More specifically, portions of the metal layer 970 different from the first to third external electrodes 111 to 113 are removed. Thereby, the second vias 93 and 96 of the second connection electrodes 90A and 90B, the second vias 104 and 108 of the third connection electrodes 100A and 100B, and the first to third external electrodes 111 to 113 are formed.

[0206] FIGS. 40 and 41 show the process of forming the encapsulation resin 920. As shown in FIG. 40, the encapsulation resin 920 is formed, for example, by transfer molding. The encapsulation resin 920 covers the side surface of the second insulating layer 840 and enters the recessed portion 844. Also, the encapsulation resin 920 shown in FIG. 40 covers the upper surfaces 111S to 113S of the first to third external electrodes 111 to 113.

[0207] Subsequently, as shown in FIG. 41, the encapsulation resin 920 is ground. In this process, the first to third external electrodes 111 to 113 may also be ground. As a result, the first to third external electrodes 111 to 113 are exposed from the encapsulation resin 920. More specifically, the upper surfaces 111S to 113S of the first to third external electrodes 111 to 113 are exposed in the Z direction from the encapsulation resin 920. On the other hand, the encapsulation resin 920 covers the side surfaces 111A to 113A of each of the first to third external electrodes 111 to 113.

[0208] FIG. 42 shows the process of grinding the substrate 820. In this step, the substrate 820 is thinned by grinding the substrate 820 from the second substrate surface 822. In the step of grinding the substrate 820, for example, the CMP (Chemical Mechanical Polishing) method is used. As a method for thinning the substrate 820, other methods, or a combination of a plurality of methods may be used.

[0209] FIG. 43 shows a step of forming a bonding layer 115 on each of the first to third external electrodes 111 to 113. In this step, for example, a cream solder is printed on each of the upper surfaces 111S to 113S of the first to third external electrodes 111 to 113, whereby the bonding layer 115 is formed. In this case, the bonding layer 115 includes a solder electrode. Note that the bonding layer 115 may be formed by electroless plating. In this case, the bonding layer 115 includes a NiPdAu layer.

[0210] FIG. 44 shows a step of singulating. In the step of singulating, first, a dicing tape 990 is adhered to the second substrate surface 822 of the substrate 820. Subsequently, for example, using a dicing blade, the encapsulation resin 920 and the substrate 820 are cut in the Z direction. Through the above steps, the chip component 10 is manufactured.

[0211] [Operation of Embodiment] The operation of the chip component 10 of this embodiment will be described. The chip component 10 of this embodiment includes a sealing resin 120 that covers the first to fourth side surfaces 40A to 40D of the second insulating layer 40 and the side surfaces 111A to 113A of the first to third external electrodes 111 to 113. Thereby, it is possible to suppress an external force from being directly applied to each of the first to fourth side surfaces 40A to 40D of the second insulating layer 40 and the first to third external electrodes 111 to 113. In addition, the sealing resin 120 suppresses relative movement between the second insulating layer 40 and the first to third external electrodes 111 to 113 in a direction intersecting the Z direction. Further, the first to fourth side surfaces 40A to 40D of the second insulating layer 40 and the side surfaces 111A to 113A of the first to third external electrodes 111 to 113 are reinforced by the sealing resin 120. Therefore, it is possible to suppress the peeling of the first to third external electrodes 111 to 113 from the second insulating layer 40.

[0212] In addition, the second insulating layer 40 includes a first recessed portion 44A and a second recessed portion 44B formed in portions different from the first to third external electrodes 111 to 113 in plan view. The sealing resin 120 enters both the first recessed portion 44A and the second recessed portion 44B. The second insulating layer 40 includes first to third mounting portions 43A to 43C formed by the first recessed portion 44A and the second recessed portion 44B. The first to third external electrodes 111 to 113 are provided on the first to third mounting portions 43A to 43C. And the sealing resin 120 covers the periphery of the first mounting portion 43A and the first external electrode 111. Therefore, the relative movement between the first mounting portion 43A and the first external electrode 111 is suppressed by the sealing resin 120. Similarly, the sealing resin 120 covers the periphery of the second mounting portion 43B and the second external electrode 112 and the periphery of the third mounting portion 43C and the third external electrode 113. Therefore, the relative movement between the second mounting portion 43B and the second external electrode 112 and the relative movement between the third mounting portion 43C and the third external electrode 113 are suppressed by the sealing resin 120. For this reason, it is possible to suppress the peeling of the first to third external electrodes 111 to 113 from the first to third mounting portions 43A to 43C.

[0213] Further, the chip component 10 of this embodiment includes a third insulating layer 50 interposed between the first insulating layer 30 and the second insulating layer 40. A third upper surface 50S of the third insulating layer 50 that contacts the second insulating layer 40 is formed to be rougher than a third lower surface 50R by, for example, ashing treatment. Thereby, the adhesion between the second insulating layer 40 and the third insulating layer 50 is improved. For this reason, the second insulating layer 40 is less likely to be peeled off from the third insulating layer 50.

[0214] The chip component 10 is joined to a wiring board (not shown) by first to third external electrodes 111 to 113. The wiring board includes, for example, a board formed of a glass epoxy resin. Thus, when stress is applied to the first to third external electrodes 111 to 113 in a state where the chip component 10 is mounted on the wiring board. For example, when the temperatures of both the chip component 10 and the wiring board change, stress is generated in the first external electrode 111 and the second external electrode 112 based on the difference between the linear expansion coefficient of the wiring board and the linear expansion coefficient of the substrate 20 of the chip component 10.

[0215] The second connection electrode 90A in the chip component 10 of this embodiment includes first vias 91A and 91B joined to the fourth wiring 64, a rewiring layer 92 joined to the first vias 91A and 91B, a first end portion 71A of a first coil LA joined to the rewiring layer 92, and a second via 93 joined to the first end portion 71A and the first external electrode 111. The first vias 91A and 91B are arranged at positions shifted from the first end portion 71A of the first coil LA in a plan view. Thereby, when the first external electrode 111 changes so as to be shifted with respect to the substrate 20, the stress due to the shift is less likely to be directly applied to the joint portion between the first vias 91A and 91B and the fourth wiring 64 by the rewiring layer 92 interposed between the first external electrode 111 and the fourth wiring 64. For this reason, the stress generated in the joint portion between the first vias 91A and 91B and the fourth wiring 64 is reduced. Thereby, it is possible to suppress the first vias 91A and 91B from being peeled off from the fourth wiring 64.

[0216] [Advantages of the Embodiment] According to the chip component 10 of this embodiment, the following advantages can be obtained. (1) A substrate 20, a first insulating layer 30 formed on the substrate 20, first to fifth capacitors CA to CE formed in the first insulating layer 30, a second insulating layer 40 formed on the first insulating layer 30, a first coil LA and a second coil LB formed in the second insulating layer 40 and electrically connected to the first to fifth capacitors CA to CE, first to third external electrodes 111 to 113 electrically connected to at least any one of the first to fifth capacitors CA to CE, the first coil LA, and the second coil LB, and a sealing resin 120 that covers the second insulating layer 40 and covers side surfaces 111A to 113A of the first to third external electrodes 111 to 113 and exposes upper surfaces 111S to 113S of the first to third external electrodes 111 to 113.

[0217] According to this configuration, since the sealing resin 120 covers the side surfaces 111A to 113A of the first to third external electrodes 111 to 113, it is possible to suppress a direct external force from being applied to the first to third external electrodes 111 to 113 in a direction orthogonal to the thickness direction of the substrate 20. Therefore, it is possible to suppress the first to third external electrodes 111 to 113 from peeling off from the second insulating layer 40.

[0218] (2) The first to third external electrodes 111 to 113 are provided on the second insulating layer 40. According to this configuration, in the second insulating layer 40, the first to third external electrodes 111 to 113 can be electrically connected to at least any one of the first to fifth capacitors CA to CE. Therefore, compared with a configuration in which the first to third external electrodes 111 to 113 are electrically connected to at least any one of the first to fifth capacitors CA to CE outside the second insulating layer 40, miniaturization of the chip component 10 can be achieved.

[0219] (3) The second insulating layer 40 includes a first recessed portion 44A and a second recessed portion 44B formed in portions different from the first to third external electrodes 111 to 113 in plan view. The sealing resin 120 enters both the first recessed portion 44A and the second recessed portion 44B.

[0220] According to this configuration, the volume of the second insulating layer 40 can be reduced as compared with a configuration in which the first recessed portion 44A and the second recessed portion 44B are not formed. Therefore, the warpage amount of the substrate 20 (820) can be reduced during the manufacture of the chip component 10. In addition, by allowing the sealing resin 120 to enter the first recessed portion 44A and the second recessed portion 44B, the contact area between the second insulating layer 40 and the sealing resin 120 can be increased. As a result, the force for suppressing the relative movement between the first to third external electrodes 111 to 113 and the second insulating layer 40 by the sealing resin 120 is increased as compared with a configuration in which the first recessed portion 44A and the second recessed portion 44B are not formed. Therefore, it is possible to suppress the first to third external electrodes 111 to 113 from peeling off from the second insulating layer 40.

[0221] (4) The second insulating layer 40 includes a first insulating film 41 disposed closer to the substrate 20 in the Z direction, a second insulating film 42 laminated on the first insulating film 41 and provided with the first coil LA and the second coil LB, and a third insulating film 43 laminated on the second insulating film 42. The first recessed portion 44A and the second recessed portion 44B penetrate the third insulating film 43 in the Z direction. The first to third external electrodes 111 to 113 are provided on the third insulating film 43.

[0222] According to this configuration, in a configuration in which the first to third external electrodes 111 to 113 are formed on the second insulating layer 40, the number of layers of the second insulating layer 40 can be minimized. Therefore, since the thickness of the second insulating layer 40 can be suppressed, the warpage amount of the substrate 20 (820) can be reduced during the manufacture of the chip component 10.

[0223] (5) The first to third external electrodes 111 to 113 are arranged at intervals from each other in the X direction. The first recessed portion 44A is provided between the first external electrode 111 and the third external electrode 113 in the X direction. The second recessed portion 44B is provided between the third external electrode 113 and the second external electrode 112 in the X direction.

[0224] According to this configuration, each of the second insulating layer 40 and the first to third external electrodes 111 to 113 can be reinforced by the sealing resin 120. Therefore, it is possible to suppress the first to third external electrodes 111 to 113 from peeling off from the second insulating layer 40.

[0225] (6) The sealing resin 120 covers the entire side surfaces 111A to 113A of the first to third external electrodes 111 to 113. According to this configuration, the first to third external electrodes 111 to 113 can be further reinforced by the sealing resin 120. Therefore, it is possible to further suppress the first to third external electrodes 111 to 113 from peeling off from the second insulating layer 40.

[0226] (7) The sealing resin 120 covers the first to fourth side surfaces 40A to 40D of the second insulating layer 40. According to this configuration, it is possible to suppress an external force from being directly applied to the first to fourth side surfaces 40A to 40D of the second insulating layer 40 by the sealing resin 120 and to reinforce the second insulating layer 40. Therefore, it is possible to suppress the second insulating layer 40 from peeling off from, for example, the third insulating layer 50.

[0227] (8) The chip component 10 is provided on both the first insulating layer 30 and the second insulating layer 40, and includes a first connection electrode 80 that electrically connects the third capacitor CC, the first coil LA, and the second coil LB, and a second connection electrode 90A, 90B that is different from the first connection electrode 80 and is provided on both the first insulating layer 30 and the second insulating layer 40 and electrically connects the first, second, fourth, and fifth capacitors CA, CB, CD, CE, the first coil LA, the second coil LB, the first external electrode 111, and the second external electrode 112.

[0228] According to this configuration, since both the first connection electrode 80 and the second connection electrodes 90A and 90B are provided on the first insulating layer 30 and the second insulating layer 40, the chip component 10 can be miniaturized as compared with a configuration in which the first connection electrode 80 and the second connection electrodes 90A and 90B are provided outside the first insulating layer 30 and the second insulating layer 40.

[0229] (9) The second connection electrode 90A includes first vias 91A and 91B joined to the first capacitor CA, and a rewiring layer 92 to which the first vias 91A and 91B and the first end portion 71A of the first coil LA are joined. In a plan view, the first vias 91A and 91B and the first end portion 71A of the first coil LA are arranged at different positions from each other.

[0230] According to this configuration, when the first external electrode 111 changes so as to be displaced with respect to the substrate 20, the stress due to the displacement is less likely to be directly applied to the joint between the first vias 91A and 91B and the first capacitor CA by the rewiring layer 92 interposed between the first external electrode 111 and the first capacitor CA. Therefore, it is possible to suppress the first vias 91A and 91B from being peeled off from the first capacitor CA.

[0231] (10) The second connection electrode 90B includes first vias 94A and 94B joined to the fifth capacitor CE, and a rewiring layer 95 to which the first vias 94A and 94B and the first end portion 71B of the second coil LB are joined. In a plan view, the first vias 94A and 94B and the first end portion 71B of the second coil LB are arranged at different positions from each other.

[0232] According to this configuration, when the second external electrode 112 changes so as to be displaced with respect to the substrate 20, the stress due to the displacement is less likely to be directly applied to the joint between the first vias 94A and 94B and the fifth capacitor CE by the rewiring layer 95 interposed between the second external electrode 112 and the fifth capacitor CE. Therefore, it is possible to suppress the first vias 94A and 94B from being peeled off from the fifth capacitor CE.

[0233] (11) The first via 91A, the first coil LA, and the rewiring layer 92 are made of the same material as each other. The first via 91A and the first capacitor CA are made of different materials from each other.

[0234] According to this configuration, the bonding strength between members made of the same material is greater than the bonding strength between members made of different materials. Therefore, the bonding strength between the first end portion 71A of the first coil LA and the rewiring layer 92 is more likely to be greater than the bonding strength between the first via 91A and the first capacitor CA. Thus, when the first external electrode 111 changes so as to be displaced with respect to the substrate 20, the bonding strength of the joint portion between the first end portion 71A of the first coil LA and the rewiring layer 92, where stress is likely to occur due to the displacement, increases, so that the first end portion 71A of the first coil LA and the rewiring layer 92 are less likely to peel off. In addition, since the bonding strength of the joint portion between the rewiring layer 92 and the first via 91A also increases, the rewiring layer 92 and the first via 91A are less likely to peel off.

[0235] (12) The first via 94A, the second coil LB, and the rewiring layer 95 are made of the same material as each other. The first via 94A and the fifth capacitor CE are made of different materials from each other.

[0236] According to this configuration, the bonding strength between members made of the same material is greater than the bonding strength between members made of different materials. Therefore, the bonding strength between the first end portion 71B of the second coil LB and the rewiring layer 95 is more likely to be greater than the bonding strength between the first via 94A and the fifth capacitor CE. Thus, when the second external electrode 112 changes so as to be displaced with respect to the substrate 20, the bonding strength of the joint portion between the first end portion 71B of the second coil LB and the rewiring layer 95, where stress is likely to occur due to the displacement, increases, so that the first end portion 71B of the second coil LB and the rewiring layer 95 are less likely to peel off. In addition, since the bonding strength of the joint portion between the rewiring layer 95 and the first via 94A also increases, the rewiring layer 95 and the first via 94A are less likely to peel off.

[0237] (13) The first via 91A, the first coil LA, and the rewiring layer 92 contain Cu. The first capacitor CA contains Al. According to this configuration, the bonding force between CUs is greater than the bonding force between Cu and Al. As a result, the bonding force between the first end portion 71A of the first coil LA and the rewiring layer 92 is likely to be greater than the bonding force between the first via 91A and the first capacitor CA. Therefore, the first end portion 71A of the first coil LA and the rewiring layer 92 are less likely to peel off.

[0238] (14) The first via 94A, the second coil LB, and the rewiring layer 95 contain Cu. The fifth capacitor CE contains Al. According to this configuration, the bonding force between CUs is greater than the bonding force between Cu and Al. As a result, the bonding force between the first end portion 71B of the second coil LB and the rewiring layer 95 is likely to be greater than the bonding force between the first via 94A and the fifth capacitor CE. Therefore, the first end portion 71B of the second coil LB and the rewiring layer 95 are less likely to peel off.

[0239] (15) The second connection electrode 90A includes a second via 93 joined to both the first end portion 71A of the first coil LA and the first external electrode 111. According to this configuration, the connection distance between the first coil LA and the first external electrode 111 can be shortened. Therefore, the connection distance between the first capacitor CA, the first coil LA, and the first external electrode 111 by the second connection electrode 90A can be shortened.

[0240] (16) The second connection electrode 90B includes a second via 96 joined to both the first end portion 71B of the second coil LB and the second external electrode 112. According to this configuration, the connection distance between the second coil LB and the second external electrode 112 can be shortened. Therefore, the connection distance between the fifth capacitor CE, the second coil LB, and the second external electrode 112 by the second connection electrode 90B can be shortened.

[0241] (17) The bonding area between the first end portion 71A of the first coil LA and the rewiring layer 92 is larger than the bonding area between the first capacitor CA and the first via 91A. According to this configuration, the bonding strength between the first end portion 71A of the first coil LA and the rewiring layer 92 can be made greater than the bonding strength between the first capacitor CA and the first via 91A.

[0242] (18) The bonding area between the first end portion 71B of the second coil LB and the rewiring layer 95 is larger than the bonding area between the fifth capacitor CE and the first via 94A. According to this configuration, the bonding strength between the first end portion 71B of the second coil LB and the rewiring layer 95 can be made greater than the bonding strength between the fifth capacitor CE and the first via 94A.

[0243] (19) The first insulating layer 30 is an inorganic insulating layer. The second insulating layer 40 is an organic insulating layer. According to this configuration, by forming the first insulating layer 30 of an inorganic insulating layer, the thickness of the first insulating layer 30 can be reduced. Therefore, the chip component 10 can be made thinner. Also, by forming the second insulating layer 40 of an organic insulating layer, the thickness of the second insulating layer 40 can be increased. Therefore, since the first coil LA and the second coil LB provided in the second insulating layer 40 can be made thicker, the resistance of the first coil LA and the second coil LB can be reduced.

[0244] (20) The chip component 10 further includes a third insulating layer 50 interposed between the first insulating layer 30 and the second insulating layer 40 and in contact with both the first insulating layer 30 and the second insulating layer 40. The third insulating layer 50 includes a third upper surface 50S in contact with the second insulating layer 40 and a third lower surface 50R facing the side opposite to the third upper surface 50S. The third upper surface 50S is formed of a rougher surface than the third lower surface 50R.

[0245] According to this configuration, since the third upper surface 50S is formed of a rougher surface, the adhesion between the third upper surface 50S and the second insulating layer 40 can be improved. Therefore, the second insulating layer 40 is less likely to peel off from the third insulating layer 50.

[0246] (21) The third insulating layer 50 is formed of a material containing polyimide. According to this configuration, since the third insulating layer 50 is made of a material containing polyimide, the third upper surface 50S of the third insulating layer 50 is easily roughened. Therefore, the adhesion between the third upper surface 50S and the second insulating layer 40 can be improved.

[0247] (22) The thickness of the second insulating layer 40 is thicker than that of the first insulating layer 30. According to this configuration, since the first coil LA and the second coil LB provided in the second insulating layer 40 can be thickened, the resistance of the first coil LA and the second coil LB can be reduced.

[0248] (23) The first to fifth capacitors CA to CE include first electrodes CA1 to CE1 and second electrodes CA2 to CE2 that face each other in the Z direction within the first insulating layer 30. According to this configuration, the first to fifth capacitors CA to CE can be formed while thinning the first insulating layer 30.

[0249] (24) The second insulating layer 40 includes a first step 45A provided between the first insulating film 41 and the second insulating film 42, and a second step 45B provided between the second insulating film 42 and the third insulating film 43.

[0250] According to this configuration, since the sealing resin 120 covers the first step 45A and the second step 45B, the contact area between the sealing resin 120 and the second insulating layer 40 can be increased. Therefore, the second insulating layer 40 can be reinforced by the sealing resin 120.

[0251] (25) The sealing resin 120 covers the third insulating layer 50. According to this configuration, the third insulating layer 50 can be reinforced by the sealing resin 120. Therefore, the third insulating layer 50 is less likely to be peeled off from the first insulating layer 30.

[0252] (26) The chip component 10 includes a third connection electrode 100A that connects the first capacitor CA and the third capacitor CC to the third external electrode 113. The third connection electrode 100A is provided in the first insulating layer 30 and the second insulating layer 40. According to this configuration, the chip component 10 can be miniaturized as compared with the case where the third connection electrode 100A is provided outside the first insulating layer 30 and the second insulating layer 40.

[0253] (27) The chip component 10 includes a third connection electrode 100B that connects the fifth capacitor CE and the third capacitor CC to the third external electrode 113. The third connection electrode 100B is provided in the first insulating layer 30 and the second insulating layer 40. According to this configuration, the chip component 10 can be miniaturized as compared with the case where the third connection electrode 100B is provided outside the first insulating layer 30 and the second insulating layer 40.

[0254] (28) The third connection electrode 100A includes a first via 101 joined to the first capacitor CA and the third capacitor CC, a rewiring layer 102 joined to the first via 101, and a connection layer 103 connected to the rewiring layer 102. In a plan view, the first via 101 and the connection layer 103 are arranged at different positions from each other.

[0255] According to this configuration, since the positions of the first via 101 and the connection layer 103 in the plan view are shifted from each other via the rewiring layer 102, when an external force is applied to the third external electrode 113, a force is transmitted to the joint portion between the connection layer 103 and the rewiring layer 102 via the third connection electrode 100A, while it is difficult for the force to be transmitted to the joint portion between the first via 101 and the first capacitor CA and the third capacitor CC. Therefore, it is possible to suppress the first via 101 from being peeled off from the first capacitor CA and the third capacitor CC.

[0256] (29) The third connection electrode 100B includes a first via 105 joined to the fifth capacitor CE and the third capacitor CC, a rewiring layer 106 joined to the first via 105, and a connection layer 107 connected to the rewiring layer 106. In plan view, the first via 105 and the connection layer 107 are arranged at different positions from each other.

[0257] According to this configuration, since the positions of the first via 105 and the connection layer 107 in plan view are shifted from each other via the rewiring layer 106, when an external force is applied to the third external electrode 113, a force is transmitted to the joint portion between the connection layer 107 and the rewiring layer 106 via the third connection electrode 100B, while it is difficult for the force to be transmitted to the joint portions between the first via 105 and the fifth capacitor CE and the third capacitor CC. Therefore, it is possible to suppress the first via 105 from being peeled off from the fifth capacitor CE and the third capacitor CC.

[0258] (30) The first via 101, the connection layer 103, and the rewiring layer 102 are made of the same material as each other. The first via 101 and the first capacitor CA and the third capacitor CC are made of different materials from each other.

[0259] According to this configuration, the bonding force between members made of the same material is greater than the bonding force between members made of different materials. For this reason, the bonding force between the connection layer 103 and the rewiring layer 102 is likely to be greater than the bonding force between the first via 101 and the first capacitor CA and the third capacitor CC. Therefore, when an external force is applied to the third external electrode 113, the bonding force of the joint portion between the connection layer 103 and the rewiring layer 102 to which the force is easily transmitted increases, so that the connection layer 103 and the rewiring layer 102 are less likely to be peeled off. In addition, since the bonding force of the joint portion between the rewiring layer 102 and the first via 101 also increases, the rewiring layer 102 and the first via 101 are less likely to be peeled off.

[0260] (31) The first via 105, the connection layer 107, and the rewiring layer 106 are made of the same material as each other. The first via 105 and the fifth capacitor CE and the third capacitor CC are made of different materials from each other.

[0261] According to this configuration, the bonding strength between members made of the same material is greater than the bonding strength between members made of different materials. Therefore, the bonding strength between the connection layer 107 and the rewiring layer 106 is likely to be greater than the bonding strength between the first via 105 and the fifth capacitor CE and the third capacitor CC. Thus, when an external force is applied to the third external electrode 113, the bonding strength of the joint portion between the connection layer 107 and the rewiring layer 106, to which the force is easily transmitted, increases, so that the connection layer 107 and the rewiring layer 106 are less likely to peel off. In addition, since the bonding strength of the joint portion between the rewiring layer 106 and the first via 105 also increases, the rewiring layer 106 and the first via 105 are less likely to peel off.

[0262] (32) The first via 101, the connection layer 103, and the rewiring layer 102 contain Cu. The first capacitor CA and the third capacitor CC contain Al. According to this configuration, the bonding strength between Cu's is greater than the bonding strength between Cu and Al. Thereby, the bonding strength between the connection layer 103 and the rewiring layer 102 is likely to be greater than the bonding strength between the first via 101 and the first capacitor CA and the third capacitor CC. Therefore, the connection layer 103 and the rewiring layer 102 are less likely to peel off.

[0263] (33) The first via 105, the connection layer 107, and the rewiring layer 106 contain Cu. The fifth capacitor CE and the third capacitor CC contain Al. According to this configuration, the bonding strength between Cu's is greater than the bonding strength between Cu and Al. Thereby, the bonding strength between the connection layer 107 and the rewiring layer 106 is likely to be greater than the bonding strength between the first via 105 and the fifth capacitor CE and the third capacitor CC. Therefore, the connection layer 107 and the rewiring layer 106 are less likely to peel off.

[0264] (34) The third connection electrode 100A includes a second via 104 joined to both the connection layer 103 and the third external electrode 113. According to this configuration, the connection distance between the connection layer 103 and the third external electrode 113 can be shortened. Therefore, the connection distance between the first capacitor CA and the third capacitor CC by the third connection electrode 100A and the third external electrode 113 can be shortened.

[0265] (35) The third connection electrode 100B includes a second via 108 joined to both the connection layer 107 and the third external electrode 113. According to this configuration, the connection distance between the connection layer 107 and the third external electrode 113 can be shortened. Therefore, the connection distance between the fifth capacitor CE and the third capacitor CC by the third connection electrode 100B and the third external electrode 113 can be shortened.

[0266] (36) The bonding area between the connection layer 103 and the rewiring layer 102 is larger than the bonding area between the first capacitor CA and the third capacitor CC and the first via 101. According to this configuration, the bonding force between the connection layer 103 and the rewiring layer 102 can be made larger than the bonding force between the first capacitor CA and the third capacitor CC and the first via 101.

[0267] (37) The bonding area between the connection layer 107 and the rewiring layer 106 is larger than the bonding area between the fifth capacitor CE and the third capacitor CC and the first via 105. According to this configuration, the bonding force between the connection layer 107 and the rewiring layer 106 can be made larger than the bonding force between the fifth capacitor CE and the third capacitor CC and the first via 105.

[0268] <Modification Example> The above embodiment can be implemented with the following modifications. Also, the following modification examples can be implemented in combination with each other within a technically non - conflicting range.

[0269] (Modification Example of Connection Electrode) · The configuration of the first connection electrode 80 can be arbitrarily changed. In one example, the first rewiring layer 82 may be omitted from the first connection electrode 80. In this case, the two first vias 81 may be directly connected to the second end portions 72A of the first coil LA and the second end portions 72B of the second coil LB. Further, the second end portions 72A of the first coil LA and the second end portions 72B of the second coil LB may be directly connected to each other.

[0270] In one example, the second rewiring layer 84 may be omitted from the first connection electrode 80. In this case, the second via 83 may be directly connected to the first connection layer 85. In one example, the third rewiring layer 87 may be omitted from the first connection electrode 80. In this case, the third via 86 may be directly connected to the second connection layer 88.

[0271] · The configurations of the second connection electrodes 90A and 90B can be arbitrarily changed. Also, the configurations of the third connection electrodes 100A and 100B can be arbitrarily changed. FIG. 45 is an example of a modification of the second connection electrodes 90A and 90B and the third connection electrodes 100A and 100B, and schematically shows a planar structure of the chip component 10 with the encapsulating resin 120 omitted.

[0272] As shown in FIG. 45, the dimension of the second via 93 of the second connection electrode 90A in the Y direction may be extended. Specifically, the dimension of the second via 93 in the Y direction may be longer than the dimension of the first end portion 71A of the first coil LA in the Y direction. Also, the dimension of the second via 93 in the Y direction may be longer than the dimension of the rewiring layer 92 in the Y direction. Further, the dimension of the second via 96 of the second connection electrode 90B in the Y direction may be extended. Specifically, the dimension of the second via 96 in the Y direction may be longer than the dimension of the first end portion 71B of the second coil LB in the Y direction. Also, the dimension of the second via 96 in the Y direction may be longer than the dimension of the rewiring layer 95 in the Y direction.

[0273] The Y-direction dimension of the second via 104 of the third connection electrode 100A may be extended. Specifically, in a plan view, the Y-direction dimension of the second via 104 may be extended so that the second via 104 overlaps with the first via 101. Also, the Y-direction dimension of the second via 104 may be longer than the Y-direction dimension of the rewiring layer 102. Further, the Y-direction dimension of the second via 108 of the third connection electrode 100B may be extended. Specifically, in a plan view, the Y-direction dimension of the second via 108 may be extended so that the second via 108 overlaps with the first via 105. Also, the Y-direction dimension of the second via 108 may be longer than the Y-direction dimension of the rewiring layer 106.

[0274] · The second connection electrode 90A may be configured as a stacked via in which the first end portion 71A of the first coil LA is directly connected to the first via 91A without the interposition of the rewiring layer 92. · The second connection electrode 90B may be configured as a stacked via in which the first end portion 71B of the second coil LB is directly connected to the first via 94A without the interposition of the rewiring layer 95.

[0275] · The third connection electrode 100A may be configured as a stacked via in which the first via 101 and the connection layer 103 are directly connected without the interposition of the rewiring layer 102. · The third connection electrode 100B may be configured as a stacked via in which the first via 105 and the connection layer 107 are directly connected without the interposition of the rewiring layer 106.

[0276] (Modification Examples of the First to Third Insulating Layers) · The thickness relationship among the first insulating layer 30, the second insulating layer 40, and the third insulating layer 50 can be arbitrarily changed. In one example, the first insulating layer 30 may be thicker than the third insulating layer 50. The first insulating layer 30 may be thicker than the second insulating layer 40. The third insulating layer 50 may be thicker than the second insulating layer 40.

[0277] · The configuration of the second insulating layer 40 can be arbitrarily changed. FIG. 46 is an example of a modified example of the second insulating layer 40, and schematically shows a planar structure of the chip component 10 with the encapsulation resin 120 omitted. As shown in FIG. 46, the second insulating layer 40 includes first to third engaging portions 46A to 46C that engage with the encapsulation resin 120. Here, the first to third engaging portions 46A to 46C are an example of the "engaging portion".

[0278] The first engaging portion 46A is provided in the first mounting portion 43A of the third insulating film 43 of the second insulating layer 40. The first engaging portion 46A is provided on each of a second side surface 43AB facing the same side as the second side surface 40B of the second insulating layer 40 in the first mounting portion 43A, a third side surface 43AC facing the same side as the third side surface 40C, and a fourth side surface 43AD facing the same side as the fourth side surface 40D. It can be said that the second to fourth side surfaces 43AB to 43AD are side surfaces of the third insulating film 43 that constitute the first recessed portion 44A.

[0279] In one example, a plurality of first engaging portions 46A are provided on each of the second to fourth side surfaces 43AB to 43AD. In one example, the number of the first engaging portions 46A provided on the second side surface 43AB is larger than the number of the first engaging portions 46A provided on the third side surface 43AC and the number of the first engaging portions 46A provided on the fourth side surface 43AD.

[0280] In the example shown in FIG. 46, three first engaging portions 46A are provided on the second side surface 43AB. These three first engaging portions 46A are provided at both ends in the Y direction and the center in the Y direction of the second side surface 43AB. Two first engaging portions 46A are provided on the third side surface 43AC. These two first engaging portions 46A are provided at both ends in the X direction of the third side surface 43AC. Two first engaging portions 46A are provided on the fourth side surface 43AD. These two first engaging portions 46A are provided at both ends in the X direction of the fourth side surface 43AD.

[0281] The first engaging portion 46A extends into the first recessed portion 44A in a plan view. More specifically, the first engaging portion 46A includes a first portion 47 protruding from each of the second to fourth side surfaces 43AB to 43AD of the first mounting portion 43A in a plan view, and a second portion 48 extending in a direction intersecting the first portion 47 in a plan view. The second portion 48 is provided continuously from the first portion 47. In one example, the second portion 48 extends in a second extending direction orthogonal to the first extending direction in which the first portion 47 extends with respect to the first portion 47 in a plan view. The second portion 48 is provided so as to protrude from both sides of the first portion 47 in the second extending direction.

[0282] Among the plurality of first engaging portions 46A, the first engaging portion 46AA provided at the end portion closer to the first side surface 40A on the third side surface 43AC and the first engaging portion 46AA provided at the end portion closer to the first side surface 40A on the fourth side surface 43AD are different in shape from the remaining first engaging portions 46A. More specifically, the second portion 48 of the first engaging portion 46AA includes a triangular shape in a plan view. The dimension of the first engaging portion 46AA in the Y direction is larger than the dimension of the first engaging portion 46A in the Y direction.

[0283] The second engaging portion 46B is provided on the second mounting portion 43B of the third insulating film 43. The second engaging portion 46B is provided on each of a first side surface 43BA facing the same side as the first side surface 40A of the second insulating layer 40 in the second mounting portion 43B, a third side surface 43BC facing the same side as the third side surface 40C, and a fourth side surface 43BD facing the same side as the fourth side surface 40D. It can be said that the first side surface 43BA, the third side surface 43BC, and the fourth side surface 43BD are side surfaces of the third insulating film 43 that constitute the second recessed portion 44B. Therefore, it can be said that the second engaging portion 46B extends into the second recessed portion 44B in a plan view.

[0284] In one example, a plurality of second engaging portions 46B are provided on each of the first side surface 43BA, the third side surface 43BC, and the fourth side surface 43BD. In one example, the number of the second engaging portions 46B provided on the first side surface 43BA is larger than the number of the second engaging portions 46B provided on the third side surface 43BC and the number of the second engaging portions 46B provided on the fourth side surface 43BD.

[0285] In the example shown in FIG. 46, three second engaging portions 46B are provided on the first side surface 43BA. These three second engaging portions 46B are provided at both ends in the Y direction and at the center in the Y direction of the first side surface 43BA. Two second engaging portions 46B are provided on the third side surface 43BC. These two second engaging portions 46B are provided at both ends in the X direction of the third side surface 43BC. Two second engaging portions 46B are provided on the fourth side surface 43BD. These two second engaging portions 46B are provided at both ends in the X direction of the fourth side surface 43BD. Note that the configuration of the second engaging portion 46B is the same as the configuration of the first engaging portions 46A and 46AA.

[0286] The third engaging portion 46C is provided on the third mounting portion 43C of the third insulating film 43. The third engaging portion 46C is provided on each of a first side surface 43CA facing the same side as the first side surface 40A of the second insulating layer 40 in the third mounting portion 43C and a second side surface 43CB facing the same side as the second side surface 40B. It can be said that the first side surface 43CA of the third mounting portion 43C is a side surface of the third insulating film 43 that constitutes the first recessed portion 44A, and it can be said that the second side surface 43CB is a side surface of the third insulating film 43 that constitutes the second recessed portion 44B. Therefore, it can be said that the third engaging portion 46C provided on the first side surface 43CA extends into the first recessed portion 44A in a plan view. It can be said that the third engaging portion 46C provided on the second side surface 43CB extends into the second recessed portion 44B in a plan view.

[0287] In one example, a plurality of third engaging portions 46C are provided on each of the first side surface 43CA and the second side surface 43CB. In one example, the number of the third engaging portions 46C provided on the first side surface 43CA is the same as the number of the third engaging portions 46C provided on the second side surface 43CB. In one example, the number of the third engaging portions 46C provided on the first side surface 43CA is larger than the number of the first engaging portions 46A provided on the second side surface 43AB of the first mounting portion 43A. In one example, the number of the third engaging portions 46C provided on the second side surface 43CB is larger than the number of the second engaging portions 46B provided on the first side surface 43BA of the second mounting portion 43B.

[0288] In one example, four third engaging portions 46C are provided on the first side surface 43CA. The four third engaging portions 46C are arranged at equal intervals in the Y direction. The two third engaging portions 46C at both ends in the Y direction are provided corresponding to both ends in the Y direction of the first side surface 43CA. In the example shown in FIG. 46, the four third engaging portions 46C are arranged with a shift in the Y direction with respect to the three first engaging portions 46A provided on the second side surface 43AB of the first mounting portion 43A.

[0289] In one example, four third engaging portions 46C are provided on the second side surface 43CB. The four third engaging portions 46C are arranged at equal intervals in the Y direction. The two third engaging portions 46C at both ends in the Y direction are provided corresponding to both ends in the Y direction of the second side surface 43CB. In the example shown in FIG. 46, the four third engaging portions 46C are arranged with a shift in the Y direction with respect to the three second engaging portions 46B provided on the first side surface 43BA of the second mounting portion 43B. Note that the configuration of the third engaging portion 46C is the same as the configuration of the first engaging portion 46A. That is, the third engaging portion 46C does not include the first engaging portion 46AA with the same configuration.

[0290] Although not shown, the sealing resin 120 that has entered the first recessed portion 44A enters between adjacent first engaging portions 46A and between a plurality of third engaging portions 46C provided on the first side surface 43CA of the third mounting portion 43C. Further, the sealing resin 120 that has entered the second recessed portion 44B enters between adjacent second engaging portions 46B and between a plurality of third engaging portions 46C provided on the second side surface 43CB of the third mounting portion 43C. According to this configuration, the contact area between the side surface of the third insulating film 43 and the sealing resin 120 increases. In addition, since the sealing resin 120 enters between the second to fourth side surfaces 43AB to 43AD of the first mounting portion 43A and the second portion 48 of the first engaging portion 46A, an anchor effect occurs. Since the sealing resin 120 enters between the first side surface 43BA, the third side surface 43BC, and the fourth side surface 43BD of the second mounting portion 43B and the second portion 48 of the second engaging portion 46B, an anchor effect occurs. Since the sealing resin 120 enters between the first side surface 43CA and the second side surface 43CB of the third mounting portion 43C and the second portion 48 of the third engaging portion 46C, an anchor effect occurs. Therefore, the adhesion between the sealing resin 120 and the third insulating film 43 is improved and the sealing resin 120 and the third insulating film 43 are less likely to peel off from each other.

[0291] Note that the number and arrangement pattern of the first engaging portions 46A are not limited to the example shown in FIG. 46 and can be arbitrarily changed. In one example, the number of the first engaging portions 46A provided on the second side surface 43AB of the first mounting portion 43A may be the same as the number of the first engaging portions 46A provided on the third side surface 43AC, or may be the same as the number of the first engaging portions 46A provided on the fourth side surface 43AD. In one example, the first engaging portion 46A may be omitted from the second side surface 43AB of the first mounting portion 43A. In one example, the first engaging portion 46A may be omitted from the third side surface 43AC. In one example, the first engaging portion 46A may be omitted from the fourth side surface 43AD.

[0292] Further, the number and arrangement pattern of the second engaging portions 46B are not limited to the example shown in FIG. 46 and can be arbitrarily changed. In one example, the number of the second engaging portions 46B provided on the first side surface 43BA of the second mounting portion 43B may be the same as the number of the second engaging portions 46B provided on the third side surface 43BC, or may be the same as the number of the second engaging portions 46B provided on the fourth side surface 43BD. In one example, the second engaging portion 46B may be omitted from the first side surface 43BA of the second mounting portion 43B. In one example, the second engaging portion 46B may be omitted from the third side surface 43BC. In one example, the second engaging portion 46B may be omitted from the fourth side surface 43BD.

[0293] Further, the number and arrangement pattern of the third engaging portions 46C are not limited to the example shown in FIG. 46 and can be arbitrarily changed. In one example, the number of the third engaging portions 46C provided on the first side surface 43CA of the third mounting portion 43C and the number of the third engaging portions 46C provided on the second side surface 43CB may be different from each other. In one example, the third engaging portion 46C may be omitted from the first side surface 43CA. In one example, the third engaging portion 46C may be omitted from the second side surface 43CB.

[0294] · The shapes of the first to third engaging portions 46A to 46C are not limited to the example shown in FIG. 46 and can be arbitrarily changed. In one example, at least one of the first to third engaging portions 46A to 46C may have a shape in which the second portion 48 is omitted, that is, a shape composed of only the first portion 47. In one example, at least one of the first to third engaging portions 46A to 46C may be formed in an L shape in plan view.

[0295] · The recessed portion 44 may be formed so as to surround the third external electrode 113 in plan view. · At least one of the first recessed portion 44A and the second recessed portion 44B may be omitted from the second insulating layer 40. When both the first recessed portion 44A and the second recessed portion 44B are omitted, the sealing resin 120 covers the second upper surface 40S and the first to fourth side surfaces 40A to 40D of the second insulating layer 40. Further, the sealing resin 120 covers the side surfaces 111A to 113A of the first to third external electrodes 111 to 113.

[0296] (Examples of changes to the external electrodes) · The configuration of the external electrode 110 can be arbitrarily changed. In one example, the chip component 10 may include first to fourth external electrodes 111 to 114 shown in FIG. 47 instead of the first to third external electrodes 111 to 113. Here, FIG. 47 schematically shows a planar structure in which the encapsulating resin 120, the first coil LA, and the second coil LB are omitted from the chip component 10.

[0297] In response to the chip component 10 including the first to fourth external electrodes 111 to 114, the third insulating film 43 of the second insulating layer 40 includes first to fourth mounting portions 43A to 43D. The sizes, shapes, and arrangement positions of the first mounting portion 43A and the second mounting portion 43B are the same as those of the first mounting portion 43A and the second mounting portion 43B in the above embodiment. Also, the sizes, shapes, and arrangement positions of the first external electrode 111 and the second external electrode 112 are the same as those of the first external electrode 111 and the second external electrode 112 in the above embodiment.

[0298] The third mounting portion 43C and the fourth mounting portion 43D are located at the center of the second insulating layer 40 in the X direction in a plan view and are arranged to be spaced apart from each other in the Y direction. The third mounting portion 43C is arranged near the third side surface 40C of the second insulating layer 40. The fourth mounting portion 43D is arranged near the fourth side surface 40D of the second insulating layer 40. Both the third mounting portion 43C and the fourth mounting portion 43D are formed in a rectangular shape in which the X direction is the longitudinal direction and the Y direction is the short side direction in a plan view.

[0299] The third external electrode 113 is formed on the third mounting portion 43C, and the fourth external electrode 114 is formed on the fourth mounting portion 43D. Both the third external electrode 113 and the fourth external electrode 114 are formed in a rectangular shape in which the X direction is the longitudinal direction and the Y direction is the short side direction in a plan view.

[0300] The second insulating layer 40 includes a recessed portion 44. The recessed portion 44 is provided so that the first to fourth mounting portions 43A to 43D are spaced apart from each other. The recessed portion 44 penetrates the third insulating film 43 in the same manner as in the above embodiment. Therefore, the recessed portion 44 exposes the second insulating film 42.

[0301] Although not shown, the encapsulating resin 120 covers the first to fourth side surfaces 40A to 40D of the second insulating layer 40 and enters the recessed portion 44, similar to the above-described embodiment. Further, the encapsulating resin 120 covers the side surfaces 111A to 113A of the first to fourth external electrodes 111 to 113. In one example, the encapsulating resin 120 may cover the side surfaces 111A to 113A of the first to fourth external electrodes 111 to 113 over the entire surface.

[0302] · The planar shape of each of the first to third external electrodes 111 to 113 can be arbitrarily changed. In one example, the planar shape of each of the first to third external electrodes 111 to 113 may be any of circular, elliptical, oval, and polygonal shapes.

[0303] (Modification example of encapsulating resin) · The encapsulating resin 120 may be configured to cover the entire surface of each of the first to fourth side surfaces 30A to 30D of the first insulating layer 30.

[0304] · The encapsulating resin 120 may be configured to cover the first to fourth side surfaces 40A to 40D of the second insulating layer 40, the side surface of the third insulating layer 50, the first to fourth side surfaces 30A to 30D of the first insulating layer 30, and the first to fourth substrate side surfaces 23 to 26 of the substrate 20.

[0305] · The encapsulating resin 120 may be configured to cover the first to fourth side surfaces 40A to 40D of the second insulating layer 40 and the side surface of the third insulating layer 50, while not covering the first to fourth side surfaces 30A to 30D of the first insulating layer 30.

[0306] · The encapsulating resin 120 may be configured to cover the first to fourth side surfaces 40A to 40D of the second insulating layer 40, while not covering the side surface of the third insulating layer 50 and the first to fourth side surfaces 30A to 30D of the first insulating layer 30.

[0307] · The encapsulation resin 120 may be configured to partially cover the first to fourth side surfaces 40A to 40D of the second insulating layer 40. In one example, the encapsulation resin 120 covers the first to fourth side surfaces 40A to 40D corresponding to the third insulating film 43 in the second insulating layer 40, while not covering the first to fourth side surfaces 40A to 40D corresponding to both the first insulating film 41 and the second insulating film 42. In one example, the encapsulation resin 120 covers the first to fourth side surfaces 40A to 40D corresponding to both the second insulating film 42 and the third insulating film 43 in the second insulating layer 40, while not covering the first to fourth side surfaces 40A to 40D corresponding to the first insulating film 41.

[0308] · The encapsulation resin 120 may be configured not to cover each of the first to fourth side surfaces 30A to 30D of the first insulating layer 30, the first to fourth side surfaces 40A to 40D of the second insulating layer 40, and the side surface of the third insulating layer 50, while covering the side surfaces 111A to 113A of the first to third external electrodes 111 to 113.

[0309] · The encapsulation resin 120 may be configured to partially cover each of the side surfaces 111A to 113A of the first to third external electrodes 111 to 113. In one example, the encapsulation resin 120 may be configured to partially cover each of the side surfaces 111A to 113A of the first to third external electrodes 111 to 113 in the Z direction. In other words, the first to third external electrodes 111 to 113 may be configured to partially protrude with respect to the upper surface 120S of the encapsulation resin 120.

[0310] · The encapsulation resin 120 may be omitted from the chip component 10. In this case, the first to fourth side surfaces 40A to 40D of the second insulating layer 40, the side surface of the third insulating layer 50, and the first to fourth side surfaces 30A to 30D of the first insulating layer 30 may be flush with the first to fourth substrate side surfaces 23 to 26 of the substrate 20.

[0311] (Modification example of the configuration of the chip component) · In the chip component 10 of the above embodiment, the first to third external electrodes 111 to 113 were formed on the upper surfaces 43AS to 43CS of the first to third placement portions 43A to 43C of the third insulating film 43 in the second insulating layer 40, but it is not limited thereto. In one example, the external electrode 110 may be disposed outward of the first to fourth side surfaces 40A to 40D of the second insulating layer 40 in a plan view. FIGS. 48 to 50 show the chip component 10 of a modified example. FIG. 48 schematically shows the planar structure of the chip component 10 of the modified example. FIG. 49 shows the cross-sectional structure of the chip component 10 of the modified example cut along the line F49-F49 in FIG. 48. FIG. 50 shows the enlarged structure of the first external electrode 111 and its periphery in the cross-sectional structure of FIG. 49.

[0312] As shown in FIG. 48, the chip component 10 of the modified example includes first to fourth external electrodes 151 to 154. The first external electrode 151 and the second external electrode 152 are provided at both ends in the X direction of the encapsulating resin 120. The third external electrode 153 and the fourth external electrode 154 are provided at both ends in the Y direction at the center in the X direction of the encapsulating resin 120.

[0313] As shown in FIGS. 48 and 49, the first external electrode 151 is disposed outward of the first side surface 40A of the second insulating layer 40 in the X direction. The first external electrode 151 is provided on the first side surface covering portion 121 of the encapsulating resin 120. The second external electrode 152 is disposed outward of the second side surface 40B of the second insulating layer 40 in the X direction. The second external electrode 152 is provided on the second side surface covering portion 122 of the encapsulating resin 120.

[0314] As shown in FIG. 48, the third external electrode 153 is disposed outward of the third side surface 40C of the second insulating layer 40 in the Y direction. The third external electrode 153 is provided on the third side surface covering portion 123 of the encapsulating resin 120. The fourth external electrode 154 is disposed outward of the fourth side surface 40D of the second insulating layer 40 in the Y direction. The fourth external electrode 154 is provided on the fourth side surface covering portion 124 of the encapsulating resin 120.

[0315] As shown in FIG. 50, the second connection electrode 90A includes a lead-out wiring 97. The lead-out wiring 97 is interposed between a first portion 91AA and a second portion 91AB of the first via 91A. That is, the lead-out wiring 97 is joined to the upper surface of the second portion 91AB. The lower surface of the first portion 91AA is joined to the lead-out wiring 97. The lead-out wiring 97 extends outward beyond the first side surface 40A of the second insulating layer 40 in the X direction. The lead-out wiring 97 is provided on the third insulating layer 50. For this reason, the third insulating layer 50 extends outward beyond the first side surface 40A of the second insulating layer 40. The first external electrode 151 is connected to the lead-out wiring 97 within the first side surface cover portion 121. The first external electrode 151 is exposed from the first side surface cover portion 121 in the Z direction.

[0316] Note that the second connection electrode 90B also similarly includes a lead-out wiring 97. The second external electrode 152 is connected to the lead-out wiring 97 of the second connection electrode 90B within the second side surface cover portion 122. The second external electrode 152 is exposed from the second side surface cover portion 122 in the Z direction.

[0317] The third connection electrode 100A includes a lead-out wiring (not shown) instead of the first portion 101A, the rewiring layer 102, the connection layer 103, and the second via 104 (both shown in FIG. 14) of the first via 101. The lead-out wiring is provided on the third insulating layer 50 (see FIG. 50). For this reason, the third insulating layer 50 extends outward beyond the third side surface 40C of the second insulating layer 40. The third external electrode 153 is connected to the lead-out wiring within the third side surface cover portion 123. The third side surface cover portion 123 is exposed from the third side surface cover portion 123 in the Z direction.

[0318] Note that the third connection electrode 100B also similarly includes a lead-out wiring. The fourth external electrode 154 is connected to the lead-out wiring of the third connection electrode 100B within the fourth side surface cover portion 124. The fourth external electrode 154 is exposed from the fourth side surface cover portion 124 in the Z direction.

[0319] According to this configuration, since each of the first to fourth external electrodes 151 to 154 is provided in the sealing resin 120, direct application of an external force to the first to fourth external electrodes 151 to 154 is suppressed. Therefore, peeling of the first to fourth external electrodes 151 to 154 from the sealing resin 120 can be suppressed.

[0320] In addition, the second insulating layer 40 is configured by a laminated structure of the first insulating film 41 and the second insulating film 42. That is, the third insulating film 43 is omitted from the second insulating layer 40. Therefore, the amount of warpage of the substrate 20 (820) caused by the second insulating layer 40 (840) can be reduced during the manufacture of the chip component 10. In addition, since the thickness of the second insulating layer 40 becomes thinner, the chip component 10 can be made thinner.

[0321] [Modification example of manufacturing method of chip component] · The chip component 10 may be manufactured such that the sealing resin 120 is formed on a part in the Z direction of the first to fourth substrate side surfaces 23 to 26 of the substrate 20. FIGS. 51 to 56 show an example of a modification example of the manufacturing method of the chip component 10.

[0322] FIGS. 51 to 53 show the step of forming the sealing resin 920. As shown in FIG. 51, a groove 823 recessed from the first substrate surface 821 to the second substrate surface 822 of the substrate 820 is formed. The groove 823 is formed, for example, by etching. The groove 823 is formed outside the second insulating layer 840 in the substrate 820.

[0323] Subsequently, as shown in FIG. 52, the sealing resin 920 is formed, for example, by transfer molding. The sealing resin 920 enters the groove 823 of the substrate 820. The sealing resin 920 shown in FIG. 52 is formed so as to cover the upper surfaces 111S to 113S of the first to third external electrodes 111 to 113.

[0324] Subsequently, as shown in FIG. 53, the encapsulation resin 920 is ground. In this process, the first to third external electrodes 111 to 113 may also be ground. As a result, the first to third external electrodes 111 to 113 are exposed from the encapsulation resin 920. On the other hand, the encapsulation resin 920 covers the side surfaces 111A to 113A of each of the first to third external electrodes 111 to 113.

[0325] FIG. 54 shows the process of grinding the substrate 820. In this process, the substrate 820 is thinned by grinding the substrate 820 from the second substrate surface 822. Note that, in the process of grinding the substrate 820, for example, the CMP method is used. As a method for thinning the substrate 820, other methods or a combination of a plurality of methods may be used.

[0326] FIG. 55 shows the process of forming the bonding layer 115 on each of the first to third external electrodes 111 to 113. In this process, the bonding layer 115 is formed by printing, for example, cream solder on each of the upper surfaces 111S to 113S of the first to third external electrodes 111 to 113.

[0327] FIG. 56 shows the process of singulation. In the process of singulation, first, the dicing tape 990 is attached to the second substrate surface 822 of the substrate 820. Subsequently, for example, using a dicing blade, the encapsulation resin 920 and the substrate 820 are cut in the Z direction. As a result, a part of the groove 823 is cut, and the chip component 10 in which a part of the first to fourth substrate side surfaces 23 to 26 in the Z direction is covered with the encapsulation resin 120 is manufactured.

[0328] One or more of the various examples described in this specification can be combined within a technically non - conflicting range. As used herein, the term "on" includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "the first element is disposed on the second element" is intended that in some embodiments, the first element may be directly disposed on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. That is, the term "on" does not exclude a structure in which other elements are formed between the first element and the second element.

[0329] The Z direction used in the present disclosure does not necessarily have to be the vertical direction and does not have to completely coincide with the vertical direction. Thus, various structures according to the present disclosure are not limited to the "up" and "down" in the Z direction described herein being the "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0330] <Supplementary Note> The technical idea understandable from the present disclosure is described below. Note that, for the purpose of assisting understanding rather than limitation, the components described in the supplementary note are assigned the reference numerals of the corresponding components in the above embodiments. The reference numerals are shown as examples for assisting understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0331] [Supplementary Note A1] a substrate (20); a first insulating layer (30) formed on the substrate (20); a capacitor (CA to CE) formed in the first insulating layer (30); a second insulating layer (40) formed on the first insulating layer (30); a coil (LA, LB) formed in the second insulating layer (40) and electrically connected to the capacitor (CA to CE); At least external electrodes (110 / 111 to 113) electrically connected to the capacitors (CA to CE) among the capacitors (CA to CE) and the coils (LA, LB), A sealing resin (120) that covers the second insulating layer (40) and covers side surfaces (111A to 113A) of the external electrodes (110 / 111 to 113) and exposes upper surfaces (111S to 113S) of the external electrodes (110 / 111 to 113), A chip component (10) including the above.

[0332] [Appendix A2] The external electrodes (110 / 111 to 113) are provided on the second insulating layer (40). The chip component according to Appendix A1.

[0333] [Appendix A3] The second insulating layer (40) includes recessed portions (44A, 44B) formed in portions different from the external electrodes (110 / 111 to 113) when viewed from the thickness direction (Z direction) of the substrate (20), The sealing resin (120) enters the recessed portions (44A, 44B). The chip component according to Appendix A1 or A2.

[0334] [Appendix A4] The second insulating layer (40) A first insulating film (41) disposed closer to the substrate (20) in the thickness direction (Z direction) of the substrate (20), A second insulating film (42) laminated on the first insulating film (41) and provided with the coils (LA, LB), A third insulating film (43) laminated on the second insulating film (42), Including The recessed portions (44A, 44B) penetrate the third insulating film (43) in the thickness direction (Z direction) of the substrate (20), The external electrodes (110 / 111 to 113) are provided on the third insulating film (43). The chip component according to Appendix A3.

[0335] [Appendix A5] The external electrode (110) includes a plurality of external electrodes (111 to 113) arranged apart from each other in a first direction (X direction) orthogonal to the thickness direction (Z direction) of the substrate (20). The recessed portions (44A, 44B) are provided between the external electrodes (111 to 113) adjacent to each other in the first direction (X direction) among the plurality of external electrodes (111 to 113). The chip component according to Appendix A3 or A4.

[0336] [Appendix A6] The encapsulating resin (120) covers the entire side surface of the external electrode (110 / 111 to 113). The chip component according to any one of Appendices A1 to A5.

[0337] [Appendix A7] The encapsulating resin (120) covers the side surfaces (40A to 40D) of the second insulating layer (40). The chip component according to any one of Appendices A1 to A6.

[0338] [Appendix A8] The third insulating film (43) includes engaging portions (46A to 46C) that extend into the recessed portions (44A, 44B) as viewed from the thickness direction (Z direction) of the substrate (20) and engage with the encapsulating resin (120). The chip component according to Appendix A4.

[0339] [Appendix A9] The engaging portions (46A to 46C) include a first portion (47) protruding from the side surface of the third insulating film (43) that constitutes the recessed portions (44A, 44B), and a second portion (48) that is continuously provided from the first portion (47) and extends in a direction intersecting the first portion (47) as viewed from the thickness direction (Z direction) of the substrate (20). and The chip component according to Appendix A8.

[0340] [Appendix A10] The sealing resin (120) includes side cover portions (121 to 124) that cover side surfaces (40A to 40D) of the second insulating layer (40). The external electrodes (110 / 111 to 113) are provided on the side cover portions (121 to 124) outside the side surfaces (40A to 40D) of the second insulating layer (40) when viewed from the thickness direction (Z direction) of the substrate (20). The chip component according to appended note A1.

[0341] [Appended note A11] A first connection electrode (80) provided on both the first insulating layer (30) and the second insulating layer (40) for electrically connecting the capacitor (CA to CE) and the coil (LA, LB); A second connection electrode (90A, 90B) provided on both the first insulating layer (30) and the second insulating layer (40) for electrically connecting the capacitor (CA to CE), the coil (LA, LB), and the external electrode (110 / 111 to 113); including The chip component according to any one of appended notes A1 to A10.

[0342] [Appended note A12] The second connection electrode (90A, 90B) includes First vias (91A, 91B, 94A, 94B) joined to the capacitor (CA, CB, CD, CE); A rewiring layer (92, 95) in which the first vias (91A, 91B, 94A, 94B) and the ends (71A, 71B) of the coil (LA, LB) are joined; including When viewed from the thickness direction (Z direction) of the substrate (20), the first vias (91A, 91B, 94A, 94B) and the ends (71A, 71B) of the coil (LA, LB) are arranged at different positions from each other. The chip component according to appended note A11.

[0343] [Appended note A13] The first vias (91A, 91B, 94A, 94B), the coils (LA, LB), and the rewiring layers (92, 95) are made of the same material as each other. The first vias (91A, 91B, 94A, 94B) and the capacitors (CA, CB, CD, CE) are made of different materials from each other. The chip component according to Supplementary Note A12.

[0344] [Supplementary Note A14] The first vias (91A, 91B, 94A, 94B), the coils, and the rewiring layers (92, 95) contain Cu. The capacitors (CA, CB, CD, CE) contain Al. The chip component according to Supplementary Note A12 or A13.

[0345] [Supplementary Note A15] The second connection electrodes (90A, 90B) include second vias (93, 96) joined to both the ends (71A, 71B) of the coils (LA, LB) and the external electrodes (111, 112). The chip component according to any one of Supplementary Notes A12 to A14.

[0346] [Supplementary Note A16] The joint area between the ends (71A, 71B) of the coils (LA, LB) and the rewiring layers (92, 95) is larger than the joint area between the capacitors (CA, CB, CD, CE) and the first vias (91A, 91B, 94A, 94B). The chip component according to any one of Supplementary Notes A12 to A15.

[0347] [Supplementary Note A17] The coils (LA, LB) include winding portions (73A, 73B) wound in a direction orthogonal to the thickness direction (Z direction) of the substrate (20). The first vias (91A, 91B, 94A, 94B) are arranged in regions (74A, 74B) inner than the winding portions (73A, 73B) when viewed from the thickness direction (Z direction) of the substrate (20). The chip component according to any one of Appendices A12 to A16.

[0348] [Appendix A18] The first insulating layer (30) is an inorganic insulating layer, The second insulating layer (40) is an organic insulating layer The chip component according to any one of Appendices A1 to A17.

[0349] [Appendix A19] Further includes a third insulating layer (50) interposed between the first insulating layer (30) and the second insulating layer (40) and in contact with both the first insulating layer (30) and the second insulating layer (40), The third insulating layer (50) is, A third upper surface (50S) in contact with the second insulating layer (40), A third lower surface (50R) facing the side opposite to the third upper surface (50S), And includes, The third upper surface (50S) is constituted by a rougher surface than the third lower surface (50R) The chip component according to any one of Appendices A1 to A18.

[0350] [Appendix A20] The third insulating layer (50) is constituted by a material containing polyimide The chip component according to Appendix A19.

[0351] [Appendix A21] The third insulating layer (50) is thicker than the first insulating layer (30) The chip component according to Appendix A19 or A20.

[0352] [Appendix A22] The third insulating layer (50) is thinner than the second insulating layer (40) The chip component according to any one of Appendices A19 to A21.

[0353] [Appendix A23] The third upper surface (50S) is composed of a surface roughened by an ashing process. The chip component according to any one of Appendices A19 to A22.

[0354] [Appendix A24] The end portions (71A, 71B) of the coils (LA, LB) are sandwiched between the rewiring layers (92, 95) and the second vias (93, 96). The chip component according to Appendix A15.

[0355] [Appendix A25] The external electrodes (110) include a plurality of external electrodes (111 to 113) spaced apart from each other in a first direction (X direction) orthogonal to the thickness direction (Z direction) of the substrate (20). The coils include a plurality of coils (LA, LB) arranged spaced apart from each other in the first direction (X direction) and electrically connected to each other. The capacitors include a plurality of capacitors (CA to CE) arranged spaced apart from each other in a direction orthogonal to the thickness direction (Z direction) of the substrate (20) and electrically connected to each other. The second connection electrodes include a plurality of second connection electrodes (90A, 90B) arranged spaced apart from each other in the first direction (X direction). The chip component according to any one of Appendices A11 to A17.

[0356] [Appendix A26] The thickness of the second insulating layer (40) is greater than the thickness of the first insulating layer (30). The chip component according to any one of Appendices A1 to A25.

[0357] [Appendix A27] The thickness of the coils (LA, LB) is greater than the thickness of the first insulating layer (30). The chip component according to any one of Appendices A1 to A26.

[0358] [Appendix A28] The thickness of the coils (LA, LB) is greater than the thickness of the rewiring layers (92, 96). The chip component according to any one of Supplementary Notes A12 to A17.

[0359] [Supplementary Note A29] The thickness of the coils (LA, LB) is less than the thickness of the first vias (91A, 91B, 94A, 94B). The chip component according to any one of Supplementary Notes A12 to A17.

[0360] [Supplementary Note A30] The capacitors (CA to CE) include a first electrode (CA1 to CE1) and a second electrode (CA2 to CE2) that face each other in the thickness direction (Z direction) of the first insulating layer (30) within the first insulating layer (30). The chip component according to any one of Supplementary Notes A1 to A29.

[0361] [Supplementary Note A31] The first vias include a plurality of first vias (91A, 91B / 94A, 94B) that are arranged spaced apart in a direction orthogonal to the thickness direction (Z direction) of the substrate (20). The chip component according to any one of Supplementary Notes A12 to A17.

[0362] [Supplementary Note B1] A substrate (20), A first insulating layer (30) formed on the substrate (20), Capacitors (CA to CE) formed within the first insulating layer (30), A second insulating layer (40) formed on the first insulating layer (30), Coils (LA, LB) formed within the second insulating layer (40), External electrodes (110 / 111 to 113) formed on the second insulating layer (40), Connection electrodes (90A, 90B) provided on both the first insulating layer (30) and the second insulating layer (40) for electrically connecting the capacitors (CA to CE), the coils (LA, LB), and the external electrodes (110 / 111 to 113), Including, The connection electrodes (90A, 90B) are First vias (91A, 91B, 94A, 94B) joined to the capacitors (CA, CB, CD, CE); a rewiring layer (92, 96) in which the first vias (91A, 91B, 94A, 94B) and the ends (71A, 71B) of the coils (LA, LB) are joined; Including, When viewed from the thickness direction (Z direction) of the substrate (20), the first vias (91A, 91B, 94A, 94B) and the ends (71A, 71B) of the coils (LA, LB) are disposed at different positions from each other. Chip components (10).

[0363] [Summary of Appendix B1] When a force is applied that moves the external electrode and the second insulating layer relative to each other, the force is transmitted to the connection electrode via the external electrode, so it is desirable for the bonding strength between the connection electrode and the capacitor to be high.

[0364] [Appendix B2] the first vias (91A, 91B, 94A, 94B), the coils (LA, LB), and the rewiring layers (92, 96) are made of the same material; The first vias (91A, 91B, 94A, 94B) and the capacitors (CA, CB, CD, CE) are made of different materials. A chip part as described in Appendix B1.

[0365] [Appendix B3] the first vias (91A, 91B, 94A, 94B), the coils (LA, LB), and the redistribution layers (92, 96) contain Cu; The capacitors (CA, CB, CD, CE) contain Al. A chip part as described in Appendix B1 or B2.

[0366] [Appendix B4] The second connection electrodes (90A, 90B) include second vias (93, 96) joined to both the end portions (71A, 71B) of the coils (LA, LB) and the external electrodes (111, 112). The chip component according to any one of Supplementary Notes B1 to B3.

[0367] [Supplementary Note B5] The end portions (71A, 71B) of the coils (LA, LB) are sandwiched between the rewiring layers (92, 96) and the second vias (93, 96). The chip component according to Supplementary Note B4.

[0368] [Supplementary Note B6] The joint area between the end portions (71A, 71B) of the coils (LA, LB) and the rewiring layers (92, 96) is larger than the joint area between the capacitors (CA, CB, CD, CE) and the first vias (91A, 91B, 94A, 94B). The chip component according to any one of Supplementary Notes B1 to B5.

[0369] [Supplementary Note B7] The coils (LA, LB) include winding portions (73A, 73B) wound in a direction orthogonal to the thickness direction (Z direction) of the substrate (20). The first vias (91A, 91B, 94A, 94B) are arranged in regions (74A, 74B) inner than the winding portions (73A, 73B) when viewed from the thickness direction (Z direction) of the substrate (20). The chip component according to any one of Supplementary Notes B1 to B6.

[0370] [Supplementary Note B8] The first via includes a plurality of first vias (91A, 91B, 94A, 94B) arranged separately in a direction orthogonal to the thickness direction (Z direction) of the substrate (20). The chip component according to any one of Supplementary Notes B1 to B7.

[0371] [Supplementary Note B9] The external electrode (110) includes a plurality of external electrodes (111 to 113) arranged to be separated from each other in a first direction (X direction) orthogonal to the thickness direction (Z direction) of the substrate (20). The coil includes a plurality of coils (LA, LB) arranged to be separated from each other in the first direction (X direction) and electrically connected to each other. The capacitor includes a plurality of capacitors (CA to CE) arranged to be separated from each other in a direction orthogonal to the thickness direction (Z direction) of the substrate (20) and electrically connected to each other. The connection electrode includes a plurality of connection electrodes (90A, 90B) arranged to be separated from each other in the first direction (X direction). The chip component according to any one of Appendices B1 to B8.

[0372] [Appendix B10] The first insulating layer (30) is an inorganic insulating layer. The second insulating layer (40) is an organic insulating layer. The chip component according to any one of Appendices B1 to B9.

[0373] [Appendix B11] Further included is a third insulating layer (50) interposed between the first insulating layer (30) and the second insulating layer (40) and in contact with both the first insulating layer (30) and the second insulating layer (40). The third insulating layer (50) A third upper surface (50S) in contact with the second insulating layer (40), A third lower surface (50R) facing the side opposite to the third upper surface (50S), and includes The third upper surface (50S) is formed of a rougher surface than the third lower surface (50R). The chip component according to any one of Appendices B1 to B10.

[0374] [Appendix B12] The third insulating layer (50) is formed of a material containing polyimide. The chip component according to Appendix B11.

[0375] [Appendix B13] The third insulating layer (50) is thicker than the first insulating layer (30). The chip component described in Appendix B11 or B12.

[0376] [Appendix B14] The third insulating layer (50) is thinner than the second insulating layer (40). The chip component described in any one of Appendices B11 to B13.

[0377] [Appendix B15] The third upper surface (50S) is composed of a surface roughened by an ashing process. The chip component described in any one of Appendices B11 to B14.

[0378] [Appendix B16] The second insulating layer (40) is thicker than the first insulating layer (30). The chip component described in any one of Appendices B1 to B15.

[0379] [Appendix B17] The thickness of the coil (LA, LB) is thicker than the thickness of the first insulating layer (30). The chip component described in any one of Appendices B1 to B16.

[0380] [Appendix B18] The thickness of the coil (LA, LB) is thicker than the thickness of the rewiring layer (92, 96). The chip component described in any one of Appendices B1 to B17.

[0381] [Appendix B19] The thickness of the coil (LA, LB) is thinner than the thickness of the first via (91A, 91B, 94A, 94B). The chip component described in any one of Appendices B1 to B18.

[0382] [Appendix B20] The capacitors (CA to CE) include a first electrode (CA1 to CE1) and a second electrode (CA2 to CE2) that face each other in the thickness direction (Z direction) of the first insulating layer (30) within the first insulating layer (30). The chip component according to any one of Appendices B1 to B19.

[0383] [Appendix C1] A substrate (20), A first insulating layer (30) formed on the substrate (20), Capacitors (CA to CE) formed within the first insulating layer (30), A second insulating layer (40) formed on the first insulating layer (30), Coils (LA, LB) formed within the second insulating layer (40), External electrodes (110 / 111 to 113) formed on the second insulating layer (40) and electrically connected to at least the capacitors (CA to CE) among the capacitors (CA to CE) and the coils (LA, LB), A third insulating layer (50) interposed between the first insulating layer (30) and the second insulating layer (40) and in contact with both the first insulating layer (30) and the second insulating layer (40), Including The third insulating layer (50) is A third upper surface (50S) in contact with the second insulating layer (40), A third lower surface (50R) facing the side opposite to the third upper surface (50S), Including The third upper surface (50S) is formed of a rougher surface than the third lower surface (50R). Chip component (10).

[0384] [Summary regarding Appendix C1] For example, in a state where a chip component is mounted on a wiring board, as the temperature of the chip component and the wiring board changes, a force is applied to the second insulating layer based on the difference in the coefficient of linear expansion of the wiring board, the substrate, and the second insulating layer. As a result, the second insulating layer may peel off.

[0385] [Appendix C2] The third insulating layer (50) is made of a material containing polyimide. The chip component described in Appendix C1.

[0386] [Appendix C3] The third insulating layer (50) is thicker than the first insulating layer (30). The chip component described in Appendix C1 or C2.

[0387] [Appendix C4] The third insulating layer (50) is thinner than the second insulating layer (40). The chip component described in any one of Appendices C1 to C3.

[0388] [Appendix C5] The third upper surface (50S) is composed of a roughened surface by ashing treatment. The chip component described in any one of Appendices C1 to C4.

[0389] [Appendix C6] The first insulating layer (30) is an inorganic insulating layer, The second insulating layer (40) is an organic insulating layer. The chip component described in any one of Appendices C1 to C5.

[0390] [Appendix C7] The second insulating layer (40) is thicker than the first insulating layer (30). The chip component described in any one of Appendices C1 to C6.

[0391] [Appendix C8] The thickness of the coil (LA, LB) is thicker than the thickness of the first insulating layer (30). The chip component described in any one of Appendices C1 to C7.

[0392] [Appendix C9] The capacitors (CA to CE) include first electrodes (CA1 to CE1) and second electrodes (CA2 to CE2) that face each other in the thickness direction (Z direction) of the first insulating layer (30) within the first insulating layer (30). The chip component according to any one of Appendices C1 to C8.

[0393] [Appendix D1] A substrate (20), A first insulating layer (30) formed on the substrate (20), Capacitors (CA to CE) formed within the first insulating layer (30), A second insulating layer (40) formed on the first insulating layer (30), Coils (LA, LB) formed within the second insulating layer (40) and electrically connected to the capacitors (CA to CE), External electrodes (110 / 111 to 113) formed on the second insulating layer (40) and electrically connected to at least the capacitors (CA to CE) among the capacitors (CA to CE) and the coils (LA, LB), A sealing resin (120) that covers the second insulating layer (40) and the side surfaces of the external electrodes (110 / 111 to 113) and exposes the upper surfaces of the external electrodes (110 / 111 to 113), A chip component (10) including the above.

[0394] [Appendix D2] A substrate (20), A first insulating layer (30) formed on the substrate (20), Capacitors (CA to CE) formed within the first insulating layer (30), A second insulating layer (40) formed on the first insulating layer (30), Coils (LA, LB) formed within the second insulating layer (40) and electrically connected to the capacitors (CA to CE), External electrodes (110 / 111 to 114) electrically connected to at least the capacitors (CA to CE) among the capacitors (CA to CE) and the coils (LA, LB), A sealing resin (120) that covers the second insulating layer (40) and covers the side surfaces of the external electrodes (110 / 111 to 114), and exposes the upper surfaces of the external electrodes (110 / 111 to 114), including The sealing resin (120) includes side cover portions (121 to 124) that cover the side surfaces (40A to 40D) of the second insulating layer (40), The external electrodes (110 / 111 to 114) are provided on the side cover portions (121 to 124) outside the side surfaces (40A to 40D) of the second insulating layer (40) when viewed from the thickness direction (Z direction) of the substrate (20). Chip component (10).

[0395] [Appendix E1] Forming a first insulating layer (830) on a substrate (820), Forming capacitors (CA to CE) in the first insulating layer (830), Forming a second insulating layer (840) on the first insulating layer (830), Forming coils (LA, LB) in the second insulating layer (840), Forming at least external electrodes (110 / 111 to 114) electrically connected to the capacitors (CA to CE) among the capacitors (CA to CE) and the coils (LA, LB), Forming a sealing resin (920) that covers the second insulating layer (840) and covers the side surfaces (111A to 113A) of the external electrodes (110 / 111 to 113) and exposes the upper surfaces (111S to 113S) of the external electrodes (110 / 111 to 113), A method for manufacturing a chip component (10) including.

[0396] [Appendix E2] Forming the second insulating layer (840) includes forming recessed portions (44A, 44B) in portions different from the external electrodes (110 / 111 to 113) when viewed from the thickness direction (Z direction) of the substrate (820). By forming the sealing resin (120), the sealing resin (920) is formed so as to enter the recessed portion (844). The method for manufacturing a chip component according to Supplementary Note E1.

[0397] [Supplementary Note E3] Forming a first connection electrode (80) provided on both the first insulating layer (830) and the second insulating layer (840) and electrically connecting the capacitor (CA to CE) and the coil (LA, LB). Different from the first connection electrode (80), forming a second connection electrode (90A, 90B) provided on both the first insulating layer (830) and the second insulating layer (840) and electrically connecting the capacitor (CA to CE), the coil (LA, LB), and the external electrode (110 / 111 to 113). Including The method for manufacturing a chip component according to Supplementary Note E1 or E2.

[0398] [Supplementary Note E4] Forming the second connection electrode (90A, 90B) includes Forming first vias (91A, 91B, 94A, 94B) so as to be joined to the capacitor (CA to CE). Forming rewiring layers (92, 95) so as to be joined to the first vias (91A, 91B, 94A, 94B). Including Forming the coil (LA, LB) includes forming ends (71A, 71B) of the coil (LA, LB) at positions different from the first vias (91A, 91B, 94A, 94B) in the rewiring layers (92, 95) when viewed from the thickness direction (Z direction) of the substrate (820). The method for manufacturing a chip component according to Supplementary Note E3.

[0399] [Supplementary Note E5] Further including forming a third insulating layer (850) on the first insulating layer (820). By forming the second insulating layer (840), the second insulating layer (840) is formed on the third insulating layer (850) so as to be in contact with the third insulating layer (850). The third insulating layer (850) has a third upper surface (850S) in contact with the second insulating layer (840), and a third lower surface (850R) facing the side opposite to the third upper surface (850S), and includes By forming the third insulating layer (850), the third surface (850S) is formed to be rougher than the third lower surface (850R). The method for manufacturing a chip component according to any one of Appendices E1 to E4.

[0400] [Appendix E6] The third surface (850S) is formed to be rougher than the third lower surface (850R) by an ashing process. The method for manufacturing a chip component according to Appendix E5.

[0401] The above description is merely illustrative. Those skilled in the art can recognize that there are many more possible combinations and substitutions other than the components and methods (manufacturing processes) listed for the purpose of explaining the technology of the present disclosure. The present disclosure is intended to include all alternatives, modifications, and changes within the scope of the present disclosure, including the scope of the claims.

Description of Reference Numerals

[0402] 10... Chip component 11... First external terminal 12... Second external terminal 13... Third external terminal 14... LC circuit 20... Substrate 21... First substrate surface 22... Second substrate surface 23 to 26... First to fourth substrate side surfaces 30... First insulating layer 30S... First upper surface 30R... First lower surface 30A to 30D... First to fourth side surfaces 31…First insulating film 32…Second insulating film 33…Third insulating film 40…Second insulating layer 40S…Second upper surface 40R…Second lower surface 40A~40D…First to fourth side surfaces 41…First insulating film 41S…Upper surface 42…Second insulating film 42S…Upper surface 43…Third insulating film 43A…First placement part 43AA…First side surface 43AB…Second side surface 43AC…Third side surface 43AD…Fourth side surface 43AS…Upper surface 43B…Second placement part 43BA…First side surface 43BB…Second side surface 43BC…Third side surface 43BD…Fourth side surface 43BS…Upper surface 43C…Third placement part 43CA…First side surface 43CB…Second side surface 43CC…Third side surface 43CD…Fourth side surface 43CS…Upper surface 43D…Fourth placement part 44…Depressed part 44A…First depressed part 44B…Second depressed part 45A…First step 45B…Second step 46A,46AA…First engaging part 46B…Second engaging part 46C…Third engaging part 47…First part 48…Second part 50…Third insulating layer 50S…Third upper surface 50R…Third lower surface 61…First wiring 61A…First electrode part 61AA…Part 1 61AB…Part 2 61B…Second electrode part 61C…Third electrode part 61CA…Part 1 61CB…Part 2 62…Second wiring 62A…Part 1 62B…Part 2 63…Third wiring 63A…Part 1 63B…Part 2 64…Fourth wiring 64A…First opposing part 64B…Second opposing part 65…Fifth wiring 65A…First opposing part 65B…Second opposing part 66…Sixth wiring 67…Seventh wiring 67A…First opposing part 67B…Second opposing part 68…Eighth wiring 68A…First opposing part 68B…Second opposing part 71A, 71B…First end 72A, 72B…Second end 73A, 73B…Winding part 74A, 74B…Inner region 80…First connecting electrode 80A…First connecting part 81…First via 81A…Part 1 81B…Part 2 82…First rewiring layer 80B…Second connecting part 83…Second via 83A…Part 1 83B…Part 2 84…Second rewiring layer 85…First connecting layer 85A…First connecting end 85B…Second connecting end 85C…Middle part 80C…Third connecting part 86…Third via 87…Third rewiring layer 88…Second connection layer 90A, 90B…Second connection electrodes 91A, 91B…First vias 91AA…First part 91AB…Second part 92…Rewiring layer 93…Second via 94A, 94B…First vias 94BA…First part 94BB…Second part 95…Rewiring layer 96…Second via 97…Lead wiring 100A, 100B…Third connection electrodes 101…First via 101A…First part 101B…Second part 102…Rewiring layer 103…Connection layer 104…Second via 105…First via 106…Rewiring layer 107…Connection layer 108…Second via 110…External electrode 111…First external electrode 111A…Side surface 111AA…First side surface 111AB…Second side surface 111AC…Third side surface 111AD…Fourth side surface 111S…Top surface 112…Second external electrode 112A…Side surface 112AA…First side surface 112AB…Second side surface 112AC…Third side surface 112AD…Fourth side surface 112S…Top surface 113…Third external electrode 113A…Side surface 113AA…First side surface 113AB…Second side surface 113AC…Third side surface 113AD…Fourth side surface 113S… above 114… the 4th external electrode 115… bonding layer 120… encapsulating resin 120S… above 121… the 1st side cover part 122… the 2nd side cover part 123… the 3rd side cover part 124… the 4th side cover part 131~134… the 1st~4th intermediate wirings 135~138… the 1st~4th vias 151~154… the 1st~4th external electrodes 820… substrate 821… the 1st substrate surface 822… the 2nd substrate surface 823… groove 830… the 1st insulating layer 831~833… the 1st~3rd insulating films 840… the 2nd insulating layer 841… the 1st insulating film 841A… through hole 842… the 2nd insulating film 842A… through hole 843… the 3rd insulating film 843A… through hole 844… recessed part 850… the 3rd insulating layer 850S… the 3rd upper surface 850R… the 3rd lower surface 920… encapsulating resin 930… metal layer 940… resist 950… metal layer 960… resist 970… metal layer 980… resist 990… dicing tape LA… the 1st coil LB… the 2nd coil CA… the 1st capacitor CB… the 2nd capacitor CC… the 3rd capacitor CD… the 4th capacitor CE… the 5th capacitor CA1 to CE1... the first electrode CA2 to CE2... the second electrode N... node WA1... the width dimension of the first part in the first electrode portion of the first wiring WA2... the width dimension of the second part in the first electrode portion of the first wiring WB... the width dimension of the second electrode portion of the first wiring WC1... the width dimension of the first part in the third electrode portion of the first wiring WC2... the width dimension of the second part in the third electrode portion of the first wiring WD... the width dimension of the first part of the second wiring WE... the width dimension of the second part of the second wiring WF... the width dimension of the first part of the third wiring WG... the width dimension of the second part of the third wiring

Claims

1. A substrate, a first insulating layer formed on the substrate, a capacitor formed within the first insulating layer, a second insulating layer formed on the first insulating layer, a coil formed within the second insulating layer and electrically connected to the capacitor, an external electrode electrically connected to at least the capacitor among the capacitor and the coil, a sealing resin that covers the second insulating layer and the side surface of the external electrode and exposes the upper surface of the external electrode, A chip component comprising the above.

2. The external electrode is provided on the second insulating layer. The chip component according to Claim 1.

3. The second insulating layer includes a recess formed in a portion different from the external electrode when viewed from the thickness direction of the substrate, The sealing resin enters the recess. The chip component according to Claim 1.

4. The second insulating layer, a first insulating film disposed closer to the substrate in the thickness direction of the substrate, a second insulating film laminated on the first insulating film and provided with the coil, a third insulating film laminated on the second insulating film, includes, The recess penetrates the third insulating film in the thickness direction of the substrate, The external electrode is provided on the third insulating film. The chip component according to Claim 3.

5. The external electrode includes a plurality of external electrodes arranged at intervals in a first direction orthogonal to the thickness direction of the substrate, The recess is provided between the external electrodes adjacent to each other in the first direction among the plurality of external electrodes. The chip component according to Claim 3.

6. The sealing resin covers the entire side surface of the external electrode. The chip component according to Claim 1.

7. The sealing resin covers the side surface of the second insulating layer. The chip component according to Claim 1.

8. The third insulating film includes an engaging portion that extends into the recess and engages with the sealing resin when viewed from the thickness direction of the substrate. The chip component according to Claim 4.

9. The engaging portion, a first portion protruding from the side surface of the third insulating film constituting the recess, a second portion continuously provided from the first portion and extending in a direction intersecting the first portion when viewed from the thickness direction of the substrate, includes. The chip component according to Claim 8.

10. The sealing resin includes a side surface covering portion that covers the side surface of the second insulating layer. The external electrode is provided on the side cover portion outside the side surface of the second insulating layer when viewed from the thickness direction of the substrate. The chip component according to claim 1.

11. A first connection electrode provided on both the first insulating layer and the second insulating layer, electrically connecting the capacitor and the coil; A second connection electrode provided on both the first insulating layer and the second insulating layer, electrically connecting the capacitor, the coil, and the external electrode; including The chip component according to claim 1.

12. The second connection electrode a first via joined to the capacitor; a rewiring layer where the first via and the end of the coil are joined; including When viewed from the thickness direction of the substrate, the first via and the end of the coil are arranged at different positions from each other. The chip component according to claim 11.

13. The first via, the coil, and the rewiring layer are made of the same material as each other, The first via and the capacitor are made of different materials from each other. The chip component according to claim 12.

14. The first via, the coil, and the rewiring layer contain Cu, The capacitor contains Al. The chip component according to claim 12.

15. The second connection electrode includes a second via joined to both the end of the coil and the external electrode. The chip component according to claim 12.

16. The joining area between the end of the coil and the rewiring layer is larger than the joining area between the capacitor and the first via. The chip component according to claim 12.

17. The coil includes a winding portion wound in a direction orthogonal to the thickness direction of the substrate, The first via is arranged in a region inner than the winding portion when viewed from the thickness direction of the substrate. The chip component according to claim 12.

18. The first insulating layer is an inorganic insulating layer, The second insulating layer is an organic insulating layer. The chip component according to claim 1.

19. Further including a third insulating layer interposed between the first insulating layer and the second insulating layer and in contact with both the first insulating layer and the second insulating layer, The third insulating layer a third upper surface in contact with the second insulating layer; a third lower surface facing the opposite side of the third upper surface; including The third upper surface is formed of a rougher surface than the third lower surface. The chip component according to any one of claims 1 to 18.

20. The third insulating layer is composed of a material containing polyimide. The chip component according to claim 19.

Images