Laminated ceramic electronic component

Abstract

To provide a laminated ceramic electronic component having high thermal shock resistance.SOLUTION: A laminated ceramic electronic component is provided, having an element main body in which dielectric layers and electrode layers are laminated. The dielectric layer contains a main component represented by a general formula ABO3. The dielectric layer includes with respect to 100 moles of a main component: Mn oxide of more than 0 and 0.050 moles or less in terms of MnO, Mg oxide of 1.00 moles or more and 2.50 moles or less in terms of MgO, and R oxide (R is at least one selected from Y, Dy, Ho, Yb, Lu, Gd, and Tb) of 0.50 moles or more and 1.50 moles or less in terms of R2O3, and Zr oxide of 0.05 moles or more and 0.45 moles or less in terms of ZrO2, and further contains Si. In the dielectric layer, the Zr / Mn ratio is 5.0 or more and 12.5 or less based on atomic number. The Zr / Si ratio is 0.40 or more and 0.80 or less based on atomic number.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a multilayer ceramic electronic component.

Background Art

[0002] Patent Document 1 describes a multilayer ceramic electronic component having a configuration in which a segregation phase containing Mg is formed in at least a part of a portion where no electrode exists. By having such a configuration, even when the dielectric layer is made thin, a multilayer ceramic electronic component having a high relative permittivity, low dielectric loss, and high reliability can be provided.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a multilayer ceramic electronic component having high thermal shock resistance.

Means for Solving the Problems

[0005] In order to achieve the above object, a multilayer ceramic electronic component according to the present invention is a multilayer ceramic electronic component having an element body in which a dielectric layer and an electrode layer are laminated, wherein the dielectric layer contains a main component represented by the general formula ABO3 (A is Ba alone, or at least one selected from Ba, Ca, and Sr, and B is Ti alone, or at least one selected from Ti, Zr, and Hf), The dielectric layer contains, based on 100 moles of the main component, more than 0 moles and less than 0.050 moles of Mn oxide in terms of MnO, 1.00 mole or more and 2.50 moles or less of Mg oxide in terms of MgO, 0.50 mole or more and 1.50 moles or less of R oxide (R is at least one selected from Y, Dy, Ho, Yb, Lu, Gd, and Tb) in terms of R2O3, 0.05 mole or more and 0.45 mole or less of Zr oxide in terms of ZrO2, and further contains Si. In the dielectric layer, the Zr / Mn ratio is 5.0 or more and 12.5 or less on an atomic number basis, and the Zr / Si ratio is 0.40 or more and 0.80 or less on an atomic number basis.

[0006] The dielectric layer may contain, based on 100 moles of the main component, 0.05 mole or more and 0.25 mole or less of V oxide in terms of V2O5.

[0007] Segregation containing Si may be formed at the interface between the electrode layer and the dielectric layer and in the region composed of the dielectric layer. The coverage rate of the electrode layer may be 80% or more and 100% or less.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Embodiments for Carrying Out the Invention

[0009] Hereinafter, the present invention will be described based on the embodiments shown in the drawings.

[0010] Multilayer ceramic capacitor 1 As shown in FIG. 1, a multilayer ceramic capacitor 1, which is a type of multilayer ceramic electronic component according to an embodiment of the present invention, has a capacitor element body 10 in which a dielectric layer 2 and an internal electrode layer 3 are alternately laminated. The internal electrode layers 3 are laminated such that their respective end faces are alternately exposed on the surfaces of the opposing ends of the capacitor element body 10. A pair of external electrodes 4 are formed at both ends of the capacitor element body 10 and are connected to the exposed end faces of the alternately arranged internal electrode layers 3 to form a capacitor circuit.

[0011] The shape of the capacitor element body 10 is not particularly limited, but as shown in FIG. 1, it is usually in the shape of a rectangular parallelepiped. Also, its dimensions are not particularly limited, and appropriate dimensions may be selected according to the application.

[0012] Dielectric layer 2 The dielectric layer 2 contains a main component represented by the general formula ABO3 (where A is Ba alone or at least one selected from Ba, Ca, and Sr, and B is Ti alone or at least one selected from Ti, Zr, and Hf), and further contains an oxide of Mn, an oxide of Mg, an oxide of R, and an oxide of Zr. Further, the dielectric layer 2 contains Si. Further, the dielectric layer 2 may contain an oxide of V.

[0013] In this embodiment, the oxides include complex oxides. For example, the oxide of Mn includes a complex oxide of Mn and other elements. The oxide of Mn, the oxide of Mg, the oxide of R, the oxide of Zr, and the oxide of V may all be simple oxides (oxides of a single metal element).

[0014] The dielectric layer 2 preferably contains barium titanate as a main component. Barium titanate is a compound represented by the composition formula Ba m TiO 2+m where m satisfies 0.995 ≦ m ≦ 1.010. Hereinafter, the case where the dielectric layer 2 contains barium titanate as a main component will be described.

[0015] The content of the manganese oxide is more than 0 mol and less than 0.050 mol in terms of MnO with respect to 100 mol of the main components. It may be 0.010 mol or more and 0.045 mol or less. When the dielectric layer 2 does not contain the manganese oxide, segregation containing Si, which will be described later, is less likely to occur, and the coverage rate, which will be described later, is likely to decrease. Then, the resistance of the multilayer ceramic capacitor 1 to thermal shock (thermal shock resistance) decreases. When the content of the manganese oxide in the dielectric layer 2 is too high, segregation containing Si, which will be described later, is less likely to occur. Then, the resistance of the multilayer ceramic capacitor 1 to thermal shock (thermal shock resistance) decreases.

[0016] The content of the magnesium oxide is 1.00 mol or more and 2.50 mol or less in terms of MgO with respect to 100 mol of the main components. It may be 1.50 mol or more and 2.00 mol or less. Whether the content of the magnesium oxide in the dielectric layer 2 is too low or too high, the resistance of the multilayer ceramic capacitor 1 to thermal shock (thermal shock resistance) decreases. In particular, when the content of the magnesium oxide is less than 1.50 mol, the sintering stability of the dielectric layer 2 is likely to deteriorate. When the content of the magnesium oxide is more than 2.00 mol, the relative permittivity of the dielectric layer 2 is likely to decrease.

[0017] The content of the oxide of R is 0.50 mol or more and 1.50 mol or less in terms of R2O3 with respect to 100 mol of the main components. It may be 0.60 mol or more and 1.20 mol or less. Whether the content of the oxide of R is too low or too high, the resistance of the multilayer ceramic capacitor 1 to thermal shock (thermal shock resistance) decreases. When the content of the oxide of R is less than 0.60 mol, the reliability of the multilayer ceramic capacitor 1 is likely to decrease. When the content of the oxide of R is more than 1.20 mol, the insulation resistance of the dielectric layer 2 is likely to decrease.

[0018] R is at least one selected from Y, Gd, Tb, Dy, Ho, Yb, and Lu. R is preferably at least one selected from Y, Dy, and Ho, and particularly preferably Y or Dy.

[0019] The content of the oxide of Zr is 0.05 mol or more and 0.45 mol or less in terms of ZrO2 based on 100 mol of the main components. It may be 0.20 mol or more and 0.40 mol or less. Whether the content of the oxide of Zr is too small or too large, the resistance of the multilayer ceramic capacitor 1 to thermal shock (thermal shock resistance) decreases. Furthermore, the smaller the content of the oxide of Zr, the less likely it is for segregation containing Si, which will be described later, to occur.

[0020] There is no particular limitation on the content of Si. For example, it may be 0.10 mol or more and 0.90 mol or less in terms of SiO2 based on 100 mol of the main components, or it may be 0.30 mol or more and 0.75 mol or less. Also, there is no particular limitation on how the dielectric layer 2 contains Si. For example, it may be contained as an oxide of Si.

[0021] There is no particular limitation on the content of the oxide of V. For example, it may contain 0.03 mol or more and 0.30 mol or less in terms of V2O5 based on 100 mol of the main components, or it may contain 0.05 mol or more and 0.25 mol or less. In particular, by containing 0.05 mol or more and 0.25 mol or less of the oxide of V, the internal stress generated during firing is reduced, so that the resistance of the multilayer ceramic capacitor 1 to thermal shock (thermal shock resistance) is more likely to be further improved.

[0022] Depending on the desired characteristics, the dielectric layer 2 may further contain other components, that is, the above-mentioned main components, the oxides of Mn, Mg, R, Zr, V, and components other than Si. There is no particular limitation on the content of the other components, and it may be within a range that does not significantly affect the performance of the multilayer ceramic capacitor 1. For example, it may be 5 wt% or less in total with respect to the dielectric layer 2.

[0023] It is preferable that the dielectric layer 2 does not substantially contain Al. Specifically, it is preferable that the content of Al is 0.1 mol or less (including 0) in terms of Al2O3. By the dielectric layer 2 not substantially containing Al, the thermal shock resistance is likely to be improved.

[0024] In the dielectric layer 2, the Zr / Mn ratio is 5.0 or more and 12.5 or less on an atomic number basis. When the Zr / Mn ratio is outside the above range, the resistance of the multilayer ceramic capacitor 1 to thermal shock (thermal shock resistance) decreases. Further, when the Zr / Mn ratio is too small, segregation containing Si described later is less likely to occur in the dielectric layer 2.

[0025] In the dielectric layer 2, the Zr / Si ratio is 0.40 or more and 0.80 or less on an atomic number basis. When the Zr / Si ratio is outside the above range, the resistance of the multilayer ceramic capacitor 1 to thermal shock (thermal shock resistance) decreases. Further, when the Zr / Si ratio is too large, segregation containing Si described later is less likely to occur in the dielectric layer 2.

[0026] There is no particular limitation on the thickness of the dielectric layer 2. In this embodiment, when the thickness (layer thickness) of the dielectric layer 2 is t1 [μm], 0.30 ≤ t1 ≤ 2.0 may be satisfied. It is preferably 0.35 ≤ t1 ≤ 1.8, and more preferably 0.40 ≤ t1 ≤ 1.5. When t1 is within the above range, it becomes less likely that the multilayer ceramic capacitor 1 has a breakdown voltage defect or a short circuit defect, and the capacitance of the multilayer ceramic capacitor 1 tends to be high.

[0027] There is no particular limitation on the number of layers of the dielectric layer 2. In this embodiment, it is preferably 20 or more, more preferably 50 or more, and particularly preferably 100 or more.

[0028] When the content of each component in the dielectric layer 2 is within the above range, the thermal shock resistance of the multilayer ceramic capacitor 1 is improved because the difference in the linear expansion coefficient between the dielectric layer 2 and the internal electrode layer 3 becomes small, and particularly because the change in the linear expansion coefficient of the dielectric layer 2 within the temperature range from -55°C to 150°C becomes small.

[0029] Internal electrode layer 3 The conductive material contained in the internal electrode layer 3 is not particularly limited. Since the constituent material of the dielectric layer 2 has reduction resistance, a relatively inexpensive base metal material can be used as the conductive material. The base metal material used as the conductive material is preferably Ni or a Ni alloy. The Ni alloy is preferably an alloy of Ni and one or more elements selected from Mn, Cr, Co, Cu, Sn, and Al. The Ni content in the Ni alloy is preferably 95% by weight or more. In addition, various trace components such as P may be contained in the base metal material in an amount of about 0.1% by weight or less each.

[0030] There is no particular limitation on the thickness of the internal electrode layer 3. In this embodiment, when the thickness (layer thickness) of the internal electrode layer 3 is t2 [μm], 0.30 ≦ t2 ≦ 1.0 may be satisfied. It is preferably 0.30 ≦ t2 ≦ 0.80, and more preferably 0.30 ≦ t2 ≦ 0.60. When t2 is within the above range, it becomes easier to reduce the size of the capacitor element body 10, particularly the height dimension. Furthermore, the coverage rate described later is likely to improve, and the capacitance of the multilayer ceramic capacitor 1 is likely to improve.

[0031] When the internal electrode layer 3 is enlarged, as shown in FIG. 2, there may be a portion where no internal electrode is actually formed (electrode discontinuous portion 3a) in the portion where the internal electrode is to be formed. This electrode discontinuous portion 3a is a region where the distance between adjacent conductive material particles has widened and the conductive material has disappeared as a result of the sphericalization of the conductive material particles (mainly Ni particles when Ni or a Ni alloy is used as the conductive material) due to grain growth during firing.

[0032] Note that FIG. 2 is a schematic enlarged cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1. In addition, there is no particular limitation on the size of the observation range for confirming the coverage rate, the presence or absence of Si segregation, etc., which will be described later, and it may be set to a size sufficient to confirm the coverage rate, the presence or absence of Si segregation, etc. For example, 2000 μm 2 may be sufficient. The image obtained by observing the observation range may be a single image with a sufficiently large area, or a plurality of images with a total area that is sufficiently large.

[0033] In the cross section shown in FIG. 2, due to the electrode discontinuous portion 3a, the internal electrode layer 3 appears to be discontinuous. However, the electrode discontinuous portions 3a are scattered on the main surface of the internal electrode layer 3. Therefore, even though the internal electrode layer 3 is discontinuous in the cross section shown in FIG. 2, it is continuous in other cross sections, and the conductivity of the internal electrode layer 3 is ensured.

[0034] In the cross section shown in FIG. 2, that is, in the cross section parallel to the X-Y plane of FIG. 2, the sum of the line length of the region where the internal electrode layer 3 is actually formed and the length of the electrode discontinuous portion 3a is the line length of the region where the internal electrode layer 3 should be formed. In the present embodiment, the ratio of the line length of the region where the internal electrode layer 3 is actually formed to the line length of the region where the internal electrode layer 3 should be formed is defined as the coverage rate of the electrode layer. It can be said that the coverage rate of the electrode layer is the ratio of the internal electrode layer 3 covering the dielectric layer 2. The coverage rate also varies depending on the thickness of the dielectric layer 2 and the thickness of the internal electrode layer 3. When the coverage rate is 100%, there is no electrode discontinuous portion 3a and each internal electrode layer exists as a single line segment.

[0035] In the present embodiment, the coverage rate may be 80% or more and 100% or less. It is preferably 85% or more and 100% or less. More preferably, it is 90% or more and 100% or less. Particularly preferably, it is 95% or more and 100% or less. The higher the coverage rate, the fewer the electrode discontinuous portions 3a. Therefore, in particular, in the manufacturing process of the multilayer ceramic capacitor 1, it becomes difficult for water or plating solution to penetrate. As a result, the resistance of the multilayer ceramic capacitor 1 to thermal shock (thermal shock resistance) is likely to be improved. When the coverage rate is 100%, there is no electrode discontinuous portion 3a.

[0036] Also, the higher the coverage rate and the fewer the electrode discontinuous portions 3a, the larger the electrode area of the multilayer ceramic capacitor 1 and the larger the capacitance of the multilayer ceramic capacitor 1. From this point as well, a high coverage rate is preferable.

[0037] Segregation phase 5 The segregation phase 5 is a phase having a composition different from that of the dielectric layer 2 and the internal electrode layer 3 mainly composed of barium titanate. The multilayer ceramic capacitor 1 according to the present embodiment may not contain the segregation phase 5, but preferably contains the segregation phase 5 containing Si as shown in FIG. 2.

[0038] FIG. 2 is a schematic enlarged cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1.

[0039] The segregation phase 5 containing Si may include the interface between the dielectric layer 2 and the internal electrode layer 3, or may cover the entire outer periphery of the dielectric layer 2. The segregation phase 5 containing Si may contain elemental components other than Si. Further, the multilayer ceramic capacitor 1 according to the present embodiment may contain a segregation phase 5 not containing Si. There is no particular limitation on the content of Si in the segregation phase 5 containing Si. For example, a segregation phase 5 having a Si content of 10 at% or more, which is higher than that of the dielectric layer 2, may be used as the segregation phase 5 containing Si.

[0040] When the multilayer ceramic capacitor 1 according to the present embodiment contains a segregation phase 5 containing Si (hereinafter sometimes simply referred to as Si segregation), it is preferable that Si segregation is formed in the region including the interface between the internal electrode layer 3 and the dielectric layer 2 and the dielectric layer 2. That is, it is preferable that Si segregation is formed at the dielectric layer 2 and / or the interface between the internal electrode layer 3 and the dielectric layer 2.

[0041] On the other hand, Si segregation may or may not be formed in the electrode discontinuous portion 3a. Further, when the coverage rate is 90% or more and 100% or less, it is difficult for Si segregation to be formed in the electrode discontinuous portion 3a.

[0042] Three internal electrode layers 3 are shown in FIG. 2. Assuming that all the segregation phases 5 shown in FIG. 2 are Si segregation, there are two electrode discontinuous portions 3a in the third internal electrode layer 3 from the top, and Si segregation is formed in a part of each electrode discontinuous portion 3a.

[0043] In the dielectric layer 2 between the second internal electrode layer 3 from the top and the third internal electrode layer 3 from the top in FIG. 2, there is an Si segregation where the entire periphery is covered by the dielectric layer 2. Such Si segregation is the Si segregation in the dielectric layer 2.

[0044] For other Si segregations in FIG. 2, a part of them overlaps with the interface between the dielectric layer 2 and the internal electrode layer 3. Such Si segregation is the Si segregation at the interface between the dielectric layer and the internal electrode layer.

[0045] The multilayer ceramic capacitor 1 in which Si segregation is formed in the region consisting of the interface between the internal electrode layer 3 and the dielectric layer 2 and the dielectric layer 2, and the coverage rate is 90% or more and 100% or less, has particularly improved thermal shock resistance. Further, it is more preferable that Si segregation is formed in both the dielectric layer 2 and the above interface. This is considered to be because the internal stress generated at the interface is more easily relaxed, and structural defects are less likely to occur during the thermal shock test.

[0046] External electrode 4 There is no particular limitation on the conductive material contained in the external electrode 4. For example, well-known Ni, Cu, Ni alloy, or Cu alloy can be used as the conductive material contained in the external electrode 4. There is no particular limitation on the thickness of the external electrode 4, and it may be appropriately determined according to the application and the like. The thickness of the external electrode 4 is preferably about 5 to 50 μm usually.

[0047] Method for manufacturing multilayer ceramic capacitor 1 The multilayer ceramic capacitor 1 of the present embodiment is manufactured by the same method as the conventional multilayer ceramic capacitor. Specifically, first, a green chip is produced by a method using paste, for example, a normal method such as a printing method or a sheet method. Next, the green chip is fired. Then, it is manufactured by printing or transferring an external electrode to the fired green chip and then firing the external electrode. Hereinafter, the manufacturing method will be specifically described.

[0048] First, prepare a dielectric raw material for forming the dielectric layer 2. The prepared dielectric raw material is made into a paint to prepare a paste for the dielectric layer. The paste for the dielectric layer may be an organic-based paint or an aqueous-based paint.

[0049] Prepare a raw material of barium titanate, a raw material of an oxide of Mn, a raw material of an oxide of Mg, a raw material of an oxide of R, a raw material of an oxide of Zr, and a raw material of an oxide of Si as the dielectric raw material. When including an oxide of V in the dielectric layer 2, also prepare a raw material of the oxide of V. As these raw materials, for example, simple oxides of each element, composite oxides of each element, or mixtures thereof can be used. Also, various compounds that become the above simple oxides or composite oxides by firing, such as carbonates, oxalates, nitrates, hydroxides, organometallic compounds, etc. of each element, can be appropriately selected and mixed for use.

[0050] Note that as the raw material of barium titanate, those produced by various methods such as so-called solid-phase methods and various liquid-phase methods (for example, oxalate method, hydrothermal synthesis method, alkoxide method, sol-gel method, etc.) can be used.

[0051] In this embodiment, the BET specific surface area of the raw material of barium titanate is preferably 6.0 m 2 / g or more in order to meet the requirement of thinning the dielectric layer 2.

[0052] When thinning the dielectric layer 2, in order to ensure sufficient reliability, it is necessary to arrange a plurality of dielectric particles between the layers of the internal electrode layer 3. In order to arrange a plurality of dielectric particles between the layers of the internal electrode layer 3, it is required to reduce the average particle size of the dielectric particles. In order to reduce the average particle size of the dielectric particles, it is conceivable to reduce the average particle size of the raw material of barium titanate. The average particle size of the raw material of barium titanate is inversely proportional to the specific surface area of the raw material of barium titanate. Therefore, it is preferable that the BET specific surface area of the raw material of barium titanate be 6.0 m 2 / g or more.

[0053] When the dielectric layer 2 contains components other than the above components, raw materials for the components are prepared. As the raw materials for the components, similar to the above components, simple oxides of the components, composite oxides of the components, or mixtures thereof can be used. In addition, various compounds that become the above simple oxides or composite oxides by firing can also be used.

[0054] The content of each compound in the dielectric raw material may be determined so that the composition of the dielectric layer 2 described above is obtained after firing. In the state before being made into a paint, the average particle size of the dielectric raw material is usually about 0.05 to 1 μm.

[0055] When the paste for the dielectric layer is an organic-based paint, the dielectric raw material and the organic vehicle are kneaded to produce an organic-based paint. The organic vehicle is a binder dissolved in an organic solvent. There is no particular limitation on the type of binder. For example, it may be appropriately selected from various binders commonly used in the art, such as ethyl cellulose and polyvinyl butyral. There is no particular limitation on the type of organic solvent. For example, it may be appropriately selected from various organic solvents such as terpineol, butyl carbitol, acetone, and toluene according to the method for manufacturing the green chip.

[0056] When the paste for the dielectric layer is an aqueous paint, the dielectric raw material and the aqueous vehicle are kneaded to produce an aqueous paint. The aqueous vehicle is a water-soluble binder, a dispersant, etc. dissolved in water. There is no particular limitation on the type of water-soluble binder. For example, it may be appropriately selected from various water-soluble binders commonly used in the art, such as polyvinyl alcohol, cellulose, and water-soluble acrylic resin.

[0057] Hereinafter, the case where the paste for the dielectric layer is an organic-based paint will be described.

[0058] The paste for the internal electrode layer is prepared by kneading the above-described various conductive materials, or various oxides, organometallic compounds, resinates, etc. that become the above-described various conductive materials after firing, and the above-described organic vehicle. Further, the paste for the internal electrode layer may contain a co-material. There is no particular limitation on the type of the co-material. It is preferable that the composition of the co-material is the same as that of the main component.

[0059] The paste for the external electrode may be prepared in the same manner as the method for preparing the paste for the internal electrode layer described above.

[0060] There is no particular limitation on the content of the organic vehicle in each of the above-described pastes. It may be the normal content in this technical field. For example, the content of the binder in each paste may be about 1 to 5% by weight, and the content of the solvent may be about 10 to 50% by weight. Further, each paste may contain additives selected from various dispersants, plasticizers, dielectrics, insulators, etc. as necessary. The total content of these additives in each paste is preferably 10% by weight or less.

[0061] When the printing method is used for producing the green chip, the paste for the dielectric layer and the paste for the internal electrode layer are printed and laminated on a substrate such as PET, cut into a predetermined shape, and then peeled off from the substrate to obtain a green chip.

[0062] When the sheet method is used for producing the green chip, first, a green sheet is formed using the paste for the dielectric layer, and the paste for the internal electrode layer is printed on the green sheet. Next, the green sheets printed with the paste for the internal electrode layer are laminated and cut into a predetermined shape to obtain a green chip.

[0063] Before firing described later, a debinding treatment is performed on the green chip. There is no particular limitation on the debinding conditions. The heating rate is preferably 5 to 300 °C / hour, the holding temperature is preferably 180 to 400 °C, and the temperature holding time is preferably 0.5 to 24 hours. Further, the atmosphere during debinding is preferably air or a reducing atmosphere.

[0064] The atmosphere during the firing of the green chip is preferably a reducing atmosphere. As the atmosphere gas for creating a reducing atmosphere, for example, a mixed gas of N2 and H2 can be humidified and used. The oxygen partial pressure during firing can be appropriately determined according to the type of conductive material in the paste for the internal electrode layer. When using a base metal such as Ni or Ni alloy as the conductive material in the paste for the internal electrode layer, the oxygen partial pressure is preferably 10 -11 ~10 -8 MPa, and the heating rate is preferably 600 to 8000 °C / hour, more preferably 800 to 8000 °C / hour.

[0065] The other conditions are preferably as follows. The holding temperature during firing is preferably 1300 °C or lower, more preferably 1000 to 1300 °C. The temperature holding time during firing is preferably 0.2 to 8 hours, more preferably 0.2 to 3 hours. In particular, when the holding temperature during firing is within the above range, it becomes easier to sufficiently promote the densification of the dielectric layer 2 while preventing electrode disconnection due to abnormal sintering of the internal electrode layer 3 and deterioration of dielectric characteristics due to excessive grain growth of dielectric particles. The cooling rate after firing is preferably 50 to 8000 °C / hour.

[0066] After firing in a reducing atmosphere, it is preferable to anneal the capacitor element body 10. Annealing is a process for re-oxidizing the dielectric layer 2. By annealing, the high-temperature load life of the multilayer ceramic capacitor 1 can be significantly extended.

[0067] The oxygen partial pressure in the atmosphere during annealing is preferably 10 -9 ~10 -5 MPa. When the oxygen partial pressure is within the above range, it becomes easier to sufficiently promote the re-oxidation of the dielectric layer 2 while preventing oxidation of the internal electrode layer 3.

[0068] The holding temperature during annealing is preferably 1100°C or lower, more preferably 900 - 1100°C. When the holding temperature during annealing is within the above range, it becomes easier to sufficiently progress the re-oxidation of the dielectric layer 2 while preventing the oxidation of the internal electrode layer 3. As a result, it becomes easier to optimize the insulation resistance (IR), high-temperature load life, and capacitance of the multilayer ceramic capacitor 1.

[0069] Note that usually, annealing is composed of a temperature rising process, a temperature holding process, and a temperature falling process, but annealing may be composed of only the temperature rising process and the temperature falling process. That is, the temperature holding time may be 0. In this case, the holding temperature is synonymous with the maximum temperature.

[0070] The conditions other than the holding temperature in annealing are shown below. The temperature holding time in annealing is preferably 0 - 30 hours, more preferably 1 - 25 hours. The temperature falling rate in annealing is preferably 50 - 500°C / hour, more preferably 100 - 300°C / hour. Also, as the annealing atmosphere gas, preferably humidified N2 gas or the like is used.

[0071] There is no particular limitation on the method of humidifying N2 gas, mixed gas, etc. in the above-mentioned debinding treatment, firing, and annealing. For example, it may be humidified using a wetter or the like. When using a wetter or the like, the water temperature is preferably about 5 - 75°C.

[0072] The debinding treatment, firing, and annealing may be performed continuously or independently.

[0073] The end faces of the capacitor element body 10 obtained as described above are polished, and an external electrode paste is applied and fired to form the external electrodes 4. There is no particular limitation on the method of end face polishing. For example, methods such as barrel polishing and sandblasting can be mentioned. Furthermore, if necessary, a coating layer may be formed on the surface of the external electrodes 4 by plating or the like.

[0074] The multilayer ceramic capacitor 1 of the present embodiment manufactured in this way is mounted on a printed circuit board or the like by soldering or the like and used in various electronic devices and the like. In particular, it is suitably used for in-vehicle electronic devices and the like that are required to be small, have high performance, high reliability, and high thermal shock resistance.

[0075] As described above, the embodiments of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention.

[0076] In the above-described embodiment, the multilayer ceramic capacitor 1 is exemplified as the multilayer ceramic electronic component according to the present invention. However, the multilayer ceramic electronic component according to the present invention is not limited to the multilayer ceramic capacitor 1, and any electronic component having the above configuration may be used.

Example

[0077] Hereinafter, the present invention will be described based on more detailed examples, but the present invention is not limited to these examples.

[0078] (Experimental Example 1) As the raw material of the main component, barium titanate powder (BaTiO3 powder) having a BET specific surface area of 8.0 m 2 / g was prepared, and as the raw materials of the sub-components, MnO powder, MgO powder, Dy2O3 powder, ZrO2 powder, V2O5 powder, and SiO2 powder were prepared respectively. In this example, R is Dy.

[0079] Next, the BaTiO3 powder prepared above and the raw materials of the sub-components were wet pulverized in a ball mill for 15 hours and dried to obtain a dielectric raw material. The addition amount of each sub-component was adjusted so that the content of the sub-component in the fired dielectric layer would be the amount shown in Table 1 with respect to 100 moles of BaTiO3 as the main component.

[0080] Next, 100 parts by weight of the obtained dielectric raw material, 10 parts by weight of polyvinyl butyral resin, 5 parts by weight of dioctyl phthalate (DOP) as a plasticizer, and 100 parts by weight of alcohol as a solvent were mixed in a ball mill to form a paste, and a paste for a dielectric layer was obtained.

[0081] Separately from the paste for the dielectric layer, 44.6 parts by weight of Ni powder, 52 parts by weight of terpineol, 3 parts by weight of ethyl cellulose, and 0.4 parts by weight of benzotriazole were kneaded with a three-roll mill to form a slurry, and a paste for an internal electrode layer was prepared.

[0082] Then, using the paste for the dielectric layer prepared by the above method, a green sheet was formed on a PET film. Next, an electrode layer that would finally become the internal electrode layer was printed in a predetermined pattern using the paste for the internal electrode layer on the green sheet. After printing the electrode layer, the green sheet was peeled off from the PET film to produce a green sheet having the electrode layer. Next, a plurality of green sheets having the electrode layer were laminated and pressure-bonded to produce a green laminate. Further, the green laminate was cut into a predetermined size to produce a green chip.

[0083] Next, the obtained green chip was subjected to a debinding treatment, firing, and annealing under the following conditions to obtain a capacitor element body as a sintered body.

[0084] The debinding treatment conditions were a heating rate of 25 °C / hour, a holding temperature of 260 °C, a temperature holding time of 8 hours, and an atmosphere of air.

[0085] The firing conditions were a heating rate of 800 °C / hour, a holding temperature of 1100 - 1300 °C, a temperature holding time of 1 hour, a cooling rate of 800 °C / hour, and an atmosphere gas of a humidified N2 + H2 mixed gas (oxygen partial pressure: 10 -10 MPa).

[0086] The annealing conditions were as follows: heating rate: 200 °C / hour, holding temperature: 1000 °C, holding time: 2 hours, cooling rate: 200 °C / hour, and atmosphere gas: humidified N2 gas (oxygen partial pressure: 10 -7 MPa).

[0087] A wetter was used for humidifying the atmosphere gas during firing and annealing.

[0088] Next, after polishing the end face of the obtained capacitor element body by sandblasting, Cu was applied as an external electrode to obtain a sample of the multilayer ceramic capacitor shown in FIG. 1. The size of the obtained capacitor sample was 3.2 mm × 1.6 mm × 0.6 mm, and the thickness t1 of the dielectric layer and the thickness t2 of the internal electrode layer were both 0.50 μm. Also, the number of dielectric layers sandwiched between the internal electrode layers was 10.

[0089] Regarding the obtained capacitor sample, observation of the segregation phase, coverage ratio, relative permittivity, dielectric loss (tan δ), and measurement of the high-temperature load life were carried out by the methods shown below, respectively.

[0090] Observation of segregation phase First, the capacitor sample was cut along a plane perpendicular to the dielectric layer. Next, SEM observation and STEM-EDX analysis were performed on this cut surface, and from the results of elemental mapping of the Si element, the presence or absence of Si segregation was confirmed at each of the dielectric layer, the interface between the dielectric layer and the internal electrode layer, and the electrode discontinuity. Specifically, when there was Si segregation where the entire surrounding was covered by the dielectric layer, it was considered that there was Si segregation in the dielectric layer. When there was Si segregation where a part overlapped with the interface between the dielectric layer and the internal electrode layer, it was considered that there was Si segregation at the interface between the dielectric layer and the internal electrode layer. When there was Si segregation where a part or all overlapped with the electrode discontinuity, it was considered that there was Si segregation at the electrode discontinuity. The results are shown in Table 1. In the capacitor sample in which no Si segregation was included in any of the dielectric layer, the interface between the dielectric layer and the internal electrode layer, and the electrode discontinuity, no Si segregation was included in other locations either.

[0091] Coating rate Regarding the above-mentioned cross-section, SEM observation was carried out, and the coverage rate was calculated from the obtained SEM photographs. Specifically, assuming that there is no electrode discontinuity in the internal electrode layer, the ratio of the line length of the region where the electrode layer is actually formed to the line length of the region where the electrode layer should be formed was calculated, and this was taken as the coverage rate. When the coverage rate was 80% or more and 100% or less, it was regarded as good, and when it was 90% or more and 100% or less, it was regarded as even better. The results are shown in Table 1.

[0092] Thermal shock test First, 300 capacitor samples were fabricated and divided into three groups of 100 each. Then, the capacitance, dielectric loss (tanδ), and insulation resistance (IR) of each capacitor sample were measured.

[0093] Next, for the capacitor samples in the first group, a thermal cycle of -55°C / 85°C was repeated 3000 times. For the capacitor samples in the second group, a thermal cycle of -55°C / 125°C was repeated 3000 times. For the capacitor samples in the third group, a thermal cycle of -55°C / 150°C was repeated 3000 times.

[0094] Specifically, the process of holding in a low-temperature (-55°C) chamber for 30 minutes and then holding in a high-temperature (85°C, 125°C, or 150°C) chamber for 30 minutes was repeated 3000 times.

[0095] Then, the capacitance, dielectric loss (tanδ), and insulation resistance (IR) of each capacitor sample after the thermal cycle were measured, and the change rates of capacitance, dielectric loss, and insulation resistance before and after the thermal cycle were calculated.

[0096] Capacitor samples in which all of the above change rates were 5% or less and no structural defects (cracks, delamination) were observed after the thermal cycle were regarded as good products, and capacitor samples other than good products were regarded as defective products. The number of defective products in each group was described in Table 1.

[0097] The capacitance was measured for the capacitor sample at a reference temperature of 25°C using a digital LCR meter (4274A manufactured by YHP) under the conditions of a frequency of 1 kHz and an input signal level (measurement voltage) of 1.0 Vrms. The dielectric loss (tanδ) was measured for the capacitor sample at a reference temperature of 25°C using a digital LCR meter (4274A manufactured by YHP) under the conditions of a frequency of 1 kHz and an input signal level (measurement voltage) of 0.5 Vrms. The insulation resistance was measured using a digital resistance meter (R8340 manufactured by ADVANTEST) at a measurement temperature of 25°C, a measurement voltage of 4 V, and a measurement time of 60 seconds. Regarding the presence or absence of structural defects, resin embedding and cross-section polishing were performed on the capacitor sample. The presence or absence of structural defects was confirmed for the obtained cross-section using an optical microscope at 50 times magnification.

[0098] For the first group, the case where the number of defective products was 0 was regarded as good. That is, the case where the ratio of defective products was less than 1% was regarded as good. For the second group, the case where the number of defective products was less than 20 was regarded as good, the case where it was less than 9 was regarded as better, and the case where it was less than 5 was regarded as particularly good. That is, the case where the ratio of defective products was less than 20% was regarded as good, the case where it was less than 9% was regarded as better, and the case where it was less than 5% was regarded as particularly good. For the third group, the case where the number of defective products was less than 30 was regarded as good, the case where it was less than 18 was regarded as better, and the case where it was less than 10 was regarded as particularly good. That is, the case where the ratio of defective products was less than 30% was regarded as good, the case where it was less than 18% was regarded as better, and the case where it was less than 10% was regarded as particularly good.

[0099]

Table 1

[0100] From Table 1, when the content of all secondary components, such as containing more than 0 mol and less than 0.050 mol of Mn oxide in terms of MnO, is within a predetermined range and the Zr / Mn ratio and Zr / Si ratio are also within a predetermined range, Si segregation occurs, the coating rate is high, and the result of the thermal shock test is good. In contrast, for Sample No. 1 that does not contain Mn oxide, Si segregation did not occur, and the coating rate became too low. And the result of the thermal shock test was inferior to that of each example. For Sample No. 8 with too much Mn oxide content, Si segregation did not occur in the dielectric layer. And the result of the thermal shock test was inferior to that of each example.

[0101] (Experimental Example 2) For Sample No. 5 of Experimental Example 1, it was carried out under the same conditions except that the content of Mg oxide was changed. The results are shown in Table 2.

[0102]

Table 2

[0103] From Table 2, when the content of all secondary components, such as containing 1.00 mol or more and 2.50 mol or less of Mg oxide in terms of MgO, is within a predetermined range and the Zr / Mn ratio and Zr / Si ratio are also within a predetermined range, Si segregation occurs, the coating rate is high, and the result of the thermal shock test is good. In contrast, for Sample No. 9 with too little Mg oxide content and Sample No. 16 with too much Mg oxide content, the results of the thermal shock test were both inferior to those of each example.

[0104] (Experimental Example 3) For Sample No. 5 of Experimental Example 1, it was carried out under the same conditions except that the content of R(Dy) oxide was changed. The results are shown in Table 3.

[0105]

Table 3

[0106] From Table 3, when the content of all secondary components is within a predetermined range, such as containing 0.50 mol or more and 1.50 mol or less of the oxide of R(Dy) in terms of R2O3, and the Zr / Mn ratio and Zr / Si ratio are also within a predetermined range, Si segregation occurs, the coating rate is high, and the result of the thermal shock test is good. On the other hand, for sample No. 17 where the content of the oxide of R is too small and sample No. 22 where the content of the oxide of R is too large, the results of the thermal shock test were inferior to those of each example.

[0107] (Experimental Example 4) For sample No. 5 in Experimental Example 1, capacitor samples numbered 23 to 26 were prepared under the same conditions except that the content of the oxide of Mn, the content of the oxide of Zr, and the content of the oxide of Si were changed. Note that the Zr / Si ratio was made the same except for sample No. 23 that does not contain Zr. The Zr / Mn ratio was made the same except for sample No. 23 that does not contain Zr and sample No. 26 where the content of the oxide of Zr is too large. The results are shown in Table 4.

[0108]

Table 4

[0109] From Table 4, for sample numbers 24 to 25 where the content of all secondary components is within a predetermined range and the Zr / Mn ratio and Zr / Si ratio are also within a predetermined range, Si segregation occurred, the coating rate was high, and the result of the thermal shock test was good. On the other hand, for sample No. 23 that does not contain the oxide of Zr and sample No. 26 where the content of the oxide of Zr is too large, the results of the thermal shock test were inferior to those of each example.

[0110] (Experimental Example 5) For sample No. 5 in Experimental Example 1, capacitor samples numbered 27 to 33 were prepared under the same conditions except that the content of the oxide of Zr and the content of the oxide of Si were changed as shown in Table 5. Note that the Zr / Si ratio was made the same for all samples. The results are shown in Table 5.

[0111]

Table 5

[0112] From Table 5, for sample numbers 28 - 32 where the contents of all secondary components were within the specified ranges and the Zr / Mn ratio and Zr / Si ratio were also within the specified ranges, Si segregation occurred, the coating rate was high, and the results of the thermal shock test were good. In contrast, for sample number 27 where the contents of all secondary components were within the specified ranges but the Zr / Mn ratio was too small, Si segregation did not occur and the results of the thermal shock test were inferior to those of each example. For sample number 33 where the contents of all secondary components were within the specified ranges but the Zr / Mn ratio was too large, the results of the thermal shock test were inferior to those of each example.

[0113] (Experimental Example 6) Regarding sample number 5 of Experimental Example 1, capacitor samples with sample numbers 34 - 39 were prepared under the same conditions except that the content of the oxide of Si was changed as shown in Table 6. The results are shown in Table 6.

[0114]

Table 6

[0115] From Table 6, for sample numbers 35 - 38 where the contents of all secondary components were within the specified ranges and the Zr / Mn ratio and Zr / Si ratio were also within the specified ranges, Si segregation occurred, the coating rate was high, and the results of the thermal shock test were good. In contrast, for sample number 34 where the contents of all secondary components were within the specified ranges but the Zr / Si ratio was too small, the results of the thermal shock test were inferior to those of each example. For sample number 39 where the contents of all secondary components were within the specified ranges but the Zr / Si ratio was too large, Si segregation did not occur and the results of the thermal shock test were inferior to those of each example.

[0116] (Experimental Example 7) Regarding sample number 5 of Experimental Example 1, capacitor samples with sample numbers 40 - 45 were prepared under the same conditions except that the content of the oxide of V was changed as shown in Table 7. The results are shown in Table 7.

[0117]

Table 7

[0118] From Table 7, for sample numbers 40 - 45 where the content of all secondary components was within a predetermined range and the Zr / Mn ratio and Zr / Si ratio were also within a predetermined range, Si segregation occurred, the coating rate was high, and the results of the thermal shock test were good. Furthermore, for sample numbers 40 - 44 where the content of vanadium oxide was 0.05 mol or more and 0.25 mol or less in terms of V₂O₅ conversion, the results of the thermal shock test were further improved compared to sample numbers 5 and 45 which were under the same conditions except that the content of vanadium oxide was less than 0.05 mol or exceeded 0.25 mol.

[0119] (Experimental Example 8) For sample number 41 in Experimental Example 7, sample numbers 41a - 41c, 46 - 49 were prepared under the same conditions except that the thickness t2 of the internal electrode layer was changed by varying the electrode printing thickness to change the coating rate. The results are shown in Table 8.

[0120]

Table 8

[0121] From Table 8, for sample numbers 41, 41c, 46 - 49 where the coating rate was 85% or more and 100% or less, the results of the thermal shock test were improved compared to sample numbers 41a and 41b where the coating rate was 80% or more and less than 85%. Furthermore, for sample numbers 46 - 49 where the coating rate was 90% or more and 100% or less and no Si segregation was formed at the electrode discontinuous part, the results of the thermal shock test were further improved compared to sample numbers 41, 41a - 41c where the coating rate was 80% or more and less than 90% and Si segregation was formed at the electrode discontinuous part. That is, for sample numbers 46 - 49, Si segregation occurred in the dielectric layer and the interface (the interface between the dielectric layer and the internal electrode layer), the coating rate was high, and the results of the thermal shock test were good.

[0122] (Experimental Example 9) For sample number 4 of Experimental Example 1, a capacitor sample of sample number 50 was prepared under the same conditions except that the content of the oxide of Zr was changed as shown in Table 9. Further, for sample number 50, the content of the oxide of Mn and the content of the oxide of Si were changed as shown in Table 9 so that the Zr / Mn ratio and the Zr / Si ratio were the same as those of sample number 4, and a capacitor sample of sample number 51 was prepared. The results are shown in Table 9.

[0123]

Table 9

[0124] From Table 9, in both sample numbers 50 and 51 where the content of Zr was too low, no Si segregation occurred in the dielectric layer, and the results of the thermal shock test were inferior to those of sample number 4. In addition, no Si segregation occurred at the electrode discontinuous part of sample number 51.

Explanation of symbols

[0125] 1… Multilayer ceramic capacitor 2… Dielectric layer 3… Internal electrode layer 3a… Electrode discontinuous part 4… External electrode 5… Segregation phase 10… Capacitor element body

Claims

1. A multilayer ceramic electronic component having an element body in which a dielectric layer and an electrode layer are laminated, The dielectric layer has a general formula ABO 3 wherein A is Ba alone or at least one selected from Ba, Ca, and Sr, and B is Ti alone or at least one selected from Ti, Zr, and Hf), and contains a main component represented by The dielectric layer contains, per 100 moles of the main component, an oxide of Mn in an amount exceeding 0 mole and less than 0.050 mole in terms of MnO, an oxide of Mg in an amount of 1.00 mole or more and 2.50 moles or less in terms of MgO, an oxide of R (R is at least one selected from Y, Dy, Ho, Yb, Lu, Gd, and Tb) in an amount of 0.50 mole or more and 1.50 moles or less in terms of R 2 O 3 in an amount of 0.50 mole or more and 1.50 moles or less in terms of ZrO, an oxide of Zr in an amount of 0.05 mole or more and 0.45 mole or less in terms of ZrO 2 and further contains Si In the dielectric layer, the Zr / Mn ratio is 5.0 or more and 12.5 or less on an atomic number basis, and the Zr / Si ratio is 0.40 or more and 0.80 or less on an atomic number basis. A multilayer ceramic electronic component.

2. The dielectric layer contains, in terms of V, 0.05 mol or more and 0.25 mol or less of an oxide of V with respect to 100 mol of the main component. 2 O 5 The multilayer ceramic electronic component according to claim 1.

3. Segregation containing Si is formed in the interface between the electrode layer and the dielectric layer and in the region composed of the dielectric layer, The multilayer ceramic electronic component according to claim 1 or 2, wherein the coverage rate of the electrode layer is 80% or more and 100% or less.

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