Multilayer ceramic capacitor

Abstract

The purpose of the present invention is to provide a multilayer ceramic capacitor capable of suppressing peeling in a lamination direction between internal electrodes while suppressing deterioration of insulation resistance.　This multilayer ceramic capacitor according to the present invention includes: a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrodes, and having a first surface and a second surface facing each other in the lamination direction, a third surface and a fourth surface facing each other in a first direction orthogonal to the lamination direction, and a fifth surface and a sixth surface facing each other in the lamination direction and a second direction orthogonal to the first direction; a first external electrode disposed on the third surface of the laminate; and a second external electrode disposed on the fourth surface of the laminate. The laminate includes an inner layer part. The inner layer part has a first internal electrode whose one end is exposed on the third surface, a second internal electrode whose one end is exposed on the fourth surface, an inner layer dielectric layer disposed between the first internal electrode and the second internal electrode, and a first connection part which connects first internal electrodes to each other. The first connection part is located at an end part on the fifth surface side of the first internal electrode and an end part on the sixth surface side of the first internal electrode.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have inner layer sections in which dielectric layers and internal electrodes are alternately stacked, and outer layer sections that are arranged to sandwich the inner layer sections. Because the inner layer sections are made up of laminated dielectric layers and internal electrodes, the adhesive strength between the different materials is insufficient, which can lead to peeling between the layers.

[0003] To increase the capacitance of multilayer ceramic capacitors, a technique is known in which a laminated body is fabricated by cutting the inner layers so that their internal ends are aligned, and a side margin is provided on the cut cross section of the laminated body. Providing a side margin can lead to various problems, such as cracks at the interface between the side margin and the laminated body, or peeling of the side margin from the laminated body. Patent Document 1, for example, addresses the problem of peeling due to the difference in sintering temperature between the laminated body having the internal electrodes and the side margin, by providing a joint extending from the y-axis end of the internal electrode in the z-axis direction. Note that this joint is formed by firing an extended portion in which the end of the internal electrode is extended in the z-axis direction, i.e., the direction of cutting with a cutting blade, during the manufacturing process of the multilayer ceramic capacitor disclosed in Patent Document 1.

[0004] Japanese Patent Application Laid-Open No. 2019-79977

[0005] However, in the configuration and manufacturing method of the multilayer ceramic capacitor described in Patent Document 1, the distance between two internal electrodes adjacent in the z-axis direction becomes short, making dielectric breakdown more likely to occur. Also, to form the joint, the length of the extended portion is changed by changing the shape of the blade, but as the thickness of the ceramic layer becomes thinner, there is a limit to how much the length of the extended portion can be changed by changing the uneven shape of the blade.

[0006] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can suppress peeling between internal electrodes in the lamination direction while suppressing deterioration of insulation resistance.

[0007] The multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrodes, the laminate having a first surface and a second surface opposing each other in the lamination direction, a third surface and a fourth surface opposing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface opposing each other in a second direction perpendicular to the lamination direction and the first direction, a first external electrode arranged on the third surface of the laminate, and a second external electrode arranged on the fourth surface of the laminate, the laminate including an inner layer portion, the inner layer portion having a first internal electrode having one end exposed on the third surface, a second internal electrode having one end exposed on the fourth surface, an inner layer dielectric layer arranged between the first internal electrode and the second internal electrode, and a first connecting portion connecting the first internal electrodes together, the first connecting portion being located at an end of the first internal electrode on the fifth surface side and an end of the first internal electrode on the sixth surface side.

[0008] According to the multilayer ceramic capacitor of the present invention, the laminate includes an inner layer portion, which has a first internal electrode having one end exposed on the third surface, a second internal electrode having one end exposed on the fourth surface, an inner layer dielectric layer arranged between the first internal electrode and the second internal electrode, and a first connecting portion connecting the first internal electrodes to each other, and the first connecting portion is located at the end of the first internal electrode on the fifth surface side and the end of the first internal electrode on the sixth surface side, so that the first internal electrodes sandwich the dielectric layer between them by the first connecting portion, thereby suppressing deterioration of insulation resistance while suppressing peeling between the internal electrodes in the stacking direction.

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the deterioration of insulation resistance and the occurrence of peeling between internal electrodes in the lamination direction.

[0010] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the invention, which proceeds with reference to the accompanying drawings.

[0011] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. 2 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. 3 is a cross-sectional view taken along line III-III in FIG. 1. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. 5 is a cross-sectional view taken along line V-V in FIG. 1. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. 9 is a cross-sectional view taken along line IX-IX in FIG. 2. 10 is a cross-sectional view taken along line XX in FIG. 2. 11 is a cross-sectional view taken along line XI-XI in FIG. 2. 12 is a cross-sectional view showing a modification of the cross-sectional view shown in FIG. 6. 13 is a cross-sectional view schematically showing a state in which third and fourth internal electrodes are arranged along line III-III in FIG. 1.

[0012] 1. Multilayer Ceramic Capacitor A multilayer ceramic capacitor according to an embodiment of the present invention will be described.

[0013] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 2. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 2. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 2. FIG. 10 is a cross-sectional view taken along line XX in FIG. 2. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 2.

[0014] As shown in FIGS. 1 to 4, the multilayer ceramic capacitor 10 includes a rectangular parallelepiped laminate 12 and external electrodes 30 disposed on both ends of the laminate 12 .

[0015] (Laminate) The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrodes 20 stacked on the dielectric layers 14. Furthermore, the laminate 12 has a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y.

[0016] Preferably, the first surface 12a and the second surface 12b, or one of them, is flat. If the first surface 12a and the second surface 12b are flat, the stress applied by the nozzle picking up the multilayer ceramic capacitor 10 can be dispersed across the flat surface. As a result, the strength of the multilayer ceramic capacitor can be improved during mounting.

[0017] The surface of the laminate 12 may be roughened.

[0018] The corners and ridges of this laminate 12 may be rounded. The intersection of two of the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, the fifth surface 12e, and the sixth surface 12f is referred to as a ridge, and the intersection of three surfaces is referred to as a corner. The ridges and corners are preferably rounded and rounded. By rounding the ridges and corners, chipping and cracking can be prevented. When the ridges and corners are rounded, the main surface may be flat on the surfaces excluding the ridges and corners.

[0019] As shown in Figures 3 and 4, the laminate 12 has an inner layer portion 16 formed by alternately stacking dielectric layers 14 and internal electrodes 20 in a stacking direction x connecting the first surface 12a and the second surface 12b, a first surface side outer layer portion 18a formed from a plurality of dielectric layers 14 located between the first surface 12a and the internal electrode 20 located closest to the first surface 12a, and a second surface side outer layer portion 18b formed from a plurality of dielectric layers 14 located between the second surface 12b and the internal electrode 20 located closest to the second surface 12b.

[0020] (Inner Layer Portion) The inner layer portion 16 is constituted by a plurality of inner dielectric layers 14a among the plurality of dielectric layers 14. That is, the inner layer portion 16 is arranged so that a plurality of inner electrodes 20 face each other with the inner dielectric layers 14a interposed therebetween.

[0021] For example, if the internal dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as the main component of the dielectric component, it can reduce the occurrence of dielectric breakdown between the internal electrodes 20. Furthermore, without being limited to this, the main component can also be SrTiO3 or the like. To increase the capacitance of the multilayer ceramic capacitor 10, it is preferable that the main component of the dielectric component be a material with a high dielectric constant, such as BaTiO3. When the above-mentioned dielectric material is contained as the main component, a minor component such as a Mn compound, Fe compound, Cr compound, Co compound, or Ni compound may be added in a smaller amount than the main component, depending on the desired characteristics of the laminate 12.

[0022] The thickness of the dielectric layer 14 after firing is preferably 0.5 μm or more and 10 μm or less. The number of laminated dielectric layers 14 is preferably 50 or more and 1000 or less.

[0023] 3 and 4, the internal electrode 20 includes a first internal electrode 20a and a second internal electrode 20b. The first internal electrodes 20a and the second internal electrodes 20b are alternately stacked with the dielectric layer 14 interposed therebetween.

[0024] The first internal electrode 20a is disposed on the dielectric layer 14 and is located inside the laminate 12. The first internal electrode 20a has a first opposing electrode portion 22a facing the second internal electrode 20b and a first lead electrode portion 24a located on one end side of the first internal electrode 20a and extending from the first opposing electrode portion 22a to the third surface 12c of the laminate 12. The end of the first lead electrode portion 24a is extended to the surface of the third surface 12c and exposed from the laminate 12. In other words, the end of the first lead electrode portion 24a is not exposed on the first surface 12a, the second surface 12b, the fourth surface 12d, the fifth surface 12e, and the sixth surface 12f. The end of the first internal electrode 20a on the fourth surface 12d side is slightly recessed from the fourth surface 12d.

[0025] The shape of the first opposing electrode portion 22a of the first internal electrode 20a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 22a may be tapered in plan view, with a slope increasing in either direction.

[0026] The shape of the first lead electrode portion 24a of the first internal electrode 20a is not particularly limited, but is preferably rectangular in plan view.

[0027] The width of the first opposing electrode portion 22a of the first internal electrode 20a and the width of the first extraction electrode portion 24a of the first internal electrode 20a may be formed to be the same width, or one of the widths may be formed to be narrower.

[0028] The second internal electrode 20b is disposed on the dielectric layer 14 and is located inside the laminate 12. The second internal electrode 20b has a second opposing electrode portion 22b facing the first internal electrode 20a and a second lead electrode portion 24b located on one end side of the second internal electrode 20b and extending from the second opposing electrode portion 22b to the fourth surface 12d of the laminate 12. The end of the second lead electrode portion 24b is extended to the surface of the fourth surface 12d and exposed from the laminate 12. In other words, the end of the first lead electrode portion 24a is not exposed on the first surface 12a, the second surface 12b, the third surface 12c, the fifth surface 12e, and the sixth surface 12f. The end of the second internal electrode 20b on the third surface 12c side is slightly recessed from the third surface 12c.

[0029] The shape of the second opposing electrode portion 22b of the second internal electrode 20b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 22b may be tapered in plan view, with a slope increasing in either direction.

[0030] The shape of the second lead electrode portion 24b of the second internal electrode 20b is not particularly limited, but is preferably rectangular in plan view.

[0031] The width of the second opposing electrode portion 22b of the second internal electrode 20b and the width of the second extraction electrode portion 24b of the second internal electrode 20b may be formed to be the same width, or one of the widths may be formed to be narrower.

[0032] The laminate 12 includes a side portion 26a of the laminate 12 formed between one end of the first opposing electrode portion 22a and the second opposing electrode portion 22b in the second direction z and the fifth surface 12e, and a side portion 26b of the laminate 12 formed between the other end of the first opposing electrode portion 22a and the second opposing electrode portion 22b in the second direction z and the sixth surface 12f. Furthermore, the laminate 12 includes an end portion 27a of the laminate 12 formed between an end portion of the first internal electrode 20a opposite to the first extraction electrode portion 24a and the fourth surface 12d, and an end portion 27b of the laminate 12 formed between an end portion of the second internal electrode 20b opposite to the second extraction electrode portion 24b and the third surface 12c.

[0033] The internal electrodes 20 can be made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. The internal electrodes 20 may further contain dielectric particles of the same composition as the ceramic contained in the dielectric layer 14. Furthermore, by including Sn in the first internal electrode 20a and the second internal electrode 20b, electric field concentration at the interface between the internal electrode 20 and the dielectric layer 14 can be alleviated, leading to improved high-temperature load reliability. In this case, Sn may be included in only one of the internal electrodes 20, either the first internal electrode 20a or the second internal electrode 20b.

[0034] The thickness of the internal electrode 20 is preferably 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrodes 20a and the second internal electrodes 20b is preferably 50 or more and 1000 or less.

[0035] 5 to 9, the inner layer portion 16 has connecting portions 28. The connecting portions 28 have first connecting portions 28a that connect the first internal electrodes 20a to each other, and second connecting portions 28b that connect the second internal electrodes 20b to each other.

[0036] The first connecting portion 28a preferably connects the ends of the first internal electrodes 20a on the fifth surface 12e side and also connects the ends of the first internal electrodes 20a on the sixth surface 12f side. The second connecting portion 28b preferably connects the ends of the second internal electrodes 20b on the fifth surface 12e side and also connects the ends of the second internal electrodes 20b on the sixth surface 12f side. This improves the adhesive strength between the side portions 26a, 26b and the internal electrode 20 and the internal dielectric layer 14a when the side portions 26a, 26b are formed by a separate bonding process during the manufacturing process of the multilayer ceramic capacitor 10. As a result, peeling between the side portions 26a, 26b and the internal electrode 20 and the internal dielectric layer 14a can be suppressed. Furthermore, since adjacent internal electrodes 20 can be connected to each other via the internal dielectric layer 14a in the stacking direction x, peeling between the internal dielectric layer 14a and the internal electrode 20 in the stacking direction x can be suppressed. The first connecting portion 28a may simply connect together at least one of the ends of the first inner electrode 20a facing the fifth surface 12e and the sixth surface 12f. Similarly, the second connecting portion 28b may simply connect together at least one of the ends of the second inner electrode 20b facing the fifth surface 12e and the sixth surface 12f.

[0037] Furthermore, the first connection portion 28a preferably connects the ends of the first lead electrode portions 24a of the first internal electrodes 20a on the fifth surface 12e side and connects the ends of the first lead electrode portions 24a of the first internal electrodes 20a on the sixth surface 12f side. In this case, the first connection portion 28a is not present in the first opposing electrode portion 22a. Similarly, the second connection portion 28b preferably connects the ends of the second lead electrode portions 24b of the second internal electrodes 20b on the fifth surface 12e side and connects the ends of the second lead electrode portions 24b of the second internal electrodes 20b on the sixth surface 12f side. In this case, the second connection portion 28b is not present in the second opposing electrode portion 22b. As a result, even if the first connection portion 28a is provided, adjacent first internal electrodes 20a are at the same potential, and even if the second connection portion 28b is provided, adjacent second internal electrodes 20b are at the same potential, so peeling between the side portions 26a, 26b and the internal electrode 20 and internal dielectric layer 14a can be suppressed without reducing the insulation resistance.

[0038] Furthermore, it is preferable that the first connection portion 28a is not exposed on the surface of the third face 12c, and the second connection portion 28b is not exposed on the surface of the fourth face 12d. This allows the connection portion 28 to be arranged without increasing the distance that moisture must travel to reach the internal electrode 20 when moisture penetrates from the outside, thereby suppressing deterioration of moisture resistance.

[0039] 6 and 7 , when the laminate 12 is divided into two equal parts in the stacking direction x, the region on the first surface 12a side is designated as the first surface side region 19a, and the region on the second surface 12b side is designated as the second surface side region 19b, it is preferable that more connecting portions 28 be arranged in the first surface side region 19a. Alternatively, when the laminate 12 is divided into two equal parts in the stacking direction x, the connecting portions 28 may be present in either the first surface side region 19a or the second surface side region 19b. Here, in the manufacturing process of the laminate 12 described below, the adhesive strength between the internal dielectric layer 14a and the internal electrode 20 differs between the start and end of stacking. Therefore, assuming that the first surface 12a side is the end of stacking, it is preferable that the number of connecting portions 28 arranged in the first surface side region 19a be greater than the number of connecting portions 28 arranged in the second surface side region 19b. This allows the connection portion 28 to be arranged on the side where the adhesive strength between the internal dielectric layer 14a and the internal electrode 20 is relatively weak, thereby further suppressing peeling between the internal dielectric layer 14a and the internal electrode 20.

[0040] It is preferable that two or more connection portions 28 are arranged for one layer of the internal electrode 20. It is also preferable that the connection portions 28 are not arranged in a straight line in the stacking direction x.

[0041] Furthermore, the multilayer ceramic capacitor 10 according to this embodiment may have only the first connecting portion 28a as the connecting portion 28.

[0042] 10 and 11 , the connecting portions 28 of the inner layer portions 16 may have third connecting portions 28c that connect the first inner electrodes 20a to each other and fourth connecting portions 28d that connect the second inner electrodes 20b to each other. Therefore, the multilayer ceramic capacitor 10 does not necessarily have to have the third connecting portions 28c and the fourth connecting portions 28d.

[0043] The third connection portion 28c is preferably arranged to be exposed on the third surface 12c so as to connect the first lead electrode portions 24a of the multiple first internal electrodes 20a exposed on the third surface 12c to each other. The third connection portion 28c is preferably arranged on the inside of the end of the first lead electrode portion 24a of the first internal electrode 20a in the direction connecting the fifth surface 12e and the sixth surface 12f (second direction z). The fourth connection portion 28d is preferably arranged to be exposed on the fourth surface 12d so as to connect the second lead electrode portions 24b of the multiple second internal electrodes 20b exposed on the fourth surface 12d to each other. The fourth connection portion 28d is preferably arranged on the inside of the end of the second lead electrode portion 24b of the second internal electrode 20b in the direction connecting the fifth surface 12e and the sixth surface 12f (second direction z). This increases the ratio of metal components disposed on at least one of the third surface 12c and the fourth surface 12d, thereby improving the adhesive strength between the external electrode 30 and the internal electrode 20.

[0044] The connection portion 28 can be made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. The connection portion 28 may further contain dielectric particles of the same composition as the ceramic contained in the dielectric layer 14. By using the same type of metal component as the internal electrode 20 as the main component, it is possible to make the shrinkage behavior during the firing process described below uniform.

[0045] As shown in FIG. 11 , dielectric regions 29 may be disposed in the first connecting portion 28 a and the second connecting portion 28 b. In this case, the dielectric regions 29 are disposed in a scattered manner in each of the first connecting portion 28 a and the second connecting portion 28 b. The dielectric regions 29 are composed of dielectric particles having the same composition as the ceramic contained in the dielectric layer 14. This further suppresses peeling between the side portions 26 a, 26 b and the internal electrode 20 and the internal dielectric layer 14 a. Furthermore, the dielectric powder can prevent over-sintering of the connecting portion 28, thereby suppressing interlayer peeling due to excessive shrinkage. The particle size of the dielectric particles constituting the dielectric region 29 is not particularly limited, but may be, for example, 0.1 μm to 3.0 μm.

[0046] (First surface side outer layer portion, second surface side outer layer portion) The first surface side outer layer portion 18a is located on the first surface 12a side of the laminate 12, and is an aggregate of multiple outer dielectric layers 14b which are multiple dielectric layers 14 located between the first surface 12a and the internal electrode 20 closest to the first surface 12a. The second surface side outer layer portion 18b is located on the second surface 12b side of the laminate 12, and is an aggregate of multiple outer dielectric layers 14b which are multiple dielectric layers 14 located between the second surface 12b and the internal electrode 20 closest to the second surface 12b. The region sandwiched between the first surface side outer layer portion 18a and the second surface side outer layer portion 18b is the inner layer portion 16.

[0047] The first surface side outer layer portion 18a and the second surface side outer layer portion 18b are each formed of an insulating material. When the first surface side outer layer portion 18a and the second surface side outer layer portion 18b are formed of the same type of dielectric material as the internal dielectric layer 14a, each of the external layer portions 18a, 18b may be formed of a plurality of external dielectric layers 14b or a single external dielectric layer 14b. The external dielectric layer 14b and the internal dielectric layer 14a may be formed of different components. For example, the internal dielectric layer 14a may be made of a material with a higher dielectric constant than the external dielectric layer 14b, and the external dielectric layer 14b may be made of a component with good moisture resistance, weather resistance, or strength resistance.

[0048] As shown in FIG. 13, it is preferable that the first surface side outer layer portion 18a and the second surface side outer layer portion 18b further include a third internal electrode 20c and a fourth internal electrode 20d made of the same metal type as the internal electrode 20.

[0049] As shown in FIG. 13 , in the inner layer portion 16, a position a1 is defined as a position 20 μm inward in the second direction z from the end portions of the first inner electrode 20 a and the second inner electrode 20 b on the fifth surface 12 e side. A1 is defined as a region in the inner layer portion 16 extending from a1 to the end portions of the first inner electrode 20 a and the second inner electrode 20 b on the fifth surface 12 e side. B1 is defined as a region in the first surface side outer layer portion 18 a and the second surface side outer layer portion 18 b extending from region A1 in the stacking direction x. The third inner electrode 20 c is preferably disposed within region B1. Furthermore, a2 is defined as a position a2 is defined as a position 20 μm inward in the second direction z from the end portions of the first inner electrode 20 a and the second inner electrode 20 b on the sixth surface 12 f side. A2 denotes a region defined within the inner layer portion 16 from a2 to the ends of the first inner electrode 20a and the second inner electrode 20b on the sixth surface 12f side. B2 denotes a region defined by extending region A2 in the first surface side outer layer portion 18a and the second surface side outer layer portion 18b in the stacking direction x. In this case, the fourth inner electrode 20d is preferably disposed within region B2. This allows the third inner electrode 20c and the fourth inner electrode 20d to prevent moisture from penetrating through the interfaces between the side portions 26a and the outer layer portions 18a, 18b, thereby improving the moisture resistance of the multilayer ceramic capacitor 10.

[0050] When the length of the third internal electrode 20c in the second direction z is w1 and the length of the stacking direction x is t1, it is preferable that w1<t1. Furthermore, when the length of the fourth internal electrode 20d in the second direction z is w2 and the length of the stacking direction x is t2, it is preferable that w2<t2. Furthermore, it is preferable that the third internal electrode 20c and the fourth internal electrode 20d are curved so as to be convex toward the outside of the laminate 12. As a result, the third internal electrode 20c and the fourth internal electrode 20d are not arranged linearly and the length in the stacking direction x is longer than the length in the second direction z, so that the third internal electrode 20c and the fourth internal electrode 20d can make the path of moisture that penetrates from the interface between the side portion 26a and the outer layer portions 18a, 18b long and complex, thereby further improving the moisture resistance of the multilayer ceramic capacitor 10.

[0051] As shown in FIGS. 1 to 4, external electrodes 30 are disposed on the third surface 12c and the fourth surface 12d of the laminate 12.

[0052] The external electrode 30 includes a base electrode layer 32 containing a metal component and glass, and a plating layer 34 disposed on the surface of the base electrode layer 32 .

[0053] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0054] The first external electrode 30a is connected to the first internal electrode 20a and is disposed on at least the surface of the third face 12c. The first external electrode 30a also extends from the third face 12c of the laminate 12 and is disposed on a portion of the first face 12a, a portion of the second face 12b, a portion of the fifth face 12e, and a portion of the sixth face 12f. In this case, the first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 20a.

[0055] The second external electrode 30b is connected to the second internal electrode 20b and is disposed on at least the surface of the fourth face 12d. The second external electrode 30b also extends from the fourth face 12d of the laminate 12 and is disposed on a portion of the first face 12a, a portion of the second face 12b, a portion of the fifth face 12e, and a portion of the sixth face 12f. In this case, the second external electrode 30b is electrically connected to the second lead electrode portion 24b of the second internal electrode 20b.

[0056] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 20a and the second opposing electrode portion 22b of the second internal electrode 20b face each other via the dielectric layer 14, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a connected to the first internal electrode 20a and the second external electrode 30b connected to the second internal electrode 20b, thereby realizing the characteristics of a capacitor.

[0057] The base electrode layer 32 includes a first base electrode layer 32a and a second base electrode layer 32b.

[0058] The first base electrode layer 32a is connected to the first internal electrode 20a and is disposed on the surface of the third surface 12c. The first base electrode layer 32a also extends from the third surface 12c and is disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. In this case, the first base electrode layer 32a is electrically connected to the first lead electrode portion 24a of the first internal electrode 20a.

[0059] The second base electrode layer 32b is connected to the second internal electrode 20b and is disposed on the surface of the fourth face 12d. The second base electrode layer 32b also extends from the fourth face 12d and is disposed on a part of the first face 12a, a part of the second face 12b, a part of the fifth face 12e, and a part of the sixth face 12f. In this case, the second base electrode layer 32b is electrically connected to the second lead electrode portion 24b of the second internal electrode 20b.

[0060] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0061] Hereinafter, each of the configurations when the base electrode layer 32 is the baked layer, the conductive resin layer, and the thin film layer will be described.

[0062] (In the case of a baking layer) The baking layer contains a metal component and glass. The metal component of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer is formed by applying a conductive paste containing glass and a metal to the laminate and baking it. The baking layer is formed by simultaneously baking a laminated chip having internal electrodes 20 and dielectric layers 14 and the conductive paste applied to the laminated chip, but it may also be baked after baking the laminated chip having internal electrodes 20 and dielectric layers 14. The baking layer may be a multi-layered layer.

[0063] The thickness of the first base electrode layer 32a located on the third surface 12c in the first direction y connecting the third surface 12c and the fourth surface 12d at the center in the stacking direction x is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0064] The thickness of the second base electrode layer 32b located on the fourth surface 12d in the first direction y connecting the third surface 12c and the fourth surface 12d at the center in the stacking direction x is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0065] The thickness in the stacking direction x connecting the first surface 12a and the second surface 12b at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on a part of the first surface 12a and the second surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0066] Furthermore, the thickness in the stacking direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on a part of the first surface 12a and the second surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0067] The thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on a part of the fifth surface 12e and the sixth surface 12f is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0068] Furthermore, it is preferable that the thickness in the second direction z connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on a part of the fifth surface 12e and the sixth surface 12f at the center in the first direction y with the fifth surface 12e and the sixth surface 12f is, for example, approximately 10 μm or more and 100 μm or less.

[0069] (Conductive Resin Layer) The conductive resin layer has a first conductive resin layer and a second conductive resin layer.

[0070] The first conductive resin layer is preferably arranged as a first base electrode layer 32a so as to further cover other layers such as a baked layer, and the second conductive resin layer is preferably arranged as a second base electrode layer 32b so as to further cover other layers such as a baked layer.

[0071] Specifically, the first and second conductive resin layers, as the first and second base electrode layers 32a and 32b, are preferably disposed on other layers, such as baked layers, located on the third and fourth surfaces 12c and 12d, and are provided so as to extend also onto other layers, such as baked layers, located on the first and second surfaces 12a and 12b, as well as the fifth and sixth surfaces 12e and 12f. However, the first and second conductive resin layers may be disposed only on other layers, such as baked layers, located on the third and fourth surfaces 12c and 12d.

[0072] The thickness of the first conductive resin layer and the second conductive resin layer is preferably, for example, about 10 μm or more and 200 μm or less.

[0073] The first conductive resin layer and the second conductive resin layer contain a thermosetting resin and a metal component.

[0074] Because the first conductive resin layer and the second conductive resin layer contain a thermosetting resin, they are more flexible than the base electrode layer 32 made of, for example, a plating film or a fired product of a conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0075] Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0076] The first conductive resin layer and the second conductive resin layer preferably contain a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0077] The metal contained in the first conductive resin layer and the second conductive resin layer may be Ag, Cu, or an alloy thereof. Alternatively, a metal powder having an Ag-coated surface may be used. When using a metal powder having an Ag-coated surface, it is preferable to use Cu or Ni as the metal powder.

[0078] Alternatively, Cu that has been treated to prevent oxidation can also be used. The reason for using Ag-coated metal is that it allows the base metal to be inexpensive while maintaining the above-mentioned properties of Ag.

[0079] The metal contained in the first conductive resin layer and the second conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0080] The shape of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited, and the conductive filler may be spherical, flat, or the like.

[0081] The average particle size of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0082] The metals contained in the first conductive resin layer and the second conductive resin layer are mainly responsible for the electrical conductivity of the conductive resin layers. Specifically, contact between the conductive fillers forms an electrical path inside the conductive resin layers.

[0083] The metal contained in the first conductive resin layer and the second conductive resin layer may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0084] The conductive resin layer may be formed directly on the laminate 12 without forming a baked layer.

[0085] Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS. 2 and 3. FIG.

[0086] The first plating layer 34a and the second plating layer 34b contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, and the like.

[0087] The first plating layer 34a is disposed so as to completely cover the first base electrode layer 32a, and the second plating layer 34b is disposed so as to completely cover the second base electrode layer 32b.

[0088] The first plating layer 34a and the second plating layer 34b may be formed of multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 by Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer by Sn plating. That is, in this case, the first plating layer 34a has a first lower plating layer 36a and a first upper plating layer 38a located on the surface of the first lower plating layer 36a. Furthermore, the second plating layer 34b has a second lower plating layer 36b and a second upper plating layer 38b located on the surface of the second lower plating layer 36b.

[0089] The Ni-plated lower layer 36 is used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10, and the Sn-plated upper layer 38 is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each of the lower layer 36 and the upper layer 38 is preferably 1.0 μm or more and 15.0 μm or less.

[0090] The dimension in the first direction y of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension L, the dimension in the stacking direction x of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension T, and the dimension in the second direction z of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are as follows: L in the first direction y is 0.1 mm or more and 3.2 mm or less, W in the second direction z is 0.05 mm or more and 2.5 mm or less, and T in the stacking direction x is 0.05 mm or more and 2.5 mm or less. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0091] In the multilayer ceramic capacitor 10 shown in FIG. 1, the inner layer portion 16 has first connection portions 28a that connect the first internal electrodes 20a to each other and second connection portions 28b that connect the second internal electrodes 20b to each other. Therefore, adjacent internal electrodes 20 can be connected to each other via the internal dielectric layer 14a in the stacking direction x, and peeling between the internal dielectric layer 14a and the internal electrode 20 in the stacking direction x can be suppressed.

[0092] In the multilayer ceramic capacitor 10 shown in FIG. 1, the first connection portion 28a connects the ends of the first extraction electrode portion 24a of the first internal electrode 20a on the fifth surface 12e side and the sixth surface 12f side, and the second connection portion 28b connects the ends of the second extraction electrode portion 24b of the second internal electrode 20b on the fifth surface 12e side and the sixth surface 12f side. This means that even if the first connection portion 28a is present, adjacent first internal electrodes 20a have the same potential, and even if the second connection portion 28b is present, adjacent second internal electrodes 20b have the same potential, so peeling between the side portions 26a, 26b and the internal electrode 20 and the internal dielectric layer 14a can be suppressed without reducing the insulation resistance.

[0093] Furthermore, in the multilayer ceramic capacitor 10 shown in FIG. 1, the first connecting portion 28a is not exposed on the surface of the third face 12c, and the second connecting portion 28b is not exposed on the surface of the fourth face 12d. This allows the connecting portions 28 to be positioned without increasing the distance to reach the internal electrodes 20, thereby suppressing deterioration of moisture resistance.

[0094] Furthermore, in the multilayer ceramic capacitor 10 shown in FIG. 1 , when the laminate 12 is divided into two equal parts in the stacking direction x, the region on the first surface 12 a side is designated as the first surface side region 19 a and the region on the second surface 12 b side is designated as the second surface side region 19 b, the connecting portions 28 are arranged in greater numbers in the first surface side region 19 a. Alternatively, when the laminate 12 is divided into two equal parts in the stacking direction x, by having the connecting portions 28 present in either the first surface side region 19 a or the second surface side region 19 b, the connecting portions 28 can be arranged on the side where the adhesive strength between the internal dielectric layer 14 a and the internal electrode 20 is relatively weak, and peeling between the internal dielectric layer 14 a and the internal electrode 20 can be further suppressed.

[0095] Furthermore, in the multilayer ceramic capacitor 10 shown in FIG. 1 , if the third connection portion 28 c is arranged so as to connect the first lead electrode portions 24 a of the plurality of first internal electrodes 20 a exposed on the third surface 12 c, and the fourth connection portion 28 d is arranged so as to connect the second lead electrode portions 24 b of the plurality of second internal electrodes 20 b exposed on the fourth surface 12 d, the ratio of metal components arranged on at least one of the third surface 12 c and the fourth surface 12 d is improved, thereby improving the adhesive strength between the external electrode 30 and the internal electrode 20.

[0096] 2. Method for Manufacturing a Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor will be described.

[0097] First, ceramic green sheets for the dielectric layers and a conductive paste for the internal electrodes are prepared. The ceramic green sheets and the conductive paste for the internal electrodes contain a binder and a solvent. The binder and the solvent may be known.

[0098] Then, a conductive paste for the internal electrodes is printed in a predetermined pattern on the ceramic green sheets for the dielectric layers by, for example, screen printing, gravure printing, etc. In this way, ceramic green sheets on which the patterns of the first internal electrodes are formed and ceramic green sheets on which the patterns of the second internal electrodes are formed are prepared.

[0099] (Process for Obtaining a Laminated Sheet) Next, a predetermined number of ceramic green sheets for outer layers, on which no internal electrode patterns are printed, are stacked to form a portion that will become the second surface side outer layer portion on the second surface side. Then, a ceramic green sheet on which a first internal electrode pattern is printed and a ceramic green sheet on which a second internal electrode pattern is printed are sequentially stacked on top of the portion that will become the second surface side outer layer portion so as to form the structure of the present invention, to form a portion that will become the inner layer portion. A predetermined number of ceramic green sheets for outer layers, on which no internal electrode patterns are printed, are stacked on top of this portion that will become the inner layer portion, to form a portion that will become the first surface side outer layer portion on the first surface side. This completes the production of a laminated sheet.

[0100] (Step of Obtaining a Laminated Block) Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0101] (Step of Obtaining a Laminated Chip) The laminated block is then cut to a predetermined size to cut out laminated chips that will become laminated sections. The laminated sections are formed so that the edges of the internal electrode patterns are exposed on each of the side surfaces parallel to the third surface 12 c and the fourth surface 12 d of the completed laminate 12.

[0102] Here, powder of the same metal component as the internal electrodes that will become the connection portions 28 is applied to the regions of the internal electrode patterns exposed on both side surfaces of the laminate. The particle size of the powder of the metal component is not particularly limited, but may be, for example, 0.05 μm or more and 0.50 μm or less. As shown in FIG. 11 , when a dielectric region 29 is to be disposed in the connection portion 28, it can be formed by mixing powder of the same metal component as the internal electrodes with powder of a dielectric component. This allows the connection portions 28 to be disposed so as to be scattered in the stacking direction x.

[0103] The connection portions 28 may be formed by applying a paste through a mask having any shape. The paste is preferably, for example, a solvent in which metal powder or dielectric powder is dispersed. Note that when the connection portions 28 are formed using a paste, the mask design limits the locations where the connection portions can be arranged, and therefore the connection portions tend to be aligned in a straight line in the stacking direction x.

[0104] Next, side margin sheets having a predetermined material composition are attached to both sides of the laminate. This forms side margins on both sides of the laminate, resulting in an unfired laminate chip. At this time, the corners and ridges of the laminate and side margins may be rounded by barrel polishing or the like.

[0105] (Step of Obtaining a Laminate) Next, the laminated chip is fired to create a laminate. By firing the laminated chip, the metal components applied to the internal electrode pattern area or the metal components and the dielectric components are sintered to form a connection. The firing temperature depends on the temperatures of the dielectric layers and the internal electrodes, but is preferably 900°C or higher and 1400°C or lower.

[0106] Next, a conductive paste for the base electrode layer containing a metal component and a glass component is prepared.

[0107] (Step of forming external electrodes) The prepared conductive paste that will become the base electrode layer is applied to both end surfaces of the laminate to form the base electrode layer. The conductive paste can be applied to both end surfaces of the laminate by, for example, dipping or screen printing. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0108] Next, if necessary, plating is applied to the surface of the base electrode layer to form a plating layer. In this embodiment, two plating layers are formed on the surface of the base electrode layer. Specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0109] In the manner described above, the multilayer ceramic capacitor 10 according to the present embodiment is manufactured.

[0110] According to the method for manufacturing a multilayer ceramic capacitor of the present invention, a multilayer ceramic capacitor having connection portions disposed in predetermined regions can be obtained.

[0111] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0112] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position or arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0113] <1> A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrodes, the laminate having first and second surfaces opposing each other in a lamination direction, third and fourth surfaces opposing each other in a first direction perpendicular to the lamination direction, and fifth and sixth surfaces opposing each other in a second direction perpendicular to the lamination direction and the first direction; a first external electrode disposed on the third surface of the laminate; and a second external electrode disposed on the fourth surface of the laminate, wherein the laminate includes an inner layer portion, the inner layer portion having: a first internal electrode having one end exposed on the third surface; a second internal electrode having one end exposed on the fourth surface; an inner dielectric layer disposed between the first internal electrode and the second internal electrode; and a first connection portion connecting the first internal electrodes to each other, wherein the first connection portion is located at an end of the first internal electrode on the fifth surface side.

[0114] <2> The multilayer ceramic capacitor according to <1>, wherein the inner layer portion has a second connection portion that connects the second internal electrodes to each other, and the second connection portion is located at an end portion of the second internal electrode on the fifth surface side.

[0115] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the first connection portion is located closer to the third surface than one end of the second internal electrode on the third surface side.

[0116] <4> The multilayer ceramic capacitor according to <2>, wherein the second connection portion is located closer to the fourth surface than one end of the first internal electrode on the fourth surface side.

[0117] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the first connection portion is not exposed on the third surface.

[0118] <6> The multilayer ceramic capacitor according to <2> or <4>, wherein the second connection portion is not exposed on the fourth surface.

[0119] <7> The multilayer ceramic capacitor according to <1> or <2>, wherein a dielectric region is disposed on the first connection portion.

[0120] <8> The multilayer ceramic capacitor according to <2> or <4>, wherein a dielectric region is disposed on the second connection portion.

[0121] <9> The multilayer ceramic capacitor according to <2>, <4>, <6>, or <8>, wherein, when the laminate is divided into two equal parts in the stacking direction, the region on the first surface side is defined as a first surface side region, and the region on the second surface side is defined as a second surface side region, the number of the first connecting portions and the second connecting portions in the first surface side region is greater than the number of the first connecting portions and the second connecting portions in the second surface side region.

[0122] <10> The multilayer ceramic capacitor according to any one of <1> to <9>, wherein at least two of the first connection portions are arranged in the first direction for each of the first internal electrodes.

[0123] <11> The multilayer ceramic capacitor according to any one of <1> to <10>, wherein the laminate includes a third connection portion that connects the first internal electrodes to each other, and the third connection portion is located at an end portion of the first internal electrode on the third surface side.

[0124] <12> The multilayer ceramic capacitor according to any one of <1> to <11>, wherein the laminate includes a fourth connection portion that connects the second internal electrodes to each other, and the fourth connection portion is located at an end portion of the second internal electrode on the fourth surface side.

[0125] REFERENCE SIGNS LIST 10 Multilayer ceramic capacitor 12 Laminate 12a First surface 12b Second surface 12c Third surface 12d Fourth surface 12e Fifth surface 12f Sixth surface 14 Dielectric layer 14a Internal dielectric layer 14b External dielectric layer 16 Internal layer portion 18a First surface side outer layer portion 18b Second surface side outer layer portion 19a First surface side region 19b Second surface side region 20 Internal electrode 20a First internal electrode 20b Second internal electrode 22 Counter electrode portion 22a First counter electrode portion 22b Second counter electrode portion 24a First lead electrode portion 24b Second lead electrode portion 26a, 26b Side portions 27a, 27b End portions 28 Connection portion 28a First connection portion 28b Second connection portion 28c Third connection portion 28d Fourth connection portion 29 Dielectric region 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 36 Base plating layer 36a First base plating layer 36b Second base plating layer 38 Top plating layer 38a First top plating layer 38b Second top plating layer x Stacking direction y First direction z Second direction

Claims

1. A laminate capacitor comprising: a plurality of stacked dielectric layers and a plurality of stacked internal electrodes; a first surface and a second surface facing each other in a stacking direction; a third surface and a fourth surface facing each other in a first direction orthogonal to the stacking direction; and a fifth surface and a sixth surface facing each other in a second direction orthogonal to the stacking direction and the first direction; a first external electrode disposed on the third surface of the laminate; a second external electrode disposed on the fourth surface of the laminate; the laminate including an inner layer portion, the inner layer portion having: a first internal electrode with one end exposed on the third surface; a second internal electrode with one end exposed on the fourth surface; an inner layer dielectric layer disposed between the first internal electrode and the second internal electrode; and a first connection portion connecting the first internal electrodes, the first connection portion being located at an end of the first internal electrode on the fifth surface side.

2. The laminate capacitor according to claim 1, wherein the inner layer portion has a second connection portion connecting the second internal electrodes, the second connection portion being located at an end of the second internal electrode on the fifth surface side.

3. The laminate capacitor according to claim 1 or 2, wherein the first connection portion is located on the third surface side of one end of the second internal electrode on the third surface side.

4. The laminate capacitor according to claim 2, wherein the second connection portion is located on the fourth surface side of one end of the first internal electrode on the fourth surface side.

5. The laminate capacitor according to any one of claims 1 to 4, wherein the first connection portion is not exposed on the third surface.

6. The laminate capacitor according to claim 2 or 4, wherein the second connection portion is not exposed on the fourth surface.

7. The laminate capacitor according to claim 1 or 2, wherein a dielectric region is disposed on the first connection portion.

8. The laminate capacitor according to claim 2 or 4, wherein a dielectric region is disposed on the second connection portion.

9. When the laminated body is bisected in the lamination direction, with the region on the first surface side being the first surface side region and the region on the second surface side being the second surface side region, the first connection part and the second connection part within the first surface side region are arranged in a greater number than the first connection part and the second connection part within the second surface side region. The multilayer ceramic capacitor according to claim 2, claim 4, or claim 8.

10. The first connection part is arranged in at least two or more in the first direction with respect to one of the first internal electrodes. The multilayer ceramic capacitor according to any one of claims 1 to 9.

11. The laminated body includes a third connection part that connects the first internal electrodes to each other, and the third connection part is located at an end portion on the third surface side of the first internal electrode. The multilayer ceramic capacitor according to any one of claims 1 to 10.

12. The laminated body includes a fourth connection part that connects the second internal electrodes to each other, and the fourth connection part is located at an end portion on the fourth surface side of the second internal electrode. The multilayer ceramic capacitor according to any one of claims 1 to 11.

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