Semiconductor device

Abstract

To provide, for example, a semiconductor device with a new structure.SOLUTION: A semiconductor device includes: a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate containing a semiconductor material. The second transistor includes an oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using semiconductor elements and a method of manufacturing the same.

Background Art

[0002] Memory devices using semiconductor elements are roughly classified into volatile ones in which stored contents are lost when power supply is cut off, and non-volatile ones in which stored contents are retained even when power supply is cut off.

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM stores information by selecting transistors constituting memory elements and accumulating electric charges in capacitors.

[0004] Based on the above principle, in DRAM, since the electric charge in the capacitor is lost when information is read out, a rewrite operation is required every time data is read out. In addition, there is a leakage current in the transistors constituting the memory elements, and electric charges flow out or flow in even when not selected, so the data retention period is short. For this reason, a rewrite operation (refresh operation) is required at a predetermined cycle, and it is difficult to sufficiently reduce power consumption. In addition, since stored contents are lost when power supply is cut off, another memory device using magnetic materials or optical materials is required for long-term retention of memory.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM stores stored contents using a circuit such as a flip-flop. ​To maintain it, a refresh operation is not required, which is advantageous over DRAM in this regard. However, since circuits such as flip - flops are used, there is a problem that the unit price per storage capacity becomes high. Also, in terms of the fact that the stored content is lost when the power supply is cut off, there is no difference from DRAM.

[0006] A representative example of a non - volatile memory device is a flash memory. A flash memory has a floating gate between the gate electrode and the channel - forming region of a transistor, and stores data by holding charges in the floating gate. Therefore, the data retention period is extremely long (semi - permanent), and it has the advantage that the refresh operation required for volatile memory devices is not necessary (see, for example, Patent Document 1). However, since the gate insulating layer constituting the memory element deteriorates due to the tunneling current generated during writing, there is a problem that the memory element stops functioning after a predetermined number of writes. To mitigate the influence of this problem, for example, a technique for equalizing the number of writes of each memory element is adopted. However, to realize this, complex peripheral circuits are required.

[0007] Thus, even if such a technique is adopted, the fundamental problem of lifespan is not solved. In other words, flash memory is not suitable for applications where the information rewrite frequency is high.

[0008] Also, to hold charges in the floating gate or to remove the charges, a high voltage is required. Furthermore, it takes a relatively long time to hold or remove charges, and there is also a problem that it is not easy to speed up writing and erasing.

Prior Art Documents

Patent Document

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] In view of the above problems, in one aspect of the disclosed invention, a semiconductor device having a new structure is provided that can retain stored content even in a situation where no power is supplied and has no limitation on the number of write operations. This is one of the objectives.

Means for Solving the Problems

[0011] One aspect of the present invention relates to a semiconductor device having a stacked structure of a transistor formed using an oxide semiconductor and a transistor formed using other materials. For example, the following configuration can be adopted.

[0012] One aspect of the present invention has a first wiring, a second wiring, a third wiring, a fourth wiring, and a fifth wiring. A plurality of memory elements are connected in parallel between the first wiring and the second wiring. One of the plurality of memory elements includes a first transistor having a first gate electrode, a first source electrode, and a first drain electrode, a second transistor having a second gate electrode, a second source electrode, and a second drain electrode, and a third transistor having a third gate electrode, a third source electrode, and a third drain electrode. The first transistor is provided on a substrate including a semiconductor material, the second transistor is configured to include an oxide semiconductor layer, and the first gate electrode is connected to one of the second source electrode or the second drain electrode. ​​​​​​​​​​ and electrically connected, the first wiring and the first source electrode are electrically connected, the first drain electrode and the third source electrode are electrically connected, the second wiring and the third dra in electrode are electrically connected, the third wiring and the second source electrode or the second dra in electrode's other side are electrically connected, the fourth wiring and the second gate electrode are electrically connected, the fifth wiring and the third gate electrode are electrically connected semiconductor device.

[0013] Further, one aspect of the present invention has the first wiring, the second wiring, the third wiring, the fourth wiring, the fifth wiring, and between the first wiring and the second wiring, a plurality of memory elements are connected in parallel connected, one of the plurality of memory elements has a first transistor having a first gate electrode, a first source electrode, and a first drain electrode, a second transistor having a second gate electrode, a second source electrode, and and a second drain electrode, and a capacitive element. The first transistor is provided on a substrate containing a semiconductor material, the second transistor is composed of an oxide semiconductor layer included, one of the first gate electrode and the second source electrode or the second drain electrode and one electrode of the capacitive element are electrically connected, the first wiring and the first source electrode are electrically connected, the second wiring and the first drain electrode are electrically connected, the third wiring and the other of the second source electrode or the second drain electrode are electrically connected thereto, the fourth wiring and the second gate electrode are electrically connected, the fifth wiring and the capacitive element the other electrode of is electrically connected semiconductor device.

[0014] In the above, the first transistor is a channel formation provided on a substrate containing a semiconductor material A region, an impurity region provided so as to sandwich the channel formation region, and on the channel formation region a first gate insulating layer, a first gate electrode on the first gate insulating layer, and a first source electrode and a first drain electrode that are electrically connected to the impurity region.

[0015] Also, in the above, the second transistor includes a second gate electrode on a substrate containing a semiconductor material, a second gate insulating layer on the second gate electrode, an oxide semiconductor layer on the second gate insulating layer, and a second source electrode and a second drain electrode that are electrically connected to the oxide semiconductor layer.

[0016] Also, in the above, the third transistor includes a channel formation region provided in a substrate containing a semiconductor material, an impurity region provided so as to sandwich the channel formation region, a third gate insulating layer on the channel formation region, a third gate electrode on the third gate insulating layer, and a third source electrode and a third drain electrode that are electrically connected to the impurity region.

[0017] Also, in the above, as the substrate containing a semiconductor material, it is preferable to employ a single crystal semiconductor substrate or an SOI substrate. In particular, it is preferable that the semiconductor material is silicon.

[0018] Also, in the above, it is preferable that the oxide semiconductor layer contains an In-Ga-Zn-O-based oxide semiconductor material. In particular, it is preferable that the oxide semiconductor layer contains crystals of In2Ga2ZnO7. Further, it is preferable that the hydrogen concentration of the oxide semiconductor layer is 5×10 / cm 19 3 or less. Also, the off-current of the second transistor is 1×10 -13 ​​​It is preferable to set it as A or less.

[0019] Also, in the above, the second transistor can be provided in a region overlapping with the first transistor. It can be configured as such.

[0020] In this specification and the like, terms such as "above" and "below" do not limit that the positional relationship of the components is "directly above" or "directly below". For example, in the expression "the first gate electrode on the gate insulating layer", those including other components between the gate insulating layer and the gate electrode are not excluded. Also, the terms "above" and "below" are merely expressions used for convenience of explanation, and unless otherwise specified, those with their upper and lower reversed are also included. For example, in the expression "the first gate electrode on the gate insulating layer", those including other components between the gate insulating layer and the gate electrode are not excluded. In addition, the terms "above" and "below" are merely expressions used for convenience of explanation, and unless otherwise specified, those with their upper and lower reversed are also included. Also, the terms "above" and "below" are merely expressions used for convenience of explanation, and unless otherwise specified, those with their upper and lower reversed are also included. In addition, the terms "above" and "below" are merely expressions used for convenience of explanation, and unless otherwise specified, those with their upper and lower reversed are also included.

[0021] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally define these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0022] Also, the functions of "source" and "drain" may be interchanged when transistors of different polarities are adopted or when the direction of current changes in the circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable. Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are adopted or when the direction of current changes in the circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" are assumed to be interchangeable. It is assumed that they can be used interchangeably.

[0023] In this specification and the like, "electrically connected" includes cases where they are connected via "something having some electrical action". Here, "something having some electrical action" In this specification and the like, "electrically connected" includes cases where they are connected via "something having some electrical action". Here, "something having some electrical action" " is not particularly limited as long as it enables the exchange of electrical signals between connection targets.

[0024] For example, "something having some electrical action" includes, of course, electrodes and wiring, as well as switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

[0025] In general, a "SOI substrate" refers to a substrate having a configuration in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification and the like, it is used as a concept including a substrate having a configuration in which a semiconductor layer made of a material other than silicon is provided on an insulating surface. That is, the semiconductor layer included in the "SOI substrate" is not limited to a silicon semiconductor layer. Also, the substrate in the "SOI substrate" is not limited to a semiconductor substrate such as a silicon wafer, but also includes non-semiconductor substrates such as glass substrates, quartz substrates, sapphire substrates, and metal substrates. That is, those having a layer made of a semiconductor material on a conductor substrate or an insulator substrate are also widely included in the "SOI substrate". Furthermore, in this specification and the like, the "semiconductor substrate" not only refers to a substrate made of only a semiconductor material, but also refers to all substrates including a semiconductor material. That is, in this specification and the like, the "SOI substrate" is also widely included in the "semiconductor substrate".

Advantages of the Invention

[0026] In one aspect of the present invention, a semiconductor device is provided that has a transistor using a material other than an oxide semiconductor at the lower part and a transistor using an oxide semiconductor at the upper part.

[0027] Since a transistor using an oxide semiconductor has an extremely small off-current, using this ​​​​​It is possible to retain the memory content for an extremely long period. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low. Therefore, the power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to retain the memory content for a long time.

[0028] Moreover, a high voltage is not required for writing information, and there is no problem of element degradation. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can be easily realized. Also, there is an advantage that an operation for erasing information is unnecessary.

[0029] In addition, since a transistor using a material other than an oxide semiconductor enables sufficient high-speed operation, it is possible to read the memory content at high speed by using this.

[0030] Thus, by providing a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor integrally, a semiconductor device having unprecedented characteristics can be realized.

Brief Description of the Drawings

[0031]

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Embodiments for Carrying Out the Invention

[0032] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not interpreted as being limited to the description of the embodiments shown below.

[0033] In addition, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. for the sake of easy understanding. Therefore, it is not necessarily limited to the position, size, range, etc. shown in the drawings, etc. Thus, it is not necessarily limited to the position, size, range, etc. shown in the drawings, etc. shown.

[0034] It should be noted that ordinal numbers such as "first", "second", "third", etc. in this specification, etc. are attached to avoid confusion of components and are not intended to be numerically limiting. This is noted.

[0035] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to an aspect of the disclosed invention will be described with reference to FIGS. 1 to 9.

[0036] <Circuit Configuration of Semiconductor Device> FIG. 1 shows an example of the circuit configuration of a semiconductor device. The semiconductor device is composed of a transistor 160 using a material other than an oxide semiconductor and a transistor 162 using an oxide semiconductor.

[0037] ​​​Here, one of the gate electrodes of transistor 160 and the source electrode or the drain electrode of transistor 162 is electrically connected. Also, the first wiring (also referred to as the source line) and the source electrode of transistor 160 are electrically connected, and the second wiring (also referred to as the bit line) and the drain electrode of transistor 160 are electrically connected. And the third wiring (also referred to as the first signal line) and the other of the source electrode or the drain electrode of transistor 162 are electrically connected, and the fourth wiring (also referred to as the second signal line)

[0038] and the gate electrode of transistor 162 are electrically connected. Since transistor 160 using a material other than an oxide semiconductor can operate at a sufficient high speed, by using this, it is possible to perform reading of stored contents and the like at high speed. Also, transistor 162 using an oxide semiconductor has a feature that the off-current is extremely

[0039] small. Therefore, by turning transistor 162 off, it is possible to hold the potential of the gate electrode of transistor 160 for an extremely long time.

[0040] By taking advantage of the feature that the potential of the gate electrode can be held, information can be written, held, and read as follows. First, writing and holding of information will be described. First, the Then, the potential of the fourth wiring is set to a potential at which the transistor 162 is in the off state. By turning off the transistor 162, the potential of the gate electrode of the transistor 160 is held (maintained).

[0041] Since the off-current of the transistor 162 is extremely small, the potential of the gate electrode of the transistor 160 is held for a long time. For example, if the potential of the gate electrode of the transistor 160 is a potential that turns on the transistor 160, the on state of the transistor 160 will be held for a long time. Also, if the potential of the gate electrode of the transistor 160 is a potential that turns off the transistor 160, the off state of the transistor 160 will be held for a long time.

[0042] Next, the reading of information will be described. As described above, in the state where the on state or off state of the transistor 160 is held, when a predetermined potential (low potential) is applied to the first wiring, the potential of the second wiring takes different values according to the on state or off state of the transistor 160. For example, when the transistor 160 is in the on state, the potential of the second wiring will decrease with respect to the potential of the first wiring. Conversely, when the transistor 160 is in the off state the potential of the second wiring does not change.

[0043] In this way, in the state where the information is held, by comparing the potential of the second wiring with a predetermined potential, the information can be read out.

[0044] Next, the rewriting of information will be described. The rewriting of information is performed by the above-mentioned writing of information and is performed in the same manner as the retention. That is, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the third wiring (the potential related to the new information) is applied to the gate electrode of the transistor 160. Thereafter, the potential of the fourth wiring is set to the potential at which the transistor 162 is turned off, and the transistor 1 62 is turned off, so that the new information is retained.

[0045] As described above, the semiconductor device according to the disclosed invention can directly rewrite information by writing information again. Therefore, the erasing operation required in a flash memory or the like is unnecessary, and a decrease in the operating speed due to the erasing operation can be suppressed. That is, high-speed operation of the semiconductor device is realized.

[0046] Note that the above description is for the case of using an n-type transistor (n-channel transistor) in which electrons are majority carriers. Needless to say, a p-type transistor in which holes are majority carriers can be used instead of the n-type transistor.

[0047] <Planar and Cross-Sectional Configurations of Semiconductor Device> FIG. 2 shows an example of the configuration of the semiconductor device. FIG. 2(A) shows a cross-section of the semiconductor device, and FIG. 2(B) shows a plan view of the semiconductor device. Here, FIG. 2(A) corresponds to a cross-section taken along lines A1 - A2 and B1 - B2 in FIG. 2(B). The semiconductor device shown in FIGS. 2(A) and 2(B ) has a transistor 160 using a material other than an oxide semiconductor at the lower part and a transistor 162 using an oxide semiconductor at the upper part. Note that the t Both the transistor 160 and the transistor 162 are described as n-type transistors, but a p-type transistor may be employed. In particular, it is easy to make the transistor 160 p-type.

[0048] The transistor 160 includes a channel formation region 116 provided on a substrate 100 containing a semiconductor material, impurity regions 114 and high-concentration impurity regions 120 (collectively also simply referred to as impurity regions) provided so as to sandwich the channel formation region 116, a gate insulating layer 108a provided on the channel formation region 116, a gate electrode 110a provided on the gate insulating layer 108a, and a source electrode or drain electrode 130a and a

[0049] source electrode or drain electrode 130b that are electrically connected to the impurity region 114. Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. Also, in a region of the substrate 100 that does not overlap with the sidewall insulating layer 118 as seen in a cross-sectional view, there is a high-concentration impurity region 120, and a metal compound region 124 is present on the high-concentration impurity region 120. Also, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160, and an interlayer insulating layer 126 and an interlayer insulating layer 128 are provided so as to cover the transistor 160. The source electrode or drain electrode 130a and the source electrode or drain electrode 130b are Also, an electrode 130c provided in the same manner as the source electrode or drain electrode 130a or the source electrode or drain electrode 130b is electrically connected to the gate electrode 110a.

[0050] The transistor 162 includes a gate electrode 136d provided on the interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136d, an oxide semiconductor layer 140 provided on the gate insulating layer 138, and a source electrode or drain electrode 142a provided on the oxide semiconductor layer 140 and electrically connected to the oxide semiconductor layer 140, and a source electrode or drain electrode 142b.

[0051] Here, the gate electrode 136d is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, an electrode 136a is formed in contact with the source electrode or drain electrode 130a, an electrode 136b is formed in contact with the source electrode or drain electrode 130b, and an electrode 136c is formed in contact with the electrode 130c.

[0052] Further, a protective insulating layer 144 is provided on the transistor 162 so as to be in contact with a part of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, openings reaching the source electrode or drain electrode 142a and the source electrode or drain electrode 142b are provided in the protective insulating layer 144 and the interlayer insulating layer 146, and through the openings, electrodes 150d and 150e are formed in contact with the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Also, Similar to the electrodes 150d and 150e, electrodes 150a, 150b, and 150c are formed which are in contact with the electrodes 136a, 136b, and 136c through openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146.

[0053] Here, it is desirable that the oxide semiconductor layer 140 has been sufficiently purified by removing impurities such as hydrogen. Specifically, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 / cm 19 or less, desirably 5×10 3 / cm 18 or less, more desirably 5×10 3 / cm 17 or less. Further, in the oxide semiconductor layer 3 140 in which the hydrogen concentration has been sufficiently reduced and purified, the carrier concentration is 5×10 / cm 14 or less, desirably 5×10 3 / cm 12 or less. Thus, by using an oxide semiconductor in which the hydrogen concentration has been sufficiently reduced and purified and which is i - type or substantially i - type, a transistor 3 162 with extremely excellent off - current characteristics can be obtained. For example, in the case where the drain voltage Vd is +1V or +10V and the gate voltage Vg is in the range from - 5V to - 20V, the off - current is 1×10 A or less. Thus, by applying the oxide semiconductor layer 140 in which the hydrogen concentration has been sufficiently reduced and purified and reducing the off - current of the transistor 162, a semiconductor device with a new configuration -1 3 can be realized. Note that the hydrogen concentration in the above - mentioned oxide semiconductor layer 140 is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spec ). ​​It is measured by

[0054] Also, an insulating layer 152 is provided on the interlayer insulating layer 146, and electrodes 154a, 154b, 154c, and 154d are provided so as to be embedded in the insulating layer 152. Here, electrode 154a is in contact with electrode 150a, electrode 154b is in contact with electrode 150 b, electrode 154c is in contact with electrodes 150c and 150d, and electrode 1 54d is in contact with electrode 150e. That is, in the semiconductor device shown in FIG. 2, the gate electrode 110a of the transistor 160 and

[0055] the source electrode or drain electrode 142a of the transistor 162 are electrically connected via electrodes 130c, electrode 136c, electrode 150c, electrode 154c, and electrode 150d. are.

[0056] <Method for manufacturing a semiconductor device> Next, an example of the method for manufacturing the semiconductor device will be described. Hereinafter, first, the method for manufacturing the lower transistor 160 will be described with reference to FIG. 3, and then, the method for manufacturing the upper transistor 162 will be described with reference to FIGS. 4 and 5.

[0057] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 3(A)). As the substrate 100 containing a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate , a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, when using a single crystal silicon substrate as the substrate 100 containing a semiconductor material ​​​​Let's take one example. Generally, a "SOI substrate" refers to a substrate having a structure in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification and the like, it is used as a concept including a substrate having a structure in which a semiconductor layer made of a material other than silicon is provided on an insulating surface. That is, the semiconductor layer included in the "SOI substrate" is not limited to a silicon semiconductor layer. Also, the SOI substrate is assumed to include those having a structure in which a semiconductor layer is provided via an insulating layer on an insulating substrate such as a glass substrate. On the substrate 100, a protective layer 102 serving as a mask for forming an element isolation insulating layer is formed (see Fig. 3(A)). As the protective layer 102, for example, an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, or the like can be used as the material. Note that before and after this step, in order to control the threshold voltage of the transistor, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity may be added to the substrate 100. When the semiconductor is silicon,

[0058] for example, phosphorus, arsenic, or the like can be used as the impurity imparting n-type conductivity. Also, for example, boron, aluminum, gallium, or the like can be used as the impurity imparting p-type conductivity. Next, using the above protective layer 102 as a mask, etching is performed to remove a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region). Thereby, separated semiconductor regions 104 are formed (see Fig. 3(B)). For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and the etching solution can be appropriately selected according to the material to be etched.

[0059] Next, using the above protective layer 102 as a mask, etching is performed to remove a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region). As a result, separated semiconductor regions 104 are formed (see Fig. 3(B)). For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and the etching solution can be appropriately selected according to the material to be etched. Thereby, separated semiconductor regions 104 are formed (see Fig. 3(B)). For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and the etching solution can be appropriately selected according to the material to be etched. and the etching solution can be appropriately selected according to the material to be etched.

[0060] Next, an insulating layer is formed to cover the semiconductor region 104, and the insulating layer in the region superimposed on the semiconductor region 104 is selectively removed to form the element isolation insulating layer 106 (see Fig. 3(B)). ) The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, etc. As methods for removing the insulating layer, there are polishing processes such as CMP and etching processes, etc., and any of them can be used. Note that after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106, the protective layer 102 is removed.

[0061] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer.

[0062] The insulating layer will become the subsequent gate insulating layer, and it is preferably a single-layer structure or a laminated structure of a film containing silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc., obtained by using the CVD method, sputtering method, etc. Alternatively, the surface of the semiconductor region 104 may be oxidized or nitrided by high-density plasma treatment or thermal oxidation treatment to form the above insulating layer. The high-density plasma treatment can be performed using, for example, a mixed gas of rare gases such as He, Ar, Kr, Xe, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. Also, the thickness of the insulating layer is not particularly limited, but for example, it can be 1 nm or more and 100 nm or less.

[0063] The layer containing the conductive material can be formed using metal materials such as aluminum, copper, titanium, tantalum, tungsten, etc. Also, semiconductor materials such as polycrystalline silicon containing a conductive material ​​​​​The method of formation is not particularly limited, and examples of the method include deposition, C Various film formation methods such as the VD method, the sputtering method, and the spin coating method can be used. In this embodiment, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0064] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. A gate electrode 110a is formed (see FIG. 3(C)).

[0065] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see FIG. 3(C)). By doping the semiconductor region 104 with phosphorus (P) or arsenic (As), an impurity region with a shallow junction depth is formed. In this case, in order to form an n-type transistor, a region 114 is formed (see FIG. 3(C)). For this purpose, phosphorus or arsenic is added, but for p-type transistors, boron (B) or An impurity element such as aluminum (Al) may be added. As a result of this formation, a channel forming region 116 is formed below the gate insulating layer 108a of the semiconductor region 104. (See FIG. 3(C)). The concentration of the added impurity can be appropriately set. However, when semiconductor elements are highly miniaturized, it is desirable to increase the concentration. In this embodiment, the step of forming the impurity region 114 is performed after forming the insulating layer 112. However, it may be possible to form the insulating layer 112 after forming the impurity region 114. stomach.

[0066] Next, a sidewall insulating layer 118 is formed (see FIG. 3(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying the etching process, it can be formed self-aligned. Also, at this time the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110a and the upper surface of the impurity region 114.

[0067] Next, an insulating layer is formed to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, phosphorus (P), arsenic (As), etc. are added to the region in contact with the impurity region 114 to form a high-concentration impurity region 120 (see Fig. 3(E)). After that, the above insulating layer is removed, and a metal layer 122 is formed to cover the gate electrode 110a, the sidewall insulating layer 118, the high-concentration impurity region 120, etc. (see Fig. 3(E)). The metal layer 122 can be formed using various film formation methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is desirably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to form a low-resistance metal compound. As such a metal material, for example, there are titanium, tantalum, tungsten, nickel, cobalt, platinum etc.

[0068] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. As a result, a metal compound region 124 in contact with the high-concentration impurity region 120 is formed (see Fig. 3(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, a metal compound region is also formed at the portion where the metal layer 122 of the gate electrode 11 0a contacts.

[0069] As the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. ​​Of course, other heat treatment methods may be used, but in order to improve the controllability of the chemical reaction related to the formation of metal compounds, it is desirable to use a method that can achieve heat treatment in a very short time. Note that the above metal compound region is formed by the reaction between the metal material and the semiconductor material, and is a region with sufficiently enhanced conductivity. By forming such a metal compound region, the electrical resistance can be sufficiently reduced and the element characteristics can be improved. After forming the metal compound region 124, the metal layer 122 is removed.

[0070] Next, an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed so as to cover each component formed by the above-described process (see FIG. 3(G)). The interlayer insulating layer 126 and the interlayer insulating layer 128 can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. It is also possible to form them using an organic insulating material such as polyimide or acrylic. Here, a two-layer structure of the interlayer insulating layer 126 and the interlayer insulating layer 128 is adopted, but the configuration of the interlayer insulating layer is not limited to this. After forming the interlayer insulating layer 128, it is desirable to flatten its surface by CMP, etching treatment, or the like.

[0071] Thereafter, an opening reaching the metal compound region 124 is formed in the above interlayer insulating layer, and a source electrode or drain electrode 130a and a source electrode or drain electrode 130b are formed in the opening (see FIG. 3(H)). The source electrode or drain electrode 130a and the source electrode or drain electrode 130b are formed, for example, in the region including the opening using a PVD method, a CVD method, or the like. After forming the conductive layer, a part of the conductive layer can be formed by removing it using methods such as etching or CMP. It can be formed by removing.

[0072] In addition, when forming the source electrode or drain electrode 130a or the source electrode or drain electrode 130b by removing a part of the conductive layer, it is desirable to process it so that its surface becomes flat. For example, after thinly forming a titanium film or a titanium nitride film in a region including an opening, when forming a tungsten film so as to fill the opening, unnecessary tungsten, titanium, titanium nitride, etc. can be removed by subsequent CMP, and the flatness of its surface can be improved. In this way, by planarizing the surface including the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. in subsequent processes. In addition, here, only the source electrode or drain electrode 130 a or the source electrode or drain electrode 130b in contact with the metal compound region 124 is shown, but in this step, an electrode (for example, the electrode 130c in FIG. 2) in contact with the gate electrode 110a can also be formed together. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a, the source electrode or drain

[0073] electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. In addition, an electrode (for example, the electrode 130c in FIG. 2) in contact with the gate electrode 110a can be formed together. There is no particular limitation on the material that can be used as the source electrode or drain electrode 130a, the source electrode or drain electrode 130b, and various conductive materials can be used. For example, conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, etc. can be used. By the above, the transistor 160 using the substrate 100 including the semiconductor material is formed.

[0074] Thus, a transistor 160 using a substrate 100 containing a semiconductor material is formed. After the above process, electrodes, wirings, insulating layers, etc. may be further formed. By adopting a multilayer wiring structure formed of a laminated structure of an interlayer insulating layer and a conductive layer for the wiring structure, a highly integrated semiconductor device can be provided.

[0075] <Fabrication method of upper transistor> Next, a process of fabricating a transistor 162 on an interlayer insulating layer 128 will be described with reference to FIGS. 4 and 5. FIGS. 4 and 5 show fabrication processes of various electrodes on the interlayer insulating layer 128 and the transistor 162, etc., and transistors 160 etc. existing below the transistor 162 are omitted.

[0076] First, an insulating layer 132 is formed on an interlayer insulating layer 128, a source electrode or a drain electrode 130a, a source electrode or a drain electrode 130b, and an electrode 130c (see FIG. 4(A)). The insulating layer 132 can be formed using a PVD method, a CVD method, etc. Also, it can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc.

[0077] Next, openings reaching the source electrode or the drain electrode 130a, the source electrode or the drain electrode 130b, and the electrode 130c are formed in the insulating layer 132. At this time, openings are also formed in the region where the gate electrode 136d will be formed later. Then, a conductive layer 134 is formed so as to fill the above openings (see FIG. 4(B)). The above openings can be formed by a method such as etching using a mask. The mask can be a photomask. It can be formed by a method such as exposure to light. As for etching, wet etching is used. Either etching or dry etching may be used, but from the viewpoint of fine processing, dry etching is preferred. The conductive layer 134 is preferably formed by a deposition method such as PVD or CVD. The conductive layer 134 can be formed by a film method. , molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Conductive materials such as ZnO, ZnSe, and scandium, as well as their alloys and compounds (e.g., nitrides) are examples of such materials. can be done.

[0078] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method has a boundary. The oxide film on the surface is reduced, and the lower electrode (here, the source electrode or drain electrode 130a, A function of reducing the contact resistance with the source electrode or drain electrode 130b, electrode 130c, etc. In addition, the titanium nitride film formed thereafter has a burr-free property that suppresses the diffusion of the conductive material. In addition, after forming a barrier film using titanium or titanium nitride, etc., plating is performed. The copper film may be formed by a method.

[0079] After the conductive layer 134 is formed, the conductive layer 13 is etched or CMP is performed. A part of the insulating layer 132 is removed to expose the electrodes 136a, 136b, and 134. 6c, a gate electrode 136d is formed (see FIG. 4(C)). The electrode 136a, the electrode 136b, the electrode 136c, and the gate electrode 136d are formed by removing the portions. When forming, it is desirable to process so that the surface becomes flat. Thus, the surface of the insulating layer 132 , the electrodes 136a, 136b, 136c, and the gate electrode 136d is planarized By doing so, in subsequent processes, it becomes possible to form good electrodes, wirings, insulating layers, semiconductor layers, etc. .

[0080] Next, a gate insulating layer 138 is formed so as to cover the insulating layer 132, the electrodes 136a, 136b, 136c, and the gate electrode 136d (see Fig. 4(D)). The gate insulating layer 138 Can be formed using a CVD method, a sputtering method, or the like. Also, the gate insulating layer 138 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, Hafnium oxide, tantalum oxide, etc. Note that the gate insulating layer 138 may have a single-layer structure or a laminated structure. For example, as a source gas , a gate insulating layer 138 made of silicon oxynitride can be formed by plasma CVD using silane (SiH4), oxygen, and nitrogen. The thickness of the gate insulating layer 138 is not particularly limited , but can be, for example, 10 nm or more and 500 nm or less. In the case of a laminated structure , for example, it is preferable to form a laminate of a first gate insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer having a film thickness of 5 nm or more and 300 nm or less on the first gate insulating layer.

[0081] Note that an oxide semiconductor (highly purified oxide semiconductor) that has been i-type or substantially i-type by removing impurities is extremely sensitive to interface levels and interface charges. Therefore, when using such an oxide semiconductor for an oxide semiconductor layer, the interface with the gate insulating layer is important ​​​​​That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high quality There will be a demand for quality improvement.

[0082] For example, the high-density plasma CVD method using microwaves (2.45 GHz) produces dense, high-insulation-voltage This is advantageous in that a high quality gate insulating layer 138 can be formed. The intimate contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be made to be a good thing.

[0083] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and interface characteristics can be improved by heat treatment after formation. In any case, the film quality of the gate insulating layer 138 is good. At the same time, the interface state density with the oxide semiconductor layer can be reduced to form a good interface. It is sufficient to form the following.

[0084] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias and thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, The bond with the main component of is broken by a strong electric field (B: bias) and high temperature (T: temperature), and the generated The dangling bonds induce a drift in the threshold voltage (Vth).

[0085] In response to this, impurities in oxide semiconductors, particularly hydrogen and water, should be eliminated as much as possible, and the above-mentioned By improving the interface characteristics with the base insulating layer, a stable transistor is produced even in the BT test. It is possible to obtain the data.

[0086] Next, an oxide semiconductor layer is formed over the gate insulating layer 138, and the oxide semiconductor layer is processed by a method such as etching using a mask to form an island-shaped oxide semiconductor layer 140 (see FIG. 4(E)).

[0087] As the oxide semiconductor layer, an In-Ga-Zn-O-based, In-Sn-Zn-O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn-Al-Zn-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor layer, particularly an amorphous oxide semiconductor layer, is preferably used. In this embodiment, an amorphous oxide semiconductor layer is formed by sputtering using a target for forming an In-Ga-Zn-O-based oxide semiconductor film. Note that crystallization can be suppressed by adding silicon to the amorphous oxide semiconductor layer. Thus, for example, a target containing 2% to 10% by weight of SiO2 may be used to form the oxide semiconductor layer.

[0088] As a target for manufacturing the oxide semiconductor layer by sputtering, for example, a target of a metal oxide mainly containing zinc oxide can be used. Also, a target for forming an oxide semiconductor film containing In, Ga, and Zn (as a composition ratio, In2O3:Ga2O3:ZnO = 1:1:1 [mol%], In:Ga:Zn = 1:1:0.5 [atom%]), etc. can be used. Also, as a target for forming an oxide semiconductor film containing In, Ga, and Zn, In:Ga:Zn = 1:1:1 [atom%], or In:Ga ​​​​​​​​​​​​​​​:A target having a composition ratio of Zn=1:1:2 [atom%] etc. may be used. Acid The filling rate of the target for forming an oxide semiconductor film is 90% or more and 100% or less, preferably 95% or more (for example, 99.9%). By using a target for forming an oxide semiconductor film with a high filling rate a dense oxide semiconductor layer is formed.

[0089] The formation atmosphere of the oxide semiconductor layer is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically it is preferable to use a high-purity gas in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of about ppm (preferably about ppb).

[0090] When forming the oxide semiconductor layer, a substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering is reduced. Then, a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber is introduced, and a metal oxide is used as a target to form the oxide semiconductor layer. To remove the residual moisture in the processing chamber it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump , or a titanium sublimation pump can be used. Also, as an exhaust means, a turbo pump with a cold trap added may be used. A film formation chamber evacuated using a cryopump contains, for example, a compound containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably Compounds containing carbon atoms, etc. are exhausted, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. The concentration of impurities contained in the layer can be reduced.

[0091] As the formation conditions, for example, the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the DC (direct current) power is 0.5 kW, the atmosphere is an oxygen (oxygen flow rate ratio 100%) atmosphere, and the like conditions can be applied. When a pulsed DC (direct current) power supply is used, the powdery substances (also called particles, dust) generated during film formation can be reduced, and the film thickness distribution also becomes uniform which is preferable. The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, so the thickness may be appropriately selected according to the material used.

[0092] Before forming the oxide semiconductor layer by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove the dust adhering to the surface of the gate insulating layer 138. Here, reverse sputtering means a method of modifying the surface by colliding ions with the processing surface, contrary to the normal sputtering where ions are collided with the sputtering target. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate and the like. Note that an atmosphere such as nitrogen, helium, or oxygen may be used instead of the argon atmosphere.

[0093] For the etching of the above oxide semiconductor layer, either dry etching or wet etching It may also be used. Of course, both can also be used in combination. Etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that it can be etched into a desired shape.

[0094] Examples of the etching gas used for dry etching include gases containing chlorine (chlorine-based gases, such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc.). Also, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF 3), etc.), hydrogen bromide (HBr), oxygen (O2), and gases obtained by adding noble gases such as helium (He) and argon (Ar) to these gases may also be used.

[0095] As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) are appropriately set so that it can be etched into a desired shape.

[0096] Examples of the etching solution used for wet etching include a solution mixed with phosphoric acid, acetic acid, and nitric acid, and ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2). Also, an etching solution such as ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0097] ​​​​​​​​Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. By this first heat treatment it is possible to dehydrate or dehydrogenate the oxide semiconductor layer. The temperature of the first heat treatment is set to 300°C or higher and 750°C or lower, preferably 400°C or higher and less than the strain point of the substrate. For example, the substrate is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 140 is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 140 is prevented from coming into contact with the atmosphere and re-mixing of water or hydrogen is prevented.

[0098] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation. For example, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the object to be treated by heat treatment are used.

[0099] For example, as the first heat treatment, a GRTA treatment may be performed in which the substrate is introduced into an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then taken out of the inert gas. Using the GRTA treatment enables high-temperature heat treatment in a short time. Also, a short-time

[0099] For example, as the first heat treatment, a GRTA treatment may be performed in which the substrate is introduced into an inert gas heated to a high temperature of 650°C to 700°C, heated for several minutes, and then taken out of the inert gas. Using the GRTA treatment enables high-temperature heat treatment in a short time. Also, a short-time heating treatment can be achieved. heating treatment can be achieved. Since it is a heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0100] The first heat treatment is preferably carried out in an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc.) and containing no water, hydrogen, etc. For example, the purity of nitrogen or a noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0101] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become microcrystalline or polycrystalline. For example, it may become an oxide semiconductor layer of microcrystals with a crystallization rate of 90% or more, or 80 % or more. Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer containing no crystal components in some cases.

[0102] Also, there may be a case where an oxide semiconductor layer is formed in which microcrystals (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in an amorphous oxide semiconductor (for example, the surface of the oxide semiconductor layer).

[0103] Also, it is possible to change the electrical characteristics of the oxide semiconductor layer by arranging microcrystals in the amorphous state. For example, when forming an oxide semiconductor layer using a target for forming an In-Ga-Zn-O-based oxide semiconductor film, the electrical characteristics of the oxide semiconductor layer can be changed by forming a microcrystalline portion in which crystal grains of In2Ga2ZnO7 having electrical anisotropy are oriented. ​

[0104] More specifically, for example, the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer. By orienting the oxide semiconductor layer in a direction parallel to the surface of the oxide semiconductor layer, the electrical conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This can improve the insulating property in the direction perpendicular to the surface of the oxide semiconductor layer. The microcrystal parts have a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. has.

[0105] Note that the oxide semiconductor layer having the above-described microcrystal portion is a GRTA-treated oxide semiconductor layer. It can be formed by surface heating. Also, the Zn content is higher than the In or Ga content. A more suitable formation can be achieved by using a smaller sputtering target.

[0106] The first heat treatment for the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0107] The heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Such dehydration and dehydrogenation treatments can also be called dehydration treatments, dehydrogenation treatments, etc. The process is performed by forming a source electrode or a drain electrode on the oxide semiconductor layer 140 after forming the oxide semiconductor layer. After laminating electrodes, forming a protective insulating layer on the source electrode or drain electrode, etc. In addition, such dehydration and dehydrogenation treatments can be carried out at the timing of The treatment may be carried out not only once but also multiple times.

[0108] Next, source electrodes or drain electrodes 142a are formed so as to be in contact with the oxide semiconductor layer 140. Source electrodes or drain electrodes 142b are formed (see FIG. 4(F)). The source electrodes or drain electrodes 142a and the source electrodes or drain electrodes 142b can be formed by forming a conductive layer so as to cover the oxide semiconductor layer 140 and then selectively etching the conductive layer.

[0109] The conductive layer can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. Further, as the material of the conductive layer, elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, alloys containing the above-described elements as components, etc. can be used. Materials selected from any one or more of manganese, magnesium, zirconium, beryllium, thorium can also be used. Further, materials in which an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium is combined singly or in plural with aluminum can also be used. The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned. Here, for the exposure during mask formation used for etching, it is preferable to use ultraviolet light, KrF laser light, or ArF laser light.

[0110]

[0111] The channel length (L) of the transistor is the lower end portion of the source electrode or drain electrode 142a and It is determined by the distance from the lower end of the source electrode or the drain electrode 142b. Note that When performing exposure with a channel length (L) of less than 25 nm, extreme ultraviolet rays with a very short wavelength of several nm to several tens of nm are used for mask formation exposure. Exposure with extreme ultraviolet rays has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length (L) of the transistors formed later to be 10 nm or more and 1000 nm or less, which can increase the operating speed of the circuit. Furthermore, since the off-current value is extremely small, the power consumption does not increase. Note that when etching the conductive layer, the respective materials and etching conditions are appropriately adjusted so that the oxide semiconductor layer 140 is not removed. Depending on the materials and etching conditions, a part of the oxide semiconductor layer 140 may be etched in this process, resulting in an oxide semiconductor layer having a groove (recess).

[0112]

[0113] In addition, an oxide conductive layer may be formed between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a, or between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142b. The oxide conductive layer and the metal layer for forming the source electrode or the drain electrode 142a or the source electrode or the drain electrode 142b can be formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region, thus realizing high-speed operation of the transistor.

[0114] ​​​​​​​​​​In addition, in order to reduce the number of masks used and the number of processes, exposure is performed such that the transmitted light has multiple intensities. A resist mask may be formed by a multi-tone mask, which is a mask, and the etching process may be performed using this resist mask. The resist mask formed using the multi-tone mask has a shape (step shape) with multiple thicknesses, and since the shape can be further deformed by ashing, it can be used for a plurality of etching processes for processing into different patterns. That is, a resist mask corresponding to at least two or more different patterns can be formed by one multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, so that the process can be simplified.

[0115] Note that after the above process, it is preferable to perform plasma treatment using a gas such as N2O, N2, or Ar. By this plasma treatment, water or the like adhering to the surface of the exposed oxide semiconductor layer is removed. Also, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0116] Next, without exposing to the atmosphere, a protective insulating layer 144 in contact with a part of the oxide semiconductor layer 140 is formed (see FIG. 4(G)).

[0117] The protective insulating layer 144 can be formed by appropriately using a method such as sputtering that does not mix impurities such as water and hydrogen into the protective insulating layer 144. Also, its thickness is at least 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. Also, its structure may be a single-layer structure, It may be a laminated structure. The substrate temperature when forming the protective insulating layer 144 is preferably room temperature or higher and 300 °C or lower, and the atmosphere is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere , or a mixed atmosphere of a noble gas (typically argon) and oxygen.

[0118] When hydrogen is contained in the protective insulating layer 144, intrusion of the hydrogen into the oxide semiconductor layer, extraction of oxygen in the oxide semiconductor layer by hydrogen, etc. may occur, and the back channel side of the oxide semiconductor layer may have a lower resistance, and there is a possibility that a parasitic channel may be formed. Therefore, it is important that the protective insulating layer 1 44 contains as little hydrogen as possible, and hydrogen is not used in the formation method.

[0119] Also, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. This is to prevent the oxide semiconductor layer 140 and the protective insulating layer 144 from containing hydrogen, hydroxyl groups or moisture.

[0120] To remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, or a titanium sublimation pump. Also, as an exhaust means, a turbo pump with a cold trap added may be used. When the film formation chamber is evacuated using a cryopump, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2 O), etc. are removed, so the concentration of impurities contained in the protective insulating layer 144 formed in the film formation chamber can be reduced.

[0121] As the sputtering gas used when forming the protective insulating layer 144, hydrogen, water, hydroxyl groups or It is preferable to use a high-purity gas in which impurities such as hydrides are removed to a concentration of about ppm (preferably about ppb). It is preferable to use a high-purity gas in which impurities such as hydrides are removed to a concentration of about ppm (preferably about ppb).

[0122] Next, it is desirable to perform a second heat treatment (preferably at 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) in an inert gas atmosphere or an oxygen gas atmosphere. For example Next, it is desirable to perform a second heat treatment (preferably at 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) in an inert gas atmosphere or an oxygen gas atmosphere. For example a second heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere. Performing the second heat treatment can reduce the variation in the electrical characteristics of the transistor. a second heat treatment is performed at 250 °C for 1 hour in a nitrogen atmosphere. Performing the second heat treatment can reduce the variation in the electrical characteristics of the transistor.

[0123] Also, heat treatment may be performed in the atmosphere at 100 °C or higher and 200 °C or lower for 1 hour or more and 30 hours or less. This heat treatment may be performed by maintaining a constant heating temperature, or by repeating the temperature increase from room temperature to a heating temperature of 100 °C or higher and 200 °C or lower and the temperature decrease from the heating temperature to room temperature a plurality of times. This heat treatment may be performed by maintaining a constant heating temperature, or by repeating the temperature increase from room temperature to a heating temperature of 100 °C or higher and 200 °C or lower and the temperature decrease from the heating temperature to room temperature a plurality of times. Also, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing the heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment may be performed instead of the second heat treatment, or may be performed before or after the second heat treatment. Performing the heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment may be performed instead of the second heat treatment, or may be performed before or after the second heat treatment. Performing the heat treatment under reduced pressure can shorten the heating time. Note that this heat treatment may be performed instead of the second heat treatment, or may be performed before or after the second heat treatment.

[0124] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Fig. 5(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, it can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. After the formation of the interlayer insulating layer 146, it is desirable to flatten its surface by a method such as CMP or etching. Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Fig. 5(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, it can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. After the formation of the interlayer insulating layer 146, it is desirable to flatten its surface by a method such as CMP or etching. Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Fig. 5(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, it can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. After the formation of the interlayer insulating layer 146, it is desirable to flatten its surface by a method such as CMP or etching. Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Fig. 5(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, it can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. After the formation of the interlayer insulating layer 146, it is desirable to flatten its surface by a method such as CMP or etching. Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Fig. 5(A)). The interlayer insulating layer 146 can be formed using a PVD method, a CVD method, or the like. Also, it can be formed using an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. After the formation of the interlayer insulating layer 146, it is desirable to flatten its surface by a method such as CMP or etching.

[0125] Next, openings reaching the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138 are formed for the electrodes 1 36a, the electrodes 136b, the electrodes 136c, the source electrode or the drain electrode 142a, the source electrode or the drain electrode 142b, and a conductive layer 148 is formed so as to fill the openings (see FIG. 5(B)). The above openings can be formed by a method such as etching using a mask . The mask can be formed by a method such as exposure using a photomask . As the etching, either wet etching or dry etching can be used, but from the viewpoint of microfabrication, it is preferable to use dry etching . The formation of the conductive layer 148 can be performed using a film formation method such as PVD method or CVD method . Examples of the material that can be used for the formation of the conductive layer 148 include conductive materials such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, and alloys and compounds (for example, nitrides) thereof . Specifically, for example, a method can be applied in which a titanium film is thinly formed by PVD method in a region including the openings, a titanium nitride film is thinly formed by CVD method, and then a tungsten film is formed so as to fill the openings . Here, the titanium film formed by PVD method has a function of reducing the interfacial oxide film and reducing the contact resistance with the lower electrodes (here, the electrodes 136a, the electrodes 136b, the electrodes 136c, the source electrode or the drain electrode 142a, the source electrode or the drain electrode 142b). Further, the titanium nitride film formed thereafter has a barrier function of suppressing the diffusion of the conductive material . Also, barrier films made of titanium, titanium nitride, etc

[0126] . Specifically, for example, a titanium film is thinly formed by PVD method in a region including the openings, a titanium nitride film is thinly formed by CVD method, and then a tungsten film is formed so as to fill the openings . Here, the titanium film formed by PVD method reduces the interfacial oxide film and reduces the contact resistance with the lower electrodes (here, the electrodes 136a, the electrodes 136b, the electrodes 136c, the source electrode or the drain electrode 142a, the source electrode or the drain electrode 142b). Further, the titanium nitride film formed thereafter has a barrier function of suppressing the diffusion of the conductive material . Also, barrier films made of titanium, titanium nitride, etc . Here, the titanium film formed by PVD method reduces the interfacial oxide film and reduces the contact resistance with the lower electrodes (here, the electrodes 136a, the electrodes 136b, the electrodes 136c, the source electrode or the drain electrode 142a, the source electrode or the drain electrode 142b). Further, the titanium nitride film formed thereafter has a barrier function of suppressing the diffusion of the conductive material . Also, barrier films made of titanium, titanium nitride, etc After forming the insulating film, a copper film may be formed by plating.

[0127] After the conductive layer 148 is formed, the conductive layer 148 is removed by a method such as etching or CMP. A part of the interlayer insulating layer 146 is removed to expose the electrodes 150a, 150b, and 15 Electrode 150c, electrode 150d, and electrode 150e are formed (see FIG. 5(C)). 48 is removed to form electrodes 150a, 150b, 150c, 150d, and When forming 150e, it is desirable to process it so that the surface is flat. The interlayer insulating layer 146, the electrodes 150a, 150b, 150c, 150d, By flattening the surface of the electrode 150e, it is possible to obtain good electrodes, wiring, and insulation in the subsequent processes. It is possible to form a layer, a semiconductor layer, etc.

[0128] Further, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, the electrode 150d, and the electrode 150e are formed, and the After forming the conductive layer as described above, a part of the conductive layer is removed by a method such as etching or CMP. , the insulating layer 152 is exposed, and the electrodes 154a, 154b, 154c, and 154 This step is the same as that for forming the electrodes 150a, etc. Therefore, I will omit the details.

[0129] In the case where the transistor 162 is manufactured by the above-described method, the hydrogen concentration in the oxide semiconductor layer 140 is Degree is 5 x 10 19 / cm 3 and the off-current of the transistor 162 is 1×10 -13 A or less. In this way, the hydrogen concentration is sufficiently reduced and the oxide semiconductor is highly purified. By applying the conductor layer 140, a transistor 162 with excellent characteristics can be obtained. In addition, a semiconductor device with excellent characteristics having a transistor 160 using a material other than an oxide semiconductor at the lower part and a transistor 162 using an oxide semiconductor at the upper part can be fabricated. possible.

[0130] Note that as a semiconductor material that can be a comparison target with an oxide semiconductor, there is silicon carbide (for example, 4H -SiC). The oxide semiconductor and 4H-SiC have some common points. Carrier density is one example. Using the Fermi-Dirac distribution at room temperature, the minority carriers of the oxide semiconductor are estimated to be about 10 / cm , which is an extremely low value similar to 6.7×10 -7 / cm 3 in 4H-SiC. Comparing with the intrinsic carrier density of silicon (about 1.4×10 / cm -11 ), it can be well understood that the degree is far from comparable. 3 10 / cm 3

[0131] In addition, the energy band gap of the oxide semiconductor is 3.0 to 3.5 eV, and the energy band gap of 4H-S iC is 3.26 eV. Therefore, also in terms of being a wide-gap semiconductor, the oxide semiconductor and silicon carbide have something in common.

[0132] On the other hand, there are extremely large differences between the oxide semiconductor and silicon carbide. That is the process temperature. In a semiconductor process using silicon carbide, generally an activation heat treatment at 1500°C to 20 00°C is required. Therefore, for a laminated structure with semiconductor elements using other semiconductor materials, Manufacturing is difficult. At such high temperatures, semiconductor substrates, semiconductor elements, etc. will be destroyed. This is because. On the other hand, oxide semiconductors can be manufactured by heat treatment at 300 to 500 °C (below the glass transition temperature, at most even about 700 °C). After forming an integrated circuit using other semiconductor materials, it becomes possible to form semiconductor elements using oxide semiconductors.

[0133] Also, different from the case of silicon carbide, it has the advantage that a substrate with low heat resistance such as a glass substrate can be used. Furthermore, in terms of not requiring heat treatment at high temperatures, it has the advantage that the energy cost can be made sufficiently low compared to silicon carbide.

[0134] In the case of oxide semiconductors, many physical property studies such as DOS (density of state) have been conducted, but these studies do not include the idea of sufficiently reducing DOS itself. In one aspect of the disclosed invention, water and hydrogen that can cause DOS are removed from the oxide semiconductor to produce a highly purified oxide semiconductor. This is based on the idea of sufficiently reducing DOS itself. And this enables the production of extremely excellent industrial products.

[0135] Furthermore, by supplying oxygen to the unbonded hands of metals generated by oxygen deficiency and reducing DOS due to oxygen defects, it is also possible to obtain a more highly purified (type-i) oxide semiconductor. For example, it is possible to form an oxygen-excess oxide film in close contact with the channel formation region and supply oxygen from the oxide film to reduce DOS due to oxygen defects.

[0136] ​​​​​​​​​​Defects in oxide semiconductors are considered to be caused by shallow levels of 0.1 to 0.2 eV below the conduction band due to excessive hydrogen, deep levels due to oxygen deficiency, and the like. To eliminate these defects, the technical concept of thoroughly removing hydrogen and sufficiently supplying oxygen is correct. In addition, although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, an i-type is achieved by removing impurities, particularly water and hydrogen. In this regard, it can be said that this is not the same as making an i-type by adding impurities like silicon, and it includes a novel technical concept. In addition, although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, an i-type is achieved by removing impurities, particularly water and hydrogen. In this regard, it can be said that this is not the same as making an i-type by adding impurities like silicon, and it includes a novel technical concept. In addition, although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, an i-type is achieved by removing impurities, particularly water and hydrogen. In this regard, it can be said that this is not the same as making an i-type by adding impurities like silicon, and it includes a novel technical concept.

[0137] In addition, although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, an i-type is achieved by removing impurities, particularly water and hydrogen. In this regard, it can be said that this is not the same as making an i-type by adding impurities like silicon, and it includes a novel technical concept. In addition, although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, an i-type is achieved by removing impurities, particularly water and hydrogen. In this regard, it can be said that this is not the same as making an i-type by adding impurities like silicon, and it includes a novel technical concept. In addition, although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, an i-type is achieved by removing impurities, particularly water and hydrogen. In this regard, it can be said that this is not the same as making an i-type by adding impurities like silicon, and it includes a novel technical concept.

[0138] In this embodiment, a bottom gate type structure is shown as the structure of the transistor 162, but one aspect of the present invention is not limited to this. For example, a top gate type structure can also be used as the structure of the transistor 162. Further, a dual gate type structure having two gate electrode layers disposed via a gate insulating layer above and below the channel formation region can also be used as the structure of the transistor 162. In this embodiment, a bottom gate type structure is shown as the structure of the transistor 162, but one aspect of the present invention is not limited to this. For example, a top gate type structure can also be used as the structure of the transistor 162. Further, a dual gate type structure having two gate electrode layers disposed via a gate insulating layer above and below the channel formation region can also be used as the structure of the transistor 162. In this embodiment, a bottom gate type structure is shown as the structure of the transistor 162, but one aspect of the present invention is not limited to this. For example, a top gate type structure can also be used as the structure of the transistor 162. Further, a dual gate type structure having two gate electrode layers disposed via a gate insulating layer above and below the channel formation region can also be used as the structure of the transistor 162. In this embodiment, a bottom gate type structure is shown as the structure of the transistor 162, but one aspect of the present invention is not limited to this. For example, a top gate type structure can also be used as the structure of the transistor 162. Further, a dual gate type structure having two gate electrode layers disposed via a gate insulating layer above and below the channel formation region can also be used as the structure of the transistor 162. In this embodiment, a bottom gate type structure is shown as the structure of the transistor 162, but one aspect of the present invention is not limited to this. For example, a top gate type structure can also be used as the structure of the transistor 162. Further, a dual gate type structure having two gate electrode layers disposed via a gate insulating layer above and below the channel formation region can also be used as the structure of the transistor 162.

[0139] <Conduction mechanism of a transistor using an oxide semiconductor> Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 24 to 27. It should be noted that the following description is only a consideration, and it is appended that the validity of the invention is not denied based on this. Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 24 to 27. It should be noted that the following description is only a consideration, and it is appended that the validity of the invention is not denied based on this. Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 24 to 27. It should be noted that the following description is only a consideration, and it is appended that the validity of the invention is not denied based on this.

[0140] FIG. 24 is a cross-sectional view of a dual gate type transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating layer (GI1) on a gate electrode layer (GE1), and a source electrode (S) and a drain electrode (D) are provided thereon. FIG. 24 is a cross-sectional view of a dual gate type transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating layer (GI1) on a gate electrode layer (GE1), and a source electrode (S) and a drain electrode (D) are provided thereon. FIG. 24 is a cross-sectional view of a dual gate type transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating layer (GI1) on a gate electrode layer (GE1), and a source electrode (S) and a drain electrode (D) are provided thereon. is provided. Further, a gate insulating layer (GI2) is provided so as to cover the oxide semiconductor layer (OS), the source electrode (S), and the drain electrode (D ), and a gate electrode (GE2) is provided over the oxide semiconductor layer (OS) with the gate insulating layer (GI2) interposed therebetween.

[0141] FIG. 25 shows an energy band diagram (schematic diagram) in the A-A' cross section of FIG. 24. FIG. 2 5(A) shows the case where the potential difference between the source and the drain is zero (equipotential, V D = 0 V), and FIG. 25(B) shows the case where the potential of the drain is made higher than that of the source (V > 0). D > 0) is shown .

[0142] FIG. 26 shows an energy band diagram (schematic diagram) in the B-B' cross section of FIG. 24. FIG. 26(A) shows a state in which a positive potential (+V G ) is applied to the gate (G1), and shows an on state in which carriers (electrons) flow between the source and the drain. Further, FIG. 26 (B) shows a state in which a negative potential (-V G ) is applied to the gate (G1), and shows a case in which it is in an off state (a state in which few carriers do not flow).

[0143] FIG. 27 shows the relationship between the vacuum level, the work function (φ M ) of the metal, and the electron affinity (χ) of the oxide semiconductor .

[0144] Conventional oxide semiconductors are n-type, and their Fermi level (E f ) is separated from the intrinsic Fermi level (E ) located at the center of the band gap and is located closer to the conduction band. Note that i in the oxide semiconductor, a part of hydrogen becomes a donor, and it is known to be one of the factors for n-type conversion. is known. is.

[0145] On the other hand, an oxide semiconductor according to one aspect of the disclosed invention removes hydrogen, which is a factor in n-type formation, from the oxide semiconductor, and highly purifies it so that elements (impurity elements) other than the main component of the oxide semiconductor are not contained as much as possible, making it intrinsic (i-type), or as close to intrinsic as possible. That is, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible to achieve a highly purified i-type (intrinsic semiconductor) or approach it. is characterized by this. As a result, the Fermi level (E ) can be made comparable to the intrinsic Fermi level (E ). f ) i ) can be made.

[0146] When the bandgap (E g ) of the oxide semiconductor is 3.15 eV, the electron affinity (χ) is said to be 4.3 eV. The work function of titanium (Ti) constituting the source electrode and the drain electrode is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons. That is, when the work function of the metal (φ

[0147] ) and the electron affinity (χ) of the oxide semiconductor are equal, when the two M ) come into contact, an energy band diagram (schematic diagram) as shown in Fig. 25(A) is shown. When the positive potential is applied to the drain, electrons cross the barrier (h) and are injected into the oxide semiconductor and flow toward the drain. The height of the barrier (h) changes depending on the gate voltage and the drain voltage, but when a positive drain voltage is

[0148] In Fig. 25(B), the black circles (●) indicate electrons. is applied, the electrons cross the barrier (h) and are injected into the oxide semiconductor and flow toward the drain. The height of the barrier (h) changes depending on the gate voltage and the drain voltage, but when a positive drain voltage is applied, the electrons cross the barrier (h) and are injected into the oxide semiconductor and flow toward the drain. The height of the barrier (h) changes depending on the gate voltage and the drain voltage, but when a positive drain voltage is When impressed, it becomes lower than half of the barrier height in Fig. 25(A) without voltage application, i.e., the bandgap (E ) g .

[0149] At this time, electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the energetically stable lowest part of the oxide semiconductor) as shown in Fig. 26(A).

[0150] Also, as shown in Fig. 26(B), when a negative potential is applied to the gate electrode (G1), since the number of minority carriers, holes, is substantially zero, the current becomes a value approaching zero infinitely.

[0151] By highly purifying so that elements (impurity elements) other than the main component of the oxide semiconductor are not contained as much as possible, it becomes intrinsic (i-type) or substantially intrinsic, and thus the interface characteristics with the gate insulating layer are manifested. Therefore, the gate insulating layer is required to be able to form a good interface with the oxide semiconductor. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power frequency in the VHF band to microwave band, or an insulating layer formed by a sputtering method, etc. are preferably used.

[0152] By highly purifying the oxide semiconductor and making the interface between the oxide semiconductor and the gate insulating layer good, for example, when the channel width W of the transistor is 1×10 μm and the channel length L is 4 3μm, an off-current of 1×10 A or less and a subthreshold swing value (S value) of 0.1V / dec. -13 (gate insulating layer thickness: 100nm) can be realized at room temperature.

[0153] ​​​​​​​​​In this way, by highly purifying so that elements other than the main component of the oxide semiconductor (impurity elements) are not contained as much as possible, the operation of the thin film transistor can be made good.

[0154] <Modification example> Figures 6 to 9 show modification examples of the configuration of the semiconductor device. In the following, as a modification example, the configuration of the transistor 162 different from the above will be described. That is, the configuration of the transistor 160 is the same as the above.

[0155] Figure 6 shows a semiconductor device having a gate electrode 136d under the oxide semiconductor layer 140, and a source electrode or a drain electrode 142a, and a source electrode or a drain electrode 142b in contact with the oxide semiconductor layer 14 0 on the lower surface of the oxide semiconductor layer 140. Note that since the planar structure may be appropriately changed corresponding to the cross section, here, only the cross section will be shown.

[0156] As a major difference between the configuration shown in Figure 6 and the configuration shown in Figure 2, the connection of the source electrode or drain electrode 142a, and the source electrode or drain electrode 142b, and the oxide semiconductor layer 140 is located. That is, in the configuration shown in Figure 2, on the upper surface of the oxide semiconductor layer 140 the source electrode or drain electrode 142a, and the source electrode or drain electrode 142b are in contact, whereas in the configuration shown in Figure 6, on the lower surface of the oxide semiconductor layer 140, the source electrode or drain electrode 142a, and the source electrode or drain electrode 142b are in contact. And due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. is different. The details of each component are the same as those in Figure 2. ​​

[0157] Specifically, the semiconductor device shown in FIG. 6 includes a gate electrode 136d provided on an interlayer insulating layer 128, a gate insulating layer 138 provided on the gate electrode 136d, and a source electrode or a drain electrode 142a, a source electrode or a drain electrode 142b provided on the gate insulating layer 138, and an oxide semiconductor layer 140 in contact with the upper surfaces of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b. 6d, a gate insulating layer 138 provided on the gate electrode 136d, and the gate insulating layer 138 On the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, and the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, and an oxide semiconductor layer 140 in contact with the upper surfaces of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b.

[0158] Here, the gate electrode 136d is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, an electrode 136a is formed in contact with the source electrode or drain electrode 130a, an electrode 136b is formed in contact with the source electrode or drain electrode 130b, and an electrode 136c is formed in contact with the electrode 130c. In addition, on the transistor 162, a protective insulating layer 144 is provided so as to be in contact with a part of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, openings reaching the source electrode or drain electrode 142a and the source electrode or drain electrode 142b are provided in the protective insulating layer 144 and the interlayer insulating layer 146, and through the openings, electrodes 150d and 150e are formed in contact with the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Similarly to the electrodes 150d and 150e, electrodes 150a, 150b, and 150c in contact with the electrodes 136a, 136b, and 136c are formed through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. In contact with the source electrode or drain electrode 130a, electrode 136a is formed, in contact with the source electrode or drain electrode 130b, electrode 136b is formed, and in contact with the electrode 130c, electrode 136c is formed. Here, the gate electrode 136d is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, an electrode 136a is formed in contact with the source electrode or drain electrode 130a, an electrode 136b is formed in contact with the source electrode or drain electrode 130b, and an electrode 136c is formed in contact with the electrode 130c.

[0159] In addition, on the transistor 162, a protective insulating layer 144 is provided so as to be in contact with a part of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, openings reaching the source electrode or drain electrode 142a and the source electrode or drain electrode 142b are provided in the protective insulating layer 144 and the interlayer insulating layer 146, and through the openings, electrodes 150d and 150e are formed in contact with the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Similarly to the electrodes 150d and 150e, electrodes 150a, 150b, and 150c in contact with the electrodes 136a, 136b, and 136c are formed through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146. On the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, and the source electrode or drain electrode 142a, the source electrode or drain electrode 142b, and an oxide semiconductor layer 140 in contact with the upper surfaces of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Here, the gate electrode 136d is provided so as to be embedded in an insulating layer 132 formed on the interlayer insulating layer 128. Similarly to the gate electrode 136d, an electrode 136a is formed in contact with the source electrode or drain electrode 130a, an electrode 136b is formed in contact with the source electrode or drain electrode 130b, and an electrode 136c is formed in contact with the electrode 130c. In addition, on the transistor 162, a protective insulating layer 144 is provided so as to be in contact with a part of the oxide semiconductor layer 140, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, openings reaching the source electrode or drain electrode 142a and the source electrode or drain electrode 142b are provided in the protective insulating layer 144 and the interlayer insulating layer 146, and through the openings, electrodes 150d and 150e are formed in contact with the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. Similarly to the electrodes 150d and 150e, electrodes 150a, 150b, and 150c in contact with the electrodes 136a, 136b, and 136c are formed through the openings provided in the gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146.

[0160] Also, an insulating layer 152 is provided on the interlayer insulating layer 146, and electrodes 154a, 154b, 154c, and 154d are provided so as to be embedded in the insulating layer 152. Here, the electrode 154a is in contact with the electrode 150a, the electrode 154b is in contact with the electrode 150 b, the electrode 154c is in contact with the electrodes 150c and 150d, and the electrode 1 54d is in contact with the electrode 150e.

[0161] FIG. 7 shows an example of the configuration of a semiconductor device having a gate electrode 136d on an oxide semiconductor layer 140. Here, FIG. 7(A) shows an example of a configuration in which a source electrode or a drain electrode 142a or a source electrode or a drain electrode 142b is in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 140, and FIG. 7(B) shows a source electrode or a drain electrode 142 a or a source electrode or a drain electrode 142b is in contact with the oxide semiconductor layer 140 on the upper surface of the oxide semiconductor layer 140.

[0162] A major difference between the configuration shown in FIGS. 2 and 6 and the configuration shown in FIG. 7 is that a gate electrode 136d is provided on the oxide semiconductor layer 140. Also, a major difference between the configuration shown in FIG. 7(A) and the configuration shown in FIG. 7(B) is that the source electrode or drain electrode 142a or the source electrode or drain electrode 142b contacts the oxide semiconductor layer 140 on either the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, the arrangements of other electrodes, insulating layers, etc. are different. The details of each component are the same as those in FIG. 2 and the like.

[0163] ​Specifically, the semiconductor device shown in FIG. 7(A) includes a source electrode or a drain electrode 142a provided on the interlayer insulating layer 128, a source electrode or a drain electrode 142b, and a source electrode or a drain electrode 142a, a source electrode or a drain electrode 142b, and an oxide semiconductor layer 140 in contact with the upper surface of the source electrode or the drain electrode 142a, a source electrode or a drain electrode 142b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and a gate electrode 136d in a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138. And it has.

[0164] Also, in FIG. 7(B), an oxide semiconductor layer 140 provided on the interlayer insulating layer 128, and an oxide A source electrode or a drain electrode 1 provided so as to be in contact with the upper surface of the semiconductor layer 140 42a, a source electrode or a drain electrode 142b, an oxide semiconductor layer 140, a source electrode Or a drain electrode 142a, and a gate insulating layer 138 provided on the source electrode or the drain electrode 142b, and a region overlapping the oxide semiconductor layer 140 on the gate insulating layer 138 And a gate electrode 136d of the above, and has.

[0165] In addition, in the configuration shown in FIG. 7, there are cases where components are omitted compared to the configuration shown in FIG. 2 (for example, the electrode 150a, the electrode 154a, etc.). In this case, a secondary effect such as simplification of the manufacturing process can also be obtained. Of course, in the configuration shown in FIG. 2 and the like, it goes without saying that non-essential Components can be omitted.

[0166] FIG. 8 is an example of a configuration having a gate electrode 136d under the oxide semiconductor layer 140 when the size of the element is relatively large. In this case, since the requirements for surface flatness and coverage are relatively loose, wiring, electrodes, etc. are formed so as to be embedded in the insulating layer It is possible to do. So that.​​​ For example, the gate electrode 136 can be formed by patterning the conductive layer after it is formed. Although not shown here, it is possible to form the transistor 160 It is also possible to prepare the same.

[0167] The major difference between the configuration shown in FIG. 8(A) and the configuration shown in FIG. 8(B) is the source electrode or drain electrode. The source electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 140. The question is whether the contact is made on the lower or upper surface of the Due to these differences, the arrangement of other electrodes, insulating layers, etc. is also different. The details of the components are the same as those in FIG.

[0168] Specifically, in FIG. 8A, a gate electrode 136d is provided on the interlayer insulating layer 128, A gate insulating layer 138 is provided on the gate electrode 136d. The source or drain electrode 142a, the source or drain electrode 142 b, and the source or drain electrode 142a, the source or drain electrode 142b and an oxide semiconductor layer 140 in contact with the upper surface of the substrate.

[0169] In FIG. 8B, a gate electrode 136d is provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on the electrode 136d, and a gate electrode on the gate insulating layer 138 The oxide semiconductor layer 140 provided in a region overlapping with the oxide semiconductor layer 136d and the oxide semiconductor layer 140 A source electrode or drain electrode 142a provided in contact with the upper surface, a source electrode or a drain electrode 142b.

[0170] In addition, also in the configuration shown in FIG. 8, components may be omitted as compared with the configuration shown in FIG. 2 and the like. Also in this case, the effect of simplifying the manufacturing process can be obtained.

[0171] FIG. 9 is an example of a configuration having a gate electrode 136d on an oxide semiconductor layer 140 when the size of the element is relatively large. Also in this case, since the requirements for the surface flatness and coverage are relatively loose, it is not necessary to form wirings, electrodes, etc. by embedding them in the insulating layer. For example, by performing patterning after forming the conductive layer, it is possible to form the gate electrode 136d and the like. Although not shown here, the transistor 160 can be manufactured in the same manner. 36d and the like.

[0172] A major difference between the configuration shown in FIG. 9(A) and the configuration shown in FIG. 9(B) is whether the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b contact on the lower surface or the upper surface of the oxide semiconductor layer 140. And due to these differences, the arrangements of other electrodes, insulating layers, etc. are different. The details of each component are the same as those in FIG. 2 and the like.

[0173] Specifically, in FIG. 9(A), the source electrode or the drain electrode 142a provided on the interlayer insulating layer 128, the source electrode or the drain electrode 142b, the oxide semiconductor layer 140 in contact with the upper surface of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b, the gate insulating layer 138 provided on the source electrode or the drain electrode 142a, the source electrode or the drain electrode 142b, and the oxide semiconductor layer 140, and the gate insulating layer 13 42b, the gate insulating layer 138 provided on the oxide semiconductor layer 140, and the gate insulating layer 13 It has a gate electrode 136d provided in a region overlapping with the oxide semiconductor layer 140 on 8. It does.

[0174] Also, in FIG. 9(B), the oxide semiconductor layer 140 provided on the interlayer insulating layer 128 and the oxide A source electrode or drain electrode 1 42a, a source electrode or drain electrode 142b, and a source electrode or drain electrode 14 2a, a source electrode or drain electrode 142b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and a region provided in a region overlapping with the oxide semiconductor layer 140 on the gate insulating layer 138 A gate electrode 136d provided. It has.

[0175] Note that also in the configuration shown in FIG. 9, components may be omitted as compared with the configuration shown in FIG. 2 or the like. Also in this case, the effect of simplifying the manufacturing process can be obtained. It is.

[0176] As described above, according to one aspect of the disclosed invention, a semiconductor device with a new configuration is realized. In this embodiment, an example of forming by laminating the transistor 160 and the transistor 162 has been described, but the configuration of the semiconductor device is not limited to this. Also, in this embodiment Although an example in which the channel length directions of the transistor 160 and the transistor 162 are perpendicular to each other has been described, the positional relationship between the transistor 160 and the transistor 162 and the like are not limited to this. Further, the transistor 160 and the transistor 162 may be provided so as to overlap each other. It is not limited to this. Furthermore, the transistor 160 and the transistor 162 may be provided so as to overlap each other. It may be provided.

[0177] Also, in this embodiment, for simplicity of understanding, a semiconductor device with a minimum storage unit (1 bit) has been described, but the configuration of the semiconductor device is not limited to this. A plurality of semiconductor devices It is not limited to this. They can also be appropriately connected to form a more advanced semiconductor device. For example, by using a plurality of the above semiconductor devices, it is possible to form a NAND-type or NOR-type semiconductor device. The wiring configuration is not limited to that shown in FIG. 1 and can be changed as appropriate. arrangement is not limited to that shown in FIG. 1 and can be changed as appropriate. The semiconductor device according to this embodiment can hold information for an extremely long time due to the low off-current characteristics of the transistor 162. That is, the refresh operation required in a DRAM or the like is unnecessary, and power consumption can be suppressed. Further, it can be used as a substantially non-volatile semiconductor device.

[0178] Also, since information writing and the like are performed by the switching operation of the transistor 162, a high voltage is not required, and there is no problem of element degradation. Further, since information writing and erasing are performed by turning the transistor on and off, high-speed operation can be easily realized. Also, there is an advantage that the operation for erasing information required in a flash memory or the like is unnecessary. Moreover, since a transistor using a material other than an oxide semiconductor can operate at a sufficiently high speed, by using this, it is possible to read the stored content at high speed. The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments. The semiconductor device according to this embodiment can hold information for an extremely long time due to the low off-current characteristics of the transistor 162. That is, the refresh operation required in a DRAM or the like is unnecessary, and power consumption can be suppressed. Further, it can be used as a substantially non-volatile semiconductor device.

[0179] Also, since information writing and the like are performed by the switching operation of the transistor 162, a high voltage is not required, and there is no problem of element degradation. Further, since information writing and erasing are performed by turning the transistor on and off, high-speed operation can be easily realized. Also, there is an advantage that the operation for erasing information required in a flash memory or the like is unnecessary. Moreover, since a transistor using a material other than an oxide semiconductor can operate at a sufficiently high speed, by using this, it is possible to read the stored content at high speed. The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments. (Embodiment 2) In this embodiment, as a semiconductor device according to an aspect of the present invention, the circuit configuration and operation of a memory element will be described.

[0180] Moreover, since a transistor using a material other than an oxide semiconductor can operate at a sufficiently high speed, by using this, it is possible to read the stored content at high speed. The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

[0181] The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments. The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

[0182] (Embodiment 2) In this embodiment, as a semiconductor device according to an aspect of the present invention, the circuit configuration and operation of a memory element will be described. The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

[0183] Fig. 10 shows an example of a circuit diagram of a memory element (hereinafter also referred to as a memory cell) included in a semiconductor device. As shown in Fig. 10, the memory cell 200 includes a first wiring SL (source line), a second wiring BL (bit line), a third wiring S1 (first signal line), a fourth wiring S2 (second signal line), a fifth wiring WL (word line), a transistor 201 (first transistor), and a trans istor 202 (second transistor), and a transistor 203 (third transistor). The transistors 201 and 203 are formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor.

[0184] Here, one of the gate electrode of the transistor 201 and the source electrode or drain electrode of the transistor 202 is electrically connected. Also, the first wiring is electrically connected to the source electrode of the transistor 201, the drain electrode of the transistor 201 is electrically connected to the source electrode of the transistor 203. And, the second wiring is electrically connected to the drain electrode of the transistor 203, the third wiring is electrically connected to the other of the source electrode or drain electrode of the transistor 202, the fourth wiring is electrically connected to the gate electrode of the transistor 202, and the fifth wiring is electrically connected to the gate electrode of the transistor 203.

[0185] Next, the operation of the circuit will be specifically described.

[0186] When writing to the memory cell 200, the first wiring is set to 0V, the fifth wiring is set to 0V, and the second Set the potential of the first wiring to 0V and the potential of the fourth wiring to 2V. When writing data "1", set the potential of the third wiring to 2V, and when writing data "0", set the potential of the third wiring to 0V. At this time, the transistor 203 is in the off state and the transistor 202 is in the on state. Note that at the end of the writing operation, before the potential of the third wiring changes, set the potential of the fourth wiring to 0V to turn off the transistor 20 2.

[0187] As a result, after writing data "1", the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 is about 2V, and after writing data "0", the potential of node A is about 0 V. Although charges corresponding to the potential of the third wiring are accumulated in node A, since the off-current of the transistor 202 is extremely small or substantially 0, the potential of the gate electrode of the transistor 201 is retained for a long time. An example of the timing chart of the writing operation is shown in Fig. 11.

[0188] Next, when reading the memory cell, set the potential of the first wiring to 0V, the potential of the fifth wiring to 2V, the fourth wiring to 0V, the potential of the third wiring to 0V, and activate the reading circuit connected to the second wiring. At this time, the transistor 203 is in the on state and the transistor 202 is in the off state.

[0189] If the data is "0", that is, when node A is in a state of about 0V, the transistor 201 is in the off state, so the resistance between the second wiring and the first wiring is in a high state. On the other hand, if the data is "1", that is, when node A is in a state of about 2V, the transistor 201 is in the on state, so the resistance between the second wiring and the first wiring is in a low state. The reading circuit determines the difference in the resistance state of the memory cell. Therefore, data "0" and "1" can be read. Note that the second wiring during writing was set to 0V, but it may be in a floating state or charged to a potential of 0V or higher. During reading the third wiring was set to 0V, but it may be in a floating state or charged to a potential of 0V or higher as well.

[0190] Note that data "1" and data "0" are for convenience of definition and may be reversed. Also the operating voltages described above are just examples. The operating voltage should be such that transistor 2 01 is in the off state when data is "0", and transistor 201 is in the on state when data is "1", and transistor 202 is in the on state during writing and in the off state otherwise, and transistor 203 is in the on state during reading. Specifically, instead of 2V, the power supply potential VDD of the surrounding logic circuit may be used.

[0191] FIG. 12 shows a block circuit diagram of a semiconductor device according to an aspect of the present invention having a storage capacity of m×n bits.

[0192] A semiconductor device according to an aspect of the present invention includes m fifth wirings and fourth wirings, n second wirings and third wirings, and a memory cell array 210 in which a plurality of memory cells 200(1, 1) to 200(m, n) are arranged in a matrix of m (rows) × n (columns) (m and n are natural numbers), and peripheral circuits such as a second wiring and third wiring driving circuit 211, a fourth wiring and fifth wiring driving circuit 213, and a reading circuit 212. As other peripheral circuits, a refresh circuit or the like may be provided.

[0193] Consider the memory cell 200(i, j) as a representative of each memory cell. Here, the memory cell 200(i, j) (where i is an integer from 1 to m and j is an integer from 1 to n) is connected to the second wiring BL(j), the third wiring S1(j), the fifth wiring WL(i), and the fourth wiring S2(i), and the first wiring respectively. The first wiring potential Vs is applied to the first wiring Also, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S1 (n) are connected to the second wiring and the third wiring drive circuit 211 and the readout circuit 212, and the fifth wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are connected to the fourth wiring and the fifth wiring drive circuit 213 respectively.

[0194] The operation of the semiconductor device shown in FIG. 12 will be described. In this configuration, writing and reading are performed for each row.

[0195] When writing to the memory cells 200(i, 1) to 200(i, n) in the i-th row, the first wiring potential Vs is set to 0V, the fifth wiring WL(i) is set to 0V, the second wirings BL(1) to BL(n) are set to 0V, and the fourth wiring S2(i) is set to 2V. At this time, the transistor 202 is in the on state The third wirings S1(1) to S1(n) are set to 2V for the columns where data "1" is to be written and 0V for the columns where data "0" is to be written. Note that at the end of writing, before the potentials of the third wirings S1 (1) to S1(n) change, the fourth wiring S2(i) is set to 0V to turn off the transistor 202. Also, the non-selected fifth wiring is set to 0V, and the non-selected fourth wiring is set to 0V.

[0196] As a result, the gate electrodes of the transistors 201 of the memory cells where data "1" has been written The potential of the node connected to it (hereinafter referred to as Node A) is approximately 2V, and data "0" is written The potential of Node A of the memory cell becomes approximately 0V. Also, the potential of Node A of the non - selected memory cell remains unchanged.

[0197] When reading the memory cells 200(i, 1) to 200(i, n) in the i - th row, the potential of the first wiring Vs is set to 0V, the potential of the fifth wiring WL(i) is set to 2V, the potential of the fourth wiring S2(i) is set to 0V, and the potentials of the third wirings S1(1) to S1(n) are set to 0V. The read - out circuit connected to the second wirings BL(1) to BL(n) is put into an operating state. In the read - out circuit, for example, data "0" and "1" can be read based on the difference in the resistance state of the memory cell. Note that the non - selected fifth wiring is at 0V, and the non - selected fourth wiring is at 0V. Note that the second wiring during writing was set to 0V, but it may be in a floating state or charged to a potential of 0V or higher. The third wiring during reading was set to 0V, but it may be in a floating state or charged to a potential of 0V or higher. It doesn't matter.

[0198] Note that data "1" and data "0" are for convenience of definition and can be reversed. Also, the above - mentioned operating voltages are just examples. The operating voltages should be such that transistor 2 01 is in an off state when data "0" is present, and transistor 201 is in an on state when data "1" is present. Also, transistor 202 should be in an on state during writing and in an off state otherwise. Also, transistor 203 should be in an on state during reading. In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuit can be used.

[0199] Next, another example of the circuit configuration and operation of the memory element according to an aspect of the present invention will be described.​​

[0200] An example of a memory cell circuit included in a semiconductor device is shown in FIG. 13. The memory cell 22 0 shown in FIG. 13 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, and a fifth wiring WL, a transistor 201 (first transistor), a transistor 202 (second transistor), and a transistor 203 (third transistor). The transistors 201 and 203 are formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor.

[0201] The circuit of the memory cell 220 shown in FIG. 13 has different directions of the third wiring and the fourth wiring as compared with the circuit of the memory cell 200 shown in FIG. 10. That is, in the circuit of the memory cell 220 in FIG. 13, the third wiring is arranged in the fifth wiring direction (row direction), and the fourth wiring is arranged in the second wiring direction (column direction).

[0202] Here, one of the gate electrode of the transistor 201 and the source electrode or drain electrode of the transistor 202 is electrically connected. Also, the first wiring and the source electrode of the transistor 2 01 are electrically connected, the drain electrode of the transistor 201 and the source electrode of the transistor 203 are electrically connected. Then, the second wiring and the drain electrode of the transistor 203 are electrically connected, the third wiring and the other of the source electrode or drain electrode of the transistor 202 are electrically connected, the fourth wiring and the gate electrode of the transistor 202 are electrically connected, and the fifth wiring and the gate electrode of the transistor 203 are electrically connected. ​​​​​​

[0203] The operation of the circuit of the memory cell 220 shown in FIG. 13 is the same as that of the circuit of the memory cell 200 shown in FIG. 10, and thus a detailed description thereof will be omitted. For this reason, a detailed description thereof will be omitted.

[0204] FIG. 14 shows a block circuit diagram of a semiconductor device according to an aspect of the present invention having a storage capacity of m×n bits. is shown.

[0205] A semiconductor device according to an aspect of the present invention includes m third wirings and fifth wirings, n second wirings and fourth wirings, and a plurality of memory cells 220(1, 1) to 220(m, n) arranged in a matrix of m rows (vertical) × n columns (horizontal) (m and n are natural numbers). A memory cell array 230, a second wiring and fourth wiring driving circuit 231, a third wiring and fifth wiring driving circuit 233, and a reading circuit 232. Other peripheral circuits such as a refresh circuit may be provided. As other peripheral circuits, a refresh circuit or the like may be provided.

[0206] The semiconductor device shown in FIG. 14 has different directions of the third wiring and the fourth wiring compared with the semiconductor device shown in FIG. 12. That is, in the semiconductor device of FIG. 14, the third wiring is arranged in the fifth wiring direction ( row direction), and the fourth wiring is arranged in the second wiring direction (column direction).

[0207] Taking the memory cell 220(i, j) as a representative of each memory cell. Here, the memory cell 220(i, j) (i is an integer from 1 to m, and j is an integer from 1 to n) is connected to the second wiring BL(j), the fourth wiring S2(j), the fifth wiring WL(i), and the third wiring S1(i), and the first wiring, respectively. A first wiring potential Vs is applied to the first wiring. It is as follows. Also, the second wirings BL(1) to BL(n) and the fourth wirings S2(1) to S2 (n) are connected to the second wiring and fourth wiring drive circuit 231 and the read circuit 232, and the fifth wir ings WL(1) to WL(m) and the third wirings S1(1) to S1(m) are connected to the third wiring and fifth wiring drive circuit 233, respectively.

[0208] The operation of the semiconductor device shown in FIG. 14 will be described. In this configuration, writing is performed column by column, and reading is performed row by row.

[0209] When writing to the memory cells 220(1, j) to 220(m, j) in the j-th column, the potential Vs of the first wiring is set to 0 V, the fifth wirings WL(1) to WL(m) are set to 0 V, the second wiring BL(j) is set to 0 V, and the fourth wiring S2(j) is set to 2 V. The third wirings S1(1) to S1(m) are set to 2 V for the rows where data "1" is to be written and 0 V for the rows where data "0" is to be written. Note that at the end of writing, before the potential of the third wirings S1(1) to S1(m) changes, the fourth wiring S2(j) is set to 0 V to turn off the transistor 202. Also, the non-selected second wiring is set to 0 V, and the non-selected fourth wiring is set to 0 V. As a result, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 of the memory cell where data "1" is written is approximately 2 V, and the potential of node A of the memory cell where data "0" is written is approximately 0 V. Also, the potential of node A of the non-selected memory cell does not change.

[0210] When reading the memory cells 220(i, 1) to 220(i, n) in the i-th row, the first

[0211] The first wiring WL(i) is set to 0 V, the fifth wiring WL(i) is set to 2 V, and the fourth wiring S2(1) to S2(n) are set to 0 V. The third wiring S1(i) is set to 0 V, and the second wirings BL(1) to BL(n) are connected to the third wiring S1(i). The read circuit is in an operating state. For example, the difference in the resistance state of the memory cell is read by the read circuit. Data "0" and "1" can be read out from the selected fifth line. The unselected third line is set to 0V. Note that the second line is set to 0V during writing, but It does not matter if the third wire is in a grounded state or is charged to a potential of 0V or higher. Although 0V is used, it may be in a floating state or may be charged to a potential of 0V or higher.

[0212] Note that data "1" and data "0" are defined for convenience, and may be reversed. The above-mentioned operating voltage is an example. When data is “1”, transistor 201 is turned on. Also, the transistor 202 is in an on state during writing and is in an off state except during writing. Also, the transistor 203 may be selected so as to be in an on state during reading. Instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0213] Since a transistor using an oxide semiconductor has an extremely low off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be sufficiently reduced. It is possible to retain the stored contents for a long period of time.

[0214] In addition, it does not require a high voltage for writing information and there is no problem of element degradation. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can also be easily realized. Also, there is an advantage that an operation for erasing information required in a flash memory or the like is unnecessary.

[0215] In addition, since a transistor using a material other than an oxide semiconductor enables sufficient high-speed operation, by using this, it is possible to read the stored content at high speed.

[0216] (Embodiment 3) In this embodiment, an example of the circuit configuration and operation of a memory element different from that of Embodiment 2 will be described.

[0217] An example of a circuit diagram of a memory cell included in a semiconductor device is shown in FIG. 15. The memory cell 240 shown in FIG. 15 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a fifth wiring WL, a transistor 201 (first transistor), a transistor 202 (second transistor), and a capacitor element 204. The transistor 201 is formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor.

[0218] Here, one of the gate electrode of the transistor 201, the source electrode or the drain electrode of the transistor 202, and one electrode of the capacitor element 204 are electrically connected. Also, the first wiring and the source electrode of the transistor 201 are electrically connected, the second wiring and the drain electrode of the transistor 201 are electrically connected, the third wiring and the transistor The other of the source electrode or the drain electrode of the transistor 202 is electrically connected to the fourth wiring, and the gate electrode of the transistor 202 is electrically connected to the fifth wiring, and the other electrode of the capacitor element 204 is electrically connected. The other of the source electrode or the drain electrode of the transistor 202 is electrically connected to the fourth wiring, and the gate electrode of the transistor 202 is electrically connected to the fifth wiring, and the other electrode of the capacitor element 204 is electrically connected. The other of the source electrode or the drain electrode of the transistor 202 is electrically connected to the fourth wiring, and the gate electrode of the transistor 202 is electrically connected to the fifth wiring, and the other electrode of the capacitor element 204 is electrically connected.

[0219] Next, the operation of the circuit will be specifically described.

[0220] When writing to the memory cell 240, the first wiring is set to 0V, the fifth wiring is set to 0V, the second wiring is set to 0V, and the fourth wiring is set to 2V. When writing data "1", the third wiring is set to 2V, and when writing data "0", the third wiring is set to 0V. At this time, the transistor 202 is turned on. When the writing is completed, before the potential of the third wiring changes, the fourth wiring is set to 0V to turn off the transistor 202. When writing to the memory cell 240, the first wiring is set to 0V, the fifth wiring is set to 0V, the second wiring is set to 0V, and the fourth wiring is set to 2V. When writing data "1", the third wiring is set to 2V, and when writing data "0", the third wiring is set to 0V. At this time, the transistor 202 is turned on. When the writing is completed, before the potential of the third wiring changes, the fourth wiring is set to 0V to turn off the transistor 202. When writing to the memory cell 240, the first wiring is set to 0V, the fifth wiring is set to 0V, the second wiring is set to 0V, and the fourth wiring is set to 2V. When writing data "1", the third wiring is set to 2V, and when writing data "0", the third wiring is set to 0V. At this time, the transistor 202 is turned on. When the writing is completed, before the potential of the third wiring changes, the fourth wiring is set to 0V to turn off the transistor 202. When writing to the memory cell 240, the first wiring is set to 0V, the fifth wiring is set to 0V, the second wiring is set to 0V, and the fourth wiring is set to 2V. When writing data "1", the third wiring is set to 2V, and when writing data "0", the third wiring is set to 0V. At this time, the transistor 202 is turned on. When the writing is completed, before the potential of the third wiring changes, the fourth wiring is set to 0V to turn off the transistor 202. When writing to the memory cell 240, the first wiring is set to 0V, the fifth wiring is set to 0V, the second wiring is set to 0V, and the fourth wiring is set to 2V. When writing data "1", the third wiring is set to 2V, and when writing data "0", the third wiring is set to 0V. At this time, the transistor 202 is turned on. When the writing is completed, before the potential of the third wiring changes, the fourth wiring is set to 0V to turn off the transistor 202.

[0221] As a result, after writing data "1", the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 is about 2V, and after writing data "0", the potential of node A is about 0V. As a result, after writing data "1", the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 is about 2V, and after writing data "0", the potential of node A is about 0V. As a result, after writing data "1", the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 is about 2V, and after writing data "0", the potential of node A is about 0V.

[0222] When reading the memory cell 240, the first wiring is set to 0V, the fifth wiring is set to 2V, the fourth wiring is set to 0V, the third wiring is set to 0V, and the reading circuit connected to the second wiring is set to the operating state. At this time, the transistor 202 is turned off. When reading the memory cell 240, the first wiring is set to 0V, the fifth wiring is set to 2V, the fourth wiring is set to 0V, the third wiring is set to 0V, and the reading circuit connected to the second wiring is set to the operating state. At this time, the transistor 202 is turned off. When reading the memory cell 240, the first wiring is set to 0V, the fifth wiring is set to 2V, the fourth wiring is set to 0V, the third wiring is set to 0V, and the reading circuit connected to the second wiring is set to the operating state. At this time, the transistor 202 is turned off.

[0223] The state of the transistor 201 when the fifth wiring is set to 2V will be described. The potential of node A that determines the state of the transistor 201 depends on the capacitance C1 between the fifth wiring and node A and the capacitances C2 between the gate-source and drain of the transistor 201. The state of the transistor 201 when the fifth wiring is set to 2V will be described. The potential of node A that determines the state of the transistor 201 depends on the capacitance C1 between the fifth wiring and node A and the capacitances C2 between the gate-source and drain of the transistor 201. The state of the transistor 201 when the fifth wiring is set to 2V will be described. The potential of node A that determines the state of the transistor 201 depends on the capacitance C1 between the fifth wiring and node A and the capacitances C2 between the gate-source and drain of the transistor 201.

[0224] FIG. 16 shows the relationship between the fifth wiring potential and the potential of node A. Here, as an example, assume that transistor 201 is in the off state with C1 / C2 ≫ 1 and in the on state with C1 / C2 = 1. Also, assume that the threshold value of transistor 201 is 2.5V. When the fifth wiring potential in the graph shown in FIG. 16 is 2V, in the state of data "0", node A becomes about 2V, but transistor 201 is in the off state. On the other hand, in the state of data "1", node A becomes about 3.25V and transistor 201 is in the on state. The memory cell is in a low-resistance state when transistor 201 is in the on state and in a high-resistance state when in the off state. Therefore, the read circuit can read data "0" and "1" from the difference in the resistance states of the memory cell. Note that when reading is not performed, that is, when the fifth wiring potential is 0V, in data "0", node A is about 0 V, and in data "1", node A is about 2V, and in both cases, transistor 201 is in the off state.

[0225] Note that the third wiring during reading is set to 0V, but it may be in a floating state or charged to a potential of 0V or higher. Data "1" and data "0" are for convenience of definition and may be reversed.

[0226] The operating voltages described above are just examples. The potential of the third wiring during writing is such that transistor 202 is in the off state after writing, and also, when the fifth wiring potential is 0V and transistor 201 is in the off state, the potentials of data "0" and "1" can be selected respectively. The fifth wiring potential during reading is such that transistor 201 is in the off state in the case of data "0", and the data ​​​​​​In the case of “1”, the transistor 201 may be selected to be in the on state. Also, the threshold voltage of the transistor 201 is just an example. As long as it is within the range that does not change the state of the transistor 201 described above, any threshold voltage may be used. The threshold voltage of the transistor 201 is also an example. As long as it is within the range that does not change the state of the transistor 201 described above, any threshold voltage may be used. As long as it is within the range that does not change the state of the transistor 201 described above, any threshold voltage may be used.

[0227] The semiconductor device according to one aspect of the present invention shown in FIG. 17 includes m fifth wirings and fourth wirings, n second wirings and third wirings, and a plurality of memory cells 240(1, 1) to (m, n) are arranged in a matrix of m (rows) × n (columns) (m and n are natural numbers), forming a memory cell array 250, and peripheral circuits such as a second wiring and third wiring driving circuit 211, a fourth wiring and fifth wiring driving circuit 213, and a read circuit 212. As other peripheral circuits, a refresh circuit or the like may be provided.

[0228] Considering the memory cell 240(i, j) as a representative of each memory cell. Here, the memory cell 240(i, j) (i is an integer from 1 to m, j is an integer from 1 to n) is connected to the second wiring BL(j), the third wiring S1(j), the fifth wiring WL(i), the fourth wiring S2(i), and the first wiring respectively. The first wiring potential Vs is applied to the first wiring. Also, the second wirings BL(1) to BL(n) and the third wirings S1(1) to S1 (n) are connected to the second wiring and third wiring driving circuit 211 and the read circuit 212, and the fifth wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are connected to the fourth wiring and fifth wiring driving circuit 213 respectively.

[0229] The operation of the semiconductor device shown in FIG. 17 will be described. In this configuration, writing and reading are performed for each row.

[0230] When writing to the memory cells 240(i, 1) to 240(i, n) in the i-th row, set the wiring potential Vs of the first to 0V, the wiring WL(i) of the fifth to 0V, the wirings BL(1) to BL(n ) to 0V, and the wiring S2(i) of the fourth to 2V. At this time, the transistor 202 is in the on state . The wirings S1(1) to S1(n) of the third are set to 2V for the columns where data "1" is written and 0V for the columns where data "0" is written. Note that at the end of writing, before the potential of the wirings S 1(1) to S1(n) changes, set the wiring S2(i) of the fourth to 0V to turn off the transistor 202. Also, set the non-selected fifth wiring to 0V and the non-selected fourth wiring to 0V.

[0231] As a result, the potential of the node (hereinafter referred to as node A) connected to the gate electrode of the transistor 201 of the memory cell where data "1" is written is about 2V, and after writing data "0" , the potential of node A becomes about 0V. Also, the potential of node A of the non-selected memory cell does not change .

[0232] When reading from the memory cells 240(i, 1) to 240(i, n) in the i-th row, set the wiring potential Vs of the first to 0V, the wiring WL(i) of the fifth to 2V, the wiring S2(i) of the fourth to 0V, and the wirings S1(1) to S1(n) of the third to 0V, and activate the readout circuit connected to the wirings BL(1) to BL(n) . At this time, the transistor 202 is in the off state . Also, set the non-selected fifth wiring to 0V and the non-selected fourth wiring to 0V.

[0233] The state of the transistor 201 during reading will be described. As already explained, the transistor ​​Assume that when the dissta 201 is in the off state, C1 / C2 ≫ 1, and when it is in the on state, C1 / C2 = 1. The relationship between the potential of the fifth wiring and the potential of node A is represented as shown in FIG. 16. Also, for the transistor 201, the threshold voltage is set to 2.5V. For non-selected memory cells, since the potential of the fifth wiring is 0V the node A of the memory cell having data "0" is approximately 0V, and the node A of the memory cell having data "1" is approximately 2V. In both cases, the transistor 201 is in the off state. In the memory cells of the i-th row, since the potential of the fifth wiring is 2V, the node A of the memory cell having data "0" is approximately 2V, and the transistor 201 is in the off state. However, the node A of the memory cell having data "1" is approximately 3.25V, and the transistor 201 is in the on state. The memory cell is in a low-resistance state when the transistor 201 is in the on state and in a high-resistance state when the transistor 201 is in the off state. As a result, in the memory cells of the i-th row, only the memory cells having data "0" are in the low-resistance state. The read circuit can read data "0" and "1" from the difference in the load resistance connected to the second wiring.

[0234] Note that although the potential of the third wiring during reading is set to 0V, it may be in a floating state or charged to a potential of 0V or higher. Data "1" and data "0" are definitions for convenience and can be reversed.

[0235] The operating voltages described above are just examples. The potential of the third wiring during writing should be selected within the range where the transistor 202 is in the off state after writing and the transistor 201 is in the off state when the potential of the fifth wiring is 0V for data "0" and "1" respectively. The potential of the fifth wiring during reading should be such that the transistor 201 is in the off state for data "0". ​​​​ In the case of “1”, the transistor 201 may be selected to be in the on state. Also, the threshold voltage of the transistor 201 is also an example. As long as it is within the range where the state of the transistor 201 described above does not change, any threshold voltage may be used. Since the off-current of a transistor using an oxide semiconductor is extremely small, it is possible to hold the stored content for an extremely long time by using this. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to hold the stored content for a long time.

[0236] Since the off-current of a transistor using an oxide semiconductor is extremely small, it is possible to hold the stored content for an extremely long time by using this. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to hold the stored content for a long time. Since the off-current of a transistor using an oxide semiconductor is extremely small, it is possible to hold the stored content for an extremely long time by using this. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to hold the stored content for a long time. Since the off-current of a transistor using an oxide semiconductor is extremely small, it is possible to hold the stored content for an extremely long time by using this. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to hold the stored content for a long time. Since the off-current of a transistor using an oxide semiconductor is extremely small, it is possible to hold the stored content for an extremely long time by using this. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to hold the stored content for a long time. Since the off-current of a transistor using an oxide semiconductor is extremely small, it is possible to hold the stored content for an extremely long time by using this. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to hold the stored content for a long time.

[0237] Also, a high voltage is not required for writing information, and there is no problem of element degradation. Furthermore, since information is written depending on the on state and off state of the transistor, high-speed operation can be easily realized. Also, there is an advantage that an operation for erasing information required in a flash memory or the like is unnecessary. Also, a high voltage is not required for writing information, and there is no problem of element degradation. Furthermore, since information is written depending on the on state and off state of the transistor, high-speed operation can be easily realized. Also, there is an advantage that an operation for erasing information required in a flash memory or the like is unnecessary. Also, a high voltage is not required for writing information, and there is no problem of element degradation. Furthermore, since information is written depending on the on state and off state of the transistor, high-speed operation can be easily realized. Also, there is an advantage that an operation for erasing information required in a flash memory or the like is unnecessary. Also, a high voltage is not required for writing information, and there is no problem of element degradation. Furthermore, since information is written depending on the on state and off state of the transistor, high-speed operation can be easily realized. Also, there is an advantage that an operation for erasing information required in a flash memory or the like is unnecessary.

[0238] Also, since a transistor using a material other than an oxide semiconductor can perform sufficiently high-speed operation, it is possible to read out the stored content at high speed by using this. Also, since a transistor using a material other than an oxide semiconductor can perform sufficiently high-speed operation, it is possible to read out the stored content at high speed by using this.

[0239] Next, another example of the circuit configuration and operation of the memory element according to one aspect of the present invention will be described.

[0240] An example of a memory cell circuit included in a semiconductor device is shown in FIG. 18. The memory cell 260 shown in FIG. 18 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, and a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, and a ​It is composed of the wiring WL of 5, the transistor 201, the transistor 202, the capacitive element 204, and the like. The transistor 201 is composed of a material other than an oxide semiconductor. The transistor 202 is formed using an oxide semiconductor.

[0241] The circuit of the memory cell 260 shown in FIG. 18 has different directions of the third wiring and the fourth wiring compared to the circuit of the memory cell 240 in FIG. 15. That is, in the memory cell 260 of FIG. 18, the third wiring is arranged in the fifth wiring direction (row direction), and the fourth wiring is arranged in the second wiring direction (column direction). Here, one of the gate electrode of the transistor 201, the source electrode or the drain electrode of the transistor 202, and one electrode of the capacitive element 204 are electrically connected. Also,

[0242] the first wiring and the source electrode of the transistor 201 are electrically connected, the second wiring and the drain electrode of the transistor 201 are electrically connected, the third wiring and the other of the source electrode or the drain electrode of the transistor 202 are electrically connected, the fourth wiring and the gate electrode of the transistor 202 are electrically connected, and the fifth wiring and the other electrode of the capacitive element 204 are electrically connected. Since the operation of the circuit of the memory cell 260 shown in FIG. 18 is the same as the operation of the circuit of the memory cell 240 shown in FIG. 15, a detailed description is omitted.

[0243] FIG. 19 shows a block circuit diagram of a semiconductor device according to an aspect of the present invention having a storage capacity of m×n bits.

[0244]

[0245] ​​​​​​A semiconductor device according to one aspect of the present invention includes m third wirings and fifth wirings, n second wirings and fourth wirings, and a plurality of memory cells 260(1, 1) to 260(m, n) arranged in a matrix of m rows × n columns (m and n are natural numbers), a memory cell array 270, a second wiring and fourth wiring driving circuit 231, a third wiring and fifth wiring driving circuit 233, and peripheral circuits such as a read circuit 232. As other peripheral circuits, a refresh circuit or the like may be provided.

[0246] The semiconductor device shown in FIG. 19 has different directions of the third wiring and the fourth wiring compared to the semiconductor device shown in FIG. 17. That is, in the semiconductor device of FIG. 19, the third wiring is arranged in the direction of the fifth wiring ( row direction), and the fourth wiring is arranged in the direction of the second wiring (column direction).

[0247] Considering the memory cell 260(i, j) as a representative of each memory cell. Here, the memory cell 260(i, j) (i is an integer from 1 to m, j is an integer from 1 to n) is connected to the second wiring BL(j), the fourth wiring S2(j), the fifth wiring WL(i), and the third wiring S1(i), and the first wiring, respectively. A first wiring potential Vs is applied to the first wiring. Also, the second wirings BL(1) to BL(n) and the fourth wirings S2(1) to S2 (n) are connected to the second wiring and fourth wiring driving circuit 231 and the read circuit 232, and the fifth wirings WL(1) to WL(m) and the third wirings S1(1) to S1(m) are connected to the third wiring and fifth wiring driving circuit 233, respectively.

[0248] Since the operation of the semiconductor device shown in FIG. 19 is the same as that of the semiconductor device shown in FIG. 17, Detailed description is omitted.

[0249] Since a transistor using an oxide semiconductor has an extremely small off-current, using this makes it possible to retain memory contents for an extremely long period. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that power consumption can be sufficiently reduced. Also, even when there is no power supply, it is possible to retain memory contents for a long period.

[0250] Moreover, a high voltage is not required for writing information, and there is no problem of element degradation. Furthermore, since information is written according to the on-state and off-state of the transistor, high-speed operation can also be easily realized. Also, there is an advantage that an operation for erasing information required in a flash memory or the like is unnecessary.

[0251] In addition, since a transistor using a material other than an oxide semiconductor enables sufficiently high-speed operation, by using this, it is possible to read memory contents at high speed.

[0252] (Embodiment 4) In this embodiment, an example of the circuit configuration and operation of a memory element different from those of Embodiments 2 and 3 will be described.

[0253] An example of a circuit diagram of a memory cell included in a semiconductor device is shown in FIG. 20. The memory cell 280a shown in FIG. 20(A) and the memory cell 280b shown in FIG. 20(B) are each different from the memory cell 200 shown in FIG. 10 and the memory cell 220 shown in FIG. 13 in that the relationship of the series connection of the first transistor and the third transistor is switched. ​​

[0254] Here, the memory cell 280a shown in FIG. 20(A) is electrically connected to the gate electrode of the transistor 201 and one of the source or drain electrodes of the transistor 202. Also, the first wiring is electrically connected to the source electrode of the transistor 203, and the drain electrode of the transistor 203 is electrically connected to the source electrode of the transistor 201. Then, the second wiring is electrically connected to the drain electrode of the transistor 201, the third wiring is electrically connected to the other of the source or drain electrodes of the transistor 202, the fourth wiring is electrically connected to the gate electrode of the transistor 202, and the fifth wiring is electrically connected to the gate electrode of the transistor 203. Also, compared with the memory cell circuit shown in FIG. 20(A), the memory cell 280b shown in FIG. 20(B) has different directions for the third and fourth wirings. That is, in the memory cell circuit shown in FIG. 20(B), the fourth wiring is arranged in the second wiring direction (column direction), and the third wiring is arranged in the fifth wiring direction (row direction).

[0255] Also, the operations of the circuits of the memory cell 280a shown in FIG. 20(A) and the memory cell 280b shown in FIG. 20(B) are the same as the operations of the circuits of the memory cell 200 shown in FIG. 10 and the memory cell 220 shown in FIG. 13, respectively, so detailed descriptions are omitted.

[0256] The operations of the circuits of the memory cell 280a shown in FIG. 20(A) and the memory cell 280b shown in FIG. 20(B) are the same as the operations of the circuits of the memory cell 200 shown in FIG. 10 and the memory cell 220 shown in FIG. 13, respectively, so detailed descriptions are omitted.

[0257] (Embodiment 5) In this embodiment, an example of the circuit configuration and operation of a memory element different from those in Embodiments 2 to 4 will be described.

[0258] ​​​​​​​An example of a circuit diagram of a memory cell included in a semiconductor device is shown in FIG. 21. The memory cell circuit 290 shown in FIG. 21 has a configuration having a capacitive element between node A and the first wiring as compared with the circuit of the memory cell 200 shown in FIG. 10.

[0259] The memory cell 290 shown in FIG. 21 includes a first wiring SL, a second wiring BL, a third wiring S1, , a fourth wiring S2, a fifth wiring WL, a transistor 201, a transistor 202, , a transistor 203, and a capacitive element 205. The transistor 201 and the transistor 203 are formed using a material other than an oxide semiconductor, and the transistor 202 is formed using an oxide semiconductor.

[0260] Here, one of the gate electrode of the transistor 201, the source electrode or the drain electrode of the transistor 202, and one electrode of the capacitive element 205 are electrically connected. Also, the first wiring, the source electrode of the transistor 201, and the other electrode of the capacitive element 205 are electrically connected, and the drain electrode of the transistor 201 and the source electrode of the transistor 203 are electrically connected. Then, the second wiring and the drain electrode of the transistor 203 are electrically connected, the third wiring and the source electrode or the other drain electrode of the transistor 202 are electrically connected, the fourth wiring and the gate electrode of the transistor 202 are electrically connected, and the fifth wiring and the gate electrode of the transistor 203 are electrically connected.

[0261] The operation of the memory cell circuit shown in FIG. 21 is the same as the operation of the memory cell circuit shown in FIG. 10. ​Therefore, detailed description is omitted. By having such a capacitive element 205, the holding characteristics are improved.

[0262] (Embodiment 6) An example of a read circuit included in a semiconductor device according to an aspect of the present invention will be described with reference to FIG. 22. Do.

[0263] The read circuit shown in FIG. 22 includes a transistor 206 and a differential amplifier.

[0264] At the time of reading, terminal A is connected to a second wiring to which a memory cell that performs reading is connected. Also, a bias voltage Vbias is applied to the gate electrode of the transistor 206 to flow a predetermined current.

[0265] The memory cell has different resistances depending on the stored data "1" / "0". Specifically, when the transistor 201 of the selected memory cell is in the on state, it becomes a low-resistance state, and when the transistor 201 of the selected memory cell is in the off state, it becomes a high-resistance state.

[0266] When the memory cell is in the high-resistance state, the potential of terminal A becomes higher than the reference potential Vref, and data "1" is output from the output of the differential amplifier. On the other hand, when the memory cell is in the low-resistance state, the potential of terminal A becomes lower than the reference potential Vref, and data "0" is output from the output of the differential amplifier. Force. In this way, the read circuit can read data from the memory cell. Note that

[0267] The read circuit of this embodiment is an example. Other known circuits may be used. For example, a pre charge circuit may be included. Instead of the reference potential Vref, a second wiring for reference is connected. ​A configuration capable of this may be used. Instead of the differential amplifier, a latch-type sense amplifier may be used.

[0268] (Embodiment 7) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment will be described with reference to FIG. 23. The semiconductor device obtained in the previous embodiment can hold information even when there is no power supply. In addition, deterioration due to writing and erasing does not occur. Furthermore, its operation is also fast. Therefore, it is possible to provide an electronic device with a new configuration using the semiconductor device. Note that the semiconductor device according to the previous embodiment is integrated and mounted on a circuit board or the like, and will be mounted inside each electronic device.

[0269] FIG. 23(A) shows a notebook personal computer including the semiconductor device according to the previous embodiment, which is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, and the like. By applying the semiconductor device according to one aspect of the present invention to a notebook personal computer, it is possible to hold information even when there is no power supply. In addition, deterioration due to writing and erasing does not occur. Furthermore, its operation is also fast. Therefore, it is suitable to apply the semiconductor device according to one aspect of the present invention to a notebook personal computer.

[0270] FIG. 23(B) shows a personal digital assistant (PDA) including the semiconductor device according to the previous embodiment. The main body 311 is provided with a display unit 313, an external interface 315, operation buttons 314, and the like. There is also a stylus 312 as an accessory for operation. By applying the semiconductor device according to one aspect of the present invention to a PDA, it is possible to hold information even when there is no power supply. ​ is possible. In addition, deterioration due to writing and erasing does not occur. Furthermore, its operation is also fast. Therefore, it is suitable to apply the semiconductor device according to one aspect of the present invention to a PDA .

[0271] FIG. 23(C) shows, as an example of an electronic paper including the semiconductor device according to the previous embodiment, an electronic book 320. The electronic book 320 is composed of two housings, a housing 321 and a housing 323 . The housing 321 and the housing 323 are integrated by a shaft portion 337, and can perform an opening / closing operation about the shaft portion 337. With such a configuration, the electronic book 320 can be used like a paper book. By applying the semiconductor device according to one aspect of the present invention to an electronic paper, it is possible to retain information even when there is no power supply. In addition, deterioration due to writing and erasing does not occur. Furthermore, its operation is also fast . Therefore, it is suitable to apply the semiconductor device according to one aspect of the present invention to an electronic paper .

[0272] A display unit 325 is incorporated in the housing 321, and a display unit 327 is incorporated in the housing 323 . The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different screens. By adopting a configuration for displaying different screens, for example, a text can be displayed on the right display unit (display unit 325 in FIG. 23(C)), and an image can be displayed on the left display unit (display unit 327 in FIG. 23(C)).

[0273] Also, FIG. 23(C) shows an example in which the housing 321 is provided with an operation unit or the like. For example, the housing 321 includes a power supply 331, operation keys 333, a speaker 335, and the like. The operation key -333 can be used to send pages. Additionally, it may be configured to include a keyboard, a pointing device, etc. on the same surface as the display unit of the housing. Further, it may be configured to include external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion part, etc. on the back surface or side surface of the housing. Moreover, the electronic book 320 may be configured to have a function as an electronic dictionary. In addition, the electronic book 320 may be configured to be able to wirelessly transmit and receive information. With wireless communication, it is also possible to purchase and download desired book data, etc. from an electronic book server. Furthermore, the electronic paper can be applied to any field as long as it can display information. For example, in addition to electronic books, it can be applied to displays on posters, in-vehicle advertisements on vehicles such as trains, and various cards such as credit cards.

[0274] Figure 23(D) shows a mobile phone including the semiconductor device according to the previous embodiment. The mobile phone is composed of two housings, namely housing 340 and housing 341. Housing 341 is provided with a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348, etc. Moreover, housing 340 is provided with a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. Also, the antenna is built into housing 341. By applying the semiconductor device according to one aspect of the present invention to the mobile phone, information can be retained even when there is no power supply.

[0275] In addition, the electronic paper can be applied to any field as long as it can display information. For example, in addition to electronic books, it can be applied to displays on posters, in-vehicle advertisements on vehicles such as trains, and various cards such as credit cards. For example, in addition to electronic books, it can be applied to displays on posters, in-vehicle advertisements on vehicles such as trains, and various cards such as credit cards. By applying the semiconductor device according to one aspect of the present invention to the mobile phone, information can be retained even when there is no power supply.

[0276] Figure 23(D) shows a mobile phone including the semiconductor device according to the previous embodiment. The mobile phone is composed of two housings, namely housing 340 and housing 341. Housing 341 is provided with a display panel 342, a speaker 343, a microphone 344, a pointing device 346, a camera lens 347, an external connection terminal 348, etc. Moreover, housing 340 is provided with a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. Also, the antenna is built into housing 341. By applying the semiconductor device according to one aspect of the present invention to the mobile phone, information can be retained even when there is no power supply. 46, a camera lens 347, an external connection terminal 348, etc. Moreover, housing 340 is provided with a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. Also, the antenna is built into housing 341. By applying the semiconductor device according to one aspect of the present invention to the mobile phone, information can be retained even when there is no power supply. By applying the semiconductor device according to one aspect of the present invention to the mobile phone, information can be retained even when there is no power supply. This is possible. Also, deterioration due to writing and erasing does not occur. Furthermore, its operation is fast. Therefore, it is suitable to apply the semiconductor device according to one aspect of the present invention to a mobile phone. This is the case.

[0277] The display panel 342 has a touch panel function, and a plurality of operation keys 345 shown by dotted lines are displayed in FIG. 23(D). Note that the mobile phone is equipped with a booster circuit for boosting the voltage output by the solar cell 349 to the voltage required for each circuit. 9 to the voltage required for each circuit. In addition to the above configuration, it can also be configured to incorporate a non-contact IC chip, a small recording device, etc. This is also possible. In addition to the above configuration, it can also be configured to incorporate a non-contact IC chip, a small recording device, etc. This is also possible.

[0278] The display direction of the display panel 342 changes appropriately according to the usage form. Also, since the camera lens 347 is provided on the same plane as the display panel 342, a video phone is possible. 42, a video phone is possible. The speaker 343 and the microphone 344 are not limited to voice calls, and are also capable of video phone calls, recording, playback, etc. 42, a video phone is possible. The speaker 343 and the microphone 344 are not limited to voice calls, and are also capable of video phone calls, recording, playback, etc. Furthermore, the housing 340 and the housing 341 can be slid from the unfolded state shown in FIG. 23(D) to an overlapping state, enabling miniaturization suitable for portability. Furthermore, the housing 340 and the housing 341 can be slid from the unfolded state shown in FIG. 23(D) to an overlapping state, enabling miniaturization suitable for portability. This is possible.

[0279] The external connection terminal 348 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication. Also, a recording medium can be inserted into the external memory slot 350 to support storage and transfer of a larger amount of data. In addition to the above functions, it may also be equipped with an infrared communication function, a TV reception function, etc. In addition to the above functions, it may also be equipped with an infrared communication function, a TV reception function, etc.

[0280] FIG. 23(E) shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera is composed of a main body 361, a display unit (A) 367, an eyepiece 363, an operation switch 364 , a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to one aspect of the present invention to a digital camera, it is possible to retain information even when there is no power supply. Also, deterioration due to writing and erasing does not occur. Furthermore, its operation is also fast. Therefore, it is suitable to apply the semiconductor device according to one aspect of the present invention to a digital camera .

[0281] FIG. 23(F) is a television apparatus including the semiconductor device according to the previous embodiment. In the television apparatus 370, a display unit 373 is incorporated in a housing 371. The display unit 373 can display an image. Here, a configuration in which the housing 371 is supported by a stand 375 is shown.

[0282] The operation of the television apparatus 370 can be performed by an operation switch provided in the housing 371 or a separate remote control operation unit 380. Channel and volume operations can be performed by operation keys 379 provided on the remote control operation unit 380 , and the image displayed on the display unit 373 can be operated . Also, the remote control operation unit 380 may be configured to be provided with a display unit 377 for displaying information output from the remote control operation unit 380 . By applying the semiconductor device according to one aspect of the present invention to a television apparatus, it is possible to retain information even when there is no power supply . Also, deterioration due to writing and erasing does not occur. Furthermore, its operation is also fast. Therefore, it is suitable to apply the semiconductor device according to one aspect of the present invention to a television apparatus .

[0283] ​​Note that the television device 370 preferably has a configuration including a receiver, a modem, etc. The receiver can receive general television broadcasts. Also, by connecting to a wired or wireless communication network via the modem, one-way (from the sender to the receiver) or two-way (between the sender and the receiver, or between receivers) information communication can be performed.

[0284] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

Explanation of Reference Numerals

[0285] 100 Substrate 102 Protection layer 104 Semiconductor region 106 Element isolation insulating layer 108a Gate insulating layer 110a Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High-concentration impurity region 122 Metal layer 124 Metal compound region 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c Electrode 130d Electrode 132 Insulating layer 134 Conductive layer 136a Electrode 136b Electrode 136c Electrode 136d Gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer​​​ 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protection insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a Electrode 150b Electrode 150c Electrode 150d Electrode 150e Electrode 152 Insulating layer 154a Electrode 154b Electrode 154c Electrode 154d Electrode 154e Electrode 160 Transistor 162 Transistor 200 Memory cell 201 Transistor 202 Transistor 203 Transistor 204 Capacitor element 205 Capacitor element 206 Transistor 210 Memory cell array 211 Second wiring and third wiring drive circuit 212 Readout circuit 213 Fourth wiring and fifth wiring drive circuit 220 Memory cell 230 Memory cell array 231 Second wiring and fourth wiring drive circuit 232 Readout circuit 233 Third wiring and fifth wiring drive circuit 240 Memory cell 250 Memory cell array 260 Memory cell 270 Memory cell array 280a Memory cell 280b Memory cell 290 Memory cell 301 Body 302 Housing 303 Display unit 304 Keyboard 311 Main body 312 Stylus 313 Display unit 314 Operation button 315 External interface 320 E-book 321 Housing 323 Housing 325 Display unit 327 Display unit 331 Power supply 333 Operation key 335 Speaker 337 Shaft part 340 Housing 341 Housing 342 Display panel 343 Speaker 344 Microphone 345 Operation key 346 Pointing device 347 Camera lens 348 External connection terminal 349 Solar cell 350 External memory slot 361 Main body 363 Eyepiece part 364 Operation switch 365 Display unit (B) 366 Battery 367 Display unit (A) 370 Television device 371 Housing 373 Display unit 375 Stand 377 Display unit 379 Operation key 380 Remote control operation unit

Claims

【Claim 1】 a first wiring; a second wiring; a third wiring; a fourth wiring; and a fifth wiring, wherein a plurality of memory elements are connected in parallel between the first wiring and the second wiring; one of the plurality of memory elements includes a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and a third transistor having a third gate electrode, a third source electrode, and a third drain electrode; the first transistor is provided on a substrate including a semiconductor material; the second transistor is configured to include an oxide semiconductor layer; the first gate electrode is electrically connected to one of the second source electrode or the second drain electrode; the first wiring is electrically connected to the first source electrode; the first drain electrode is electrically connected to the third source electrode; the second wiring is electrically connected to the third drain electrode; the third wiring is electrically connected to the other of the second source electrode or the second drain electrode; the fourth wiring is electrically connected to the second gate electrode; and the fifth wiring is electrically connected to the third gate electrode, a semiconductor device.

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