Control system, control method for control system, and control program for control system

Abstract

To suitably perform control based on advanced logic operation by using a multiplexed controller having a plurality of CPU cores.SOLUTION: The present application relates to a control system including a plurality of controllers that have a plurality of CPU cores capable of executing a logic operation including a plurality of operation tasks for controlling a control target and are multiplexed with each other. Each of the plurality of controllers stores operation results of the plurality of operation tasks as a first local data array, and stores operation results received from the other controllers as a second local data array. Data elements selected from the first local data array and the second local data array are stored as a global data array to be referred to among the plurality of operation tasks. The first local data array is transmitted to the other controllers as tracking data.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a control system, a control method for a control system, and a control program for a control system.

Background Art

[0002] For example, a control system for controlling plant facilities such as a power generation plant includes a controller including an arithmetic device such as a CPU. In this type of controller, a field signal from a field device such as a sensor installed in the plant facility to be controlled is input, and a control logic including a plurality of logic sheets described in a graphic language such as a problem-oriented language (POL) (or the FBD (Function Block Diagram) language of IEC 61131-3, which is an international standard language for PLC (Programmable Logic Controller)) is executed. By outputting the calculation result to an operation terminal such as an actuator or a switch, the plant facility is controlled. Such a series of arithmetic processes by the controller are periodically executed according to a predetermined arithmetic cycle.

[0003] By the way, this type of control system may be configured to include controllers multiplexed with each other for reliability improvement. In a system in which controllers are multiplexed, even when a malfunction such as a failure occurs in the controller in the control state, the control function can be maintained by switching to another controller in the standby state. In such a system in which controllers are multiplexed, there is a system having means for synchronizing the calculation results of the control logic between the controllers so that the output to the operation terminal does not suddenly change when switching the controllers (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] In a control system composed of an arithmetic processing unit, in order to improve its arithmetic performance, a controller having a plurality of CPU cores (multi-core CPU) may be used. In such a controller, the arithmetic operations of each logic sheet included in the control logic are executed in parallel by a plurality of CPU cores. However, depending on the arithmetic execution states of the respective CPU cores, there may be differences in the logic operation results among the multiplexed controllers. If there are differences in the logic operation results among the multiplexed controllers, there is a risk that the output value to the operation terminal will suddenly change when switching to the standby-side controller. Therefore, in a control system having multiplexed controllers, even if the controller has a plurality of CPU cores, the control logic operation is executed by a single CPU core so that there are no differences in the operation results among the controllers. At present, the advantages of the multi-core CPU are not fully utilized.

[0006] In addition, in recent years, the logic operations performed as arithmetic processing in control systems have become more sophisticated. For example, advanced control such as model predictive control (MPC) and advanced arithmetic processing such as artificial intelligence (AI) are described in general-purpose programming languages such as C and Python, and there is already a mechanism in which functions in the object code are called from the control logic and executed. However, when such logic operations are performed by a single CPU core, the processing time in the convergence calculation for obtaining the optimal solution by iterative calculation and the learning operation becomes long, and there is a risk that the logic operation result cannot be output to the operation terminal within a previously defined control cycle. Intelligence) are described in general-purpose programming languages such as C and Python, and there is already a mechanism in which functions in the object code are called from the control logic and executed. However, when such logic operations are performed by a single CPU core, the processing time in the convergence calculation for obtaining the optimal solution by iterative calculation and the learning operation becomes long, and there is a risk that the logic operation result cannot be output to the operation terminal within a previously defined control cycle.

[0007] At least one embodiment of the present disclosure has been made in view of the above circumstances, and an object thereof is to provide a control system capable of suitably performing control based on advanced logic operations, a control method for the control system, and a control program for the control system, using a multiplexed controller including a plurality of CPU cores.

Means for Solving the Problems

[0008] In order to solve the above problems, a control system according to at least one embodiment of the present disclosure is a control system having a plurality of CPU cores capable of executing a logic operation including a plurality of arithmetic tasks for controlling a control target, and including a plurality of controllers multiplexed with each other, each of the plurality of controllers includes a first local data array storage unit that stores the arithmetic results of the plurality of arithmetic tasks as a first local data array, a second local data array storage unit that stores the arithmetic results received from other controllers as a second local data array, a global data array storage unit that stores data elements selected from the first local data array and the second local data array as a global data array that can be referred to among the plurality of arithmetic tasks, a tracking data transmission unit that transmits the first local data array as tracking data to the other controllers, and is provided with.

[0009] In order to solve the above problems, a control method for a control system according to at least one embodiment of the present disclosure is a control method for a control system having a plurality of CPU cores capable of executing a logic operation including a plurality of arithmetic tasks for controlling a control target, and including a plurality of controllers multiplexed with each other, in each of the plurality of controllers, a step of storing the arithmetic results of the plurality of arithmetic tasks as a first local data array, storing the operation result received from another controller as a second local data array; storing data elements selected from the first local data array and the second local data array as a reference-free global data array among the plurality of operation tasks; transmitting the first local data array as tracking data to the other controller; and comprising.

[0010] A control program for a control system according to at least one embodiment of the present disclosure, in order to solve the above problems, is a control program for a control system having a plurality of CPU cores capable of executing logical operations including a plurality of operation tasks for controlling a control target, and comprising a plurality of controllers multiplexed with each other, on a computer device, in each of the plurality of controllers, storing the operation results of the plurality of operation tasks as a first local data array; storing the operation result received from another controller as a second local data array; storing data elements selected from the first local data array and the second local data array as a reference-free global data array among the plurality of operation tasks; transmitting the first local data array as tracking data to the other controller; and being executable.

Advantages of the Invention

[0011] According to at least one embodiment of the present disclosure, it is possible to provide a control system, a control method for a control system, and a control program for a control system that can suitably implement control based on advanced logical operations using a multiplexed controller including a plurality of CPU cores.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Embodiments for Carrying out the Invention

[0013] Hereinafter, some embodiments of the present invention will be described with reference to the accompanying drawings. However, the configurations described as embodiments or shown in the drawings are not intended to limit the scope of the present invention, but are merely illustrative examples.

[0014] First, with reference to FIGS. 1 and 2, the schematic configuration of a control system 1 according to an embodiment will be described. FIG. 1 is a schematic diagram showing the overall configuration of the control system 1 according to an embodiment, and FIG. 2 is a schematic diagram showing the configuration of the controller unit 4 in FIG. 1.

[0015] The control system 1 controls a plant facility composed of a large number of devices as a control target 2. The specific configuration of the control target 2 is not limited, but the control target 2 is, for example, a plant facility constituting an infrastructure such as oil, gas, electricity, and manufacturing. In FIG. 1, as some examples of the control target 2, an oscillator 2a, a switching device 2b, a control valve 2c, and a shut-off valve 2d, which are constituent devices of the plant facility, are shown.

[0016] The control system 1 includes a controller unit 4 capable of realizing various functions for controlling the controlled object 2. The controller unit 4 includes a plurality of controllers 6 (in the following description, when distinguishing the plurality of controllers 6 included in the controller unit 4, they are appropriately referred to as controller 6A, 6B, ··· respectively). Each controller 6 is composed of, for example, a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM (Read Only Memory), and a computer-readable storage medium, etc. And a series of processes for realizing various functions are stored in a storage medium or the like as a control program. The CPU reads this control program into the RAM or the like and executes information processing and arithmetic processing, whereby various functions are realized. In particular, in this embodiment, the control program is prepared as a plurality of logic sheets LS including a control logic CL described in a graphical language.

[0017] Note that the control program may be applied in a form pre-installed in a ROM or other storage medium, a form provided in a state stored in a computer-readable storage medium, a form distributed via wired or wireless communication means, etc. A computer-readable storage medium is a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, etc.

[0018] The plurality of controllers 6 included in the controller unit 4 are multiplexed with each other. The multiplicity of the plurality of controllers 6 may be 2 or more. Each of the multiplexed plurality of controllers 6 has substantially the same configuration, and as an operation mode, either a control mode capable of controlling the control target 2 or a standby mode can be selected. In the controller unit 4, when any one of the plurality of controllers 6 selected from the plurality of controllers 6, i.e., controller 6A, is set to the control mode, the control of the control target 2 is carried out, and the other controllers 6B, 6C,... are set to the standby mode. When an event occurs in which the control of the control target 2 cannot be continued for some reason in the controller 6A in the control mode, the operation mode of the controller 6A can be excluded from the control mode or switched to the critical failure mode, and the operation mode of any one of the other controllers 6B, 6C,... can be switched from the standby mode to the control mode, whereby the control of the control target 2 can be continued.

[0019] Also, each of the plurality of controllers 6 included in the controller unit 4 is of a so-called multi-core CPU type having a plurality of CPU cores 8 as a CPU for performing a logic operation including a plurality of arithmetic tasks by executing a control program. Each controller 6 has 2 or more CPU cores 8. In the example of FIG. 2, the case where each controller 6 has 2 CPU cores 8 is shown (for example, controller 6A has CPU cores 8A-1 and 8A-2, and controller 6B has CPU cores 8B-1 and 8B-2).

[0020] Each controller 6 can transmit and receive various types of information necessary for arithmetic processing to and from the control target 2 via the I / O unit 10. The I / O unit 10 is an input / output interface for performing input / output of various types of information between the controller 6 and the control target 2, and is connected to the controller 6 via the I / O communication network 12. Input information from the control target 2 is taken into the controller 6 via the I / O unit 10 and input to a plurality of logic sheets LS pre-installed in each controller 6. The input information (analog data or digital data) input to each logic sheet LS is used for the calculation of the control logic CL described in POL, and the calculation result (analog data or digital data) is output. The calculation result output from each logic sheet LS is output to the control target 2 as a control signal via the I / O unit 10.

[0021] Subsequently, in the control system 1 having the above configuration, the functional configuration of each controller 6 will be described. FIG. 3 is an internal configuration diagram of the controller 6 in FIG. 2. In the following description, the controller 6A among the plurality of controllers 6 provided in the controller unit 4 will be described representatively. However, unless otherwise specified, the same applies to the other controllers 6B, 6C, ···.

[0022] The controller 6A has a first CPU core 8A-1, a second CPU core 8A-2, and a memory unit 20. The first CPU core 8A-1 and the second CPU core 8A-2 execute a plurality of arithmetic tasks corresponding to the plurality of logic sheets LS pre-installed as described above. The memory unit 20 includes a first local data array storage unit 22, a second local data array storage unit 24, and a global data array storage unit 26.

[0023] In the controller 6A, based on a plurality of pre-installed logic sheets LS, arithmetic tasks to be executed by each CPU core 8 (the first CPU core 8A-1 and the second CPU core 8A-2) included in the controller 6A are created. Each of the plurality of logic sheets LS has a defined control period corresponding to the control logic CL included therein. The controller 6A divides the plurality of logic sheets LS into logic sheet groups LSG for each control period, creates an arithmetic task (hereinafter referred to as "arithmetic task 1") for calculating the logic sheet group LSG with the shortest control period among them, and assigns it to the first CPU core 8A-1.

[0024] Further, the controller 6A creates arithmetic tasks for executing logic sheet groups other than the logic sheet group included in the arithmetic task 1 as arithmetic tasks N (N = 2, 3,...) in ascending order of the control period. Here, the control period of the arithmetic task N is n (n = 1, 2,...) times that of the arithmetic task 1.

[0025] Here, the plurality of logic sheets LS executed by the controller 6A include, for example, control logic CL for executing general-purpose programs with a huge amount of calculations such as convergence calculations for obtaining optimal solutions by iterative calculations and artificial intelligence (AI). Such logic sheets LS with a huge amount of calculations have a relatively long control period and may not be completed within a pre-defined control period. Therefore, they are not included in the arithmetic task 1 and are distributed to the logic sheet group LSG to be executed by an arithmetic task N different from the arithmetic task 1 (for example, the arithmetic task 2).

[0026] Each of the controllers 6A, 6B, ··· included in the controller unit 4 is configured such that the execution timings of specific arithmetic tasks are synchronized. In the present embodiment, as will be described later, among a plurality of arithmetic tasks, the execution timing of the arithmetic task 1 with the shortest control period is synchronized among one of the CPU cores 8A-1, 8B-1, ··· of each of the controllers 6A, 6B, ···. After the execution of the arithmetic task 1, the arithmetic task N (N = 2, 3, ···) is woken up from the arithmetic task 1 at a predetermined timing and executed on the other CPU cores 8A-2, 8B-2, ··· of each of the controllers 6A, 6B, ···.

[0027] The first local data array storage unit 22 is a configuration for storing the calculation results of a plurality of arithmetic tasks executed by the controller 6A as the first local data array D1. That is, in each arithmetic task executed by the controller 6A, the intermediate calculation value or the final calculation value passed to other arithmetic tasks is stored as a specified data element of the first local data arrangement storage unit 22. In FIG. 3, in data element 1 of the first local data array D1, the calculation result of the logic sheet LS1-1 executed by the first CPU core 8A-1 is stored, and in data elements 101 and 102, the calculation results of the logic sheet LS2-1 executed by the second CPU core 8A-2 are stored. An example of this is illustrated. Each data element stored in the first local data array D1 in this way is transmitted as tracking data to other controllers 6B, 6C, ···.

[0028] The second local data array storage unit 24 is configured to store, as a second local data array D2, the calculation results referred to among a plurality of calculation tasks received as tracking data from other controllers 6B, 6C, ···. That is, for each data element of the second local data array D2, the calculation result corresponding to each data element of the first local data array D1 is received and stored from other controllers 6B, 6C, ···. In FIG. 3, the second local data array storage unit 24 has a plurality of second local data arrays D2 corresponding to each of the other controllers 6B, 6C, ···. Specifically, for each data element of the second local data array D2 corresponding to the other controller 6B, the calculation result received as tracking data from the controller 6B is stored. Also, for each data element of the second local data array D2 corresponding to the other controller 6C, the calculation result received as tracking data from the controller 6C is stored.

[0029] The global data array storage unit 26 has a global data array Dg capable of storing data elements selected from the first local data array D1 and the second local data array D2. In the data elements of the global data array Dg, the result of comparing the data elements of the first local data array D1 and the data elements of the second local data array D2 is stored. Here, as for which data elements are to be stored as the data elements of the global data array Dg, input selection is made according to a predetermined rule such that each of the controllers 6A, 6B, ··· multiplexed with each other has the same calculation result. For example, for each data element of the global data array Dg, the median value of the data elements of the first local data array D1 and the data elements of the second local data array D2 may be stored. Also, for each data element of the global data array Dg, the value selected as the most frequent value (i.e., the majority vote) among the data elements of the first local data array D1 and the data elements of the second local data array D2 may be stored. Each data element stored in the global data array Dg in this way is transmitted as a calculation result referred to among a plurality of calculation tasks for each calculation task performed by the controller 6A.

[0030] Next, a control method for the control system 1 having the above configuration will be described. FIG. 4 is a flowchart showing the control method of the control system 1 in FIG. 1. In FIG. 4, the processes regarding the arithmetic tasks 1 and N are sequentially shown in the two CPU cores 8A-1 and 8A-2 of the controller 6A. Note that the processes performed by the other controllers 6B, 6C,... are the same as those of the controller 6A unless otherwise specified.

[0031] In each of the multiplexed controllers 6A, 6B,..., the arithmetic task 1 is executed synchronously. In the controller 6A, when the arithmetic task 1 is executed synchronously with the other controllers 6B, 6C,..., in the first CPU core 8A-1 that executes the arithmetic task 1, each data element stored in the first local data array D1 of the other controllers 6B, 6C,... is received as tracking data (step S1-1). These data elements received as tracking data are stored in the second local data array D2 of the controller 6A, and as described above, the result of comparing the data elements selected from the first local data array D1 and the second local data array D2 is stored in the global data array Dg (step S1-2). Each data element stored in the global data array Dg can be referred to in a plurality of arithmetic tasks in the controller 6A as an arithmetic result referred to between the plurality of arithmetic tasks (step S1-3).

[0032] Subsequently, in the first CPU core 8A-1, it is determined whether it is the wake-up timing of the arithmetic task N in the other second CPU core 8A-2 of the controller 6A (step S1-4). When it is the wake-up timing of the arithmetic task N in the second CPU core 8A-2 (step S1-4: YES), in the second CPU core 8A-2 independent of the first CPU core 8A-1, the arithmetic task N (N = 2, 3 ···) is woken up (step S1-5). As a result, in the first CPU core 8A-1, the operation of the control logic corresponding to the arithmetic task 1 is started (step S1-6), and in the second CPU core 8A-2, the operation of the control logic corresponding to the arithmetic task N is started (step S2-1).

[0033] In addition, when it is not the wake-up timing of the arithmetic task N in the second CPU core 8A-2 (step S1-4: NO), that is, when the operation of the logic sheet of the arithmetic task N has not been completed in the second CPU core 8A-2, the wake-up of the arithmetic task N is not performed.

[0034] Subsequently, in the first CPU core 8A-1, the operation of each logic sheet corresponding to the arithmetic task 1 is performed (step S1-7). In step S1-7, in the first CPU core 8A-1, the input element (IFAI: InterFace Analog Input) and the analog output element (IFAO: InterFace Analog Output), which are POL elements described in each logic sheet, interface the arithmetic tasks. Among these dedicated POL elements, for the input element, by referring to the global data array Dg stored in the global data array storage unit 26, data elements necessary for the operation can be input. Also, the output element stores the operation result as the first local data D1 in the first local data array storage unit 22, which is a local buffer.

[0035] In the first CPU core 8A-1, when the operation of all logic sheets is completed (step S1-8), the first CPU core 8A-1 determines whether the logic operation of the operation task N in the other second CPU core 8A-2 has been completed (step S1-9). Still, in the determination of step S1-8, until the operation of all logic sheets is completed, the process returns to step S1-6, and the operation of the next logic sheet is performed. Such repetition of the process is carried out until the operation of all logic sheets is completed.

[0036] On the other hand, in the second CPU core 8A-2, the operation of the logic sheet corresponding to the operation task N is performed (step S2-2). In step S2-2, in the second CPU core 8A-2, the input element (IFAI: InterFace Analog Input) and the analog output element (IFAO: InterFace Analog Output), which are POL elements described in each logic sheet, interface the operation tasks. Among these dedicated POL elements, for the input element, by referring to the global data array Dg stored in the global data array storage unit 26, data elements necessary for the operation can be input. Also, the output element stores the operation result as the first local data D1 in the first local data array storage unit 22, which is a local buffer.

[0037] In the second CPU core 8A-2, when the operations on all the logic sheets are completed (step S2-3), the second CPU core 8A-2 determines whether the logic operation of operation task 1 in the other CPU core 8A-1 has been completed (step S2-4). Then, when it is confirmed that the operations of operation tasks 1 and N executed by the first CPU core 8A-1 and the second CPU core 8A-2 are completed (step S1-9: YES & step S204: YES), the first CPU core 8A-1 and the second CPU core 8A-2 each transmit each data element stored in the first local data array D1 as tracking data to other controllers 6B, 6C, ··· (steps S1-10, S2-5). The timing of transmitting this tracking data is set to be when both operations of operation tasks 1 and N are completed so as not to transmit the states during the operations in each operation task. In addition, in the determination of step S2-3, until the operations on all the logic sheets are completed, the process returns to step S2-1, and the operations on the next logic sheet are performed. Such repetition of the process is carried out until the operations on all the logic sheets are completed.

[0038] As described above, according to the above embodiment, in each multiplexed controller 6 including a plurality of CPU cores, the calculation results of a plurality of calculation tasks are stored as a first local data array D1. Each data element stored in the first local data array D1 is stored as tracking data in the second local data array D2 of another controller 6. The second local data array D2 stores each data element received as tracking data from the first local data array D1 of another controller 6. The global data array Dg stores data elements selected from the first local data array D1 and the second local data array D2 stored in this way, and can be referenced in the calculations of a plurality of calculation tasks in the controller 6. As a result, since there is no difference in the calculation results of each controller 6 having a plurality of CPU cores, even when control is switched to another controller 6 when a problem occurs in a specific controller 6, no mutation occurs in the output signal to the control target. As a result, control based on advanced logic operations can be suitably implemented using the multiplexed controller 6 including a plurality of CPU cores.

[0039] In addition, without departing from the spirit of the present disclosure, it is possible to appropriately replace the components in the above-described embodiment with well-known components, and the above-described embodiments may be appropriately combined.

[0040] The content described in each of the above embodiments is understood as follows, for example.

[0041] (1) A control system according to one aspect is a control system having a plurality of CPU cores capable of executing a logic operation including a plurality of calculation tasks for controlling a control target, and including a plurality of controllers multiplexed with each other, each of the plurality of controllers a first local data array storage unit that stores the calculation results of the plurality of calculation tasks as a first local data array, A second local data array storage unit that stores the calculation result received from another controller as a second local data array; A global data array storage unit that stores data elements selected from the first local data array and the second local data array as a global data array that can be referenced among the plurality of calculation tasks; A tracking data transmission unit that transmits the first local data array as tracking data to the other controller; It is provided with.

[0042] According to the aspect of (1) above, in each multiplexed controller including a plurality of CPU cores, the calculation results of a plurality of calculation tasks are stored as a first local data array. Each data element stored in the first local data array is transmitted to another controller as tracking data, and is stored in the second local data array of the other controller. The second local data array stores each data element received as tracking data from the first local data array of another controller. The global data array stores data elements selected from the first local data array and the second local data array stored in this way, and can be referenced in the calculations of a plurality of calculation tasks in the controller. As a result, there is no difference in the calculation results of each controller having a plurality of CPU cores, so even when control switching to another controller occurs when a problem occurs in a specific controller, there is no sudden change in the output signal to the control target. As a result, control based on advanced logic operations can be suitably implemented using a multiplexed controller including a plurality of CPU cores.

[0043] (2) In another aspect, in the aspect of (1) above, The global data array is selected to have a median value between the first local data array and the second local data array.

[0044] According to the aspect (2) above, by adopting the median value of the first local data array and the second local data array as the global data array, it is possible to effectively prevent differences from occurring in the calculation results of each controller.

[0045] (3) In other aspects, in the aspect (1) or (2) above, the plurality of arithmetic tasks are a first arithmetic task that executes the logic sheet group with the shortest control period among the plurality of logic sheet groups obtained by dividing the plurality of logic sheets in which the logic operation is executable for each control period; a Nth arithmetic task (where N = 2, 3,...) having a control period that is n times (n = 1, 2,...) that of the first arithmetic task and executing the plurality of logic sheet groups in ascending order of the control period and includes.

[0046] According to the aspect (3) above, when executing a plurality of arithmetic tasks including the first arithmetic task and the Nth arithmetic task in a plurality of CPU cores, it is possible to effectively prevent differences from occurring in the calculation results among the multiplexed controllers.

[0047] (4) In other aspects, in the aspect (3) above, the plurality of CPU cores are a first CPU core that executes the first arithmetic task; a second CPU core that executes the Nth arithmetic task and includes.

[0048] According to the aspect (4) above, the first arithmetic task including the logic sheet group with the shortest control period is assigned to the first CPU core, and the other Nth arithmetic tasks are assigned to the second CPU core. As a result, efficient arithmetic operations are possible in a control system in which controllers having a plurality of CPU cores are multiplexed.

[0049] (5) In other aspects, in the aspect (4) above, The plurality of controllers synchronize the execution timing of the first arithmetic task in the first CPU core.

[0050] According to the aspect of (5) above, in each of the multiplexed controllers, the execution timing of the first arithmetic task in the first CPU core is controlled to be synchronized.

[0051] (6) In another aspect, in the aspect of (4) above, The Nth arithmetic task in the second CPU core is woken up by the first arithmetic task executed in the first CPU core.

[0052] According to the aspect of (6) above, in each of the multiplexed controllers, the Nth arithmetic task executed in the second CPU core is controlled to be woken up by the first arithmetic task executed in the first CPU core.

[0053] (7) In another aspect, in any one of the aspects (1) to (6) above, The plurality of arithmetic tasks include an arithmetic operation whose processing time is equal to or more than a predetermined value.

[0054] According to the aspect of (7) above, an arithmetic logic including an arithmetic target that may exceed a preset control cycle due to a processing time equal to or more than a predetermined value, such as a convergence calculation or a learning calculation, can be preferably calculated by a control system including a multiplexed controller having a plurality of CPU cores.

[0055] (8) A control method of a control system according to an aspect is A control method of a control system including a plurality of CPU cores capable of executing a logical operation including a plurality of arithmetic tasks for controlling a control target and including a plurality of controllers multiplexed with each other, In each of the plurality of controllers, a step of storing the arithmetic results of the plurality of arithmetic tasks as a first local data array; a step of storing the operation result received from another controller as a second local data array; a step of storing data elements selected from the first local data array and the second local data array as a global data array that is not referenced among the plurality of arithmetic tasks; a step of transmitting the first local data array as tracking data to the other controller; comprising.

[0056] According to the aspect of (8) above, in each multiplexed controller having a plurality of CPU cores, the operation results of a plurality of arithmetic tasks are stored as a first local data array. Each data element stored in the first local data array is transmitted to another controller as tracking data and stored in the second local data array of the other controller. The second local data array stores each data element received as tracking data from the first local data array of another controller. The global data array stores data elements selected from the first local data array and the second local data array stored in this way, and can be referenced in the operations of a plurality of arithmetic tasks in the controller. As a result, there is no difference in the operation results of each controller having a plurality of CPU cores, so even when control is switched to another controller when a problem occurs in a specific controller, there is no sudden change in the output signal to the control target. As a result, control based on advanced logic operations can be suitably implemented using a multiplexed controller having a plurality of CPU cores.

[0057] (9) The control program of the control system according to one aspect is a control program of a control system having a plurality of CPU cores capable of executing a logic operation including a plurality of arithmetic tasks for controlling a control target, and including a plurality of controllers multiplexed with each other, in a computer device, in each of the plurality of controllers, The step of storing the calculation results of the plurality of calculation tasks as a first local data array; The step of storing the calculation results received from other controllers as a second local data array; The step of storing data elements selected from the first local data array and the second local data array as a global data array that can be referenced among the plurality of calculation tasks; The step of transmitting the first local data array as tracking data to the other controllers; is executable.

[0058] According to the aspect of (9) above, in each multiplexed controller including a plurality of CPU cores, the calculation results of a plurality of calculation tasks are stored as a first local data array. Each data element stored in the first local data array is transmitted as tracking data to other controllers and stored in the second local data array of the other controllers. The second local data array stores each data element received as tracking data from the first local data array of other controllers. The global data array stores data elements selected from the first local data array and the second local data array stored in this way, and can be referenced in the calculations of a plurality of calculation tasks in the controller. As a result, there is no difference in the calculation results of each controller having a plurality of CPU cores. Therefore, even when control switching to another controller occurs when a problem or the like occurs in a specific controller, no mutation occurs in the output signal to the control target. As a result, control based on advanced logic operations can be suitably implemented using a multiplexed controller including a plurality of CPU cores.

Explanation of symbols

[0059] 1 Control system 2 Control target 2a Oscillator 2b Switching device 2c Control valve 2d Shut-off valve 4 Controller Unit 6 (6A, 6B, ···) Controllers 8 CPU Cores 10 I / O Unit 12 I / O Communication Network 20 Memory Section 22 First Local Data Array Storage Section 24 Second Local Data Array Storage Section 26 Global Data Array Storage Section LS Logic Sheet CL Control Logic D1 First Local Data Array D2 Second Local Data Array Dg Global Data Array

Claims

1. A control system having a plurality of CPU cores capable of executing a logic operation including a plurality of arithmetic tasks for controlling a control target, and comprising a plurality of controllers multiplexed with each other, each of the plurality of controllers a first local data array storage unit that stores the operation results of the plurality of arithmetic tasks as a first local data array; a second local data array storage unit that stores the operation results received from other controllers as a second local data array; a global data array storage unit that stores data elements selected from the first local data array and the second local data array as a global data array that can be referenced among the plurality of arithmetic tasks; a tracking data transmission unit that transmits the first local data array as tracking data to the other controllers; A control system comprising.

2. The control system according to claim 1, wherein the global data array is selected so as to have an intermediate value between the first local data array and the second local data array.

3. The plurality of arithmetic tasks a first arithmetic task that executes a logic sheet group with the shortest control cycle among a plurality of logic sheet groups obtained by dividing a plurality of logic sheets included in the logic operation into control cycles; a Nth arithmetic task (where N = 2, 3,...) having a control cycle n times (n = 1, 2,...) that of the first arithmetic task, and executing the plurality of logic sheet groups in ascending order of the control cycle; The control system according to claim 1 or 2, comprising.

4. The plurality of CPU cores a first CPU core that executes the first arithmetic task; a second CPU core that executes the Nth arithmetic task; The control system according to claim 3, comprising.

5. The control system according to claim 4, wherein the plurality of controllers synchronize the execution timing of the first arithmetic task in the first CPU core.

6. The control system according to claim 4, wherein the Nth arithmetic task in the second CPU core is awakened by the first arithmetic task executed by the first CPU core.

7. The control system according to claim 1 or 2, wherein the plurality of arithmetic tasks include an operation whose processing time is equal to or longer than a predetermined value.

8. A control method for a control system having a plurality of CPU cores capable of executing a logic operation including a plurality of arithmetic tasks for controlling a control target, and including a plurality of controllers multiplexed with each other, In each of the plurality of controllers, a step of storing the operation results of the plurality of arithmetic tasks as a first local data array; a step of storing the operation results received from another controller as a second local data array; a step of storing data elements selected from the first local data array and the second local data array as a global data array that can be referred to among the plurality of arithmetic tasks; a step of transmitting the first local data array as tracking data to the other controller; A control method for a control system, comprising:

9. A control program for a control system having a plurality of CPU cores capable of executing a logic operation including a plurality of arithmetic tasks for controlling a control target, and including a plurality of controllers multiplexed with each other, On a computer device, In each of the plurality of controllers, a step of storing the operation results of the plurality of arithmetic tasks as a first local data array; a step of storing the operation results received from another controller as a second local data array; a step of storing data elements selected from the first local data array and the second local data array as a global data array that can be referred to among the plurality of arithmetic tasks; a step of transmitting the first local data array as tracking data to the other controller; A control program for a control system that can execute:

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