Semiconductor storage device, method for controlling semiconductor storage device, and method for manufacturing semiconductor storage device

Abstract

To provide a semiconductor storage device capable of improving electrical characteristics, a method for controlling the semiconductor storage device, and a method for manufacturing the semiconductor storage device.SOLUTION: In a semiconductor storage device of one embodiment, when the distance between a first edge of a first gate electrode layer adjacent to a columnar body and a second edge of the first gate electrode layer adjacent to the columnar body from the opposite side of the first edge is defined as a first distance in a boundary between the first gate electrode layer and a first insulation layer, and the distance between a third edge of the first gate electrode layer adjacent to the columnar body and a fourth edge of the first gate electrode layer adjacent to the columnar body from the opposite side of the third edge is defined as a second distance in a boundary between the first gate electrode layer and a second insulation layer, and when the distance between a fifth edge of a second gate electrode layer adjacent to the columnar body and a sixth edge of the second gate electrode layer adjacent to the columnar body from the opposite side of the fifth edge in a boundary between the second gate electrode layer and the second insulation layer is defined as a third distance, the second distance is greater than the first distance and also greater than the third distance.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device, a control method for a semiconductor memory device, and a manufacturing method for a semiconductor memory device.

Background Art

[0002] A semiconductor memory device having a laminate in which a conductive layer and an insulating layer are alternately laminated, and a columnar body penetrating the laminate is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment provides a semiconductor memory device, a control method for a semiconductor memory device, and a manufacturing method for a semiconductor memory device that can improve electrical characteristics.

Means for Solving the Problems

[0005] A semiconductor memory device according to an embodiment includes a stacked body and a columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. The plurality of gate electrode layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The columnar body extends in the first direction within the stacked body and includes a memory film and a channel layer. The plurality of gate electrode layers include a first gate electrode layer and a second gate electrode layer disposed on a first side of the first gate electrode layer in the first direction and adjacent to the first gate electrode layer among the plurality of gate electrode layers. The plurality of insulating layers include a first insulating layer adjacent to the first gate electrode layer from a second side opposite to the first side in the first direction, and a second insulating layer positioned between the first gate electrode layer and the second gate electrode layer. When viewed in a cross section along the first direction and a second direction orthogonal to the first direction, at a first boundary along the second direction located between the first gate electrode layer and the first insulating layer, a distance between a first edge of the first gate electrode layer adjacent to the columnar body and a second edge of the first gate electrode layer adjacent to the columnar body from a side opposite to the first edge is defined as a first distance; at a second boundary along the second direction located between the first gate electrode layer and the second insulating layer, a distance between a third edge of the first gate electrode layer adjacent to the columnar body and a fourth edge of the first gate electrode layer adjacent to the columnar body from a side opposite to the third edge is defined as a second distance; at a third boundary along the second direction located between the second gate electrode layer and the second insulating layer, a distance between a fifth edge of the second gate electrode layer adjacent to the columnar body and a sixth edge of the second gate electrode layer adjacent to the columnar body from a side opposite to the fifth edge is defined as a third distance. In this case, the second distance is greater than the first distance and greater than the third distance.

Brief Description of Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, a semiconductor memory device, a control method of the semiconductor memory device, and a manufacturing method of the semiconductor memory device according to embodiments will be described with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. And redundant descriptions of these components may be omitted. In the following description, when reference numerals with numbers or letters at the end for distinction do not need to be distinguished from each other, the numbers or letters at the end may be omitted.

[0008] In this application, terms are defined as follows. "Parallel", "orthogonal", or "the same" may include cases where they are respectively "substantially parallel", "substantially orthogonal", or "substantially the same". "Connection" is not limited to mechanical connection and may include electrical connection. That is, "connection" is not limited to the case where a plurality of elements are directly connected, and may include the case where a plurality of elements are connected with another element intervening therebetween. "Adjacent" and "adjacent to" are not limited to the case of being in contact, and may also include the case of being arranged with another element intervening therebetween.

[0009] The +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as follows. The +X direction is the direction in which the word line WL described later extends (see FIG. 3). The -X direction is the opposite direction of the +X direction. When the +X direction and the -X direction are not distinguished, it is simply referred to as the X direction. The +Y direction intersects (for example, is orthogonal to) the X direction. The +Y direction is the direction in which the bit line BL extends (see FIG. 3). The -Y direction is the opposite direction of the +Y direction. When the +Y direction and the -Y direction are not distinguished, it is simply referred to as the Y direction. The +Z direction is a direction orthogonal to the X direction and the Y direction. The +Z direction is the direction from the laminate 30 described later toward the bit line BL (see FIG. 3). The -Z direction is the opposite direction of the +Z direction. When the +Z direction and the -Z direction are not distinguished, it is simply referred to as the Z direction. In the following description, the position in the Z direction may be referred to as "height". The Z direction is an example of the "first direction". The X direction is an example of the "second direction". In the drawings described below, illustrations of configurations not related to the description may be omitted.

[0010] (First Embodiment) <1. Configuration of Semiconductor Memory Device> FIG. 1 is a block diagram showing a part of the configuration of the semiconductor memory device 1. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device and is a NAND type flash memory. The semiconductor memory device 1 can be connected to an external host device and can be used as a storage space of the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0011] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k - 1) (k is an integer of 1 or more). A plurality of memory cell transistors are provided in the block BLK. The block BLK is used as a data erasure unit. A plurality of bit lines and a plurality of word lines are provided in the memory cell array 11. Each memory cell transistor is associated with one bit line and one word line.

[0012] The command register 12 holds a command CMD received by the semiconductor memory device 1 from the host device. The address register 13 holds address information ADD received by the semiconductor memory device 1 from the host device. The address information ADD is used for selecting the block BLK, the word line, and the bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a data write operation, a read operation, an erase operation, etc. based on the command CMD held in the command register 12.

[0013] The driver module 15 includes a voltage generation circuit. The voltage generation circuit generates the voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line in a write operation. In a read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage or current of each bit line, and transfers the determination result to the host device as read data DAT.

[0014] <2. Electrical Configuration of Memory Cell Array> FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 11. FIG. 2 shows one block BLK included in the memory cell array 11. The block BLK includes a plurality (for example, four) of strings STR0 to STR3.

[0015] Each string STR includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer of 1 or more). Each NAND string NS includes, for example, a plurality of memory cell transistors MT0 to MT7, one or more dummy memory cell transistors MTD, one or more drain side selection transistors STD, and one or more source side selection transistors STS. In FIG. 2, for convenience of explanation, only eight memory cell transistors MT0 to MT7 are shown for each NAND string NS. However, each NAND string NS may include more memory cell transistors MT.

[0016] In each NAND string NS, the memory cell transistors MT0 to MT7 are electrically connected in series. Each memory cell transistor MT includes a control gate and a charge storage unit. The control gate of the memory cell transistor MT is electrically connected to any one of the word lines WL0 to WL7. Each memory cell transistor MT accumulates charge in the charge storage unit according to the voltage applied to the control gate via the word line, and holds the data non-volatilely.

[0017] In this embodiment, each block BLK includes a first sub-block BLKSA and a second sub-block BLKSB. Each sub-block BLKS is a unit capable of erasing data independently of other sub-blocks BLKS included in the same block BLK.

[0018] In the example shown in FIG. 2, the first sub-block BLKSA includes sub-strings STRA0 to STRA3. The sub-string STRA0 includes the memory cell transistors MT0 to MT3 of each NAND string NS in the string STR0. The sub-string STRA1 includes the memory cell transistors MT0 to MT3 of each NAND string NS in the string STR1. The sub-string STRA2 includes the memory cell transistors MT0 to MT3 of each NAND string NS in the string STR2. The sub-string STRA3 includes the memory cell transistors MT0 to MT3 of each NAND string NS in the string STR3. In FIG. 2, for convenience of explanation, only four memory cell transistors MT0 to MT3 are shown for each sub-string STRA. However, each sub-string STRA may include more memory cell transistors MT.

[0019] Similarly, the second sub-block BLKSB includes sub-strings STRB0 to STRB3. The sub-string STRB0 includes the memory cell transistors MT4 to MT7 of each NAND string NS in the string STR0. The sub-string STRB1 includes the memory cell transistors MT4 to MT7 of each NAND string NS in the string STR1. The sub-string STRB2 includes the memory cell transistors MT4 to MT7 of each NAND string NS in the string STR2. The sub-string STRB3 includes the memory cell transistors MT4 to MT7 of each NAND string NS in the string STR3. In FIG. 2, for convenience of explanation, only four memory cell transistors MT4 to MT7 are shown for each sub-string STRB. However, each sub-string STRB may include more memory cell transistors MT.

[0020] The dummy memory cell transistor MTD has the same configuration as the memory cell transistor MT, but is a transistor that is not used for holding valid data. The dummy memory cell transistor MTD is disposed between the memory cell transistors MT0 to MT3 included in the first sub-block BLKSA and the memory cell transistors MT4 to MT7 included in the second sub-block BLKSB in each NAND string NS. The dummy memory cell transistor MTD is arranged, for example, to suppress the influence of the data erasing operation from reaching other sub-blocks BLKS (for example, sub-blocks BLKS that do not erase data) when the data of a certain sub-block BLKS is erased. Note that the number of dummy memory cell transistors MTD disposed between two sub-blocks BLKS in each NAND string NS is not limited to one, and may be two or more.

[0021] The drain of the drain-side selection transistor STD is electrically connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side selection transistor STD is electrically connected to one end of the memory cell transistors MT0 to MT7 connected in series electrically. The control gate of the drain-side selection transistor STD is electrically connected to any one of the drain-side selection gate lines SGD0 to SGD3. The drain-side selection transistor STD is electrically connected to the row decoder module 16 via the drain-side selection gate line SGD. The drain-side selection transistor STD electrically connects the NAND string NS and the bit line BL when a predetermined voltage is applied to the corresponding drain-side selection gate line SGD.

[0022] The drain of the source-side selection transistor STS is electrically connected to the other ends of the memory cell transistors MT0 to MT7 that are electrically connected in series. The source of the source-side selection transistor STS is electrically connected to the source line SL. The control gate of the source-side selection transistor STS is electrically connected to the source-side selection gate line SGS. The source-side selection transistor STS electrically connects the NAND string NS and the source line SL when a predetermined voltage is applied to the source-side selection gate line SGS.

[0023] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are electrically commonly connected to the corresponding word lines WL0 to WL7, respectively. Also, in the same block BLK, the control gate of the dummy memory cell transistor MTD is electrically commonly connected to the dummy word line WLD. In the same string STR, the control gates of the drain-side selection transistors STD are electrically commonly connected to the corresponding drain-side selection gate lines SGD0 to SGD3. The control gate of the source-side selection transistor STS is electrically commonly connected to the source-side selection gate line SGS. In the memory cell array 11, the bit line BL is shared by the NAND strings NS to which the same column address is assigned in a plurality of strings STR.

[0024] <3. Physical Configuration of Semiconductor Memory Device> Next, the physical configuration of the semiconductor memory device 1 will be described. FIG. 3 is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 includes, for example, a first chip 2 and a second chip 3.

[0025] <3.1 First Chip> The first chip 2 is a circuit chip including a peripheral circuit. The first chip 2 includes, for example, a semiconductor substrate 21, a peripheral circuit 22, an insulating portion 23, and a plurality of pads 24.

[0026] The semiconductor substrate 21 is a substrate that serves as the base of the first chip 2. At least a part of the semiconductor substrate 21 is plate-shaped along the X direction and the Y direction. The peripheral circuit 22 is a circuit for operating the memory cell array 11 described above. The peripheral circuit 22 includes one or more of the command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17 described above. The insulating portion 23 covers the peripheral circuit 22. The plurality of pads 24 are provided on the surface of the insulating portion 23. Each pad 24 is electrically connected to the peripheral circuit 22.

[0027] <3.2 Second Chip> The second chip 3 is an array chip including the memory cell array 11. The second chip 3 has, for example, a memory cell array 11, an insulating portion 25, and a plurality of pads 26. Here, the insulating portion 25 and the plurality of pads 26 will be described, and the memory cell array 11 will be described later.

[0028] The insulating portion 25 covers the memory cell array 11. The plurality of pads 26 are provided on the surface of the insulating portion 25. Each pad 26 is electrically connected to the wiring included in the memory cell array 11. In the present embodiment, the first chip 2 and the second chip 3 are integrated by facing and bonding the plurality of pads 24 of the first chip 2 and the plurality of pads 26 of the second chip 3.

[0029] <4. Physical Configuration of Memory Cell Array> Next, the physical configuration of the memory cell array 11 will be described. As shown in FIG. 3, the memory cell array 11 has a stacked body 30, a source line SL, a plurality of memory pillars MH, a plurality of bit lines BL, a plurality of contacts CH for memory pillars, a plurality of contacts VY for memory pillars, a plurality of contacts CC for conductive layers, and a wiring portion 80.

[0030] <4.1 Stacked Body> First, the stacked body 30 will be described. FIG. 4 is a cross-sectional view showing an enlarged area surrounded by the F4 line of the semiconductor memory device 1 shown in FIG. 3. Hereinafter, in FIGS. 4 and later, the configuration of the semiconductor memory device 1 is shown in a posture where the +Z direction is the upper side and the -Z direction is the lower side. In the following description, the +Z direction side may be referred to as "upper" and the -Z direction side may be referred to as "lower". However, these expressions are for convenience of explanation and do not define the direction of gravity.

[0031] The stacked body 30 includes a first stacked body 31, a second stacked body 32, and an intermediate insulating layer 33. The first stacked body 31 is disposed on the +Z direction side with respect to the source line SL. The second stacked body 32 is disposed on the +Z direction side with respect to the first stacked body 31. The intermediate insulating layer 33 is disposed between the first stacked body 31 and the second stacked body 32 in the Z direction. The thickness of the intermediate insulating layer 33 in the Z direction is equal to or greater than the thickness of the insulating layer 42 in the Z direction described later. The intermediate insulating layer 33 is formed of, for example, a film containing silicon and oxygen.

[0032] Each of the first stacked body 31 and the second stacked body 32 includes a plurality of conductive layers 41 and a plurality of insulating layers 42. In each of the first stacked body 31 and the second stacked body 32, the plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately stacked one layer at a time in the Z direction.

[0033] The conductive layer 41 is a layer along the X direction and the Y direction and has conductivity. Each conductive layer 41 contains, for example, a conductive material such as tungsten, molybdenum, or silicon doped with impurities. The conductive layer 41 is an example of a "gate electrode layer".

[0034] One or more of the plurality of conductive layers 41 located above in the stacked body 30 can function as a drain side selection gate line SGD. The drain side selection gate line SGD is commonly provided for a plurality of memory pillars MH arranged in the X direction and the Y direction. The intersection of the drain side selection gate line SGD and the channel layer 52 (described later) of each memory pillar MH functions as the above-described drain side selection transistor STD.

[0035] In the laminate 30, one or more of the conductive layers 41 positioned below among the plurality of conductive layers 41 can function as a source-side selection gate line SGS. The source-side selection gate line SGS is provided in common for a plurality of memory pillars MH arranged in the X direction and the Y direction. The intersection of the source-side selection gate line SGS and the channel layer 52 of each memory pillar MH functions as the above-described source-side selection transistor STS.

[0036] In the laminate 30, at least a part of the remaining conductive layers 41 provided between the conductive layers 41 functioning as the drain-side selection gate line SGD and the source-side selection gate line SGS among the plurality of conductive layers 41 can function as a word line WL. The word line WL is provided in common for a plurality of memory pillars MH arranged in the X direction and the Y direction. In the present embodiment, the intersection of the word line WL and the channel layer 52 of each memory pillar MH functions as a memory cell transistor MT. The memory cell transistor MT will be described in detail later.

[0037] In the present embodiment, the plurality of word lines WL include a plurality of word lines WLA corresponding to the first sub-block BLKSA and a plurality of word lines WLB corresponding to the second sub-block BLKSB. The plurality of word lines WLA are included in the first laminate 31. The plurality of word lines WLB are included in the second laminate 32.

[0038] In the laminate 30, at least another part of the remaining conductive layers 41 provided between the conductive layers 41 functioning as the drain-side selection gate line SGD and the source-side selection gate line SGS among the plurality of conductive layers 41 can function as a dummy word line WLD. The dummy word line WLD is provided in common for a plurality of memory pillars MH arranged in the X direction and the Y direction. In the present embodiment, the intersection of the dummy word line WLD and the channel layer 52 of each memory pillar MH functions as a dummy memory cell transistor MTD.

[0039] In this embodiment, one or more conductive layers 41 located at the uppermost position among the plurality of conductive layers 41 included in the first laminate 31 and one or more conductive layers 41 located at the lowermost position among the plurality of conductive layers 41 included in the second laminate 32 are provided as dummy word lines WLD. In other words, the dummy word lines WLD are arranged between the plurality of word lines WLA and the plurality of word lines WLB in the Z direction.

[0040] The insulating layer 42 is provided between two adjacent conductive layers 41 in the Z direction and is an insulating film that insulates the two conductive layers 41. The insulating layer 42 is a layer along the X direction and the Y direction. The insulating layer 42 contains, for example, silicon and oxygen.

[0041] <4.2 Source Line> The source line SL is arranged on the -Z direction side with respect to the laminate 30. The source line SL is a conductive layer that spreads in the X direction and the Y direction. The source line SL contains a conductive material such as tungsten, molybdenum, or silicon doped with impurities.

[0042] <4.3 Memory Pillar> The plurality of memory pillars MH are arranged in the X direction and the Y direction (see FIG. 3). Each memory pillar MH extends in the Z direction within the laminate 30 and penetrates the laminate 30. The lower end of each memory pillar MH is in contact with the source line SL. The upper end of each memory pillar MH is in contact with a contact CH, which will be described later. The memory pillar MH is an example of a "columnar body".

[0043] FIG. 5 is a cross-sectional view taken along the F5 - F5 line of the semiconductor memory device 1 shown in FIG. 4. The memory pillar MH has, for example, a memory film (multilayer film) 51, a channel layer 52, an insulating core 53, and a cap portion 54 (see FIG. 4).

[0044] The memory film 51 is provided on the outer peripheral side of the channel layer 52. The memory film 51 is located between the plurality of conductive layers 41 and the channel layer 52. The memory film 51 contains, for example, a block insulating film 61, a charge trap film 62, and a tunnel insulating film 63.

[0045] The block insulating film 61 is provided between the plurality of conductive layers 41 and the charge trap film 62. The block insulating film 61 is an insulating film that suppresses back tunneling. Back tunneling is a phenomenon in which charges return from the word line WL to the charge trap film 62. The block insulating film 61 is formed in a ring shape and extends in the Z direction. The block insulating film 61, for example, extends over the entire length of the memory pillar MH in the Z direction. The block insulating film 61 is, for example, a laminated structure film in which a plurality of insulating films such as a film containing silicon and oxygen or a film containing metal and oxygen are laminated. An example of the film containing metal and oxygen is aluminum oxide. The block insulating film 61 may contain a high dielectric constant material (High-k material) such as silicon nitride or hafnium oxide.

[0046] The charge trap film 62 is located between the block insulating film 61 and the tunnel insulating film 63. The charge trap film 62 is formed in a ring shape and extends in the Z direction. The charge trap film 62, for example, extends over the entire length of the memory pillar MH in the Z direction. The charge trap film 62 is a functional film having a large number of crystal defects (trapping levels) and capable of trapping charges in the crystal defects. The charge trap film 62 contains, for example, silicon and nitrogen. A portion of the charge trap film 62 adjacent to each word line WL is an example of a "charge storage portion" capable of storing information by accumulating charges.

[0047] The tunnel insulating film 63 is provided between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63 is, for example, annular along the outer peripheral surface of the channel layer 52 and extends in the Z direction along the channel layer 52. The tunnel insulating film 63, for example, extends over the entire length of the memory pillar MH in the Z direction. The tunnel insulating film 63 is a potential barrier between the channel layer 52 and the charge trap film 62. The tunnel insulating film 63 contains silicon and oxygen, or silicon, oxygen, and nitrogen.

[0048] The channel layer 52 is provided inside the memory film 51. The channel layer 52 is, for example, formed in an annular shape. The channel layer 52 extends in the Z direction. The channel layer 52, for example, extends over the entire Z-direction length of the memory pillar MH. The channel layer 52 contains a semiconductor material such as polysilicon. The channel layer 52 may be doped with impurities. When a voltage is applied to the word line WL, the channel layer 52 can form a channel to electrically connect the bit line BL and the source line SL.

[0049] As a result, at the same height as each word line WL, a memory cell transistor MT of, for example, the MANOS (Metal - Al - Nitride - Oxide - Silicon) type is formed by the edge of the word line WL adjacent to the memory pillar MH, the block insulating film 61, the charge trap film 62, the tunnel insulating film 63, and the channel layer 52. Note that the memory film 51 may have a floating gate type charge storage part (floating gate electrode) as a charge storage part instead of the charge trap film 62. The floating gate electrode contains, for example, silicon doped with impurities.

[0050] The insulating core 53 is provided inside the channel layer 52. The insulating core 53 fills at least a part of the inside of the channel layer 52. The insulating core 53 contains silicon and oxygen. A part of the insulating core 53 is formed in a columnar shape along the inner peripheral surface of the channel layer 52. The insulating core 53 may have a space part (air gap) inside the insulating core 53. The insulating core 53 extends in the Z direction. The insulating core 53, for example, extends over most of the Z direction of the memory pillar MH except for the upper end part of the memory pillar MH (see FIG. 4).

[0051] Next, returning to FIG. 4, the cap portion 54 will be described. The cap portion 54 is provided above the insulating core 53. The cap portion 54 contains a semiconductor material such as amorphous silicon or polysilicon. The cap portion 54 may be doped with impurities. The cap portion 54 is disposed on the inner peripheral side of the upper end portion of the memory film 51 and is integrally formed with the channel layer 52. The cap portion 54, together with the upper end portion of the channel layer 52, forms the upper end portion of the memory pillar MH. A contact CH contacts the cap portion 54 in the Z direction.

[0052] As shown in FIG. 4, each memory pillar MH is, for example, a two-stage columnar body in the Z direction and includes a first columnar portion 71 and a second columnar portion 72. The first columnar portion 71 is located between the source line SL and the second columnar portion 72 in the Z direction. The second columnar portion 72 is disposed on the +Z direction side with respect to the first columnar portion 71. The diameter of each of the first columnar portion 71 and the second columnar portion 72 gradually decreases as it progresses in the -Z direction. In other words, the width in the X direction of each of the first columnar portion 71 and the second columnar portion 72 gradually decreases as it progresses in the -Z direction. In the present embodiment, the width in the X direction of the upper end of the first columnar portion 71 is larger than the width in the X direction of the lower end of the second columnar portion 72. Also in the present embodiment, the width W1 in the X direction of the +Z direction side end MHe1 of the memory pillar MH is larger than the width W2 in the X direction of the -Z direction side end MHe2 of the memory pillar MH. The width W2 in the X direction of the -Z direction side end MHe2 means the width in the X direction at the contact position between the memory pillar MH and the surface of the source line SL.

[0053] <4.4 Bit Lines> Next, the bit line BL will be described. The bit line BL is a wiring for selecting at least one memory pillar MH from among a plurality of memory pillars MH. The plurality of bit lines BL are arranged on the +Z direction side with respect to the stacked body 30. The plurality of bit lines BL are spaced apart in the X direction and arranged side by side in the X direction. Each bit line BL extends in the Y direction. Each bit line BL is connected to the channel layer 52 of the memory pillar MH via the contact VY, the contact CH, and the cap portion 54. Thereby, any memory cell transistor MT can be selected from among the plurality of three-dimensionally arranged memory cell transistors MT by the combination of the word line WL and the bit line BL.

[0054] <4.5 Contact for Conductive Layer> As shown in FIG. 3, the contact CC is an electrical connection portion that electrically connects the conductive layer 41 and the wiring included in the wiring portion 80. The plurality of contacts CC extend in the Z direction, and for example, the lengths in the Z direction are different from each other. One end of each contact CC is electrically connected to the corresponding conductive layer 41. The other end of each contact CC is electrically connected to the wiring included in the wiring portion 80.

[0055] <5. Shape of Word Line> Next, the shape of the conductive layer 41 of the present embodiment will be described. FIG. 6 is a cross-sectional view showing an enlarged view of the region surrounded by the F6 line of the semiconductor memory device 1 shown in FIG. 4. Each word line WL includes a conductive portion 45 and a barrier metal film 46.

[0056] The conductive portion 45 is a portion that forms the main part of the word line WL. The conductive portion 45 extends in layers in the X direction and the Y direction. The conductive portion 45 includes the above-described conductive material (for example, tungsten, molybdenum, or silicon doped with impurities).

[0057] The barrier metal film 46 is a film for suppressing the diffusion of the conductive material contained in the conductive portion 45. The barrier metal film 46 is provided along the surface of the conductive portion 45. For example, the barrier metal film 46 is provided along the surfaces of both the +Z-direction side surface and the -Z-direction side surface of the conductive portion 45. The barrier metal film 46 includes, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen.

[0058] (Configuration of the second laminate) First, the configuration of the second laminate 32 will be described. As shown in FIG. 6, the plurality of word lines WLB of the second laminate 32 include, for example, word line WLB-1, word line WLB-2, and word line WLB-3. In the present embodiment, the +Z-direction side is an example of the "first side". The word line WLB-1 is an example of the "first gate electrode layer". The word line WLB-2 is disposed on the +Z-direction side with respect to the word line WLB-1 and is the word line WLB located next to the word line WLB-1 among the plurality of word lines WLB. The word line WLB-2 is an example of the "second gate electrode layer". The word line WLB-3 is disposed on the +Z-direction side with respect to the word line WLB-2 and is the word line WLB located next to the word line WLB-2 among the plurality of word lines WLB.

[0059] Also, the plurality of insulating layers 42 of the second laminate 32 include, for example, insulating layer 42B-1, insulating layer 42B-2, and insulating layer 42B-3. In the present embodiment, the -Z-direction side is an example of the "second side". The insulating layer 42B-1 is adjacent to the word line WLB-1 on the -Z-direction side. The insulating layer 42B-1 is an example of the "first insulating layer". The insulating layer 42B-2 is located between the word line WLB-1 and the word line WLB-2. The insulating layer 42B-2 is an example of the "second insulating layer". The insulating layer 42B-3 is located between the word line WLB-2 and the word line WLB-3.

[0060] (Shape of the word line of the second laminate) Next, the shape of the word line WLB will be described. In this embodiment, each word line WLB includes a base portion 101 and a recessed portion 102.

[0061] The base portion 101 is included, for example, between the center of the word line WLB in the Z direction and the surface on the -Z direction side of the word line WLB in the word line WLB. The base portion 101 has a shape along the memory pillar MH in the Z direction. The base portion 101 has an edge 101a adjacent to the memory pillar MH in the X direction.

[0062] The recessed portion 102 is located on the +Z direction side with respect to the base portion 101. The recessed portion 102 is included, for example, between the center of the word line WLB in the Z direction and the surface on the +Z direction side of the word line WLB in the word line WLB. At least a part of the recessed portion 102 is recessed with respect to the base portion 101 so as to be away from the memory pillar MH in the X direction. The recessed portion 102 is inclined so as to be away from the memory pillar MH as it is located on the +Z direction side. The recessed portion 102 has an edge 102a adjacent to the memory pillar MH in the X direction.

[0063] In this embodiment, the memory film 51 of the memory pillar MH has a bulging portion 51a bulging toward the recessed portion 102 of the word line WLB at a height corresponding to the recessed portion 102 of each word line WLB. Similarly, the channel layer 52 of the memory pillar MH has a bulging portion 52a bulging toward the recessed portion 102 of the word line WLB at a height corresponding to the recessed portion 102 of each word line WLB. Each of the bulging portion 51a and the bulging portion 52a is formed, for example, in an annular shape when viewed from the Z direction.

[0064] In this embodiment, the base portion 101 of the word line WLB-1 is an example of the "first portion". The edge 101a of the base portion 101 of the word line WLB-1 is an example of the "first edge portion". The recessed portion 102 of the word line WLB-1 is an example of the "second portion". The edge 102a of the recessed portion 102 of the word line WLB-1 is an example of the "second edge portion". The edge 102a of the word line WLB-1 is greatly inclined with respect to the edge 101a of the word line WLB-1 in the Z direction.

[0065] Similarly, the base 101 of the word line WLB-2 is an example of a "third part". The edge 101a of the base 101 of the word line WLB-2 is an example of a "third edge". The recessed portion 102 of the word line WLB-2 is an example of a "fourth part". The edge 102a of the recessed portion 102 of the word line WLB-2 is an example of a "fourth edge". The edge 102a of the word line WLB-2 is greatly inclined with respect to the edge 101a of the word line WLB-2 in the Z direction.

[0066] (Dimensional relationships of word lines in the second laminate) Next, the dimensional relationships of the word lines WLB of the second laminate 32 will be described. When viewed in the cross-section shown in FIG. 6 (a cross-section along the X direction and the Z direction), the following dimensional relationships are satisfied. The word line WLB-1 has a first edge E1 adjacent to the memory pillar MH in the X direction at a first boundary B1 along the X direction at the boundary between the word line WLB-1 and the insulating layer 42B-1, and a second edge E2 adjacent to the memory pillar MH from the side opposite to the first edge E1 in the X direction. And the distance in the X direction between the first edge E1 and the second edge E2 is defined as a first distance L1.

[0067] Also, the word line WLB-1 has a third edge E3 adjacent to the memory pillar MH in the X direction at a second boundary B2 along the X direction at the boundary between the word line WLB-1 and the insulating layer 42B-2, and a fourth edge E4 adjacent to the memory pillar MH from the side opposite to the third edge E3 in the X direction. And the distance in the X direction between the third edge E3 and the fourth edge E4 is defined as a second distance L2.

[0068] Also, the word line WLB-2 has a fifth edge E5 adjacent to the memory pillar MH in the X direction at a third boundary B3 along the X direction at the boundary between the word line WLB-2 and the insulating layer 42B-2, and a sixth edge E6 adjacent to the memory pillar MH from the side opposite to the fifth edge E5 in the X direction. And the distance in the X direction between the fifth edge E5 and the sixth edge E6 is defined as a third distance L3.

[0069] In this case, the second distance L2 is greater than the first distance L1 and greater than the third distance L3. From another perspective, the shortest distance between the channel layer 52 and the third edge E3 is greater than the shortest distance between the channel layer 52 and the first edge E1 and greater than the shortest distance between the channel layer 52 and the fifth edge E5.

[0070] This relationship is also satisfied between the other two word lines WLB included in the second laminate 32. For example, this relationship is also satisfied between the word line WLB-2 and the word line WLB-3. In this case, in the above description regarding the word line WLB-1 and the word line WLB-2, "word line WLB-1" may be read as "word line WLB-2", "word line WLB-2" may be read as "word line WLB-3", "insulating layer 42B-1" may be read as "insulating layer 42B-2", and "insulating layer 42B-2" may be read as "insulating layer 42B-3".

[0071] FIG. 7 is a cross-sectional view taken along the F7-F7 line of the semiconductor memory device 1 shown in FIG. 6. As shown in FIG. 7, when viewed from the Z direction, at the second boundary B2 (see FIG. 6) along the X direction at the boundary between the word line WLB-1 and the insulating layer 42B-2, an annular first boundary line BD1 is defined between the word line WLB-1 and the memory pillar MH by the annular edge EC1 of the word line WLB-1. Similarly, when viewed from the Z direction, at the third boundary B3 (see FIG. 6) along the X direction at the boundary between the word line WLB-2 and the insulating layer 42B-2, an annular second boundary line BD2 is defined between the word line WLB-2 and the memory pillar MH by the annular edge EC2 of the word line WLB-2. And when viewed from the Z direction, the second boundary line BD2 is located inside the first boundary line BD1.

[0072] This relationship is also satisfied between the other two word lines WLB included in the second laminate 32. For example, the above relationship is also satisfied between word line WLB-2 and word line WLB-3. In this case, in the above description regarding word line WLB-1 and word line WLB-2, "word line WLB-1" may be read as "word line WLB-2", "word line WLB-2" may be read as "word line WLB-3", and "insulating layer 42B-2" may be read as "insulating layer 42B-3".

[0073] (Configuration of the First Laminate) Next, the configuration of the first laminate 31 will be described. As shown in FIG. 6, the plurality of word lines WLA of the first laminate 31 include, for example, word line WLA-1, word line WLA-2, and word line WLA-3. Word line WLA-1 is disposed on the -Z direction side with respect to word line WLB-1. Word line WLA-1 is an example of a "third gate electrode layer". Word line WLA-2 is disposed between word line WLA-1 and word line WLB-1, and is the word line WLA located adjacent to word line WLA-1 among the plurality of word lines WLA. Word line WLA-2 is an example of a "fourth gate electrode layer". Word line WLA-3 is disposed on the +Z direction side with respect to word line WLA-2, and is the word line WLB located adjacent to word line WLA-2 among the plurality of word lines WLA.

[0074] Also, the plurality of insulating layers 42 of the first laminate 31 include, for example, insulating layer 42A-1, insulating layer 42A-2, and insulating layer 42A-3. Insulating layer 42A-1 is located between word line WLA-1 and word line WLA-2. Insulating layer 42A-1 is an example of a "third insulating layer". Insulating layer 42A-2 is located between word line WLA-2 and word line WLA-3, and is adjacent on the +Z direction side with respect to word line WLA-2. Insulating layer 42A-2 is an example of a "fourth insulating layer". Insulating layer 42A-3 is adjacent on the +Z direction side with respect to word line WLA-3.

[0075] (Shape of the Word Lines of the First Laminate) Next, the shape of the word line WLA will be described. In this embodiment, each word line WLA includes a base portion 111 and a recessed portion 112.

[0076] The base portion 111 is included, for example, between the center of the word line WLA in the Z direction and the surface on the +Z direction side of the word line WLA in the word line WLA. The base portion 111 has a shape along the memory pillar MH in the Z direction. The base portion 111 has an edge 111a adjacent to the memory pillar MH in the X direction.

[0077] The recessed portion 112 is located on the -Z direction side with respect to the base portion 111. The recessed portion 112 is included, for example, between the center of the word line WLA in the Z direction and the surface on the -Z direction side of the word line WLA in the word line WLA. At least a part of the recessed portion 112 is recessed with respect to the base portion 111 so as to be away from the memory pillar MH in the X direction. The recessed portion 112 is inclined so as to be away from the memory pillar MH as it is located on the -Z direction side. The recessed portion 112 has an edge 112a adjacent to the memory pillar MH in the X direction.

[0078] In this embodiment, the memory film 51 of the memory pillar MH has a bulging portion 51a that bulges toward the recessed portion 112 of each word line WLA at a height corresponding to the recessed portion 112 of each word line WLA. Similarly, the channel layer 52 of the memory pillar MH has a bulging portion 52a that bulges toward the recessed portion 112 of each word line WLA at a height corresponding to the recessed portion 112 of each word line WLA. Each of the bulging portion 51a and the bulging portion 52a is formed in an annular shape, for example, when viewed from the Z direction.

[0079] In this embodiment, the edge 112a of the word line WLA-1 is greatly inclined with respect to the edge 111a of the word line WLA-1 in the Z direction. Similarly, the edge 112a of the word line WLA-2 is greatly inclined with respect to the edge 111a of the word line WLA-2 in the Z direction.

[0080] (Dimension relationship of word lines in the first stacked body) Next, the dimension relationship of the word line WLA of the first stacked body 31 will be described. When viewed in the cross section shown in FIG. 6 (the cross section along the X direction and the Z direction), the following dimensional relationships are satisfied. The word line WLA-1 has, at the fourth boundary B4 along the X direction, which is the boundary between the word line WLA-1 and the insulating layer 42A-1, a seventh edge E7 adjacent to the memory pillar MH in the X direction and an eighth edge E8 adjacent to the memory pillar MH from the side opposite to the seventh edge E7 in the X direction. And let the distance in the X direction between the seventh edge E7 and the eighth edge E8 be the fourth distance L4.

[0081] Also, the word line WLA-2 has, at the fifth boundary B5 along the X direction, which is the boundary between the word line WLA-2 and the insulating layer 42A-1, a ninth edge E9 adjacent to the memory pillar MH in the X direction and a tenth edge E10 adjacent to the memory pillar MH from the side opposite to the ninth edge E9 in the X direction. And let the distance in the X direction between the ninth edge E9 and the tenth edge E10 be the fifth distance L5.

[0082] Also, the word line WLA-2 has, at the sixth boundary B6 along the X direction, which is the boundary between the word line WLA-2 and the insulating layer 42A-2, an eleventh edge E11 adjacent to the memory pillar MH in the X direction and a twelfth edge E12 adjacent to the memory pillar MH from the side opposite to the eleventh edge E11 in the X direction. And let the distance in the X direction between the eleventh edge E11 and the twelfth edge E12 be the sixth distance L6.

[0083] In this case, the fifth distance L5 is larger than the fourth distance L4 and also larger than the sixth distance L6. Viewed from another perspective, the shortest distance between the channel layer 52 and the ninth edge E9 is larger than the shortest distance between the channel layer 52 and the seventh edge E7 and also larger than the shortest distance between the channel layer 52 and the eleventh edge E11.

[0084] This relationship is also satisfied between the other two word lines WLA included in the first laminate 31. For example, the above relationship is also satisfied between the word line WLA-2 and the word line WLA-3. In this case, in the above description regarding the word line WLA-1 and the word line WLA-2, “word line WLA-1” may be read as “word line WLA-2”, “word line WLA-2” may be read as “word line WLA-3”, “insulating layer 42A-1” may be read as “insulating layer 42A-2”, and “insulating layer 42A-2” may be read as “insulating layer 42A-3”.

[0085] FIG. 8 is a cross-sectional view taken along the F8-F8 line of the semiconductor memory device 1 shown in FIG. 6. As shown in FIG. 8, when viewed from the Z direction, at the boundary between the word line WLA-2 and the insulating layer 42A-1, which is the fifth boundary B5 (see FIG. 6) along the X direction, an annular fourth boundary line BD4 is defined between the word line WLA-2 and the memory pillar MH by the annular edge EC4 of the word line WLA-2. Similarly, when viewed from the Z direction, at the boundary between the word line WLA-1 and the insulating layer 42A-1, which is the fourth boundary B4 (see FIG. 6) along the X direction, an annular third boundary line BD3 is defined between the word line WLA-1 and the memory pillar MH by the annular edge EC3 of the word line WLA-1. And when viewed from the Z direction, the third boundary line BD3 is located inside the fourth boundary line BD4.

[0086] This relationship is also satisfied between the other two word lines WLA included in the first laminate 31. For example, the above relationship is also satisfied between the word line WLA-2 and the word line WLA-3. In this case, in the above description regarding the word line WLA-1 and the word line WLA-2, “word line WLA-1” may be read as “word line WLA-2”, “word line WLA-2” may be read as “word line WLA-3”, “insulating layer 42A-1” may be read as “insulating layer 42A-2”.

[0087] <6. Configuration of the End Region> Next, the end region ER of the memory cell array 11 will be described. FIG. 9 is a cross-sectional view taken along the line F9-F9 of the semiconductor memory device 1 shown in FIG. 2. The laminate 30 has a memory region CR and an end region ER.

[0088] The memory region CR includes the plurality of conductive layers 41 and the plurality of insulating layers 42 described above. The plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately stacked one layer at a time in the Z direction. The plurality of conductive layers 41 are formed by performing a replacement process in which a sacrificial layer (insulating layer 130 described later) provided during manufacturing is replaced with the conductive layer 41.

[0089] On the other hand, the end region ER includes a plurality of insulating layers 130 instead of the plurality of conductive layers 41. That is, the end region ER includes the plurality of insulating layers 130 and the plurality of insulating layers 42. The plurality of insulating layers 130 and the plurality of insulating layers 42 are alternately stacked one layer at a time in the Z direction. The insulating layer 130 is an insulating layer that remains in the laminate 30 without being replaced with the conductive layer 41 by the above-described replacement process by existing in the end region ER. Note that a plurality of dummy memory pillars MHD are provided in the end region ER. The dummy memory pillar MHD has the same configuration as the memory pillar MH, but is a columnar body that is not used for data storage.

[0090] FIG. 10 is an enlarged cross-sectional view showing a region surrounded by the line F10 of the semiconductor memory device 1 shown in FIG. 9.

[0091] (Structure of the second laminate) First, the structure of the second laminate 32 will be described. The second laminate 32 includes a plurality of insulating layers 130B as the plurality of insulating layers 130. Each insulating layer 130B includes an insulating layer 131B and an insulating layer 132B.

[0092] The insulating layer 131B is included, for example, in the insulating layer 130B between the center of the insulating layer 130B in the Z direction and the surface on the -Z direction side of the insulating layer 130B. The insulating layer 131B can have the same thickness and the same shape as the base 101 of the word line WLB. The insulating layer 131B includes a first material. An example of the first material includes nitrogen and silicon (for example, silicon nitride (SiN)).

[0093] The insulating layer 132B is located on the +Z direction side with respect to the insulating layer 131B. The insulating layer 132B is included, for example, between the center in the Z direction of the insulating layer 130B and the surface on the +Z direction side of the insulating layer 130B in the insulating layer 130B. At least a part of the insulating layer 132B recedes from the dummy memory pillar MHD with respect to the insulating layer 131B in the X direction. The insulating layer 132B is inclined, for example, so as to be farther from the dummy memory pillar MHD as it is located on the +Z direction side. The insulating layer 132B may have the same thickness and the same shape as the recessed portion 102 of the word line WLB. The insulating layer 132B contains a second material. The second material has a composition different from that of the first material. The second material is a material that is more easily removed by the first etchant than the first material (for example, a material having a different wet rate with respect to the first etchant). An example of the second material contains nitrogen and silicon and has a higher oxygen content than the above-described first material (for example, silicon nitride (SiN) doped with oxygen).

[0094] The presence of the two insulating layers of the insulating layer 131B and the insulating layer 132B can be confirmed by observing the interface between the insulating layer 131B and the insulating layer 132B using a transmission electron microscope (TEM), and detecting that the components (for example, oxygen concentration) are different between the insulating layer 131B and the insulating layer 132B by component analysis. The same applies to the insulating layer 131A and the insulating layer 132A described later.

[0095] (Structure of the first laminate) Next, the structure of the first laminate 31 will be described. The first laminate 31 includes a plurality of insulating layers 130A as the plurality of insulating layers 130. Each insulating layer 130A includes an insulating layer 131A and an insulating layer 132A.

[0096] The insulating layer 131A is included, for example, in the insulating layer 130A between the center of the insulating layer 130A in the Z direction and the surface on the +Z direction side of the insulating layer 130A. The insulating layer 131A may have the same thickness and the same shape as the base portion 111 of the word line WLA. The insulating layer 131A contains the first material.

[0097] The insulating layer 132A is located on the -Z direction side with respect to the insulating layer 131A. The insulating layer 132A is included, for example, in the insulating layer 130A between the center of the insulating layer 130A in the Z direction and the surface on the -Z direction side of the insulating layer 130A. At least a part of the insulating layer 132A recedes from the dummy memory pillar MHD with respect to the insulating layer 131A in the X direction. The insulating layer 132A is inclined so as to be farther from the dummy memory pillar MHD as it is located on the -Z direction side. The insulating layer 132A may have the same thickness and the same shape as the receding portion 112 of the word line WLA. The insulating layer 132A contains the second material.

[0098] <7. Control method> Next, a control method of the semiconductor memory device 1 will be described. The control method described below is executed, for example, by the control circuit 14.

[0099] <7.1 Writing order> FIG. 11 is a diagram showing the writing order of the first embodiment. As shown in FIG. 11, writing of data to the first sub-block BLKSA is performed by applying a program voltage Vpgm for data writing to the word lines WLA located one by one in order to the word line WLA located at the uppermost position among the plurality of word lines WLA of the first stacked body 31 starting from the word line WLA (see arrow A1 in the figure). On the other hand, writing of data to the second sub-block BLKSB is performed by applying a program voltage Vpgm for data writing to the word lines WLB located one by one in order to the word line WLB located at the lowermost position among the plurality of word lines WLB of the second stacked body 32 starting from the word line WLB (see arrow A2 in the figure).

[0100] In the present application, "applying a program voltage" means, for example, repeating a program loop including an applying operation of a program voltage Vpgm, a program verify for determining whether or not the threshold voltage of a memory cell transistor MT to be written has reached a threshold voltage corresponding to a desired data when the program voltage Vpgm is applied, and a voltage changing operation of increasing a set value of the program voltage Vpgm when the program verify fails, until a predetermined condition is satisfied.

[0101] In the present embodiment, a memory cell transistor MTA-1 is formed at an intersection of a word line WLA-1 and a memory pillar MH. A memory cell transistor MTA-2 is formed at an intersection of a word line WLA-2 and the memory pillar MH. A memory cell transistor MTA-3 is formed at an intersection of a word line WLA-3 and the memory pillar MH. The memory cell transistor MTA-1 is an example of the "third memory cell transistor". The memory cell transistor MTA-2 is an example of the "fourth memory cell transistor".

[0102] The memory cell transistors MTA-1 to MTA-3 are arranged in the -Z direction in the order of the memory cell transistor MTA-3, the memory cell transistor MTA-2, and the memory cell transistor MTA-1. In this case, the control circuit 14 performs a writing operation of injecting charges into the memory cell transistor MTA-3, then performs a writing operation of injecting charges into the memory cell transistor MTA-2, and then performs a writing operation of injecting charges into the memory cell transistor MTA-1.

[0103] On one hand, a memory cell transistor MTB-1 is formed at the intersection of the word line WLB-1 and the memory pillar MH. A memory cell transistor MTB-2 is formed at the intersection of the word line WLB-2 and the memory pillar MH. A memory cell transistor MTB-3 is formed at the intersection of the word line WLB-3 and the memory pillar MH. The memory cell transistor MTB-1 is an example of the "first memory cell transistor". The memory cell transistor MTB-2 is an example of the "second memory cell transistor".

[0104] The memory cell transistors MTB-1 to MTB-3 are arranged in the -Z direction in the order of the memory cell transistor MTB-3, the memory cell transistor MTB-2, and the memory cell transistor MTB-1. In this case, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTB-1, then performs a writing operation of injecting charge into the memory cell transistor MTB-2, and then performs a writing operation of injecting charge into the memory cell transistor MTB-3.

[0105] <7.2 Voltage Management of Channel Layer> Here, the voltage management of the channel layer 52 will be described. If for some reason the potential of the channel layer 52 drops to a negative potential before the writing operation, the voltage of the channel layer 52 will not rise sufficiently during the writing operation, and a large potential difference will occur when the program voltage Vpgm is applied, which may cause the threshold voltage of the memory cell transistor MT that is not the writing target to increase. Therefore, the control circuit 14 of the present embodiment performs a channel precharge to reset the voltage of the channel layer 52 to 0V before the writing operation.

[0106] FIG. 12 is a diagram schematically showing a memory pillar MH. FIG. 13 is a timing chart for explaining a write operation regarding the memory pillar MH shown in FIG. 12. In FIG. 13, among the voltages applied to the word line WL, the voltage marked as "Vpgm" means the above-described program voltage Vpgm. On the other hand, among the voltages applied to the word line WL, the voltage between 0 and Vpgm without the mark of "Vpgm" is high enough to turn on the memory cell transistor MT, but low enough not to perform writing.

[0107] As shown in FIG. 13, in the write operation for the first stacked body 31 (write operation for the first sub-block BLKSA), before the write operation is performed on each memory cell transistor MT, a channel precharge PA is performed by applying a voltage to the source-side selection gate line SGS to electrically connect the channel layer 52 and the source line SL and set the voltage of the channel layer 52 to 0V. Therefore, in the write operation for the first stacked body 31 (write operation for the first sub-block BLKSA), after performing the channel precharge PA using the source-side selection gate line SGS, the write operation is performed in the order of the memory cell transistor MT3, the memory cell transistor MT2, the memory cell transistor MT1, and the memory cell transistor MT0.

[0108] On the other hand, in the writing to the second stacked body 32 (writing to the second sub-block BLKSB), since the first stacked body 31 (first sub-block BLKSA) has already been written, it becomes difficult to perform channel precharge PA using the source-side selection gate line SGS. Therefore, in the writing to the second stacked body 32 (writing to the second sub-block BLKSB), before the writing operation to each memory cell transistor MT is performed, a voltage is applied to the drain-side selection gate line SGD to electrically connect the channel layer 52 and the bit line BL, and channel precharge PB is performed to set the voltage of the channel layer 52 to 0V. Therefore, in the writing to the second stacked body 32 (writing to the second sub-block BLKSB), after performing channel precharge PB using the drain-side selection gate line SGD, the writing operations are performed in the order of the memory cell transistor MT4, the memory cell transistor MT5, the memory cell transistor MT6, and the memory cell transistor MT7.

[0109] <8. Manufacturing Method> Next, a manufacturing method of the semiconductor memory device 1 will be described. FIGS. 14A and 14B are cross-sectional views for explaining a manufacturing method of the semiconductor memory device 1. Hereinafter, for convenience of explanation, illustration of the manufacturing process of the dummy word line WLD is omitted. Also, hereinafter, the manufacturing process mainly related to a plurality of word lines WL will be described. The processes other than those described below can be implemented by known techniques.

[0110] First, an insulating layer 141 is formed on the insulating layer 42. The insulating layer 141 is a sacrificial layer that will be replaced with the source-side selection gate line SGS in the replacement process described later. Next, a stacked body 151 is formed above the insulating layer 141. The stacked body 151 is formed by repeatedly stacking the insulating layer 132A, the insulating layer 131A, and the insulating layer 42 in the Z direction in the order of the insulating layer 132A, the insulating layer 131A, and the insulating layer 42. Next, an intermediate insulating layer 33 is stacked above the stacked body 151 (see ST1 in FIG. 14A).

[0111] Next, a hole HA that penetrates the intermediate insulating layer 33, the laminate 151, and the insulating layer 141 in the Z direction is formed (see ST2 in FIG. 14A). Next, the inside of the hole HA is filled with the insulating portion 142. Next, a laminate 152 is formed above the intermediate insulating layer 33. The laminate 152 is formed by repeatedly laminating the insulating layer 131B, the insulating layer 132B, and the insulating layer 42 in this order of the insulating layer 131B, the insulating layer 132B, and the insulating layer 42 in the Z direction. The insulating layer 131B is an example of the "first layer". The insulating layer 132B is an example of the "second layer". The insulating layer 42 is an example of the "third layer". Next, an insulating layer 143 is formed above the laminate 152. The insulating layer 143 is a sacrificial layer that is replaced with the drain-side select gate line SGD in a replacement process described later (see ST3 in FIG. 14A).

[0112] Next, a hole HB that penetrates the insulating layer 143 and the laminate 152 in the Z direction is formed. Next, the insulating portion 142 in the hole HA is removed by etching through the hole HB (see ST4 in FIG. 14B). Next, etching (for example, wet etching) is performed by supplying a first etchant into the holes HA and HB. At this time, the second material contained in the insulating layer 132A and the insulating layer 132B is more easily removed by the first etchant than the first material contained in the insulating layer 131A and the insulating layer 131B. For this reason, the insulating layer 132A is largely etched away compared to the insulating layer 131A and retreats in a direction away from the hole HA with respect to the insulating layer 131A. As a result, a step is formed between the insulating layer 132A and the insulating layer 42. Similarly, the insulating layer 132B is largely etched away compared to the insulating layer 131B and retreats in a direction away from the hole HB with respect to the insulating layer 131B. As a result, a step is formed between the insulating layer 132B and the insulating layer 42. (See ST5 in FIG. 14B).

[0113] Next, a memory pillar MH is formed inside the holes HA and HB. That is, the memory pillar MH is formed by sequentially supplying the materials of the memory film 51, the channel layer 52, and the insulating core 53 into the holes HA and HB.

[0114] Next, the replacement process is performed. That is, the insulating layer 131A, the insulating layer 131B, the insulating layer 132A, the insulating layer 132B, the insulating layer 141, and the insulating layer 143 are removed by etching through a groove (not shown). Then, a conductive material is supplied to the space where the insulating layer 131A and the insulating layer 132A are removed, thereby forming the word line WLA. Similarly, a conductive material is supplied to the space where the insulating layer 131B and the insulating layer 132B are removed, thereby forming the word line WLB. A conductive material is supplied to the space where the insulating layer 141 is removed, thereby forming the source-side select gate line SGS. A conductive material is supplied to the space where the insulating layer 143 is removed, thereby forming the drain-side select gate line SGD (see ST6 in FIG. 14B). Thus, the manufacturing process for the plurality of word lines WL is completed.

[0115] <9. Operation> Next, the operation of the semiconductor memory device 1 will be described. FIG. 15 is a cross-sectional view for explaining the operation of the semiconductor memory device 1. Here, the word line WLB will be taken as an example to explain its effect.

[0116] As shown in FIG. 15, the word line WLB has a base portion 101 and a recessed portion 102 located on the +Z direction side with respect to the base portion 101. Here, according to the research of the present inventor, in the memory cell transistor MTB (for example, the memory cell transistor MTB-2) to be written, which is connected to the word line WLB having the recessed portion 102, it has been confirmed that charges are concentrated and accumulated in the region on the +Z direction side rather than the center of the memory cell transistor MTB in the Z direction.

[0117] Therefore, by providing the recessed portion 102 in the word line WLB, the region where charges are concentrated and stored in the memory cell transistor MTB-2 can be unevenly distributed to the +Z direction side away from the written memory cell transistor MTB (for example, the memory cell transistor MTB-1) with respect to the center of the memory cell transistor MTB-2 in the Z direction. As a result, the influence (so-called adjacent interference influence) of the write operation on the memory cell transistor MTB-2 on the written memory cell transistor MTB-1 is reduced. For this reason, the electrical characteristics of the semiconductor memory device 1 are improved. The same applies to the word line WLA having the recessed portion 112.

[0118] (Second Embodiment) Next, the second embodiment will be described. The second embodiment is different from the first embodiment in that the memory pillar MH includes three columnar portions 71, 72, and 73. The configuration other than that described below is the same as that of the first embodiment.

[0119] FIG. 16 is a cross-sectional view showing the semiconductor memory device 1A of the second embodiment. In the present embodiment, the laminate 30 includes a first laminate 31, a second laminate 32, an intermediate insulating layer 33, a third laminate 34, and an intermediate insulating layer 35.

[0120] The second laminate 32 is disposed on the +Z direction side with respect to the first laminate 31. The intermediate insulating layer 33 is disposed between the first laminate 31 and the second laminate 32 in the Z direction. The third laminate 34 is disposed on the +Z direction side with respect to the second laminate 32. The intermediate insulating layer 35 is disposed between the second laminate 32 and the third laminate 34 in the Z direction. The thickness of the intermediate insulating layer 35 in the Z direction is larger than the thickness of the insulating layer 42 in the Z direction. The intermediate insulating layer 35 contains, for example, silicon and oxygen.

[0121] Each of the first to third laminates 31, 32, 33 includes a plurality of conductive layers 41 and a plurality of insulating layers 42. In each of the first to third laminates 31, 32, 33, the plurality of conductive layers 41 and the plurality of insulating layers 42 are alternately laminated one layer at a time in the Z direction.

[0122] In this embodiment, the word lines WL included in the first stack 31 and the word lines WL included in the lower half of the second stack 32 are the word line WLA. On the other hand, the word lines WL included in the third stack 34 and the word lines WL included in the upper half of the second stack 32 are the word line WLB. The third stack 34 has one or more dummy word lines WLD between the word line WLA and the word line WLB.

[0123] Each memory pillar MH is, for example, a three-stage columnar body in the Z direction, and includes a first columnar portion 71, a second columnar portion 72, and a third columnar portion 73. The first columnar portion 71 is provided in the first stack 31 and the intermediate insulating layer 33. The second columnar portion 72 is provided in the second stack 32 and the intermediate insulating layer 35. The third columnar portion 73 is provided in the third stack 34. The diameter of each of the first to third columnar portions 71, 72, 73 gradually decreases as it proceeds in the -Z direction. In other words, the width in the X direction of each of the first to third columnar portions 71, 72, 73 gradually decreases as it proceeds in the -Z direction.

[0124] In this embodiment, a plurality of memory cell transistors MTA are formed at the intersections of the plurality of word lines WLA and the memory pillar MH. The plurality of memory cell transistors MTA include memory cell transistors MTA-1, MTA-2, MTA-3 formed at the intersection of the first stack 31 and the first columnar portion 71, and memory cell transistors MTA-4, MTA-5 formed at the intersection of the second stack 32 and the second columnar portion 72. These are arranged in the -Z direction in the order of memory cell transistor MTA-5, memory cell transistor MTA-4, memory cell transistor MTA-3, memory cell transistor MTA-2, memory cell transistor MTA-1.

[0125] Similarly, a plurality of memory cell transistors MTB are formed at the intersections of the plurality of word lines WLB and the memory pillars MH. The plurality of memory cell transistors MTB include the memory cell transistors MTB-1 and MTB-2 formed at the intersection of the second stacked body 32 and the second columnar portion 72, and the memory cell transistors MTB-3, MTB-4, and MTA-B formed at the intersection of the third stacked body 34 and the third columnar portion 73. These are arranged in the -Z direction in the order of memory cell transistor MTB-5, memory cell transistor MTB-4, memory cell transistor MTB-3, memory cell transistor MTB-2, and memory cell transistor MTB-1.

[0126] In this embodiment, the writing of data to the first sub-block BLKSA is performed by applying a program voltage Vprg to the word lines WLA (word line WLA) corresponding to the first sub-block BLKSA, starting from the uppermost word line WLA and sequentially applying it to the word lines WLA located one by one below. For example, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTA-5, then performs a writing operation of injecting charge into the memory cell transistor MTA-4, then performs a writing operation of injecting charge into the memory cell transistor MTA-3, then performs a writing operation of injecting charge into the memory cell transistor MTA-2, and then performs a writing operation of injecting charge into the memory cell transistor MTA-1.

[0127] On the other hand, writing data to the second sub-block BLKSB is performed by applying a program voltage Vprg to the word lines WLB located one by one upward in order, starting from the lowermost word line WLB among the word lines WL (word line WLB) corresponding to the second sub-block BLKSB. For example, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTB-1, and then performs a writing operation of injecting charge into the memory cell transistor MTB-2, and then performs a writing operation of injecting charge into the memory cell transistor MTB-3, and then performs a writing operation of injecting charge into the memory cell transistor MTB-4, and then performs a writing operation of injecting charge into the memory cell transistor MTB-5.

[0128] According to such a configuration, similarly to the first embodiment, it is possible to provide the semiconductor memory device 1A capable of improving electrical characteristics.

[0129] (Third Embodiment) Next, the third embodiment will be described. The third embodiment is different from the first embodiment in that the word line WL included in the first laminate 31 is the word line WLA'. The configuration other than that described below is the same as the configuration of the first embodiment.

[0130] FIG. 17 is a cross-sectional view showing the semiconductor memory device 1B of the third embodiment. In the present embodiment, the word line WL (the word line corresponding to the first sub-block BLKSA) included in the first laminate 31 is the word line WLA'. The word line WLA' is a word line WL having no retreat portion 112. The operation of the control circuit 14 is the same as the operation of the first embodiment. Even with such a configuration, for example, it is possible to provide the semiconductor memory device 1B capable of improving electrical characteristics at least with respect to the word line WLB.

[0131] (Fourth Embodiment) Next, a fourth embodiment will be described. The fourth embodiment is different from the first embodiment in that the word line WL included in the first laminate 31 is the word line WLB. The configuration other than that described below is the same as that of the first embodiment.

[0132] FIG. 18 is a cross-sectional view showing the semiconductor memory device 1C of the fourth embodiment. In the present embodiment, the word line WL included in the first laminate 31 is the word line WLB. Writing data to the first sub-block BLKSA is performed by applying a program voltage Vprg to the word line WLB located most downward in the word lines WL (word lines WLB) corresponding to the first sub-block BLKSA, and then sequentially to the word lines WLB located upward one by one. For example, the control circuit 14 performs a writing operation of injecting charge into the memory cell transistor MTA-1, then a writing operation of injecting charge into the memory cell transistor MTA-2, and then a writing operation of injecting charge into the memory cell transistor MTA-3. According to such a configuration, a semiconductor memory device 1C capable of improving electrical characteristics can be provided.

[0133] (Fifth Embodiment) Next, a fifth embodiment will be described. The fifth embodiment is different from the first embodiment in that the word line WL included in the second laminate 32 is the word line WLA. The configuration other than that described below is the same as that of the first embodiment.

[0134] FIG. 19 is a cross-sectional view showing the semiconductor memory device 1D of the fifth embodiment. The word line WL included in the second laminate 32 is the word line WLA. In the present embodiment, the -Z direction side is an example of the "first side". The +Z direction side is an example of the "second side". The word line WLA-1 is an example of the "first gate electrode layer". The word line WLA-2 is an example of the "second gate electrode layer". The seventh edge E7, the eighth edge E8, the ninth edge E9, the tenth edge E10, the eleventh edge E11, and the twelfth edge E12 are examples of the "first edge", the "second edge", the "third edge", the "fourth edge", the "fifth edge", and the "sixth edge", respectively. The fourth distance L4, the fifth distance L5, and the sixth distance L6 are examples of the "first distance", the "second distance", and the "third distance", respectively.

[0135] Writing data to the second sub-block BLKSB is performed by applying a program voltage Vprg to the word lines WLA located one by one in the lower side in order, starting from the word line WLA located at the uppermost position among the word lines WL (word line WLA) corresponding to the second sub-block BLKSB. For example, the control circuit 14 performs a writing operation of injecting charges into the memory cell transistor MTB-3, then performs a writing operation of injecting charges into the memory cell transistor MTB-2, and then performs a writing operation of injecting charges into the memory cell transistor MTB-1. According to such a configuration, it is possible to provide a semiconductor memory device 1C capable of improving electrical characteristics.

[0136] Although some embodiments have been described above, the embodiments are not limited to the above examples. For example, some of the above-described embodiments may be combined with each other and implemented.

[0137] According to at least one embodiment described above, the semiconductor memory device includes a stacked body and a columnar body. At the boundary between the first gate electrode layer and the first insulating layer, the distance between the first edge of the first gate electrode layer adjacent to the columnar body and the second edge of the first gate electrode layer adjacent to the columnar body from the side opposite to the first edge is defined as the first distance. At the boundary between the first gate electrode layer and the second insulating layer, the distance between the third edge of the first gate electrode layer adjacent to the columnar body and the fourth edge of the first gate electrode layer adjacent to the columnar body from the side opposite to the third edge is defined as the second distance. At the boundary between the second gate electrode layer and the second insulating layer, when the distance between the fifth edge of the second gate electrode layer adjacent to the columnar body and the sixth edge of the second gate electrode layer adjacent to the columnar body from the side opposite to the fifth edge is defined as the third distance, the second distance is greater than the first distance and greater than the third distance. With such a configuration, improvement in electrical characteristics can be achieved.

[0138] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

Description of Reference Numerals

[0139] 1, 1A, 1B, 1C, 1D... Semiconductor memory device, 30... Stacked body, 41... Conductive layer (gate electrode layer), 42... Insulating layer, 51... Memory film, 52... Channel layer, 101... Base (first part), 102... Retracted part (second part), WLB-1... Word line (first gate electrode layer), WLB-2... Word line (second gate electrode layer), WLA-1... Word line (third gate electrode layer), WLA-2... Word line (fourth gate electrode layer), 42B-1... Insulating layer (first insulating layer), 42B-2... Insulating layer (second insulating layer), 42A-1... Insulating layer (third insulating layer), 42A-2... Insulating layer (fourth insulating layer), MH... Memory pillar (columnar body).

Claims

1. A laminate including a plurality of gate electrode layers and a plurality of insulating layers, wherein the plurality of gate electrode layers and the plurality of insulating layers are alternately laminated one by one in a first direction; A columnar body extending in the first direction within the laminate and including a memory film and a channel layer; Comprising: The plurality of gate electrode layers include a first gate electrode layer and a second gate electrode layer disposed on a first side in the first direction with respect to the first gate electrode layer and located adjacent to the first gate electrode layer among the plurality of gate electrode layers; The plurality of insulating layers include a first insulating layer adjacent to the first gate electrode layer from a second side opposite to the first side in the first direction, and a second insulating layer located between the first gate electrode layer and the second gate electrode layer; Taking a direction orthogonal to the first direction as a second direction, when viewed in a cross-section along the first direction and the second direction, At a first boundary located between the first gate electrode layer and the first insulating layer and along the second direction, a distance between a first edge of the first gate electrode layer adjacent to the columnar body and a second edge of the first gate electrode layer adjacent to the columnar body from a side opposite to the first edge is defined as a first distance; At a second boundary located between the first gate electrode layer and the second insulating layer and along the second direction, a distance between a third edge of the first gate electrode layer adjacent to the columnar body and a fourth edge of the first gate electrode layer adjacent to the columnar body from a side opposite to the third edge is defined as a second distance; When, at a third boundary located between the second gate electrode layer and the second insulating layer and along the second direction, a distance between a fifth edge of the second gate electrode layer adjacent to the columnar body and a sixth edge of the second gate electrode layer adjacent to the columnar body from a side opposite to the fifth edge is defined as a third distance, The second distance is greater than the first distance and greater than the third distance; A semiconductor memory device.

2. When viewed from the first direction, At the second boundary, an annular first boundary line is defined between the first gate electrode layer and the columnar body by an edge of the first gate electrode layer; At the third boundary, an annular second boundary line is defined between the second gate electrode layer and the columnar body by an edge of the second gate electrode layer; When viewed from the first direction, the second boundary line is located inside the first boundary line; The semiconductor memory device according to Claim 1.

3. The first gate electrode layer includes a first portion and a second portion located on the first side with respect to the first portion. The first portion has a first edge adjacent to the columnar body. The second portion has a second edge adjacent to the columnar body. The second edge is inclined more greatly with respect to the first direction than the first edge. The second gate electrode layer includes a third portion and a fourth portion located on the first side with respect to the third portion. The third portion has a third edge adjacent to the columnar body. The fourth portion has a fourth edge adjacent to the columnar body. The fourth edge is inclined more greatly with respect to the first direction than the third edge. The semiconductor memory device according to claim 1.

4. The shortest distance between the channel layer and the third edge of the first gate electrode layer is greater than the shortest distance between the channel layer and the first edge of the first gate electrode layer. The semiconductor memory device according to any one of claims 1 to 3.

5. The width in the second direction of the end on the first side of the columnar body is greater than the width in the second direction of the end on the second side of the columnar body. The third edge and the fourth edge are located on the first side with respect to the first edge and the second edge. The semiconductor memory device according to any one of claims 1 to 3.

6. The width in the second direction of the end on the second side of the columnar body is greater than the width in the second direction of the end on the first side of the columnar body. The third edge and the fourth edge are located on the first side with respect to the first edge and the second edge. The semiconductor memory device according to any one of claims 1 to 3.

7. It further includes a control circuit. A first memory cell transistor is formed at the intersection of the first gate electrode layer and the columnar body, and a second memory cell transistor is formed at the intersection of the second gate electrode layer and the columnar body. The control circuit can control the first memory cell transistor and the second memory cell transistor to perform a second writing operation after a first writing operation. The first writing operation includes an operation of injecting charge into the first memory cell transistor when writing data. The first writing operation includes an operation of injecting charge into the second memory cell transistor when writing data. The semiconductor memory device according to any one of claims 1 to 3.

8. The plurality of gate electrode layers includes a third gate electrode layer disposed on the second side with respect to the first gate electrode layer, and a fourth gate electrode layer disposed between the first gate electrode layer and the third gate electrode layer and adjacent to the third gate electrode layer among the plurality of gate electrode layers. The plurality of insulating layers includes a third insulating layer positioned between the third gate electrode layer and the fourth gate electrode layer, and a fourth insulating layer adjacent to the fourth gate electrode layer from the first side. When viewed in the cross section, At a fourth boundary along the second direction located between the third gate electrode layer and the third insulating layer, a distance between a seventh edge of the third gate electrode layer adjacent to the columnar body and an eighth edge of the third gate electrode layer adjacent to the columnar body from a side opposite to the seventh edge is defined as a fourth distance. At a fifth boundary along the second direction located between the fourth gate electrode layer and the third insulating layer, a distance between a ninth edge of the fourth gate electrode layer adjacent to the columnar body and a tenth edge of the fourth gate electrode layer adjacent to the columnar body from a side opposite to the ninth edge is defined as a fifth distance. At a sixth boundary along the second direction located between the fourth gate electrode layer and the fourth insulating layer, when a distance between an eleventh edge of the fourth gate electrode layer adjacent to the columnar body and a twelfth edge of the fourth gate electrode layer adjacent to the columnar body from a side opposite to the eleventh edge is defined as a sixth distance, the fifth distance is greater than the fourth distance and greater than the sixth distance. The semiconductor memory device according to any one of claims 1 to 3.

9. Further comprising a control circuit, A first memory cell transistor is formed at an intersection of the first gate electrode layer and the columnar body, a second memory cell transistor is formed at an intersection of the second gate electrode layer and the columnar body, a third memory cell transistor is formed at an intersection of the third gate electrode layer and the columnar body, and a fourth memory cell transistor is formed at an intersection of the fourth gate electrode layer and the columnar body. The control circuit can control the first memory cell transistor, the second memory cell transistor, the third memory cell transistor, and the fourth memory cell transistor to perform a second writing operation after a first writing operation and to perform a third writing operation after a fourth writing operation. The first writing operation includes an operation of injecting charge into the first memory cell transistor when writing data. The second writing operation includes an operation of injecting charge into the second memory cell transistor when writing data. The third writing operation includes an operation of injecting charge into the third memory cell transistor when writing data. The fourth writing operation includes an operation of injecting charge into the fourth memory cell transistor when writing data. The semiconductor memory device according to claim 8.

10. A control method for a semiconductor memory device, wherein the semiconductor memory device includes a plurality of gate electrode layers and a plurality of insulating layers, and a stack in which the plurality of gate electrode layers and the plurality of insulating layers are alternately stacked one layer at a time in a first direction, and a columnar body that extends in the first direction within the stack and includes a memory film and a channel layer. The semiconductor memory device is provided with The plurality of gate electrode layers include a first gate electrode layer, a second gate electrode layer disposed on a first side of the first gate electrode layer in the first direction and adjacent to the first gate electrode layer among the plurality of gate electrode layers, a third gate electrode layer disposed on a second side opposite to the first side of the first gate electrode layer in the first direction, and a fourth gate electrode layer disposed between the first gate electrode layer and the third gate electrode layer and adjacent to the third gate electrode layer among the plurality of gate electrode layers. The plurality of insulating layers include a first insulating layer adjacent to the first gate electrode layer from the second side, a second insulating layer positioned between the first gate electrode layer and the second gate electrode layer, a third insulating layer positioned between the third gate electrode layer and the fourth gate electrode layer, and a fourth insulating layer adjacent to the fourth gate electrode layer from the first side. Taking a direction orthogonal to the first direction as a second direction, when viewed in a cross-section along the first direction and the second direction, at a first boundary along the second direction positioned between the first gate electrode layer and the first insulating layer, a distance between a first edge of the first gate electrode layer adjacent to the columnar body and a second edge of the first gate electrode layer adjacent to the columnar body from a side opposite to the first edge is defined as a first distance. At a second boundary located between the first gate electrode layer and the second insulating layer and along the second direction, a distance between a third edge of the first gate electrode layer adjacent to the columnar body and a fourth edge of the first gate electrode layer adjacent to the columnar body from the side opposite to the third edge is defined as a second distance. At a third boundary located between the second gate electrode layer and the second insulating layer and along the second direction, when a distance between a fifth edge of the second gate electrode layer adjacent to the columnar body and a sixth edge of the second gate electrode layer adjacent to the columnar body from the side opposite to the fifth edge is defined as a third distance. The second distance is greater than the first distance and greater than the third distance. At a fourth boundary located between the third gate electrode layer and the third insulating layer and along the second direction, a distance between a seventh edge of the third gate electrode layer adjacent to the columnar body and an eighth edge of the third gate electrode layer adjacent to the columnar body from the side opposite to the seventh edge is defined as a fourth distance. At a fifth boundary located between the fourth gate electrode layer and the third insulating layer and along the second direction, a distance between a ninth edge of the fourth gate electrode layer adjacent to the columnar body and a tenth edge of the fourth gate electrode layer adjacent to the columnar body from the side opposite to the ninth edge is defined as a fifth distance. At a sixth boundary located between the fourth gate electrode layer and the fourth insulating layer and along the second direction, when a distance between an eleventh edge of the fourth gate electrode layer adjacent to the columnar body and a twelfth edge of the fourth gate electrode layer adjacent to the columnar body from the side opposite to the eleventh edge is defined as a sixth distance. The fifth distance is greater than the fourth distance and greater than the sixth distance. A first memory cell transistor is formed at an intersection of the first gate electrode layer and the columnar body, a second memory cell transistor is formed at an intersection of the second gate electrode layer and the columnar body, a third memory cell transistor is formed at an intersection of the third gate electrode layer and the columnar body, and a fourth memory cell transistor is formed at an intersection of the fourth gate electrode layer and the columnar body. When writing data, the control method After a first writing operation of injecting charge into the first memory cell transistor, a second writing operation of injecting charge into the second memory cell transistor is performed. After the third writing operation of injecting charge into the third memory cell transistor, a fourth writing operation of injecting charge into the fourth memory cell transistor is performed. Including A control method for a semiconductor memory device.

11. A first layer, a second layer that is more easily removed by a first etchant than the first layer, and an insulating third layer are repeatedly laminated in this order of the first layer, the second layer, and the third layer in a first direction to form a laminate. A hole extending in the first direction is formed in the laminate. The first etchant is supplied into the hole to perform etching to remove a part of the second layer, thereby forming a step between the second layer and the third layer. A columnar body including a memory film and a channel layer is formed inside the hole. The first layer and the second layer are removed by etching, and a gate electrode layer is formed in the space where the first layer and the second layer are removed. Including A method of manufacturing a semiconductor memory device.

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