Solid state drive, information processing apparatus, and control method

Abstract

To reduce power consumption and to suppress performance degradation caused by temperature rise.SOLUTION: A solid state drive is configured to be connected to an information processing apparatus, the solid state drive comprising: an electrically rewritable nonvolatile memory; and a memory controller that receives a processing command for the nonvolatile memory and performs processing corresponding to the processing command, the memory controller being configured to switch between a first processing mode with higher processing power for the nonvolatile memory and a second processing mode with lower processing power than the first processing mode, depending on a value of queue depth (QD) indicating the number of the processing commands to be issued by the information processing apparatus at a time.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a solid state drive, an information processing apparatus, and a control method.

Background Art

[0002] In recent years, information processing apparatuses such as personal computers (PCs) equipped with solid state drives (SSDs) have become widespread. In such information processing apparatuses, those using a PCIe (Peripheral Component Interconnect-Express) bus for connecting an SSD are known in order to speed up data transfer (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the conventional information processing apparatuses and SSDs as described above, as the data transfer of the SSD is accelerated, the power consumption tends to increase without depending on the processing load. Therefore, in the conventional information processing apparatuses and SSDs, the operation of the information processing apparatus may be restricted due to a temperature rise.

[0005] The present invention has been made to solve the above problems, and an object thereof is to provide a solid state drive, an information processing apparatus, and a control method capable of reducing power consumption and suppressing a decrease in performance due to a temperature rise.

Means for Solving the Problems

[0006] To solve the above problems, one aspect of the present invention is a solid state drive connectable to an information processing device, comprising: a non-volatile memory that can be electrically rewritten; and a memory controller that receives a processing command for the non-volatile memory and executes a process corresponding to the processing command, wherein the memory controller switches between a first processing mode with high processing ability for the non-volatile memory and a second processing mode with lower processing ability than the first processing mode according to a QD (Queue Depth) value indicating the number of the processing commands issued by the information processing device at a time.

[0007] Also, one aspect of the present invention is the above solid state drive, which can be connected to the information processing device via a PCIe (Peripheral Component Interconnect-Express) bus, and the memory controller checks the buffer storage unit in response to receiving a notification indicating that the processing command has been stored in the buffer storage unit provided in the information processing device, and switches to the first processing mode when the QD value is equal to or greater than a predetermined threshold, and may switch to the second processing mode when the QD value is less than the predetermined threshold.

[0008] Also, one aspect of the present invention is the above solid state drive, wherein the memory controller changes to a mode with a lower transfer speed of the PCIe bus than the first processing mode in the second processing mode, and may change to a mode with a higher transfer speed of the PCIe bus than the second processing mode in the first processing mode.

[0009] Also, one aspect of the present invention is the above solid state drive, wherein the memory controller can process the processing commands in parallel by a plurality of threads, and may switch to the first processing mode when at least one of the QD values corresponding to each of the plurality of threads stored in the buffer storage unit is equal to or greater than the predetermined threshold.

[0010] Also, one aspect of the present invention is an information processing apparatus incorporating the above solid-state drive.

[0011] Also, one aspect of the present invention is a solid-state drive including an electrically rewritable non-volatile memory and a memory controller that receives a processing command for the non-volatile memory and executes processing corresponding to the processing command, and a main control unit that issues the processing command, wherein the main control unit switches between a first processing mode with high processing ability for the non-volatile memory and a second processing mode with lower processing ability than the first processing mode according to the value of QD (Queue Depth) indicating the number of the processing commands issued to the solid-state drive at one time. The information processing apparatus includes a main control unit.

[0012] Also, one aspect of the present invention is a control method for a solid-state drive including an electrically rewritable non-volatile memory and a memory controller that receives a processing command for the non-volatile memory and executes processing corresponding to the processing command, and being connectable to an information processing apparatus, the control method including a processing step in which the memory controller switches between a first processing mode with high processing ability for the non-volatile memory and a second processing mode with lower processing ability than the first processing mode according to the value of QD (Queue Depth) indicating the number of the processing commands issued by the information processing apparatus at one time.

Advantages of the Invention

[0013] According to the above aspect of the present invention, power consumption can be reduced and a decrease in performance due to a temperature rise can be suppressed.

Brief Description of the Drawings

[0014]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

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Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0015] Hereinafter, a solid state drive, an information processing apparatus, and a control method according to an embodiment of the present invention will be described with reference to the drawings.

[0016] FIG. 1 is a diagram showing an example of the main hardware configuration of the information processing apparatus 1 and the SSD 40 according to the first embodiment. As shown in FIG. 1, the information processing apparatus 1 is, for example, a notebook personal computer, and includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, an embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40. Here, the information processing apparatus 1 is, for example, a notebook personal computer (notebook PC).

[0017] The CPU (Central Processing Unit) 11 executes various arithmetic processes under program control and controls the entire information processing apparatus 1.

[0018] The main memory 12 is a writable memory that is used as a loading area for the execution program of the CPU 11 or as a working area for writing the processing data of the execution program. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. This execution program includes an OS (Operating System), various drivers for operating peripheral devices in hardware, various services / utilities, application programs, and the like.

[0019] The video subsystem 13 is a subsystem for realizing functions related to image display and includes a video controller. This video controller processes the drawing commands from the CPU 11, writes the processed drawing information to the video memory, reads the drawing information from the video memory, and outputs it as drawing data (display data) to the display unit 14.

[0020] The display unit 14 is, for example, a liquid crystal display, and displays a display screen based on the drawing data (display data) output from the video subsystem 13.

[0021] The chipset 21 is provided with controllers such as a USB (Universal Serial Bus), Serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus (PCIe), and LPC (Low Pin Count) bus, to which a plurality of devices are connected. In FIG. 1, as an example of devices, a BIOS memory 22 and an SSD 40 are connected to the chipset 21. Note that in this embodiment, the CPU 11 and the chipset 21 correspond to the main control unit 10.

[0022] The BIOS (Basic Input Output System) memory 22 is composed of an electrically rewritable non-volatile memory such as, for example, an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash ROM (flash memory). The BIOS memory 22 stores the BIOS and system firmware for controlling the embedded controller 31 and the like.

[0023] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the system state of the information processing apparatus 1. The embedded controller 31 also has a power management function for controlling the power supply circuit 33. Note that the embedded controller 31 is composed of a CPU, ROM, RAM, etc. (not shown), and is provided with a plurality of channels of A / D input terminals, D / A output terminals, timers, and digital input / output terminals. To the embedded controller 31, for example, the input unit 32 and the power supply circuit 33 are connected via those input / output terminals, and the embedded controller 31 controls the operations thereof.

[0024] The input unit 32 is, for example, an input device such as a keyboard or a pointing device such as a touch pad.

[0025] The power supply circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, an AC / DC adapter, etc., and converts a DC voltage supplied from an external power supply via an AC / DC adapter or from a battery into a plurality of voltages necessary for operating the information processing apparatus 1. The power supply circuit 33 also supplies power to each part of the information processing apparatus 1 based on control from the embedded controller 31.

[0026] An SSD (Solid State Drive) 40 is a memory drive device having rewritable non-volatile memory, and stores an OS, various drivers, various services / utilities, application programs, and various data. The information processing apparatus 1 executes various information processes using the data stored in the SSD 40. The SSD 40 is connected to the chipset 21, for example, via Serial ATA or a PCI-Express bus.

[0027] In this embodiment, it is assumed that the SSD 40 is connected via a PCI-Express bus (PCIe bus). The SSD 40 also includes a plurality of flash memories 41 and a memory controller 42.

[0028] The flash memory 41 is, for example, a NAND flash memory. The flash memory 41 includes, for example, a memory cell of a floating gate type, a charge trap type memory cell that stores data by trapping electrons in a charge trap layer without a floating gate, and the like. Further, the memory cells of the flash memory 41 are multi-bit cells that store multi-bit data in one memory cell, and are, for example, MLC (Multiple Level Cell), TLC (Triple Level Cell), and QLC (Quad Level Cell). Here, the multi-bit cell is a memory cell capable of storing the equivalent of multiple bits in one memory cell by providing a plurality of data write thresholds.

[0029] A temperature sensor 43 is a sensor for detecting the internal temperature of the SSD 40. The temperature sensor 43 outputs a detection value for temperature conditions to the memory controller 42.

[0030] The memory controller 42 is a processor including, for example, a CPU, a ROM, a RAM, etc. (not shown), and comprehensively controls the SSD 40. The SSD controller 42 executes processes such as control processing of a host interface (host I / F) with the chipset 21, control processing of a memory interface (memory I / F) with the flash memory 41, and data management processing of the flash memory 41.

[0031] Also, the memory controller 42 detects the temperature of the SSD 40 based on the detected value detected by the temperature sensor 43, and controls so that the detected temperature does not exceed a predetermined threshold temperature. For example, when the detected temperature reaches the predetermined threshold temperature, the memory controller 42 limits the operation of the SSD 40 to lower the temperature of the SSD 40.

[0032] In addition, the memory controller 42 has a high-performance mode (first processing mode) with high processing power and an ECO (Ecology) mode (second processing mode) with lower processing power than the high-performance mode, and switches between the performance mode and the ECO mode according to the value of QD (Queue Depth). The details of the process of switching the processing mode according to the value of QD will be described later.

[0033] Next, with reference to FIG. 2, the functional configuration of the information processing apparatus 1 according to the present embodiment will be described. FIG. 2 is a functional block diagram showing an example of the functional configuration of the information processing apparatus 1 according to the present embodiment.

[0034] As shown in FIG. 2, the information processing apparatus 1 includes a main control unit 10, an SSD 40, and a storage unit 50. Note that the main control unit 10 and the SSD 40 are connected by a PCIe bus.

[0035] The storage unit 50 is, for example, a storage unit realized by the main memory 12, and stores various information used by the information processing apparatus 1. The storage unit 50 includes a command buffer storage unit 51.

[0036] The command buffer storage unit 51 (an example of a buffer storage unit) is a storage unit realized by, for example, the main memory 12, and stores processing commands to the SSD 40. The command buffer storage unit 51 can store a plurality of processing commands, with QD being the number of processing commands that the information processing apparatus 1 issues to the SSD 40 at one time. The command buffer storage unit 51 stores the processing commands in association with data. Further, the command buffer storage unit 51 stores QD for each of a plurality of threads. Each of the plurality of threads is processed in parallel by the SSD 40.

[0037] Note that the processing commands for the SSD 40 are commands for executing various processes such as data reading and data writing to the SSD 40. The processing commands are once stored in the command buffer storage unit 51 and are executed by being read out to the SSD 40.

[0038] The main control unit 10 is a functional unit realized by the CPU 11 and the chipset 21 executing a program stored in the main memory 12, and executes various processes based on the OS. The main control unit 10 executes various processes based on, for example, data stored in the SSD 40. The main control unit 10 includes an AP processing unit 101 and an SSD device driver unit 102.

[0039] The AP processing unit 101 is a functional unit that processes application programs executed on the OS. The AP processing unit 101 accesses, for example, the SSD 40 to read and write data. The AP processing unit 101 accesses the SSD 40 via the SSD device driver unit 102 described later.

[0040] The SSD device driver unit 102 is a functional unit that realizes a device driver for accessing the SSD 40. In response to an access to the SSD 40, the SSD device driver unit 102 stores a processing command in the command buffer storage unit 51 and then notifies the SSD 40 that the processing command has been stored in the command buffer storage unit 51. When the processing command is a read command, for example, the SSD device driver unit 102 acquires the read data from the SSD 40 and outputs it to the OS or an application program.

[0041] The SSD 40 includes a memory controller 42, a temperature sensor 43, and an SSD storage unit 410. The SSD storage unit 410 is a storage unit realized by, for example, the flash memory 41 of the SSD 40, and includes a management information storage unit 411, a mode information storage unit 412, and a data storage unit 413.

[0042] The management information storage unit 411 is a storage unit realized by, for example, the flash memory 41, and stores the management information of the SSD 40. The management information storage unit 411 stores, for example, conversion table information between the physical address and the logical address (e.g., LBA: Logical Block Addressing (logical location information)) of the flash memory 41, management information of the free area and the used area of the flash memory 41, and the like.

[0043] The mode information storage unit 412 is a storage unit realized by, for example, the flash memory 41, and stores, for example, processing modes such as a performance mode and an ECO mode, and information indicating a power state. Note that the SSD 40 according to the present embodiment has a power state as shown in FIG. 3.

[0044] FIG. 3 is a diagram showing an example of the power state and power consumption of the SSD 40 according to the present embodiment. As shown in FIG. 3, the power states of the SSD 40 include PS01-Perf, PS0-Eco, PS1, PS2, PS3, and PS4.

[0045] PS01-Perf and PS0-Eco are power states in which normal processing of the SSD 40 is possible, PS01-Perf corresponds to the performance mode, and PS0-Eco corresponds to the ECO mode.

[0046] Also, PS1 and PS2 are in a state where some functions of the SSD 40 are restricted, and are used for Thermal Throttling to restrict functions so as not to exceed a predetermined threshold temperature.

[0047] Also, PS3 and PS4 are in a standby state, which is a state changed by a processing command from the information processing apparatus 1 or a timeout of the SSD 40.

[0048] Again, referring back to FIG. 2, the data storage unit 413 is a storage unit realized by, for example, the flash memory 41, and stores various data. The data storage unit 413 stores, for example, various data of the information processing apparatus 1, programs of the OS and applications, and the like.

[0049] The memory controller 42 includes a command processing unit 421, a mode switching unit 422, and a temperature control unit 423.

[0050] The command processing unit 421 acquires a processing command from the command buffer storage unit 51 in response to a notification from the SSD device driver unit 102 of the main control unit 10, and executes the processing of the SSD 40 corresponding to the processing command. The command processing unit 421 executes processing such as writing data to the SSD storage unit 410 and reading data from the SSD storage unit 410, according to the processing command.

[0051] The mode switching unit 422 switches between a performance mode (first processing mode) with high processing ability for the flash memory 41 and an ECO mode (second processing mode) with lower processing ability than the performance mode, according to the value of QD. Here, QD indicates the number of processing commands of the SSD 40 issued by the information processing apparatus 1 (main control unit 10) at one time.

[0052] For example, when the value of QD is equal to or greater than a predetermined threshold (e.g., two or more), the mode switching unit 422 switches to the performance mode. When switching to the performance mode, the mode switching unit 422 causes the mode information storage unit 412 to store mode information indicating the performance mode, and sets the PCIe bus to the PCIe Gen4 with the highest transfer speed.

[0053] For example, when the value of QD is less than a predetermined threshold (e.g., less than two), the mode switching unit 422 switches to the ECO mode. When switching to the ECO mode, the mode switching unit 422 causes the mode information storage unit 412 to store mode information indicating the ECO mode, and sets the PCIe bus to the PCIe Gen3 with a transfer speed lower than that in the performance mode. Here, with reference to FIG. 4, the transfer speed of the PCIe bus will be described.

[0054] FIG. 4 is a diagram showing the relationship between the mode of the PCIe bus and the transfer speed. As shown in FIG. 4, there are four Gens (generations) for the PCIe bus, and the transfer speed increases as the number of Gens (generations) increases. For example, in PCIe Gen4, the maximum transfer speed is 16 Gbps (gigabits per second), and the sequential read speed in the SSD 40 is 4000 MB / s (megabytes per second).

[0055] For example, in PCIe Gen3, the maximum transfer speed is 8 Gbps, and the sequential read speed in the SSD 40 is 3300 MB / s. For example, in PCIe Gen2, the maximum transfer speed is 4 Gbps, and the sequential read speed in the SSD 40 is 1600 MB / s. For example, in PCIe Gen1, the maximum transfer speed is 2 Gbps, and the sequential read speed in the SSD 40 is 800 MB / s.

[0056] In this embodiment, as an example, the mode switching unit 422 uses PCIe Gen4 (16 Gbps) for the performance mode and PCIe Gen3 (8 Gbps) for the ECO mode.

[0057] Also, when there are a plurality of threads in the buffer storage unit 51, the mode switching unit 422 switches to the performance mode when at least one of the QD values corresponding to each of the plurality of threads is equal to or greater than a predetermined threshold value (for example, two or more). Further, when there are a plurality of threads in the buffer storage unit 51, the mode switching unit 422 switches to the ECO mode when the QD value is less than the predetermined threshold value (for example, less than two) in all threads.

[0058] The temperature control unit 423 uses the temperature sensor 43 to detect the internal temperature of the SSD 40 and controls the SSD 40 so that the detected temperature does not exceed a predetermined threshold temperature. For example, when the detected temperature reaches the predetermined threshold temperature, the temperature control unit 423 restricts the operation of the SSD 40 to lower the temperature of the SSD 40. Specifically, when the detected temperature reaches the predetermined threshold temperature, the temperature control unit 423 changes the power state from PS01-Perf or PS0-Eco to PS1 or PS2. Note that PS1 or PS2 is a state in which some functions of the SSD 40 are restricted, for example, a state in which the clock signal is stopped or the frequency is decreased.

[0059] Next, with reference to the drawings, the operations of the information processing apparatus 1 and the SSD 40 according to this embodiment will be described. FIG. 5 is a diagram showing an example of command processing to the SSD 40 in the information processing apparatus 1 according to this embodiment.

[0060] As shown in FIG. 5, when accessing the SSD 40, the SSD device driver unit 102 first transmits a command and data to the command buffer storage unit 51 (step S11). The SSD device driver unit 102 expands the processing to the SSD 40 into commands (processing commands), and stores each command and data (for example, write data, etc.) in the command buffer storage unit 51.

[0061] Note that multiple commands (processing commands) can be executed at once as QD. In the example shown in FIG. 5, four processing commands (QD value is "4") are stored in thread A, and two processing commands (QD value is "2") are stored in thread B.

[0062] Next, the SSD device driver unit 102 notifies the memory controller 42 of the SSD 40 to store the command (step S12). The SSD device driver unit 102 notifies (command notification) the memory controller 42 that it has stored (remembered) the processing command in the command buffer storage unit 51.

[0063] Next, the memory controller 42 acquires the command and data from the command buffer storage unit 51 (step S13). The command processing unit 421 of the memory controller 42 acquires the processing command and data from the command buffer storage unit 51 in response to the notification.

[0064] Next, the memory controller 42 executes command processing (step S14). The command processing unit 421 executes command processing according to the processing command acquired from the command buffer storage unit 51.

[0065] Next, with reference to FIG. 6, the mode switching process of the SSD 40 will be described. FIG. 6 is a flowchart showing an example of the mode switching process of the SSD 40 according to the present embodiment.

[0066] As shown in FIG. 6, the memory controller 42 of the SSD 40 first determines whether a command notification has been received (step S101). The mode switching unit 422 of the memory controller 42 determines whether a command notification as shown in step S12 of FIG. 5 described above has been received. When the mode switching unit 422 receives a command notification (step S101: YES), the process proceeds to step S102. Also, when the mode switching unit 422 has not received a command notification (step S101: NO), the process returns to step S101.

[0067] In step S102, the mode switching unit 422 checks the QD of the command buffer storage unit 51.

[0068] Next, the mode switching unit 422 determines whether the QD is N or more (step S103). Here, N is a predetermined threshold value, for example, "2". When the QD is N or more (for example, the value of QD is two or more) (step S103: YES), the mode switching unit 422 advances the process to step S104. Also, when the QD is less than N (the value of QD is less than two) (step S103: NO), the mode switching unit 422 advances the process to step S107.

[0069] In step S104, the mode switching unit 422 sets the SSD 40 to the performance mode. The mode switching unit 422 stores mode information indicating the performance mode in the mode information storage unit 412 and sets the PCIe bus setting to the highest transfer speed PCIe Gen4.

[0070] Next, the command processing unit 421 of the memory controller 42 executes command processing (step S105). That is, the command processing unit 421 executes command processing in the performance mode (PCIe Gen4).

[0071] Next, the memory controller 42 maintains the performance mode for a predetermined period (a fixed period) (step S106). After the process of step S106, the memory controller 42 returns the process to step S101.

[0072] Also, in step S107, the mode switching unit 422 sets the SSD 40 to the ECO mode. The mode switching unit 422 causes the mode information storage unit 412 to store mode information indicating the ECO mode, and sets the PCIe bus setting to PCIe Gen3 with a lower transfer speed than the performance mode.

[0073] Next, the command processing unit 421 of the memory controller 42 executes command processing (step S108). That is, the command processing unit 421 executes command processing in the ECO mode (PCIe Gen3). After the process of step S108, the memory controller 42 returns the process to step S101.

[0074] Next, the temperature control process of the SSD 40 according to the present embodiment will be described. FIG. 7 is a flowchart showing an example of the temperature control process of the SSD 40 according to the present embodiment.

[0075] As shown in FIG. 7, the memory controller 42 of the SSD 40 first determines whether the temperature of the SSD 40 is equal to or higher than the threshold temperature (step S201). The temperature control unit 423 of the memory controller 42 uses the temperature sensor 43 to detect the internal temperature of the SSD 40 and determines whether the detected temperature is equal to or higher than the threshold temperature. When the detected temperature is equal to or higher than the threshold temperature (step S201: YES), the temperature control unit 423 advances the process to step S202. Also, when the detected temperature is less than the threshold temperature (step S201: NO), the temperature control unit 423 advances the process to step S203.

[0076] In step S202, the temperature control unit 423 changes the power state to PS1 or PS2. The temperature control unit 423 causes the mode information storage unit 412 to store mode information indicating PS1 or PS2, and restricts part of the operations. After the process of step S202, the temperature control unit 423 returns the process to step S201.

[0077] Also, in step S203, the temperature control unit 423 changes the power state to PS0 (PS01-Perf or PS0-Eco). The temperature control unit 423 causes the mode information storage unit 412 to store mode information indicating PS0 (performance mode or ECO mode), and releases the operation restrictions. After the process of step S203, the temperature control unit 423 returns the process to step S201.

[0078] Next, with reference to FIG. 8, the effects of the information processing apparatus 1 and the SSD 40 according to the present embodiment will be described. In FIG. 8, the horizontal axis of the graph is time, and the vertical axis indicates the temperature and performance of the SSD 40.

[0079] The waveform W1 shown in FIG. 8 indicates the temperature change in a conventional SSD. Also, the waveform W2 indicates the performance in a conventional SSD. Also, the waveform W3 indicates the temperature change in the SSD 40 according to the present embodiment. Also, the waveform W4 indicates the performance in the SSD 40 according to the present embodiment.

[0080] As shown in the waveform W1, in a conventional SSD, it is fixed to the PCIe Gen4 setting, and the base temperature is the temperature Tm1. In this state, when continuously operated, at time T1, the threshold temperature Tmth is reached, and for example, it is changed to PS2 or PS3. As a result, the temperature of the conventional SSD decreases. Also, as shown in the waveform W2, in a conventional SSD, after time T1, the performance also decreases.

[0081] On the other hand, in the SSD 40 according to the present embodiment, as shown in the waveform W3, since the performance mode and the ECO mode are switched, the base temperature is the temperature Tm2. That is, the temperature Tm2 is a value lower than the temperature Tm1 by the temperature difference ΔTmp. In this case, when the SSD 40 is continuously operated, at a time T2 later than the time T1, the threshold temperature Tmth is reached and, for example, it is changed to PS2 or PS3.

[0082] Note that in the SSD 40 according to the present embodiment, as shown in the waveform W4, since the performance does not decrease even when the performance mode and the ECO mode are switched, the performance decreases after the time T2. As described above, in the SSD 40 according to the present embodiment, the period until the threshold temperature Tmth is reached can be extended, and the period of high performance can be extended.

[0083] As described above, the SSD 40 (solid state drive) according to the present embodiment is an SSD connectable to the information processing apparatus 1, and includes a flash memory 41 (non-volatile memory) and a memory controller 42. The flash memory 41 is an electrically rewritable non-volatile memory. The memory controller 42 receives a processing command for the flash memory 41 and executes a process corresponding to the processing command. Further, the memory controller 42 switches between a performance mode (first processing mode) having a high processing ability for the flash memory 41 and an ECO mode (second processing mode) having a lower processing ability than the performance mode according to the value of QD. Here, QD indicates the number of processing commands issued by the information processing apparatus 1 at a time.

[0084] Thereby, the SSD 40 according to the present embodiment can reduce power consumption by reducing the processing ability in the ECO mode, and thus can suppress the temperature rise of the SSD 40. That is, the SSD 40 according to the present embodiment can reduce power consumption and suppress a decrease in performance due to temperature rise.

[0085] In addition, in this embodiment, the SSD 40 can be connected to the information processing apparatus 1 via a PCIe bus. In response to receiving a notification indicating that the information processing apparatus 1 has stored a processing command in the command buffer storage unit 51, the memory controller 42 checks the command buffer storage unit 51 (buffer storage unit). The SSD 40 switches to the performance mode when the value of QD is equal to or greater than a predetermined threshold (for example, two or more), and switches to the ECO mode when the value of QD is less than the predetermined threshold (for example, two).

[0086] Accordingly, the SSD 40 according to this embodiment can switch to the performance mode when the value of QD is equal to or greater than a predetermined threshold (for example, two or more), and thus can cope with processing with a large additional processing with a margin. In addition, the SSD 40 according to this embodiment can reduce power consumption by switching to the ECO mode when the value of QD is less than the predetermined threshold (for example, two). Therefore, the SSD 40 according to this embodiment can suppress a decrease in performance while reducing power consumption.

[0087] In addition, in this embodiment, the memory controller 42 changes to a mode (PCIe Gen3 setting mode) in which the transfer speed of the PCIe bus is lower than that in the performance mode (PCIe Gen4 setting mode) in the ECO mode. Further, the memory controller 42 changes to a mode (PCIe Gen4 setting mode) in which the transfer speed of the PCIe bus is higher than that in the ECO mode (PCIe Gen3 setting mode) in the performance mode.

[0088] Accordingly, the SSD 40 according to this embodiment can easily reduce power consumption by setting it to the ECO mode (PCIe Gen3 setting mode), as shown in FIGS. 3 and 4. In addition, as shown in waveforms W3 and W4 in FIG. 8, since the power consumption of the SSD 40 according to this embodiment is reduced, the base temperature (temperature Tm2) is reduced, and the period until the threshold temperature is reached can be extended, and high performance can be maintained.

[0089] Also, in the present embodiment, the memory controller 42 can parallel-process processing commands by a plurality of threads, and switches to the performance mode when at least one of the QD values corresponding to each of the plurality of threads stored in the command buffer storage unit 51 is equal to or greater than a predetermined threshold value.

[0090] Thereby, the SSD 40 according to the present embodiment can suppress a decrease in performance while reducing power consumption in response to a plurality of threads.

[0091] Also, the information processing apparatus 1 according to the present embodiment incorporates the above-described SSD 40. Thereby, the information processing apparatus 1 according to the present embodiment exhibits the same effects as the above-described SSD 40, can reduce power consumption, and can suppress a decrease in performance due to a temperature rise.

[0092] Also, the control method according to the present embodiment is a control method of the SSD 40 that includes an electrically rewritable flash memory 41 and a memory controller 42 that receives a processing command for the flash memory 41 and executes processing corresponding to the processing command, and is connectable to the information processing apparatus 1, and includes a processing step. In the processing step, the memory controller 42 switches between a performance mode with high processing ability for the flash memory 41 and an ECO mode with lower processing ability than the performance mode according to the value of QD indicating the number of processing commands issued by the information processing apparatus 1 at a time.

[0093] Thereby, the control method according to the present embodiment exhibits the same effects as the above-described SSD 40 and information processing apparatus 1, can reduce power consumption, and can suppress a decrease in performance due to a temperature rise.

[0094] Next, with reference to FIG. 9, a modified example of the present embodiment will be described. In the above-described present embodiment, an example in which the SSD 40 includes the mode switching unit 422 and switches between the performance mode and the ECO mode has been described. However, the main control unit 10 of the information processing apparatus 1 may perform the switching. Here, with reference to FIG. 9, a modified example in which the main control unit 10 switches between the performance mode and the ECO mode will be described.

[0095] FIG. 9 is a functional block diagram showing the functional configuration of the information processing apparatus 1a according to a modified example of the present embodiment. As shown in FIG. 9, the information processing apparatus 1a includes a main control unit 10a, an SSD 40a, and a storage unit 50.

[0096] In FIG. 9, the same components as those in FIG. 2 described above are denoted by the same reference numerals, and the description thereof is omitted.

[0097] The main control unit 10a is a functional unit realized by the CPU 11 and the chipset 21 executing a program stored in the main memory 12, and executes various processes based on the OS. The main control unit 10a executes various processes based on, for example, data stored in the SSD 40. The main control unit 10a includes an AP processing unit 101, an SSD device driver unit 102, and a mode switching unit 103.

[0098] The mode switching unit 103 switches the SSD 40a between a performance mode (first processing mode) with a high processing ability for the SSD 40a and an ECO mode (second processing mode) with a lower processing ability than the performance mode according to the value of QD.

[0099] For example, when the value of QD is equal to or greater than a predetermined threshold (for example, two or more), the mode switching unit 103 sends a mode switching request to the SSD 40a and switches to the performance mode.

[0100] Further, for example, when the value of QD is smaller than a predetermined threshold (e.g., smaller than 2), the mode switching unit 103 transmits a mode switching request to the SSD 40a and switches to the ECO mode.

[0101] The SSD 40a includes a memory controller 42a and an SSD storage unit 410. The memory controller 42a includes a command processing unit 421 and a temperature control unit 423. When the memory controller 42a receives a request to switch to the performance mode from the mode switching unit 103, it stores mode information indicating the performance mode in the mode information storage unit 412 and sets the PCIe bus to the highest transfer speed PCIe Gen4.

[0102] Also, when the memory controller 42a receives a request to switch to the ECO mode from the mode switching unit 103, it stores mode information indicating the ECO mode in the mode information storage unit 412 and sets the PCIe bus to PCIe Gen3.

[0103] As described above, the information processing apparatus 1a according to the modification of the present embodiment includes the SSD 40a and the main control unit 10a. The SSD 40a includes an electrically rewritable flash memory 41 and a memory controller 42 that receives a processing command for the flash memory 41 and executes a process corresponding to the processing command. The main control unit 10a is a main control unit that issues a processing command. Depending on the value of QD indicating the number of processing commands issued to the SSD 40 at one time, the main control unit 10a causes the flash memory 41 to switch between a performance mode with high processing ability and an ECO mode with lower processing ability than the performance mode.

[0104] Thereby, the information processing apparatus 1a according to the modification of the present embodiment has the same effects as the above-described SSD 40 and information processing apparatus 1, can reduce power consumption, and can suppress a decrease in performance due to a temperature rise. In this way, the information processing apparatus 1a may be configured such that the main control unit 10 includes some or all of the functions of the mode switching unit 422 of the SSD 40.

[0105] Note that the present invention is not limited to the above-described embodiments, and can be modified without departing from the spirit of the present invention. For example, in the above-described embodiment, an example in which the information processing apparatus 1 is a notebook personal computer (mobile computer) has been described. However, the present invention is not limited to this, and for example, other information processing apparatuses such as a desktop personal computer or a tablet terminal device may be used.

[0106] Also, in the above-described embodiment, an example in which the performance mode and the ECO mode are set and switched to modes with different transfer speeds of the PCIe bus has been described. However, the present invention is not limited to this, and for example, the mode may be switched to a mode in which the processing ability of the SSD 40 (40a) is limited.

[0107] Also, in the above-described embodiment, an example in which the setting mode of PCIe Gen4 and the setting mode of PCIe Gen3 are switched when switching between the performance mode and the ECO mode has been described. However, the present invention is not limited to this, and for example, the setting mode of PCIe Gen4 and the setting mode of PCIe Gen2 may be switched, or the setting mode of PCIe Gen3 and the setting mode of PCIe Gen2 may be switched. That is, if the setting of two transfer speeds out of the four transfer speeds shown in FIG. 4 described above is switched, other combinations may be used.

[0108] Also, in the above-described embodiment, an example of a personal computer-based configuration in which the information processing apparatus 1 (1a) includes the embedded controller 31 has been described. However, the present invention is not limited to this, and a configuration that does not include the embedded controller 31 may be used. Also, the OS of the information processing apparatus 1 is not limited to Windows (registered trademark), and for example, it may be applied to other OSs such as Android (registered trademark) and iOS (registered trademark).

[0109] Also, in the above-described embodiment, an example in which the information processing apparatus 1 (1a) and the SSD 40 (40a) are connected by a PCIe bus has been described. However, the present invention is not limited to this. When a bus faster than the PCIe bus is newly realized, other buses may be used.

[0110] Each configuration included in the information processing apparatus 1 (1a) and the SSD 40 (40a) described above has a computer system inside. Then, a program for realizing the functions of each configuration included in the information processing apparatus 1 (1a) and the SSD 40 (40a) described above is recorded on a computer-readable recording medium, and the program recorded on this recording medium is read into the computer system and executed, whereby the processing in each configuration included in the information processing apparatus 1 (1a) and the SSD 40 (40a) described above may be performed. Here, "reading and executing the program recorded on the recording medium into the computer system" includes installing the program in the computer system. The "computer system" referred to here is assumed to include hardware such as an OS and peripheral devices.

[0111] Also, the "computer system" may include a plurality of computer devices connected via a network including a communication line such as the Internet, WAN, LAN, or dedicated line. Further, the "computer-readable recording medium" refers to a portable medium such as a flexible disk, magneto-optical disk, ROM, CD-ROM, or a storage device such as a hard disk built into the computer system. In this way, the recording medium storing the program may be a non-transitory recording medium such as a CD-ROM.

[0112] In addition, the recording medium also includes an internal or external recording medium provided so as to be accessible from a distribution server for distributing the program. Note that the program may be divided into a plurality of parts and downloaded at different timings, and then combined by each configuration included in the information processing apparatus 1 (1a) and the SSD 40 (40a), or the distribution servers for distributing the respective divided programs may be different. Further, the "computer-readable recording medium" includes those that hold a program for a certain period of time, such as a volatile memory (RAM) inside a computer system serving as a server or a client when the program is transmitted via a network. Also, the above-described program may be for realizing a part of the above-described functions. Furthermore, it may be a so-called difference file (difference program) that can realize the above-described functions in combination with a program already recorded in a computer system.

[0113] In addition, part or all of the above-described functions may be realized as an integrated circuit such as an LSI (Large Scale Integration). Each of the above-described functions may be individually processed by a processor, or part or all of them may be integrated and processed by a processor. Also, the method of integrating into an integrated circuit is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. Further, when a technology for integrating into an integrated circuit that replaces LSI appears due to the progress of semiconductor technology, an integrated circuit using such technology may be used.

Explanation of Reference Numerals

[0114] 1, 1a Information processing apparatus 10 Main control unit 11 CPU 12 Main memory 13 Video subsystem 14 Display unit 21 Chipset 22 BIOS memory 31 Embedded controller (EC) 32 Input unit 33 Power supply circuit 40, 40a SSD 41 Flash Memory 42 Memory Controller 43 Temperature Sensor 50 Storage Unit 51 Command Buffer Storage Unit 101 AP Processing Unit 102 SSD Device Driver Unit 103, 422 Mode Switching Unit 410 SSD Storage Unit 411 Management Information Storage Unit 412 Mode Information Storage Unit 413 Data Storage Unit 421 Command Processing Unit 423 Temperature Control Unit

Claims

1. A solid-state drive connectable to an information processing apparatus, an electrically rewritable non-volatile memory, and a memory controller that receives a processing command for the non-volatile memory and executes a process corresponding to the processing command, and switches between a first processing mode with high processing ability for the non-volatile memory and a second processing mode with lower processing ability than the first processing mode according to a value of QD (Queue Depth) indicating the number of the processing commands issued by the information processing apparatus at a time A solid-state drive comprising the same.

2. Connectable to the information processing apparatus via a PCIe (Peripheral Component Interconnect-Express) bus, wherein the memory controller checks the buffer storage unit in response to receiving a notification indicating that the processing command has been stored in the buffer storage unit provided in the information processing apparatus, and switches to the first processing mode when the value of QD is equal to or greater than a predetermined threshold, and switches to the second processing mode when the value of QD is less than the predetermined threshold The solid-state drive according to claim 1.

3. The memory controller in the second processing mode, changes to a mode with a lower transfer speed of the PCIe bus than in the first processing mode, and in the first processing mode, changes to a mode with a higher transfer speed of the PCIe bus than in the second processing mode The solid-state drive according to claim 2.

4. The memory controller is capable of parallel processing of the processing commands by a plurality of threads, and switches to the first processing mode when at least one of the QD values corresponding to each of the plurality of threads stored in the buffer storage unit is equal to or greater than the predetermined threshold The solid-state drive according to claim 3.

5. An information processing apparatus incorporating the solid-state drive according to any one of claims 1 to 4 therein.

6. A solid-state drive including an electrically rewritable non-volatile memory and a memory controller that receives a processing command for the non-volatile memory and executes a process corresponding to the processing command, and A main control unit that issues the processing command, which causes the solid state drive to switch between a first processing mode with high processing capacity for the non-volatile memory and a second processing mode with lower processing capacity than the first processing mode according to the value of QD (Queue Depth) indicating the number of processing commands issued at one time to the solid state drive. An information processing apparatus comprising the same. **Claim 7** A control method for a solid state drive that can be connected to an information processing apparatus, the solid state drive comprising an electrically rewritable non-volatile memory and a memory controller that receives a processing command for the non-volatile memory and executes a process corresponding to the processing command, the method comprising: A processing step in which the memory controller switches between a first processing mode with high processing capacity for the non-volatile memory and a second processing mode with lower processing capacity than the first processing mode according to the value of QD (Queue Depth) indicating the number of processing commands issued at one time by the information processing apparatus. A control method.

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