Signal transmission system and signal transmission method

Abstract

To provide a signal transmission system and a signal transmission method for easily and inexpensively achieving distribution of a clock signal and a long period signal synchronized with the clock signal.SOLUTION: A signal transmission system 200 includes a plurality of control units 220-1, 220-2, ..., 220-n, and a signal distribution device 210 for distributing a clock signal CK and a long period signal LP having a period of twice or more of the clock signal CK and synchronized with the clock signal CK to the plurality of control units 220-1, 220-2, ..., 220-n. The signal distribution device 210 is provided with a modulation circuit for generating a modulation signal MD obtained by superimposing the long period signal LP on the clock signal CK by modulating the long period signal LP with the clock signal CK, and distributes the modulation signal MD to the plurality of control units 220-1, 220-2, ..., 220-n through transmission paths 230-1, 230-2, ..., 230-n, respectively.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a signal transmission system and a signal transmission method.

Background Art

[0002] In large-scale computer systems such as large-scale quantum computer systems, a plurality of control units need to operate with high precision in synchronization based on a low-jitter clock signal. For the long-term stable operation of such large-scale computer systems, it is necessary to distribute a low-jitter clock signal and a long-period signal synchronized with the clock signal to a plurality of control units.

[0003] FIG. 1 shows the configuration of a signal transmission system 100 in a conventional large-scale computer system. The signal transmission system 100 includes a signal distribution device 110 and a plurality of control units 120-1, 120-2,..., 120-n (n is an integer of 2 or more) connected to the signal distribution device 110. The signal distribution device 110 generates a low-jitter clock signal CK and a long-period signal LP, and distributes the clock signal CK and the long-period signal LP to a plurality of control units 120-1, 120-2,..., 120-n via separate transmission paths (cables) (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the conventional signal transmission system 100, since the clock signal CK and the long-period signal LP were transmitted to each control unit through separate transmission paths, it was necessary to adjust the cable length and manage the temperature of the distribution mechanism in order to suppress the fluctuation between the clock signal CK and the long-period signal LP, which was accompanied by difficulties. Also, in order to distribute the long-period signal LP to a large number of control units over a long distance, low-loss transmission is required. However, since the period of the long-period signal LP is very long, there is also a problem that transmission cannot be substantially achieved even by using an optical cable for long-distance and low-loss transmission. Furthermore, in order to construct a large-scale computer system, increasing the number of cables and the cable length makes it even more difficult to solve the above-described problems and also causes high costs.

[0006] The present invention has been made in view of the above problems, and an object thereof is to provide a signal transmission system and a signal transmission method that can easily and at low cost realize the distribution of a clock signal and a long-period signal synchronized with the clock signal.

Means for Solving the Problems

[0007] The signal transmission system according to the present invention includes a plurality of control units, a clock signal, and a signal distribution device for distributing to the plurality of control units a long-period signal having a period twice or more that of the clock signal and synchronized with the clock signal. The signal distribution device includes a modulation circuit that generates a modulation signal in which the long-period signal is superimposed on the clock signal by modulating the long-period signal with the clock signal, and distributes the modulation signal to the plurality of control units via a transmission path.

[0008] The signal transmission method according to the present invention is a method for distributing a clock signal and a long-period signal having a period twice or more that of the clock signal and synchronized with the clock signal to a plurality of control units by a signal distribution device. The modulation circuit of the signal distribution device generates a modulation signal in which the long-period signal is superimposed on the clock signal by modulating the long-period signal with the clock signal, and the signal distribution device distributes the modulation signal to the plurality of control units via a transmission path.

Effects of the Invention

[0009] According to the present invention, a modulation signal obtained by superimposing a long-period signal on a clock signal is generated, and the modulation signal is transmitted via a transmission path, so that the clock signal and the long-period signal are distributed to each control unit through the same path. As a result, transmission fluctuations are reduced, and it becomes possible to easily and inexpensively realize the distribution of the clock signal and the long-period signal.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 5

Figure 6

Figure 7A

Figure 7B

Figure 8A

Figure 8B

Figure 9A

Figure 9B

Embodiment for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In this embodiment, a signal transmission system and a signal transmission method applied to a large-scale computer system such as a large-scale quantum computer system are targeted.

[0012] FIG. 2 shows the configuration of a signal transmission system 200 according to this embodiment. The signal transmission system 200 includes a signal distribution device 210 and a plurality of control units 220-1, 220-2,..., 220-n respectively connected to the signal distribution device 210 via transmission paths 230-1, 230-2,..., 230-n (n is an integer of 2 or more).

[0013] The signal distribution device 210 is a device for distributing a low-jitter clock signal CK and a long-period signal LP synchronized with the clock signal CK to the plurality of control units 220-1, 220-2,..., 220-n. The frequency range of the clock signal CK is 10 MHz to 100 GHz. The frequency range of the long-period signal LP is 1 Hz or more and half or less of the frequency of the clock signal CK (2 times or more the period of the clock signal CK). In this embodiment, it is assumed that the long-period signal LP has the same pulse width as the clock signal CK, but it is not limited thereto.

[0014] The signal distribution device 210 includes a modulation circuit 310 (FIG. 3A) for generating a modulation signal MD in which a long-period signal LP is superimposed on a clock signal CK by modulating the long-period signal LP with the clock signal CK by pulse-width modulation (PWM). The modulation signal MD is distributed to the control units 220-1, 220-2, …, 220-n via the transmission paths 230-1, 230-2, …, 230-n, respectively.

[0015] As shown in FIG. 3A, the modulation circuit 310 includes a clock generation source 312, a long-period signal generation circuit 314, a phase shift circuit 316, an OR gate 318, and an AND gate 320.

[0016] The clock generation source 312 generates a clock signal CK. The clock signal CK from the clock generation source 312 is output to the long-period signal generation circuit 314, the phase shift circuit 316, and the AND gate 320. The long-period signal generation circuit 314 generates a long-period signal LP from the clock signal CK. The phase shift circuit 316 obtains a phase shift signal M1 by shifting the phase of the clock signal CK. The range of the phase shift amount of the clock signal CK will be described later (see FIGS. 4A to 4D).

[0017] The OR gate 318 outputs a composite signal M2 of the phase shift signal M1 and the long-period signal LP by performing an OR operation on the phase shift signal M1 and the long-period signal LP. The AND gate 320 outputs a modulation signal MD by performing an AND operation on the composite signal M2 and the clock signal CK.

[0018] At least some functions of the modulation circuit 310 can be realized by a programmable logic device such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).

[0019] In this embodiment, the modulation signal MD can be distributed by an arbitrary distribution method. For example, if the signal distribution device 210 includes n modulation circuits 310, the n modulation signals MD generated by the n modulation circuits 310 can be transmitted to the control units 220-1, 220-2, ..., 220-n via the transmission paths 230-1, 230-2, ..., 230-n, respectively.

[0020] When the transmission paths 230-1, 230-2, ..., 230-n are optical cables, a converter for converting the modulation signal MD, which is an electrical signal, into an optical signal may be provided at the output stage of each modulation circuit 310. In this case, the n optical signals output from the n converters are transmitted to the control units 220-1, 220-2, ..., 220-n via the transmission paths 230-1, 230-2, ..., 230-n, respectively.

[0021] As another distribution method, one modulation signal MD generated by one modulation circuit 310 may be divided into n modulation signals MD by a passive distributor.

[0022] For example, as shown in FIG. 3B, the amplifier 332 amplifies the modulation signal MD generated by the modulation circuit 310 with a gain of n, and the distributor 334 divides the amplified signal into n signals. Although the n signals are attenuated by the distribution by the distributor 334, since the original modulation signal MD is amplified before attenuation, the n signals have the same signal level as the original modulation signal MD.

[0023] Alternatively, as shown in FIG. 3C, the distributor 342 divides the modulation signal MD generated by the modulation circuit 310 into n signals, and the n amplifiers 344-1, 344-2, ..., 344-n amplify the n signals with a gain of n, respectively. Although the n signals are attenuated by the distribution by the distributor 342, since the n signals are amplified by the n amplifiers 344-1, 344-2, ..., 344-n, respectively, the signal level of the original modulation signal MD is maintained.

[0024] When the transmission paths 230-1, 230-2, …, 230-n are electrical cables, a high-frequency (RF) distributor can be used as the above-described distributor. When the transmission paths 230-1, 230-2, …, 230-n are optical cables, an optical amplifier and an optical distributor can be used as the above-described amplifier and distributor, respectively. In this case, a converter for converting the modulation signal MD, which is an electrical signal, into an optical signal is provided at the output stage of the modulation circuit 310, and the optical signal output from the converter is input to the circuit of FIG. 3B or FIG. 3C. Note that other circuit configurations may be adopted as long as they can output an optical signal to an optical cable. For example, a converter may be provided between the amplifier and the distributor.

[0025] By using the distributors 334 and 342 as shown in FIGS. 3B and 3C, the signal distribution device 210 only needs to include one modulation circuit 310, and n modulation signals MD can be obtained with a simple configuration. In addition, compared with an AND gate, the amplifier and the distributor are lower in cost, easier to obtain, and less likely to cause phase noise degradation. Therefore, the configurations of FIGS. 3B and 3C are superior in terms of cost, availability, and performance to the configuration including n modulation circuits 310 having AND gates 320.

[0026] When the conventional signal distribution device 110 shown in FIG. 1 includes a distributor for dividing one clock signal CL into n clock signals CK and a distributor for dividing one long-period signal LP into n long-period signals LP, there is a possibility that skew occurs between these two distributors. On the other hand, in the configurations of FIGS. 3B and 3C, since the signal distribution device 210 only needs to include one distributor, such skew does not occur.

[0027] Next, with reference to the timing charts of FIGS. 4A to 4D, the range of the phase shift amount δ of the clock signal CK in the phase shift circuit 316 will be described.

[0028] When 0 < δ ≤ 90° (Fig. 4A), the modulation signal MD has a frequency that is kept constant with respect to the falling edge reference, the same as that of the clock signal CK, but the frequency with respect to the rising edge reference is not constant (see the double-headed arrow of the dotted line in Fig. 4A).

[0029] As shown in Figs. 4A to 4D, in the modulation signal MD, a pulse (hereinafter referred to as a long-period pulse) W having a relatively long pulse width appears in the cycle of the long-period signal LP, and the pulse width of the long-period pulse W is the same as that of the clock signal CK and the long-period signal LP.

[0030] When 90° < δ < 180° (Fig. 4B), the modulation signal MD also has a frequency that is kept constant with respect to the falling edge reference, the same as that of the clock signal CK, but the frequency with respect to the rising edge reference is not constant (see the double-headed arrow of the dotted line in Fig. 4B).

[0031] On the other hand, when 180° < δ ≤ 270° (Fig. 4C) and 270° < δ < 360° (Fig. 4D), the modulation signal MD has a frequency that is kept constant with respect to the rising edge reference with the same jitter accuracy as that of the clock signal CK.

[0032] Therefore, by setting 180° < δ < 360° (Figs. 4C and 4D), the long-period signal LP can be superimposed on the clock signal CK while maintaining the jitter accuracy of the clock signal CK, and a modulation signal MD in which a long-period pulse W appears in the cycle of the long-period signal LP can be generated. The actual range of δ is determined depending on the hold time required by the phase synchronization circuit (PLL) IC (described later) of each control unit on the demodulation side. Considering the hold time on the demodulation side, it is preferable to set 225° ≤ δ < 270°.

[0033] Each of the plurality of control units 220-1, 220-2, …, 220-n includes a demodulation circuit 510 (Fig. 5) for demodulating the modulation signal MD. As shown in Fig. 5, the demodulation circuit 510 includes a clock signal recovery circuit 520 for obtaining a clock signal RECK reproduced from the modulation signal MD based on a local clock, and a long-period signal recovery circuit 530 for obtaining a long-period signal RELP reproduced from the modulation signal MD.

[0034] When the transmission paths 230-1, 230-2, …, 230-n are optical cables, each of the plurality of control units 220-1, 220-2, …, 220-n includes a converter for converting the modulation signal MD as an optical signal input via the optical cable into an electrical signal, and the modulation signal MD as the electrical signal output from the converter is input to the demodulation circuit 510.

[0035] The clock signal recovery circuit 520 includes a PLL. As shown in Fig. 6, the rising edge of the modulation signal MD is input to the PLL, and using the PLL, a reproduced clock signal RECK having the same period as the rising edge of the modulation signal MD and a pulse width that is half of that period is output. The reproduced clock signal RECK is branched into two, one of which becomes the operation clock of the control unit, and the other is output to the long-period signal recovery circuit 530.

[0036] Fig. 7A shows the configuration of a long-period signal recovery circuit 530-1 as an example of the long-period signal recovery circuit 530, Fig. 8A shows the configuration of a long-period signal recovery circuit 530-2 as a modification of Fig. 7A, and Fig. 9A shows the configuration of a long-period signal recovery circuit 530-3 as another example of the long-period signal recovery circuit 530. Fig. 7B shows the timing chart of the long-period signal recovery circuit 530-1 shown in Fig. 7A, Fig. 8B shows the timing chart of the long-period signal recovery circuit 530-2 shown in Fig. 8A, and Fig. 9B shows the timing chart of the long-period signal recovery circuit 530-3 shown in Fig. 9A.

[0037] The long-period signal recovery circuit 530-1 shown in FIG. 7A includes a phase shift circuit 710, a multiplier 712, sampling circuits 714 and 716, and an AND gate 718.

[0038] The phase shift circuit 710 generates a phase shift signal R1 by shifting the phase of the reproduced clock signal RECK by δ / 4 or more and less than 90°. Here, δ is the amount of phase shift in the phase shift circuit 316 of the modulation circuit 310.

[0039] The multiplier 712 generates a high-frequency signal R2 having a frequency N times that of the phase shift signal R1 (N is an integer of 2 or more). FIG. 7B shows an example in which the frequency of the high-frequency signal R2 is 4 times that of the phase shift signal R1.

[0040] The sampling circuit 714 is a D flip-flop, captures the modulation signal MD at the rising edge of the high-frequency signal R2, and outputs a first sampling signal R3. The sampling circuit 716 is also a D flip-flop, captures the first sampling signal R3 at the rising edge of the high-frequency signal R2, and outputs a second sampling signal R4. As shown in FIG. 7B, the second sampling signal R4 is a signal obtained by shifting the first sampling signal R3 by one period of the high-frequency signal R2.

[0041] The AND gate 718 outputs the reproduced long-period signal RELP by performing an AND operation on the first sampling signal R3 and the second sampling signal R4.

[0042] The long-period signal recovery circuit 530-2 shown in FIG. 8A has the same configuration as that obtained by swapping the phase shift circuit 710 and the multiplier 712 in FIG. 7A, and includes a multiplier 810, a phase shift circuit 812, sampling circuits 814 and 816, and an AND gate 818.

[0043] The multiplier 810 generates a first high-frequency signal R11 having a frequency N times (N is an integer of 2 or more) that of the reproduced clock signal RECK. FIG. 8B shows an example in which the frequency of the first high-frequency signal R11 is 4 times that of the reproduced clock signal RECK.

[0044] The phase shift circuit 812 generates a second high-frequency signal R12 by shifting the phase of the first high-frequency signal R11 by δ or more and less than 360°.

[0045] The sampling circuit 814 is a D flip-flop, captures the modulation signal MD at the rising edge of the second high-frequency signal R12, and outputs a first sampling signal R13. The sampling circuit 816 is also a D flip-flop, captures the first sampling signal R13 at the rising edge of the second high-frequency signal R12, and outputs a second sampling signal R14. As shown in FIG. 8B, the second sampling signal R14 is a signal obtained by shifting the first sampling signal R13 by one period of the second high-frequency signal R12.

[0046] The AND gate 818 outputs the reproduced long-period signal RELP by performing an AND operation on the first sampling signal R13 and the second sampling signal R14.

[0047] The long-period signal recovery circuit 530-3 shown in FIG. 9A is a circuit that outputs the reproduced long-period signal RELP by finding the long-period pulse W from the modulation signal MD, and includes a multiplier 910, a counter 912, and a pulse output circuit 914.

[0048] The multiplier 910 generates a high-frequency signal R21 having a frequency N times (N is an even number of 2 or more) that of the reproduced clock signal RECK. Here, as shown in FIG. 9B, when the pulse width of the long-period pulse W of the modulation signal MD is set to 1, the pulse width other than the long-period pulse W is (δ - 180°) / 180°. The value of N is set so that the pulse width 1 and the pulse width (δ - 180°) / 180° can be distinguished (for example, N = 8, N = 16, etc.). FIG. 9B shows an example of N = 8.

[0049] The counter 912 counts the number of times the modulation signal MD is continuously at a high level at the rising edge of the high-frequency signal R21 to obtain a count value R22, and outputs it to the pulse output circuit 914. In the example of FIG. 9B, the count value R22 of the long-period pulse W is 4, and the count value R22 of the pulses other than the long-period pulse W is 3.

[0050] The pulse output circuit 914 outputs, as a pulse of the long-period signal RELP obtained by reproducing a pulse having a pulse width corresponding to a predetermined value using the high-frequency signal R21, at the timing when the count value R22 reaches a relatively large predetermined value (that is, at the timing when a slot having a relatively long pulse width is found). Specifically, the pulse output circuit 914 generates a pulse having a pulse width corresponding to R22 = N / 2 at the timing when the count value R22 reaches half of the multiple (R22 = N / 2). Thereby, the reproduced long-period signal RELP is obtained.

[0051] At least some functions of the long-period signal recovery circuits 530-1, 530-2, and 530-3 respectively shown in FIGS. 7A, 8A, and 9A can be realized by a programmable logic device such as an FPGA or an ASIC.

[0052] According to the signal transmission system 200 according to the present embodiment, by modulating the long-period signal LP with the low-jitter clock signal CK, a modulation signal MD in which the long-period signal LP is superimposed on the clock signal CK is generated, and the modulation signal MD is transmitted via the transmission paths 230-1, 230-2,..., 230-n to the control units 220-1, 220-2,..., 220-n, respectively, for distribution.

[0053] As a result, the clock signal CK and the long-period signal LP are transmitted through the same path, and synchronization deviation due to the wiring length or temperature between the clock signal CK and the long-period signal LP will not occur in principle. In addition, compared with the conventional signal transmission system 100 shown in FIG. 1, the number of transmission paths (cables) can be reduced by half, so that the cost can be reduced. Furthermore, since not only electrical cables but also optical cables can be used, the cable length can be increased for long-distance transmission of the long-period signal LP in a large-scale computer system.

[0054] Note that the present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present invention. Other embodiments and modifications made by those skilled in the art are also included in the present invention.

Explanation of Reference Numerals

[0055] 200 Signal transmission system 210 Signal distribution device 220-1, 220-2, 220-n Control unit 230-1, 230-2, 230-n Transmission path 310 Modulation circuit 312 Clock generation source 314 Long-period signal generation circuit 316 Phase shift circuit 318 OR gate 320 AND gate 332, 344-1, 344-2, 344-n Amplifier 334, 342 Distributor 510 Demodulation circuit 520 Clock signal recovery circuit 530, 530-1, 530-2, 530-3 Long-period signal recovery circuit 710, 812 Phase shift circuit 712, 810 Multiplier 714, 716, 814, 816 Sampling circuit 718, 818 AND gate 910 Multiplier 912 Counter 914 Pulse Output Circuit CK Clock Signal LP Long Period Signal MD Modulation Signal M1 Phase Shift Signal M2 Composite Signal RECK Re-generated Clock Signal RELP Re-generated Long Period Signal R1 Phase Shift Signal R2, R21 High Frequency Signal R3, R13 First Sampling Signal R4, R14 Second Sampling Signal R11 First High Frequency Signal R12 Second High Frequency Signal R22 Count Value

Claims

1. A plurality of control units, a clock signal, and a signal distribution device for distributing to the plurality of control units a long-period signal having a period that is two times or more that of the clock signal and synchronized with the clock signal, A signal transmission system comprising: The signal distribution device includes a modulation circuit that generates a modulation signal in which the long-period signal is superimposed on the clock signal by modulating the long-period signal with the clock signal, A signal transmission system that distributes the modulation signal to the plurality of control units via a transmission path.

2. The signal distribution device generates the modulation signal by pulse width modulation. The signal transmission system according to claim 1.

3. The modulation circuit obtains a phase shift signal by shifting the phase of the clock signal, obtains a composite signal of the phase shift signal and the long-period signal by performing an OR operation on the phase shift signal and the long-period signal, The signal transmission system according to claim 1, wherein the modulation signal is generated by performing an AND operation on the composite signal and the clock signal.

4. The modulation circuit obtains the phase shift signal by shifting the phase of the clock signal in a range greater than 180° and less than 360°. The signal transmission system according to claim 3.

5. Each of the plurality of control units includes a demodulation circuit that obtains a reproduced clock signal and a reproduced long-period signal from the modulation signal, The demodulation circuit includes a clock signal recovery circuit that obtains the reproduced clock signal based on a rising edge of the modulation signal, and a long-period signal recovery circuit that obtains the reproduced long-period signal from the modulation signal and the reproduced clock signal. The signal transmission system according to claim 1.

6. The long-period signal recovery circuit generates a high-frequency signal by shifting the phase of the reproduced clock signal to multiply the frequency or by multiplying the frequency of the reproduced clock signal and then shifting the phase, obtains a first sampling signal by sampling the modulation signal with the high-frequency signal, obtains a second sampling signal by sampling the first sampling signal with the high-frequency signal, The signal transmission system according to claim 5, wherein the reproduced long-period signal is obtained by performing an AND operation on the first sampling signal and the second sampling signal.

7. The long-period signal recovery circuit: generates a high-frequency signal by multiplying the frequency of the reproduced clock signal; counts the number of times the modulation signal is continuously at a high level at the rising edge of the high-frequency signal to obtain a count value; When the count value reaches a predetermined value that is relatively large, a pulse having a pulse width corresponding to the predetermined value is output as a pulse of the reproduced long-period signal using the high-frequency signal. The signal transmission system according to claim 5. **Claim 8** The signal distribution device further includes a distributor that divides the modulation signal generated by the modulation circuit into a plurality of modulation signals; The plurality of modulation signals are respectively transmitted to the plurality of control units. The signal transmission system according to claim 1. **Claim 9** A signal transmission method for distributing a clock signal and a long-period signal having a period that is two or more times that of the clock signal and synchronized with the clock signal to a plurality of control units by a signal distribution device, wherein the modulation circuit of the signal distribution device generates a modulation signal in which the long-period signal is superimposed on the clock signal by modulating the long-period signal with the clock signal; A signal transmission method in which the signal distribution device distributes the modulation signal to the plurality of control units via a transmission path. **Claim 10** The modulation signal is generated by pulse width modulation. The signal transmission method according to claim 9. **Claim 11** The generation of the modulation signal includes: obtaining a phase shift signal by shifting the phase of the clock signal; obtaining a composite signal of the phase shift signal and the long-period signal by performing an OR operation on the phase shift signal and the long-period signal; generating the modulation signal by performing an AND operation on the composite signal and the clock signal. The signal transmission method according to claim 9. **Claim 12** The phase shift signal is obtained by shifting the phase of the clock signal within a range greater than 180° and less than 360°. The signal transmission method according to claim 11. **Claim 13** By each demodulation circuit of the plurality of control units, a reproduced clock signal is obtained based on the rising edge of the modulation signal; A reproduced long-period signal is obtained from the modulation signal and the reproduced clock signal. The signal transmission method according to claim 9. **Claim 14** When obtaining the reproduced long-period signal, A high-frequency signal is generated by phase-shifting the reproduced clock signal to multiply the frequency, or by multiplying the frequency of the reproduced clock signal and then phase-shifting it. A first sampling signal is obtained by sampling the modulation signal with the high-frequency signal. A second sampling signal is obtained by sampling the first sampling signal with the high-frequency signal. The signal transmission method according to claim 13, comprising obtaining the reproduced long-period signal by performing an AND operation on the first sampling signal and the second sampling signal.

15. When obtaining the reproduced long-period signal, A high-frequency signal is generated by multiplying the frequency of the reproduced clock signal. The number of times the modulation signal is continuously at a high level at the rising edge of the high-frequency signal is counted to obtain a count value. The signal transmission method according to claim 13, comprising outputting, as a pulse of the reproduced long-period signal, a pulse having a pulse width corresponding to the predetermined value using the high-frequency signal when the count value reaches a relatively large predetermined value.

16. The modulation signal generated by the modulation circuit is divided into a plurality of modulation signals by a distributor. The signal transmission method according to claim 9, wherein the plurality of modulation signals are respectively transmitted to the plurality of control units.

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