Image pick-up device

Abstract

To prevent the influence of IR drop occurring due to the difference in wire length between pixels, and prevent unevenness occurring in a picked-up image.SOLUTION: An aspect of the present invention is an image pick-up device. The image pick-up device comprises a plurality of pixels including first pixels and second pixels, which are provided side by side in a first direction and a second direction intersecting the first direction. The image pick-up device comprises first power lines connected to the first pixels and supplying first voltage. The image pick-up device comprises second power lines connected to the second pixels and supplying second voltage.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to an image sensor.

Background Art

[0002] As an image sensor, for example, there is a technique described in Patent Document 1 below. However, it is desired to suppress the influence of IR drop caused by the difference in wiring length for each pixel and suppress the unevenness generated in the captured image.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] One aspect of the present invention is an image sensor. The image sensor includes a plurality of pixels arranged side by side in a first direction and a second direction intersecting the first direction, and includes a first pixel and a second pixel. The image sensor includes a first power supply line connected to the first pixel and supplying a first voltage. The image sensor includes a second power supply line connected to the second pixel and supplying a second voltage.

Brief Description of the Drawings

[0005]

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MODE FOR CARRYING OUT THE INVENTION

[0006] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, for the purpose of explaining the embodiments, the scale is appropriately changed such as enlarging or emphasizing a part, and the shape, dimensions, etc. may be different from those of the actual product. In the drawings, there is a diagram for explaining the directions in the figure using the XYZ coordinate system. In this XYZ coordinate system, the plane parallel to the chip constituting the image sensor is defined as the XY plane. One direction in this XY plane is denoted as the X direction (first direction), and the direction orthogonal to the X direction is denoted as the Y direction (second direction). The direction perpendicular to the XY plane is denoted as the Z direction (third direction).

[0007] [First Embodiment] The first embodiment will be described. FIG. 1 is a schematic diagram showing the overall configuration of the imaging device 1A. As shown in FIG. 1, the imaging device 1A is, for example, a CMOS image sensor in which a plurality of pixels are two-dimensionally arranged. The imaging device 1A is provided in an imaging unit of, for example, a digital camera, a digital video camera, a portable information terminal having an imaging function (e.g., a smartphone, a tablet, a mobile phone with a camera), etc. The imaging device 1A captures an image formed by an imaging optical system provided in the imaging unit. The imaging result of the imaging device 1A includes, for example, information on gradation values for each color of each pixel (e.g., RGB data). The imaging device 1A outputs the imaging result in the data format of a full-color image, for example.

[0008] The imaging device 1A includes a pixel section 2 and a circuit section 4A. When viewed from the Z direction, the imaging device 1A is composed of, for example, a rectangular plate-shaped chip 11. The chip 11 is formed along the XY plane. The chip 11 has a pad arrangement area 12 and a pixel area 13. The pad arrangement area 12 is arranged along the four sides of the chip 11 at the outer peripheral portion of the chip 11. The pixel area 13 is arranged inside the pad arrangement area 12. The pixel area 13 is arranged surrounded by the pad arrangement area 12.

[0009] The pixel section 2 is arranged in the pixel area 13 arranged at the central portion of the chip 11. The pixel section 2 has a plurality of pixels 20. The plurality of pixels 20 are arranged along the XY plane. The plurality of pixels 20 are arranged in a matrix along the X direction and the Y direction. Specifically, the plurality of pixels 20 are arranged in a plurality of columns with or without intervals in the X direction. In each column, the plurality of pixels 20 are arranged in a plurality of rows with or without intervals in the Y direction.

[0010] FIG. 2 is a diagram showing the circuit configuration of pixel 20 of imaging device 1A. As shown in FIG. 2, each pixel 20 functionally includes a photoelectric conversion unit 21, a transfer unit 22, a reset unit 23, and an output unit 24. The photoelectric conversion unit 21 is composed of, for example, a photodiode 21d. The photoelectric conversion unit 21 photoelectrically converts the received light to generate charges. The photoelectric conversion unit 21 outputs the generated charges to the transfer unit 22.

[0011] The transfer unit 22, the reset unit 23, and the output unit 24 constitute a readout circuit that reads the charges (signals) generated by the photoelectric conversion unit 21. The transfer unit 22 is composed of, for example, a transfer transistor 22t. The charges output from the photoelectric conversion unit 21 are accumulated by the capacitance (so-called floating diffusion) of the wiring unit 25 that connects the transfer unit 22 and the output unit 24. The transfer unit 22 outputs the charges output from the photoelectric conversion unit 21 and accumulated in the wiring unit 25 to the output unit 24. The output of the charges of the transfer unit 22 to the output unit 24 is controlled by a command signal from the circuit unit 4A. When the command signal is input, the transfer unit 22 outputs the charges accumulated in the wiring unit 25 to the output unit 24. The reset unit 23 is composed of, for example, a reset transistor 23t. The reset unit 23 discharges the charges accumulated in the wiring unit 25 to the power supply circuit 50A. The reset unit 23 resets the pixel 20 by discharging the charges accumulated in the wiring unit 25 each time shooting is performed.

[0012] The output unit 24 outputs the charges output by the transfer unit 22 to a processing unit 60 described later. The output unit 24 includes a current-voltage conversion unit 26 and a selection unit 27. The current-voltage conversion unit 26 is composed of a gate transistor 26t that constitutes a drain-grounded circuit (source follower circuit). The current-voltage conversion unit 26 generates a voltage signal corresponding to the charges accumulated in the wiring unit 25. The selection unit 27 is composed of a selection transistor 27t. When the selection signal is ON, the selection unit 27 outputs the voltage signal generated by the current-voltage conversion unit 26 to the signal line 41 by the current supplied from the pixel current source provided in the circuit unit 4A.

[0013] Here, the pixel 20 in the present embodiment includes one photoelectric conversion unit 21 (PD) and four transistors (transfer transistor 22t, reset transistor 23t, gate transistor 26t, selection transistor 27t), but is not limited thereto. The number of photodiodes constituting the photoelectric conversion unit 21 and the number of transistors constituting the transfer unit 22, the reset unit 23, and the output unit 24 of the pixel 20 can be appropriately changed. The circuit unit 4A mainly includes a power supply circuit 50A and a signal line 41, which will be described in detail later. The power supply circuit 50A supplies power (voltage) supplied from a pixel power supply arranged outside the imaging device 1A to each pixel 20. The signal line 41 transmits a voltage signal output from each pixel 20 to the processing unit 60.

[0014] The pixel 20 as described above sequentially executes the following operations under the control of an imaging device controller (not shown). First, before imaging, the charge in the photodiode 21d of the photoelectric conversion unit 21 is reset. For this, the reset transistor 23t and the transfer transistor 22t are turned ON, and the photodiode 21d and the power supply circuit 50A are electrically connected. With this configuration, the charge accumulated in the photodiode 21d is discharged to the power supply circuit 50A and reset.

[0015] Next, the reset transistor 23t and the transfer transistor 22t are switched to OFF. With this configuration, exposure starts in the photodiode 21d. The photodiode 21d converts the irradiated light into charge and accumulates it. After a predetermined exposure time has elapsed, the transfer transistor 22t is switched to ON. As a result, the charge accumulated in the photodiode 21d is transferred to the wiring unit 25. The imaging device controller (not shown) sequentially reads out voltage signals from a plurality of pixels 20 in a predetermined readout order. When the selection signal of the selection transistor 27t of the pixel 20 becomes ON, a voltage signal corresponding to the charge accumulated in the wiring unit 25 is generated by the gate transistor 26t of the current-voltage conversion unit 26. The generated voltage signal is output to the signal line 41 via the selection transistor 27t of the selection unit 27.

[0016] FIG. 3 is a cross-sectional view of the chip 11 that constitutes the imaging device 1A. The chip 11 of the imaging device 1A having the circuit configuration as described above has a stacked structure. The chip 11 of the imaging device 1A has a first layer 110 and a second layer 120 stacked on the first layer 110. The first layer 110 and the second layer 120 are each arranged along the XY plane. The first layer 110 and the second layer 120 are stacked in the Z direction. The first layer 110 and the second layer 120 are manufactured individually. The first layer 110 and the second layer 120 are bonded to each other by bonding pads 15.

[0017] A pixel portion 2 is formed in the first layer 110. The first layer 110 has a substrate layer 101a and a wiring layer 101b. The substrate layer 101a has a substrate body 111, a light-shielding metal 114, a color filter 112, and a lens 113. The substrate body 111 is arranged along the XY plane and has a predetermined thickness in the Z direction. The substrate body 111 is mainly formed of a silicon material. A photodiode 21d made of a semiconductor and constituting the photoelectric conversion portion 21 is embedded in the substrate body 111. The photodiodes 21d are arranged at intervals in the X direction and the Y direction, respectively. The silicon material forming the substrate body 111 is interposed between the photodiodes 21d adjacent to each other in the X direction and the Y direction.

[0018] The light-shielding metal 114 is arranged so as to cover the surface 111f on one side in the Z direction of the substrate body 111. The light-shielding metal 114 has openings 114a at positions facing the photodiodes 21d of the pixels 20 adjacent to each other in the XY plane in the Z direction. The light-shielding metal 114 has a grid 114c that closes the space between the openings 114a of the pixels 20 adjacent to each other in the XY direction.

[0019] The color filter 112 is laminated and disposed on one side in the Z direction with respect to the light-shielding metal 11r. The color filter 112 has an R filter that transmits red light, a G filter that transmits green light, and a B filter that transmits blue light arranged in a predetermined array. Each of the R filter, the G filter, and the B filter is disposed on one side in the Z direction with respect to the light-shielding metal 114 so as to cover the opening 114a of the light-shielding metal 114. The lens 113 is disposed on one side in the Z direction with respect to the color filter 112 so as to cover each of the R filter, the G filter, and the B filter.

[0020] The wiring layer 101b has wirings and elements constituting a digital circuit embedded in an insulator 117 formed with a predetermined thickness in the Z direction. Examples of the wirings and elements embedded in the insulator 117 include the transfer transistor 22t, the wiring portion 25, the reset transistor 23t, the gate transistor 26t, the selection transistor 27t, and the power supply circuit 50A. The second layer 120 has wirings and elements constituting an analog circuit embedded therein. Examples of the wirings and elements embedded in the second layer 120 include a signal line 41 described later, an ADC (analog-digital converter) as the processing unit 60, and a pixel current source 61.

[0021] FIG. 4 is a plan view showing the configuration of the pixel block 200. The pixel portion 2 including the pixel 20 as described above has a plurality of pixel blocks 200. As shown in FIG. 4, each pixel block 200 is composed of a plurality of pixels 20 arranged in each of the X direction and the Y direction. For example, in the present embodiment, one pixel block 200 is composed of 4 pixels in the X direction, 4 pixels in the Y direction, and a total of 16 pixels 20.

[0022] The power supply circuit 50A supplies the voltage supplied from the pixel power supply to each pixel 20. The power supply circuit 50A includes a main power supply line (third power supply line) 51A, a connection portion 52A, and a pixel power supply line 53A. The main power supply line 51A extends in parallel in the X direction or the Y direction. In the present embodiment, as shown in FIG. 1, the main power supply line 51A extends in parallel in the X direction so as to straddle the pixel region 13. A plurality of main power supply lines 51A are provided at intervals in the Y direction. As shown in FIG. 4, each main power supply line 51A is arranged so as to pass through the central portion of a plurality of pixel blocks 200 arranged in the X direction. The end of the main power supply line 51A is connected to a power supply pad 14 (see FIG. 1) formed in the pad arrangement region 12 of the chip 11. The main power supply line 51A is arranged on the other side (the second layer 120 side) in the Z direction in the wiring layer 101b of the first layer 110.

[0023] The connection portion 52A connects the main power supply line 51A and the pixel power supply line 53A. Four connection portions 52A are arranged for each pixel block 200. In each pixel block 200, each of the four connection portions 52A is arranged at intervals in the X direction. Each connection portion 52A extends in the Z direction, and one end thereof is connected to the main power supply line 51A. The other end of the connection portion 52A is connected to the pixel power supply line 53A. The connection portion 52A is arranged on one side in the Z direction with respect to the main power supply line 51A.

[0024] The pixel power line 53A is arranged in each column in the X direction in each pixel block 200. That is, each pixel block 200 includes four pixel power lines 53A spaced apart in the X direction. Each pixel power line 53A extends orthogonally to the main power line 51A when viewed from the Z direction. The pixel power line 53A extends from the connection part 52A (main power line 51A) to both sides in the Y direction. The pixel power line 53A is arranged on one side in the Z direction with respect to the connection part 52A. The pixel power line 53A is provided with a first power line 54A connected to the first pixel 201A and a second power line 55A connected to the second pixel 202A on both sides in the Y direction, respectively. In the present embodiment, the first pixel 201A and the second pixel 202A are adjacent to each other in the Y direction. The first pixel 201A is arranged closer to the connection part 52A than the second pixel 202A. The second pixel 202A is arranged on the side farther from the connection part 52A than the first pixel 201A.

[0025] The first power line 54A includes a first branch line 541 extending in the Y direction from the connection part 52A and a first pixel connection line 542 extending in the Z direction from the first branch line 541 and connected to the first pixel 201A. The second power line 55A includes a second branch line 551 extending in the Y direction from the connection part 52A and a second pixel connection line 552 extending in the Z direction from the second branch line 551 and connected to the second pixel 202A. Here, a part on the connection part 52A side in the second branch line 551 is shared with the first branch line 541. Specifically, the entire first branch line 541 is a shared wiring part 53k shared with a part of the second branch line 551. In this way, a part of the first power line 54A (the first branch line 541) and a part of the second power line 55A (the second branch line 551) are shared and connected to the connection part 52A.

[0026] The signal lines 41 are arranged in sets of one for each pixel block 200. The signal lines 41 connect the selection transistors 27t of each pixel 20 arranged in the first layer 110 and the pixel current source 61 arranged in the second layer 120. The pixel current source 61 is connected to the processing unit 60. The signal lines 41 have main signal lines 411 extending in the Z direction and branch signal lines (not shown) that branch from the main signal lines 411 and are connected to the selection transistors 27t of the respective pixels 20 of the pixel block 200.

[0027] In the present embodiment, the main signal line 411 is arranged at the central portion of the pixel block 200 in the XY plane. That is, in the Y direction, the first pixel 201A is arranged closer to the signal line 41 (main signal line 411) than the second pixel 202A. For this reason, the lengths of the branch signal lines (not shown) connected to the respective pixels 20 within the pixel block 200 are different. With this configuration, the wiring length from the readout circuit (selection transistor 27t) of the first pixel 201A to the processing unit 60 via the signal line 41 and the pixel current source 61 is different from the wiring length from the readout circuit (selection transistor 27t) of the second pixel 202A to the processing unit 60 via the signal line 41 and the pixel current source 61. As a result, the voltage drop amount (so-called IR drop) from the second pixel 202A to the processing unit 60 through the signal line 41 is larger than the voltage drop amount from the first pixel 201A to the processing unit 60 through the signal line 41.

[0028] Also, the wiring lengths of the first power line 54A and the second power line 55A from the connection part 52A are different. Therefore, if the cross-sectional areas of the wirings of the first power line 54A and the second power line 55A are the same, due to the difference in the wiring lengths of the first power line 54A and the second power line 55A, the resistances of the wirings from the connection part 52A to the first pixel 201A and the second pixel 202A via the first power line 54A and the second power line 55A are different. With this configuration, the second power line 55A with a longer wiring length from the connection part 52A has a greater resistance than the first power line 54A. As a result, the voltage drop amount in the first power line 54A from the connection part 52A to the first pixel 201A is smaller than the voltage drop amount in the second power line 55A from the connection part 52A to the second pixel 202A.

[0029] In such a configuration, in order to cancel out the difference in the voltage drop amounts in the first pixel 201A and the second pixel 202A, the first voltage V1 supplied to the first pixel 201A by the first power line 54A and the second voltage V2 supplied to the second pixel 202A by the second power line 55B are adjusted. The first power line 54A supplies the first voltage V1 to the first pixel 201A. The second power line 55A supplies the second voltage V2 to the second pixel 202A. Specifically, the first voltage V1 supplied by the first power line 54A to the first pixel 201A with a smaller voltage drop amount is made lower than the second voltage V2 supplied by the second power line 55B to the second pixel 202A with a larger voltage drop amount.

[0030] Therefore, in this embodiment, the cross-sectional areas of the first power line 54A and the second power line 55A are made different. Specifically, the cross-sectional area of the second power line 55A is made larger than that of the first power line 54A. Here, since a part of the first branch line 541 and the second branch line 551 is the shared wiring portion 53k, in the second power line 55A, the cross-sectional area of the wiring is made different at the portion individually connected from the shared wiring portion 53k to the first pixel 201A and the second pixel 202A. For example, the cross-sectional area of the second pixel connection line 552 is made larger than that of the first pixel connection line 542. In addition to this, the cross-sectional area of the portion other than the shared wiring portion 53k in the second branch line 551 may be made larger than the cross-sectional area of the first pixel connection line 542. As a result, the amount of voltage drop due to the IR drop in the first power line 54A becomes larger than the amount of voltage drop due to the IR drop in the second power line 55A. As a result, the first voltage V1 supplied by the first power line 54A to the first pixel 201A becomes lower than the second voltage V2 supplied by the second power line 55A to the second pixel 202A.

[0031] As described above, according to this embodiment, within the pixel block 200, by making the cross-sectional areas different between the first power line 54A and the second power line 55A having different wiring lengths, the first voltage V1 is supplied to the first pixel 201A and the second voltage V2 is supplied to the second pixel 202A. With this configuration, it is possible to suppress the influence of the IR drop caused by the difference in wiring length among the plurality of pixels 20 in the pixel block 200 and suppress the unevenness generated in the captured image in the imaging device 1A.

[0032] [Second Embodiment] The second embodiment will be described. FIG. 5 is a cross-sectional view showing the configuration of the power supply circuit 50B in the imaging device 1B. FIG. 6 is a plan view showing the arrangement of the power supply circuit 50B with respect to the pixel block 200. In the present embodiment, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. As shown in FIGS. 5 and 6, the imaging device 1B includes a pixel portion 2 and a circuit portion 4B. The circuit portion 4B mainly includes a power supply circuit 50B and a signal line 41. The power supply circuit 50B includes a main power supply line (third power supply line) 51B, a connection portion 52B, a distribution wiring 56B, and a pixel power supply line 53B.

[0033] The main power supply line 51B extends in parallel in the X direction or the Y direction. In the present embodiment, the main power supply line 51B extends in parallel in the X direction. A plurality of main power supply lines 51B are provided at intervals in the Y direction. Each main power supply line 51B is arranged so as to pass through the central portion of a plurality of pixel blocks 200 arranged in the X direction. The main power supply line 51B is arranged on the wiring layer 101b of the first layer 110 on the other side (the second layer 120 side) in the Z direction.

[0034] The connection portion 52B connects the main power supply line 51B and the pixel power supply line 53B. Four connection portions 52B are arranged in each pixel block 200. In each pixel block 200, the four connection portions 52B are arranged at intervals in the X direction. Each connection portion 52B extends in the Z direction, and one end thereof is connected to the main power supply line 51B. The other end of the connection portion 52B is connected to the distribution wiring 56B.

[0035] The distribution wiring 56B is arranged along the XY plane. The distribution wiring 56B is formed in a grid pattern when viewed from the Z direction. The distribution wiring 56B has an X-direction wiring portion 56x extending in the X direction and a Y-direction wiring portion 56y extending in the Y direction. Four X-direction wiring portions 56x are provided at intervals in the Y direction. Four Y-direction wiring portions 56y are provided at intervals in the X direction. These X-direction wiring portions 56x and Y-direction wiring portions 56y are formed so as to intersect at positions overlapping the respective pixel power lines 53B when viewed from the Z direction. The distribution wiring 56B is arranged on one side in the Z direction with respect to the main power line 51B. The distribution wiring 56B distributes and supplies the voltage supplied from the main power line 51B via the connection portion 52B to a plurality of pixel power lines 53B connected to each pixel 20 within the pixel block 200.

[0036] The pixel power line 53B is arranged at the intersection of the X-direction wiring portion 56x and the Y-direction wiring portion 56y that constitute the distribution wiring 56B. The pixel power line 53B extends in the Z direction and connects the intersection of the X-direction wiring portion 56x and the Y-direction wiring portion 56y to the selection transistor 27t of each pixel 20 within the pixel block 200. The pixel power line 53B is arranged on one side in the Z direction with respect to the distribution wiring 56B. In this way, each pixel block 200 has a pixel power line 53B for each pixel 20. These plurality of pixel power lines 53B include a first power line 54B connected to the first pixel 201B and a second power line 55B connected to the second pixel 202B. The first power line 54B and the second power line 55B share the distribution wiring 56B.

[0037] In this embodiment, the first pixel 201B is disposed at the center of the pixel block 200. The second pixel 202B is disposed at the outer peripheral portion of the pixel block 200. The first pixel 201B is disposed closer to the signal line 41 connected to the processing unit 60 than the second pixel 202B. The second pixel 202B is disposed on the side farther from the signal line 41 than the first pixel 201B. As a result, the voltage drop amount from the second pixel 202B to the processing unit 60 through the signal line 41 is larger than the voltage drop amount from the first pixel 201B to the processing unit 60 through the signal line 41.

[0038] Also, the wiring lengths of the first power supply line 54B and the second power supply line 55B from the connection portion 52B are different. The wiring lengths of the first power supply line 54B and the second power supply line 55B to the first pixel 201B and the second pixel 202B through the distribution wiring 56B from the connection portion 52B are different. The wiring length of the first power supply line 54B from the connection portion 52B to the first pixel 201B through the distribution wiring 56B is longer than the wiring length of the second power supply line 55B from the connection portion 52B to the second pixel 202B through the distribution wiring 56B.

[0039] In such a configuration, the first voltage V1 supplied to the first pixel 201B by the first power supply line 54B and the second voltage V2 supplied to the second pixel 202B by the second power supply line 55B are adjusted so as to cancel the difference in the voltage drop amounts in the first pixel 201B and the second pixel 202B. The first power supply line 54B supplies the first voltage V1 to the first pixel 201B. The second power supply line 55B supplies the second voltage V2 to the second pixel 202B. Specifically, the first voltage V1 supplied to the first pixel 201B by the first power supply line 54B is made lower than the second voltage V2 supplied to the second pixel 202B by the second power supply line 55B. For this purpose, the cross-sectional area of the second power supply line 55B is made larger than that of the first power supply line 54B. As a result, the voltage drop amount due to the IR drop in the first power supply line 54B becomes larger than the voltage drop amount due to the IR drop in the second power supply line 55B. As a result, the first voltage V1 supplied to the first pixel 201B by the first power supply line 54B becomes lower than the second voltage V2 supplied to the second pixel 202B by the second power supply line 55B.

[0040] As described above, according to the present embodiment, within the pixel block 200, the first power line 54B and the second power line 55B having different wiring lengths from the connection portion 52B have different cross-sectional areas, so that the first voltage V1 is supplied to the first pixel 201B and the second voltage V2 is supplied to the second pixel 202B. With this configuration, it is possible to suppress the influence of the IR drop caused by the difference in wiring length among the plurality of pixels 20 in the pixel block 200 and suppress the unevenness occurring in the captured image in the imaging device 1B.

[0041] [Third Embodiment] The third embodiment will be described. FIG. 7 is a plan view showing the arrangement of the power supply circuit 50C with respect to the pixel block 200. In the present embodiment, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. As shown in FIG. 7, the imaging device 1C includes a pixel portion 2 and a circuit portion 4C. The power supply circuit 50C of the circuit portion 4C includes a main power line (third power line) 51C, a connection portion 52C, a distribution wiring 56C, and a pixel power line 53C.

[0042] The main power line 51C extends in parallel in the X direction or the Y direction. In the present embodiment, the main power line 51C extends in parallel in the X direction. A plurality of main power lines 51C are provided at intervals in the Y direction. Each main power line 51C is arranged so as to pass between a plurality of adjacent pixel blocks 200 in the Y direction. The connection portion 52C connects the main power line 51C and the pixel power line 53C. Each connection portion 52C extends in the Z direction, and one end thereof is connected to the main power line 51C. The other end of the connection portion 52C is connected to the distribution wiring 56C.

[0043] The distribution wiring 56C is arranged along the XY plane. The distribution wiring 56C is formed in a grid pattern when viewed from the Z direction. In the present embodiment, the distribution wiring 56C is provided across a plurality of adjacent pixel blocks 200 in the Y direction. The distribution wiring 56C distributes and supplies the voltage supplied from the main power line 51C via the connection portion 52C to half of the pixels 20 in each of the plurality of adjacent pixel blocks 200 in the Y direction.

[0044] The pixel power supply line 53C is arranged at the intersection of the X-direction wiring part 56x and the Y-direction wiring part 56y that constitute the distribution wiring 56C. The pixel power supply line 53C extends in the Z direction and connects the intersection of the X-direction wiring part 56x and the Y-direction wiring part 56y to the selection transistor 27t of each pixel 20 within the pixel block 200. In this way, a pixel power supply line 53C is arranged for each pixel 20 in each pixel block 200. These multiple pixel power supply lines 53C include a first power supply line 54C connected to the first pixel 201C and a second power supply line 55C connected to the second pixel 202C. The first power supply line 54C and the second power supply line 55C share the distribution wiring 56C.

[0045] In this embodiment, the first pixel 201C is arranged at the central part of the pixel block 200. The second pixel 202C is arranged at the outer peripheral part of the pixel block 200. The first pixel 201C is arranged closer to the signal line 41 connected to the processing unit 60 than the second pixel 202C. The second pixel 202C is arranged on the side farther from the signal line 41 than the first pixel 201C. For this reason, the voltage drop amount from the second pixel 202C to the processing unit 60 through the signal line 41 is larger than the voltage drop amount from the first pixel 201C to the processing unit 60 through the signal line 41.

[0046] In such a configuration, in order to cancel out the difference in the voltage drop amount between the first pixel 201C and the second pixel 202C, the first voltage V1 supplied to the first pixel 201C by the first power supply line 54C and the second voltage V2 supplied to the second pixel 202C by the second power supply line 55C are adjusted. The first power supply line 54C supplies the first voltage V1 to the first pixel 201C. The second power supply line 55C supplies the second voltage V2 to the second pixel 202C. Specifically, the first voltage V1 supplied by the first power supply line 54C to the first pixel 201C is made lower than the second voltage V2 supplied by the second power supply line 55C to the second pixel 202C.

[0047] The first power supply line 54C and the second power supply line 55C have different wiring lengths from the connection part 52C. The first power supply line 54C and the second power supply line 55C have different wiring lengths from the connection part 52C to the first pixel 201C and the second pixel 202C via the distribution wiring 56C. The wiring length of the first power supply line 54C from the connection part 52C to the first pixel 201C via the distribution wiring 56C is longer than the wiring length of the second power supply line 55C from the connection part 52C to the second pixel 202C via the distribution wiring 56C.

[0048] Also, the cross-sectional areas of the wirings of the first power supply line 54C and the second power supply line 55C are made different. Specifically, the cross-sectional area of the second power supply line 55C is made larger than that of the first power supply line 54C. As a result, the amount of voltage drop due to the IR drop in the first power supply line 54C becomes larger than the amount of voltage drop due to the IR drop in the second power supply line 55C. As a result, the first voltage V1 supplied by the first power supply line 54C to the first pixel 201C becomes lower than the second voltage V2 supplied by the second power supply line 55C to the second pixel 202C.

[0049] Thus, according to the present embodiment, within the pixel block 200, by making the cross-sectional areas different between the first power supply line 54C and the second power supply line 55C, which have different wiring lengths from the connection part 52C to the signal line 41, it is possible to suppress the influence of the IR drop caused by the difference in wiring length among the plurality of pixels 20 in the pixel block 200, and suppress the unevenness generated in the captured image in the imaging device 1C.

[0050] [Fourth Embodiment] The fourth embodiment will be described. FIG. 8 is a plan view showing the arrangement of the power supply circuit 50D with respect to the pixel block 200. In the present embodiment, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. As shown in FIG. 8, the imaging device 1D includes a pixel portion 2 and a circuit portion 4D. The circuit portion 4D mainly includes a power supply circuit 50D and a signal line 41. The power supply circuit 50D includes a main power supply line (third power supply line) 51D, a connection part 52D, a distribution wiring 56D, and a pixel power supply line 53D.

[0051] The main power line 51D extends in parallel in the X direction or the Y direction. In this embodiment, the main power line 51D extends in parallel in the X direction. A plurality of main power lines 51D are provided at intervals in the Y direction. Each main power line 51D is arranged so as to pass between a plurality of adjacent pixel blocks 200 in the Y direction. The connection portion 52D connects the main power line 51D and the pixel power line 53D. Four connection portions 52D are arranged for each distribution wiring 56D. In each pixel block 200, the four connection portions 52D are arranged at intervals in the X direction. Each connection portion 52D extends in the Z direction, and one end thereof is connected to the main power line 51D. The other end of the connection portion 52D is connected to the distribution wiring 56D.

[0052] The distribution wiring 56D is arranged along the XY plane. The distribution wiring 56D is formed in a grid pattern when viewed from the Z direction. In this embodiment, the distribution wiring 56D is provided across four adjacent pixel blocks 200 in the X direction and the Y direction. That is, distribution wirings 56D are arranged at the four corners of each pixel block 200, respectively. The center of the distribution wiring 56D is arranged at the four corners of the pixel block 200. The distribution wiring 56D distributes and supplies the voltage supplied from the main power line 51D via the connection portion 52D to four adjacent pixel blocks 200 in the X direction and the Y direction, with 1 / 4 of the pixels 20 in each pixel block 200.

[0053] The pixel power line 53D extends in the Z direction and connects the distribution wiring 56D and each pixel 20 in the pixel block 200. In this way, a pixel power line 53D is arranged for each pixel 20 in each pixel block 200. The plurality of pixel power lines 53D include a first power line 54D connected to the first pixel 201D and a second power line 55D connected to the second pixel 202D. The first power line 54D and the second power line 55D share the distribution wiring 56D.

[0054] In this embodiment, the first pixel 201D is disposed at the center of the pixel block 200. The second pixel 202D is disposed at the outer peripheral portion of the pixel block 200. The first pixel 201D is disposed closer to the signal line 41 connected to the processing unit 60 than the second pixel 202D. The second pixel 202D is disposed on the side separated from the signal line 41 more than the first pixel 201D. In such a configuration, for this reason, the voltage drop amount from the second pixel 202D to the processing unit 60 through the signal line 41 is larger than the voltage drop amount from the first pixel 201D to the processing unit 60 through the signal line 41.

[0055] In such a configuration, the first voltage V1 supplied to the first pixel 201D by the first power supply line 54D and the second voltage V2 supplied to the second pixel 202D by the second power supply line 55D are adjusted so as to cancel the difference in the voltage drop amount between the first pixel 201D and the second pixel 202D. For this reason, the first power supply line 54D supplies the first voltage V1 to the first pixel 201D. The second power supply line 55D supplies the second voltage V2 to the second pixel 202D. Specifically, the first voltage V1 supplied by the first power supply line 54D to the first pixel 201D is made lower than the second voltage V2 supplied by the second power supply line 55D to the second pixel 202D.

[0056] The wiring lengths of the first power supply line 54D and the second power supply line 55D from the connection portion 52D are different. In the first power supply line 54D and the second power supply line 55D, the wiring lengths from the connection portion 52D to the first pixel 201D and the second pixel 202D via the distribution wiring 56D are different. The wiring length of the first power supply line 54D from the connection portion 52D to the first pixel 201D via the distribution wiring 56D is longer than the wiring length of the second power supply line 55D from the connection portion 52D to the second pixel 202D via the distribution wiring 56D.

[0057] Also, the cross-sectional areas of the first power line 54D and the second power line 55D are made different. Specifically, the cross-sectional area of the second power line 55D is made larger than that of the first power line 54D. As a result, the voltage drop amount due to the IR drop in the first power line 54D becomes larger than the voltage drop amount due to the IR drop in the second power line 55D. As a result, the first voltage V1 supplied by the first power line 54D to the first pixel 201D becomes lower than the second voltage V2 supplied by the second power line 55D to the second pixel 202D.

[0058] Thus, according to the present embodiment, within the pixel block 200, the cross-sectional areas of the first power line 54D and the second power line 55D, whose wiring lengths from the connection portion 52D to the signal line 41 are different, are made different, so that the first voltage V1 is supplied to the first pixel 201D and the second voltage V2 is supplied to the second pixel 202D. With this configuration, it is possible to suppress the influence of the IR drop caused by the difference in wiring length among the plurality of pixels 20 in the pixel block 200 and suppress the unevenness occurring in the captured image in the imaging device 1D.

[0059] [Fifth Embodiment] The fifth embodiment will be described. FIG. 9 is a plan view showing the arrangement of the power supply circuit 50E with respect to the pixel block 200. FIG. 10 is a cross-sectional view showing the configuration of the power supply circuit 50E in the imaging device 1E. In the present embodiment, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. As shown in FIGS. 9 and 10, the imaging device 1E includes a pixel portion 2 and a circuit portion 4E. The circuit portion 4E mainly includes a power supply circuit 50E and a signal line 41. The power supply circuit 50E includes a main power line (third power line) 51E, a connection portion 52E, a distribution wiring 56E, and a pixel power line 53E.

[0060] The main power supply line 51E extends parallel to the X direction or the Y direction. In this embodiment, the main power supply line 51E extends parallel to the X direction. A plurality of main power supply lines 51E are provided at intervals in the Y direction. Each main power supply line 51E is arranged so as to pass between a plurality of adjacent pixel blocks 200 in the Y direction. The main power supply line 51E is arranged on the other side (the second layer 120 side) in the Z direction in the wiring layer 101b of the first layer 110.

[0061] The connection part 52E connects the main power supply line 51E and the pixel power supply line 53E. The connection part 52E is arranged at the intersection of four pixel blocks 200 adjacent to each other in the X direction and the Y direction. The connection part 52E extends in the Z direction, and one end thereof is connected to the main power supply line 51E. The other end of the connection part 52E is connected to the distribution wiring 56E.

[0062] The distribution wiring 56E is arranged along the XY plane. The distribution wiring 56E has an X-direction wiring part 56x extending in the X direction and a Y-direction wiring part 56y extending in the Y direction. The X-direction wiring part 56x is arranged so as to overlap the main power supply line 51E when viewed from the Z direction. The X-direction wiring part 56x is arranged so as to pass between two adjacent pixel blocks 200 in the Y direction. The X-direction wiring part 56x extends from the other end of the connection part 52E to both sides in the X direction and is arranged so as to straddle both of a plurality of adjacent pixel blocks 200 in the X direction. Four Y-direction wiring parts 56y are provided at intervals in the X direction. Each Y-direction wiring part 56y extends from the X-direction wiring part 56x to both sides in the Y direction and straddles both of a plurality of adjacent pixel blocks 200 in the Y direction. The distribution wiring 56E is arranged on one side in the Z direction with respect to the main power supply line 51E.

[0063] In the present embodiment, the distribution wiring 56E is provided across four pixel blocks 200 adjacent in the X direction and the Y direction. In other words, the distribution wiring 56E is disposed at each of the four corners of each pixel block 200. The center of each distribution wiring 56E is disposed at the intersection of the four pixel blocks 200. The distribution wiring 56E distributes and supplies the voltage supplied from the main power line 51E via the connection portion 52E to the four pixel blocks 200 adjacent in the X direction and the Y direction, to the pixels 20, each being one-fourth of each pixel block 200.

[0064] The pixel power line 53E is disposed at a position corresponding to the selection transistor 27t of each pixel 20. One end of the pixel power line 53E is connected to the Y-direction wiring portion 56y of the distribution wiring 56E. The pixel power line 53E extends in the Z direction and is connected to the selection transistor 27t of each pixel 20. The pixel power line 53E is disposed on one side in the Z direction with respect to the distribution wiring 56E. In this way, each pixel block 200 is provided with a pixel power line 53E for each pixel 20. These plurality of pixel power lines 53E include a first power line 54E connected to the first pixel 201E and a second power line 55E connected to the second pixel 202E. The first power line 54E and the second power line 55E share the distribution wiring 56E.

[0065] In the present embodiment, the first pixel 201E is disposed at the central portion of the pixel block 200. The second pixel 202E is disposed at the outer peripheral portion of the pixel block 200. The first pixel 201E is disposed closer to the signal line 41 connected to the processing unit 60 than the second pixel 202E. The second pixel 202E is disposed on the side farther from the signal line 41 than the first pixel 201E. For this reason, the voltage drop amount from the second pixel 202E to the processing unit 60 through the signal line 41 is larger than the voltage drop amount from the first pixel 201E to the processing unit 60 through the signal line 41.

[0066] In such a configuration, the first voltage V1 supplied to the first pixel 201E through the first power line 54E and the second voltage V2 supplied to the second pixel 202E through the second power line 55E are adjusted so as to cancel out the difference in the voltage drop amounts between the first pixel 201E and the second pixel 202E. For this purpose, the first power line 54E supplies the first voltage V1 to the first pixel 201E. The second power line 55E supplies the second voltage V2 to the second pixel 202E. Specifically, the first voltage V1 supplied by the first power line 54E to the first pixel 201E is made lower than the second voltage V2 supplied by the second power line 55E to the second pixel 202E.

[0067] The first power line 54E and the second power line 55E have different wiring lengths from the connection portion 52E. In the first power line 54E and the second power line 55E, the wiring lengths from the connection portion 52E to the first pixel 201E and the second pixel 202E via the distribution wiring 56E are different. The wiring length of the first power line 54E from the connection portion 52E to the first pixel 201E via the distribution wiring 56E is longer than the wiring length of the second power line 55E from the connection portion 52E to the second pixel 202E via the distribution wiring 56E. For this reason, the voltage drop amount due to the IR drop in the distribution wiring 56E from the connection portion 52E to the second pixel 202E and the second power line 55E is smaller than the voltage drop amount due to the IR drop in the distribution wiring 56E from the connection portion 52E to the first pixel 201E and the first power line 54E. With this configuration, in this imaging device 1E, the first voltage V1 supplied by the first power line 54E to the first pixel 201E is lower than the second voltage V2 supplied by the second power line 55E to the second pixel 202E.

[0068] As described above, according to the present embodiment, the wiring length of the second power line 55E that supplies voltage to the second pixel 202E located on the outer peripheral portion of the pixel block 200 is made shorter than the wiring length of the first power line 54E that supplies voltage to the first pixel 201E located on the inner peripheral portion of the pixel block 200. With this configuration, it is possible to suppress the influence of the IR drop caused by the difference in the wiring length among the plurality of pixels 20 in the pixel block 200, and to suppress unevenness in the captured image in the imaging device 1E.

[0069] In addition, in the fifth embodiment, similar to the first to fourth embodiments, the cross-sectional areas of the wirings may be made different between the first power line 54E and the second power line 55E. Specifically, the cross-sectional area of the second power line 55E connected to the second pixel 202E may be made larger than that of the first power line 54E connected to the first pixel 201E.

[0070] [Sixth Embodiment] The sixth embodiment will be described. FIG. 11 is a plan view showing the arrangement of the power supply circuit 50F with respect to the pixel block 200. In the present embodiment, the same components as those in the above-described embodiments are denoted by the same reference numerals, and the description thereof is omitted or simplified. As shown in FIG. 11, the imaging device 1F includes a pixel portion 2 and a circuit portion 4F. The circuit portion 4F mainly includes a power supply circuit 50F and a signal line 41. The power supply circuit 50F includes a main power line (third power line) 51F, a connection portion 52F, a distribution wiring 56F, and a pixel power line 53F.

[0071] The main power line 51F extends in parallel in the X direction or the Y direction. In the present embodiment, the main power line 51F extends in parallel in the X direction. A plurality of main power lines 51F are provided at intervals in the Y direction. Each main power line 51F is arranged so as to pass between a plurality of adjacent pixel blocks 200 in the Y direction.

[0072] The connection portion 52F connects the main power line 51F and the pixel power line 53F. The connection portion 52F is arranged between two pixel blocks 200 adjacent to each other in the Y direction. When viewed from each pixel block 200, two connection portions 52F are arranged on both sides of the pixel block 200 in the Y direction. Each connection portion 52F is arranged at the center portion of the pixel block 200 in the X direction. Each connection portion 52F extends in the Z direction, and one end thereof is connected to the main power line 51F. The other end of the connection portion 52F is connected to the distribution wiring 56F.

[0073] The distribution wiring 56F is arranged along the XY plane. The distribution wiring 56F has an X-direction wiring portion 56x extending in the X direction and a Y-direction wiring portion 56y extending in the Y direction. The X-direction wiring portion 56x is arranged so as to overlap the main power line 51F when viewed from the Z direction. The X-direction wiring portion 56x extends from the other end of the connection portion 52F to both sides in the X direction. Four Y-direction wiring portions 56y are provided at intervals in the X direction. Each Y-direction wiring portion 56y extends from the X-direction wiring portion 56x to both sides in the Y direction and straddles both of a plurality of adjacent pixel blocks 200 in the Y direction.

[0074] In this embodiment, the distribution wiring 56F is provided so as to straddle two adjacent pixel blocks 200 in the Y direction. The center of the distribution wiring 56F is arranged between two adjacent pixel blocks 200 in the Y direction. The distribution wiring 56F distributes and supplies the voltage supplied from the main power line 51F via the connection portion 52F to two adjacent pixel blocks 200 in the Y direction, with each pixel block 200 receiving half of the pixels 20, i.e., 1 / 2 of the pixels 20 in each pixel block 200.

[0075] The pixel power line 53F is arranged at a position corresponding to the selection transistor 27t of each pixel 20. One end of the pixel power line 53F is connected to the Y-direction wiring portion 56y of the distribution wiring 56F. The pixel power line 53F extends in the Z direction and is connected to the selection transistor 27t of each pixel 20. The pixel power line 53F is arranged on one side in the Z direction with respect to the distribution wiring 56F. In this way, each pixel block 200 has a pixel power line 53F for each pixel 20. These multiple pixel power lines 53F include a first power line 54F connected to the first pixel 201F and a second power line 55F connected to the second pixel 202F. The first power line 54F and the second power line 55F share the distribution wiring 56F.

[0076] In this embodiment, the first pixel 201F is disposed at the central portion in the Y direction of the pixel block 200. The second pixel 202F is disposed at the outer peripheral portion in the Y direction of the pixel block 200. The first pixel 201F is disposed closer to the signal line 41 connected to the processing unit 60 than the second pixel 202F in the Y direction. The second pixel 202F is disposed on the side farther from the signal line 41 than the first pixel 201F in the Y direction. As a result, the voltage drop amount from the second pixel 202F to the processing unit 60 through the signal line 41 is larger than the voltage drop amount from the first pixel 201F to the processing unit 60 through the signal line 41.

[0077] In such a configuration, the first voltage V1 supplied to the first pixel 201F by the first power supply line 54F and the second voltage V2 supplied to the second pixel 202F by the second power supply line 55F are adjusted so as to cancel the difference in the voltage drop amounts between the first pixel 201F and the second pixel 202F. For this reason, the first power supply line 54F supplies the first voltage V1 to the first pixel 201F. The second power supply line 55F supplies the second voltage V2 to the second pixel 202F. Specifically, the first voltage V1 supplied by the first power supply line 54F to the first pixel 201F is made lower than the second voltage V2 supplied by the second power supply line 55F to the second pixel 202F.

[0078] The wiring lengths from the connection portion 52F to the first pixel 201F and the second pixel 202F via the respective Y-direction wiring portions 56y of the distribution wiring 56F are different between the first power supply line 54F and the second power supply line 55F. The wiring length from the connection portion 52F to the first pixel 201F via the Y-direction wiring portion 56y in the first power supply line 54F is longer than the wiring length from the connection portion 52F to the second pixel 202F via the Y-direction wiring portion 56y in the second power supply line 55F. For this reason, in each Y-direction wiring portion 56y, the voltage drop amount due to the IR drop in the second power supply line 55F is smaller than the voltage drop amount due to the IR drop in the first power supply line 54F. With this configuration, the first voltage V1 supplied by the first power supply line 54F to the first pixel 201F is made lower than the second voltage V2 supplied by the second power supply line 55F to the second pixel 202F.

[0079] As described above, according to this embodiment, in each Y-direction wiring portion 56y, the wiring length of the second power supply line 55F that supplies voltage to the second pixel 202F located at the outer peripheral portion of the pixel block 200 is made shorter than the wiring length of the first power supply line 54F that supplies voltage to the first pixel 201F located at the inner peripheral portion of the pixel block 200. With this configuration, it is possible to suppress the influence of IR drop caused by the difference in wiring length among the plurality of pixels 20 in the pixel block 200, and suppress unevenness in the captured image in the imaging device 1F.

[0080] In addition, in the above-described sixth embodiment, similar to the first to fifth embodiments, the cross-sectional areas of the wirings may be made different between the first power supply line 54F and the second power supply line 55F. Specifically, the cross-sectional area of the second power supply line 55F connected to the second pixel 202F may be made larger than the cross-sectional area of the first power supply line 54F connected to the first pixel 201F.

[0081] [Seventh Embodiment] The seventh embodiment will be described. FIG. 12 is a plan view showing the arrangement of the power supply circuit 50G with respect to the pixel block 200. In this embodiment, the same components as those in the above-described embodiments are denoted by the same reference numerals, and the description thereof is omitted or simplified. As shown in FIG. 12, the imaging device 1G includes a pixel portion 2 and a circuit portion 4G. The circuit portion 4G mainly includes a power supply circuit 50G and a signal line 41. The power supply circuit 50G includes a main power supply line (third power supply line) 51G, a connection portion 52G, a distribution wiring 56G, and a pixel power supply line 53G.

[0082] The main power line 51G extends parallel to the X direction or the Y direction. In this embodiment, the main power line 51G extends parallel to the X direction. A plurality of main power lines 51G are provided at intervals in the Y direction. Each main power line 51G is arranged so as to pass through the central portion of a plurality of pixel blocks 200 arranged in the X direction. The connection portion 52G connects the main power line 51G and the pixel power line 53G. The connection portion 52G is arranged at the central portion of each pixel block 200. The connection portion 52G extends in the Z direction, and one end thereof is connected to the main power line 51G. The other end of the connection portion 52G is connected to the distribution wiring 56G.

[0083] The distribution wiring 56G is arranged along the XY plane. The distribution wiring 56G has an X-direction wiring portion 56x extending in the X direction and a Y-direction wiring portion 56y extending in the Y direction. The X-direction wiring portion 56x is arranged so as to overlap the main power line 51G when viewed from the Z direction. The X-direction wiring portion 56x extends from the other end of the connection portion 52G to both sides in the X direction. Four Y-direction wiring portions 56y are provided at intervals in the X direction. Each Y-direction wiring portion 56y extends from the X-direction wiring portion 56x to both sides in the Y direction.

[0084] The pixel power line 53G is arranged at a position corresponding to the selection transistor 27t of each pixel 20. One end of the pixel power line 53G is connected to the Y-direction wiring portion 56y of the distribution wiring 56G. The pixel power line 53G extends in the Z direction and is connected to the selection transistor 27t of each pixel 20. The pixel power line 53G is arranged on one side in the Z direction with respect to the distribution wiring 56G. In this way, each pixel block 200 is provided with a pixel power line 53G for each pixel 20. These plurality of pixel power lines 53G include a first power line 54G connected to the first pixel 201G and a second power line 55G connected to the second pixel 202G. The first power line 54G and the second power line 55G share the distribution wiring 56G.

[0085] In this embodiment, the first pixel 201G is disposed at the center of the pixel block 200. The second pixel 202G is disposed at the outer periphery of the pixel block 200. The first pixel 201G is disposed closer to the signal line 41 connected to the processing unit 60 than the second pixel 202G. The second pixel 202G is disposed on the side farther from the signal line 41 than the first pixel 201G. Therefore, the voltage drop amount from the second pixel 202G to the processing unit 60 through the signal line 41 is larger than the voltage drop amount from the first pixel 201G to the processing unit 60 through the signal line 41.

[0086] Also, the wiring lengths of the first power supply line 54G and the second power supply line 55G from the connection part 52G are different. The voltage drop amount in the first power supply line 54G from the connection part 52G to the first pixel 201G is smaller than the voltage drop amount in the second power supply line 55G from the connection part 52G to the second pixel 202G.

[0087] In such a configuration, the first voltage V1 supplied to the first pixel 201G by the first power supply line 54G and the second voltage V2 supplied to the second pixel 202G by the second power supply line 55G are adjusted so as to cancel the difference in the voltage drop amounts between the first pixel 201G and the second pixel 202G. Therefore, the first power supply line 54G supplies the first voltage V1 to the first pixel 201G. The second power supply line 55G supplies the second voltage V2 to the second pixel 202G. Specifically, the first voltage V1 supplied by the first power supply line 54G to the first pixel 201G is made lower than the second voltage V2 supplied by the second power supply line 55G to the second pixel 202G. For this reason, the cross-sectional area of the second power supply line 55G is made larger than that of the first power supply line 54G. As a result, the voltage drop amount due to the IR drop in the first power supply line 54G becomes larger than the voltage drop amount due to the IR drop in the second power supply line 55G. As a result, the first voltage V1 supplied by the first power supply line 54G to the first pixel 201G becomes lower than the second voltage V2 supplied by the second power supply line 55G to the second pixel 202G.

[0088] As described above, according to the present embodiment, the cross-sectional area of the first power supply line 54G that supplies voltage to the first pixel 201G located in the inner peripheral portion of the pixel block 200 is made shorter than the cross-sectional area of the second power supply line 55G that supplies voltage to the second pixel 202G located in the outer peripheral portion of the pixel block 200. With this configuration, it is possible to suppress the influence of IR drop caused by the difference in wiring length among the plurality of pixels 20 in the pixel block 200, and to suppress unevenness in the captured image in the imaging device 1G.

[0089] [Eighth Embodiment] The eighth embodiment will be described. FIG. 13 is a plan view showing the arrangement of the power supply circuit 50H with respect to the pixel block 200. In the present embodiment, the same components as those in the above-described embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. As shown in FIG. 13, the imaging device 1H includes a pixel portion 2 and a circuit portion 4H. The circuit portion 4H mainly includes a power supply circuit 50H and signal lines 41. The power supply circuit 50H includes a main power supply line (third power supply line) 51H, a connection portion 52H, a distribution wiring 56H, and a pixel power supply line 53H.

[0090] The main power supply line 51H extends in parallel in the X direction or the Y direction. In the present embodiment, the main power supply line 51H extends in parallel in the X direction. A plurality of main power supply lines 51H are provided at intervals in the Y direction. Each main power supply line 51H is arranged so as to pass through the central portion of a plurality of pixel blocks 200 arranged in the X direction. The connection portion 52H connects the main power supply line 51H and the pixel power supply line 53H. The connection portion 52H is arranged between a plurality of pixel blocks 200 adjacent to each other in the X direction. The connection portion 52H extends in the Z direction, and one end thereof is connected to the main power supply line 51H. The other end of the connection portion 52H is connected to the distribution wiring 56H.

[0091] The distribution wiring 56H is arranged along the XY plane. The distribution wiring 56H has an X-direction wiring portion 56x extending in the X direction and a Y-direction wiring portion 56y extending in the Y direction. The X-direction wiring portion 56x is arranged so as to overlap the main power supply line 51H when viewed from the Z direction. The X-direction wiring portion 56x extends from the other end of the connection portion 52H to both sides in the X direction. The X-direction wiring portion 56x extends so as to straddle both of a plurality of adjacent pixel blocks 200 in the X direction. Four Y-direction wiring portions 56y are provided at intervals in the X direction. Each Y-direction wiring portion 56y extends from the X-direction wiring portion 56x to both sides in the Y direction.

[0092] In this way, in the present embodiment, the distribution wiring 56H is provided so as to straddle two adjacent pixel blocks 200 in the X direction. The center of the distribution wiring 56H is arranged between two adjacent pixel blocks 200 in the X direction. The distribution wiring 56H distributes and supplies the voltage supplied from the main power supply line 51H via the connection portion 52H to two adjacent pixel blocks 200 in the X direction, supplying half of each pixel block 200 to the pixels 20.

[0093] The pixel power supply line 53H is arranged at a position corresponding to the selection transistor 27t of each pixel 20. One end of the pixel power supply line 53H is connected to the Y-direction wiring portion 56y of the distribution wiring 56H. The pixel power supply line 53H extends in the Z direction and is connected to the selection transistor 27t of each pixel 20. The pixel power supply line 53H is arranged on one side in the Z direction with respect to the distribution wiring 56H. In this way, each pixel block 200 is provided with a pixel power supply line 53H for each pixel 20. These plurality of pixel power supply lines 53H include a first power supply line 54H connected to the first pixel 201H and a second power supply line 55H connected to the second pixel 202H. The first power supply line 54H and the second power supply line 55H share the distribution wiring 56H.

[0094] In this embodiment, the first pixel 201H is disposed at the center of the pixel block 200. The second pixel 202H is disposed at the outer periphery of the pixel block 200. The first pixel 201H is disposed closer to the signal line 41 connected to the processing unit 60 than the second pixel 202H. The second pixel 202H is disposed on the side separated from the signal line 41 farther than the first pixel 201H. Therefore, the voltage drop amount from the second pixel 202H to the processing unit 60 through the signal line 41 is larger than the voltage drop amount from the first pixel 201H to the processing unit 60 through the signal line 41.

[0095] Also, the wiring lengths of the first power supply line 54H and the second power supply line 55H from the connection part 52H are different. The voltage drop amount in the first power supply line 54H from the connection part 52H to the first pixel 201H is smaller than the voltage drop amount in the second power supply line 55H from the connection part 52H to the second pixel 202H.

[0096] In such a configuration, the first voltage V1 supplied to the first pixel 201H by the first power supply line 54H and the second voltage V2 supplied to the second pixel 202H by the second power supply line 55H are adjusted so as to cancel the difference in the voltage drop amounts in the first pixel 201H and the second pixel 202H. For this reason, the first power supply line 54H supplies the first voltage V1 to the first pixel 201H. The second power supply line 55H supplies the second voltage V2 to the second pixel 202H. Specifically, the first voltage V1 supplied to the first pixel 201H by the first power supply line 54H is made lower than the second voltage V2 supplied to the second pixel 202H by the second power supply line 55H. For this reason, the cross-sectional area of the second power supply line 55H is made larger than that of the first power supply line 54H. As a result, the voltage drop amount due to the IR drop in the first power supply line 54H becomes larger than the voltage drop amount due to the IR drop in the second power supply line 55H. As a result, the first voltage V1 supplied to the first pixel 201H by the first power supply line 54H becomes lower than the second voltage V2 supplied to the second pixel 202H by the second power supply line 55H.

[0097] Thus, according to this embodiment, the cross-sectional area of the first power line 54H that supplies voltage to the first pixel 201H located in the inner peripheral portion of the pixel block 200 is made shorter than the cross-sectional area of the second power line 55H that supplies voltage to the second pixel 202H located in the outer peripheral portion of the pixel block 200. With this configuration, it is possible to suppress the influence of IR drop caused by the difference in wiring length among the plurality of pixels 20 in the pixel block 200, and suppress unevenness in the captured image in the imaging device 1H.

[0098] [Embodiment 9] Embodiment 9 will be described. FIG. 14 is a plan view showing the arrangement of the power supply circuit 50I with respect to the pixel block 200. FIG. 15 is a cross-sectional view showing the configuration of the power supply circuit 50IE in the imaging device 1I. In this embodiment, the same components as those in the above-described embodiments are denoted by the same reference numerals, and the description thereof is omitted or simplified. As shown in FIGS. 14 and 15, the imaging device 1I includes a pixel portion 2 and a circuit portion 4I.

[0099] The circuit portion 4I mainly includes a power supply circuit 50I and signal lines 41. The power supply circuit 50I includes a main power line (third power line) 51I and a pixel power line 53I. The main power line 51I extends in parallel in the X direction or the Y direction. In this embodiment, the main power line 51I extends in parallel in the X direction. A plurality of main power lines 51I are provided at intervals in the Y direction. Each main power line 51I is arranged so as to straddle a plurality of pixels 20 arranged in the X direction. The main power line 51I is arranged on the wiring layer 101b of the first layer 110 on the farthest side in the Z direction (the second layer 120 side).

[0100] The pixel power line 53I is arranged at a position corresponding to each pixel 20 when viewed from the Z direction. The pixel power line 53I extends in the Z direction and connects the main power line 51I and the selection transistor 27t of each pixel 20. The pixel power line 53I is arranged on one side in the Z direction with respect to the connection portion 52I. In this way, each pixel block 200 has a pixel power line 53I for each pixel 20. These plurality of pixel power lines 53I include a first power line 54I connected to the first pixel 201I and a second power line 55I connected to the second pixel 202I. In the present embodiment, the first pixel 201I is arranged at the central portion of the pixel block 200. The second pixel 202I is arranged at the outer peripheral portion of the pixel block 200. The first pixel 201I is arranged closer to the signal line 41 than the second pixel 202I. The second pixel 202I is arranged on the side separated from the signal line 41 more than the first pixel 201I.

[0101] In such a configuration, the first power line 54I supplies the first voltage V1 to the first pixel 201I. The second power line 55I supplies the second voltage V2 to the second pixel 202I. Specifically, the first voltage V1 supplied by the first power line 54I to the first pixel 201I is made lower than the second voltage V2 supplied by the second power line 55I to the second pixel 202I. For this, the cross-sectional areas of the wirings of the first power line 54I and the second power line 55I are made different. Specifically, the cross-sectional area of the second power line 55I is made larger than that of the first power line 54I.

[0102] In this way, according to the present embodiment, within the pixel block 200, by making the cross-sectional areas different between the first power line 54I and the second power line 55I having different wiring lengths to the signal line 41, the first voltage V1 is supplied to the first pixel 201I and the second voltage V2 is supplied to the second pixel 202I. With this configuration, it is possible to suppress the influence of the IR drop caused by the difference in wiring length among the plurality of pixels 20 in the pixel block 200 and suppress the unevenness occurring in the captured image in the imaging device 1I.

[0103] Although the embodiments have been described above, the technical scope of the present invention is not limited to the aspects described in the above embodiments and the like. One or more of the requirements described in the above embodiments and the like may be omitted. Further, the requirements described in the above embodiments and the like can be combined as appropriate. Also, to the extent permitted by law, the disclosures of all the documents cited in this specification are incorporated by reference and made part of the description herein.

Explanation of Reference Numerals

[0104] 1A to 1I... imaging elements, 40... processing unit, 51A to 51I... main power supply lines (third power supply lines), 52A to 52I... connection parts, 54A to 54I... first power supply lines, 55A to 55I... second power supply lines, 110... first layer, 120... second layer, 200... pixel block, 201A to 201I... first pixels, 202A to 202I... second pixels, V1... first voltage, V2... second voltage

Claims

Claim 1 A plurality of pixels arranged side by side in a first direction and a second direction intersecting the first direction, the plurality of pixels including a first pixel and a second pixel, A first power supply line connected to the first pixel and supplying a first voltage, A second power supply line connected to the second pixel and supplying a second voltage, An imaging device comprising the above.

Images