Avalanche photodiode array

Abstract

To provide an APD (avalanche photodiode) array capable of reducing a dead area by a simple configuration and of achieving detection of a desired electromagnetic wave or a particle beam.SOLUTION: In an APD array 1, a plurality of APDs 15 include a first semiconductor layer 21, a plurality of second semiconductor layers 22, and a multiplication layer 40. The first semiconductor layer 21 is provided at a second surface 12 side from a semiconductor region 20. The plurality of second semiconductor layers 22 are arranged along a first surface 11. The multiplication layer 40 is provided in the semiconductor region 20, between the plurality of second semiconductor layers 22 and the first semiconductor layer 21 in a direction orthogonal to the first surface 11. Each of a third semiconductor layer 23 and a fourth semiconductor layer 24 of the multiplication layer 40 are provided continuously so as to be overlapped with the plurality of second semiconductor layers 22 when seen from the direction orthogonal to the first surface 11. The third semiconductor layer 23 is provided at the first surface 11 side from the fourth semiconductor layer 24.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an avalanche photodiode array.

Background Art

[0002] An avalanche photodiode array having a plurality of avalanche photodiodes is known (for example, Patent Document 1). In the avalanche photodiode array described in Patent Document 1, a plurality of avalanche photodiodes are arranged on a semiconductor substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In an optical detection device using an avalanche photodiode array, there was a dead area between adjacent avalanche photodiodes where light could not be detected. The optical detection device of Patent Document 1 includes a microlens array, and is configured to refract light incident on the dead area by the microlens and guide it to a detectable area if there is no microlens array. Thereby, the light reception range can be substantially expanded.

[0005] However, in a configuration using a microlens array, the cost is high and the number of manufacturing process steps is large by the amount corresponding to the microlens array. Therefore, in such a configuration, it is difficult to reduce the cost and the number of manufacturing process steps. Further, in a configuration using a microlens array, a reduction effect of a dead area cannot be expected for particle beams such as electromagnetic waves and electron beams transmitted through the microlens. For this reason, an avalanche photodiode array is expected which has a simple configuration with reduced members such as a microlens array, can reduce the dead area, and can realize detection of a desired electromagnetic wave or particle beam.

[0006] One aspect of the present invention aims to provide an avalanche photodiode array capable of reducing a dead area and realizing detection of a desired electromagnetic wave or particle beam with a simple configuration.

Means for Solving the Problems

[0007] The avalanche photodiode array according to one aspect of the present invention includes a semiconductor substrate. The semiconductor substrate has a first surface and a second surface facing each other. The semiconductor substrate includes a semiconductor region provided on the first surface side. The semiconductor substrate has a plurality of avalanche photodiodes. The plurality of avalanche photodiodes are arranged along the first surface. The plurality of avalanche photodiodes include a first semiconductor layer of a first conductivity type, a plurality of second semiconductor layers of a second conductivity type, and a multiplication layer. The first semiconductor layer is provided on the second surface side of the semiconductor region. The plurality of second semiconductor layers are arranged along the first surface. Each second semiconductor layer is surrounded by the semiconductor region when viewed from a direction orthogonal to the first surface. The multiplication layer is provided in the semiconductor region and is provided between the plurality of second semiconductor layers and the first semiconductor layer in a direction orthogonal to the first surface. When viewed from a direction orthogonal to the first surface, the plurality of second semiconductor layers and the multiplication layer are provided within a range where the first semiconductor layer is located. The multiplication layer includes a third semiconductor layer of the second conductivity type and a fourth semiconductor layer of the second conductivity type facing each other. The third semiconductor layer is provided on the first surface side of the fourth semiconductor layer. Each of the third semiconductor layer and the fourth semiconductor layer is continuously provided so as to overlap the plurality of second semiconductor layers when viewed from a direction orthogonal to the first surface.

[0008] In one aspect, the plurality of avalanche photodiodes include a first semiconductor layer of a first conductivity type, a plurality of second semiconductor layers of a second conductivity type, and a multiplication layer. Each of the third semiconductor layer and the fourth semiconductor layer of the multiplication layer is continuously provided so as to overlap the plurality of second semiconductor layers when viewed in a direction orthogonal to the first surface. In this case, carriers generated by the incidence of electromagnetic waves or particle beams to be detected are multiplied by the multiplication layer that is continuously provided so as to overlap the plurality of second semiconductor layers. The carriers multiplied in the multiplication layer are output from each second semiconductor layer. According to this configuration, the dead area can be reduced. Since the multiplication layer is provided separately from the plurality of second semiconductor layers, the concentration of the electric field in each second semiconductor layer is suppressed. Therefore, edge breakdown in each second semiconductor layer is also suppressed. For this reason, in a simple configuration without a microlens array or the like, the dead area is reduced and desired electromagnetic waves or particle beams can be detected. According to this configuration, the sensitivity layer can be configured to be relatively wide. Therefore, in particular, detection of electromagnetic waves or particle beams that require a relatively wide sensitivity layer can be realized.

[0009] In one aspect, the impurity concentration of the first semiconductor layer and the impurity concentration of the fourth semiconductor layer may be higher than the impurity concentration of the semiconductor region. The impurity concentration of the first semiconductor layer may be higher than the impurity concentration of the fourth semiconductor layer. The impurity concentration of each second semiconductor layer may be higher than the impurity concentration of the third semiconductor layer.

[0010] In one aspect, in the direction orthogonal to the first surface, the shortest distance between the first semiconductor layer and the fourth semiconductor layer may be larger than the shortest distance between the plurality of second semiconductor layers and the third semiconductor layer. In this case, a relatively wide sensitivity layer is ensured between the first semiconductor layer and the fourth semiconductor layer. Therefore, the detection accuracy of electromagnetic waves or particle beams that require a relatively wide sensitivity layer can be improved.

[0011] In one of the above aspects, the impurity concentration of the third semiconductor layer is higher than that of the fourth semiconductor layer. In this case, during operation, the electric field strength between the first semiconductor layer and the fourth semiconductor layer is greater than the electric field strength between the first surface and the third semiconductor layer. Therefore, the migration speed of the generated carriers can be ensured between the first semiconductor layer and the fourth semiconductor layer, and high-speed response can be achieved. Edge breakdown between the plurality of second semiconductor layers and the multiplication layer can be further suppressed.

[0012] In one of the above aspects, taking an arbitrary position from the first surface in the direction orthogonal to the first surface as "x", the impurity concentration of the third semiconductor layer at the arbitrary position "x" as "f(x)", the impurity concentration of the fourth semiconductor layer at the arbitrary position "x" as "g(x)", the thickness of the third semiconductor layer in the direction orthogonal to the first surface as "L α ", the thickness of the fourth semiconductor layer in the direction orthogonal to the first surface as "L β ", the shortest distance between the first surface and the third semiconductor layer in the direction orthogonal to the first surface as "A", and the shortest distance between the first surface and the fourth semiconductor layer in the direction orthogonal to the first surface as "B", the formula (1) may be satisfied. [Number] In this case, the migration speed of the generated carriers can be ensured between the first semiconductor layer and the fourth semiconductor layer, and high-speed response can be achieved. Edge breakdown between the plurality of second semiconductor layers and the multiplication layer can be further suppressed.

[0013] In one of the above aspects, the semiconductor substrate may include a fifth semiconductor layer of the second conductivity type that surrounds the entire region where the plurality of second semiconductor layers are arranged when viewed from the direction orthogonal to the first surface. When viewed from the direction orthogonal to the first surface, the third semiconductor layer and the fifth semiconductor layer may at least partially overlap each other. In this case, the variation in gain in each second semiconductor layer can be further reduced. Furthermore, the movement of carriers generated outside the detection target range to the second semiconductor layer can be suppressed.

[0014] In one of the above aspects, when viewed from a direction orthogonal to the first surface, the edges of the respective second semiconductor layers may be covered by a junction termination extension region. The junction termination extension region covering each second semiconductor layer may be a semiconductor of a second conductivity type having an impurity concentration lower than the impurity concentration of the second semiconductor layer. In this case, edge breakdown in each second semiconductor layer can be further suppressed.

[0015] In one of the above aspects, the portion of each second semiconductor layer facing the semiconductor region may be covered by a junction termination extension region. In this case, edge breakdown in each second semiconductor layer can be further suppressed.

[0016] In one of the above aspects, the junction termination extension region covering each second semiconductor layer may be spaced apart from the multiplication layer. In this case, the electric field strength between each second semiconductor layer and the multiplication layer can be made more uniform.

[0017] In one of the above aspects, when viewed from a direction orthogonal to the first surface, the edge of the fifth semiconductor layer may be covered by a junction termination extension region. The junction termination extension region covering the fifth semiconductor layer may be a semiconductor of a second conductivity type having an impurity concentration lower than the impurity concentration of the fifth semiconductor layer. In this case, edge breakdown in the fifth semiconductor layer can be suppressed.

[0018] In one of the above aspects, the semiconductor substrate may include a sixth semiconductor layer of a first conductivity type. The sixth semiconductor layer may be provided between adjacent second semiconductor layers among the plurality of second semiconductor layers when viewed from a direction orthogonal to the first surface. The impurity concentration of the sixth semiconductor layer may be higher than the impurity concentration of the semiconductor region. In this case, the movement of carriers between adjacent second semiconductor layers can be suppressed.

[0019] In one of the above aspects, in the direction orthogonal to the first surface, the thickness of the sixth semiconductor layer may be smaller than the thickness of each second semiconductor layer. In this case, edge breakdown between the sixth semiconductor layer and the third semiconductor layer can be suppressed.

[0020] In one of the above aspects, the semiconductor substrate may contain silicon. The second conductivity type may be an N type.

[0021] In one of the above aspects, the semiconductor substrate may contain indium phosphide. The second conductivity type may be a P type.

[0022] In one of the above aspects, the multiplication layer may be provided in a range of 10 μm or less from the first surface in a direction orthogonal to the first surface. In this case, it has a configuration in which formation is relatively easy.

[0023] In one of the above aspects, in a direction along the first surface, the width of each second semiconductor layer may be greater than 10 μm. In this case, the size of each pixel for detection can be ensured.

[0024] In one of the above aspects, when viewed from a direction orthogonal to the first surface, the multiplication layer may include a pair of edges facing each other. A plurality of second semiconductor layers may be arranged in three or more in the facing direction of the pair of edges. When viewed from a direction orthogonal to the first surface, in the above-mentioned facing direction, the plurality of second semiconductor layers may be located between the pair of edges. In this case, variations in gain in each second semiconductor layer can be further suppressed.

[0025] In one of the above aspects, when viewed from a direction orthogonal to the first surface, in a plurality of second semiconductor layers, the areas of the regions where each second semiconductor layer overlaps with the multiplication layer may be equal to each other. In this case, variations in gain in each second semiconductor layer can be further suppressed.

[0026] In one of the above aspects, when viewed from a direction orthogonal to the first surface, the edge of the multiplication layer may overlap with the shielding member. In this case, the generation of carriers outside the detection target region can be suppressed.

[0027] In one of the above aspects, each avalanche photodiode may be a surface incidence type in which detection light is incident from the first surface or a back surface incidence type in which detection light is incident from the second surface.

[0028] In one of the above aspects, when viewed in a direction orthogonal to the first surface, a portion of each second semiconductor layer that overlaps with the multiplication layer may have a rectangular shape extending in a direction along the first surface.

[0029] In one of the above aspects, when viewed in a direction orthogonal to the first surface, the width of each second semiconductor layer may be larger than the shortest distance between adjacent second semiconductor layers. In this case, the directions of the electric lines of force from the second semiconductor layers are gathered, and the generated carriers are easily induced in the second semiconductor layers.

Advantages of the Invention

[0030] One aspect of the present invention can provide an avalanche photodiode array in which a dead area can be reduced and detection of a desired electromagnetic wave or particle beam can be realized with a simple configuration.

Brief Description of the Drawings

[0031]

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Mode for Carrying Out the Invention

[0032] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals will be used for the same elements or elements having the same function, and redundant descriptions will be omitted.

[0033] First, with reference to FIGS. 1 to 4, the configuration of the avalanche photodiode array in the present embodiment will be described. Hereinafter, the "avalanche photodiode" will be referred to as "APD". FIG. 1 is a schematic plan view of the APD array in the present embodiment. FIG. 2 is a cross-sectional view of the APD array. FIG. 3 is a plan view of the APD array. FIG. 4 is a partially enlarged view of the APD array. The X-axis, Y-axis, and Z-axis are orthogonal to each other. The direction D1 coincides with the Z-axis direction. The direction D2 is orthogonal to the direction D1 and parallel to the XY-plane. Hereinafter, the direction D1 will also be referred to as the "Z-axis direction".

[0034] The APD array 1 is used for detecting electromagnetic waves or particle beams. The APD array 1 can be used, for example, as a photodetector for LiDAR (Light Detection and Ranging). The APD array 1 can also be used, for example, as a detector for high-energy particles. In particular, the APD array 1 is used for detecting electromagnetic waves or particle beams that require a relatively wide sensitive layer. For example, the electromagnetic waves detected by the APD array 1 include electromagnetic waves having a wavelength of 600 nm to 1200 nm or X-rays. The particle beams detected by the APD array 1 include, for example, high-energy particle beams such as electron beams. Hereinafter, X-rays and high-energy particle beams are collectively referred to as "high-energy rays". In the present embodiment, the APD array 1 is a surface incidence type.

[0035] As shown in FIGS. 1 and 2, the APD array 1 includes a semiconductor substrate 10. As shown in FIG. 2, the semiconductor substrate 10 has a first surface 11 and a second surface 12 facing each other.

[0036] The semiconductor substrate 10 has a plurality of APDs 15. The plurality of APDs 15 are arranged along the first surface 11. As shown in FIG. 3, the APD array 1 includes a detection target area DA. The APD array 1 outputs a detection signal corresponding to the electromagnetic waves or particles incident on the detection target area DA. Each APD 15 operates in a linear mode.

[0037] In the present embodiment, each APD 15 is of a surface incidence type in which detection light is incident from the first surface 11. That is, in the present embodiment, the first surface 11 corresponds to the incident surface. The Z-axis is perpendicular to the first surface 11. The X-axis and the Y-axis extend along the first surface 11.

[0038] As shown in FIG. 2, the semiconductor substrate 10 includes a semiconductor region 20 provided on the first surface 11 side. The semiconductor region 20 is of the first conductivity type. In the present embodiment, the semiconductor region 20 forms a part of the first surface 11. The semiconductor substrate 10 further includes a first semiconductor layer 21, a plurality of second semiconductor layers 22, and a multiplication layer 40. The plurality of APDs 15 include the first semiconductor layer 21, the plurality of second semiconductor layers 22, and the multiplication layer 40 provided in the semiconductor substrate 10. The first semiconductor layer 21 is of the first conductivity type. The plurality of second semiconductor layers 22 are of the second conductivity type.

[0039] The first semiconductor layer 21 is provided on the second surface 12 side rather than the semiconductor region 20. The first semiconductor layer 21 is provided along the second surface 12. In the present embodiment, the first semiconductor layer 21 forms the second surface 12. The first semiconductor layer 21 is in contact with the semiconductor region 20 within the semiconductor substrate 10. When viewed from the Z-axis direction, the plurality of second semiconductor layers 22 and the multiplication layer 40 are provided within the range where the first semiconductor layer 21 is located. In the present embodiment, the first semiconductor layer 21 corresponds to the anode.

[0040] The plurality of second semiconductor layers 22 are arranged along the first surface 11. Each second semiconductor layer 22 forms a part of the first surface 11. Each second semiconductor layer 22 is surrounded by the semiconductor region 20 when viewed from the Z-axis direction. In the present embodiment, each second semiconductor layer 22 is in contact with the semiconductor region 20 on a surface other than the surface forming the first surface 11. When viewed from the Z-axis direction, the semiconductor region 20 is provided between the second semiconductor layers 22 adjacent to each other. Each second semiconductor layer 22 corresponds to a channel layer that outputs a detection signal of each APD 15.

[0041] As shown in FIG. 1, when viewed from the Z-axis direction, the portion of each second semiconductor layer 22 that overlaps with the multiplication layer 40, for example, exhibits a rectangular shape extending in the X-axis direction. In this specification, "overlap" is not limited to the case where the contours of each other coincide, but includes the case where they overlap at least partially with each other. When viewed from the Z-axis direction, the portion of each second semiconductor layer 22 that overlaps with the detection target region DA, for example, exhibits a rectangular shape extending in the X-axis direction. In this specification, "rectangular shape" also includes a shape with rounded corners. When viewed from the Z-axis direction, the width W1 of each second semiconductor layer 22 is larger than the shortest distance L1 between adjacent second semiconductor layers 22. When viewed from the Z-axis direction, the width W1 of each second semiconductor layer 22 is, for example, larger than 10 μm. The width W1 of the second semiconductor layer 22 is, for example, the length in the direction along the X-axis.

[0042] The multiplication layer 40 multiplies carriers. The multiplication layer 40 is provided in the semiconductor region 20. The multiplication layer 40 is provided between the plurality of second semiconductor layers 22 and the first semiconductor layer 21 in the Z-axis direction. The multiplication layer 40 is provided, for example, in the range of 10 μm or less from the first surface 11 in the Z-axis direction. The multiplication layer 40 may be provided in the range of 1 μm or more and 10 μm or less from the first surface 11 in the Z-axis direction.

[0043] The multiplication layer 40, for example, exhibits a rectangular shape. The multiplication layer 40 extends, for example, in the X-axis direction. When viewed from the Z-axis direction, the multiplication layer 40 includes a pair of edges 41a, 41b facing each other in the X-axis direction and edges 41c, 41d facing each other in the Y-axis direction.

[0044] In the surface-incident type APD array 1, when a plurality of second semiconductor layers 22 are two-dimensionally arranged in a matrix, the plurality of second semiconductor layers 22 are arranged so as to be two rows or less in the row direction or the column direction. In the present embodiment, as shown in FIG. 1, the plurality of second semiconductor layers 22 are arranged in two rows or less in the Y-axis direction. Three or more of the plurality of second semiconductor layers 22 are arranged in the X-axis direction. The arrangement of the plurality of second semiconductor layers 22 is two rows or less and three columns or more. In the configuration shown in FIG. 1, the plurality of second semiconductor layers 22 are arranged in two rows and four columns.

[0045] When viewed from the Z-axis direction, in the X-axis direction, the plurality of second semiconductor layers 22 are located between a pair of edges 41a, 41b. In other words, when viewed from the Z-axis direction, a pair of edges 41a, 41b of the multiplication layer 40 are located outside the edge 44a of the second semiconductor layer 44 that is located most outward in the X-axis direction among the plurality of second semiconductor layers 22. When the arrangement of the plurality of second semiconductor layers 22 is two rows or less and three columns or more, the multiplication layer 40 is arranged so as to straddle the plurality of second semiconductor layers 22 when viewed from the Z-axis direction.

[0046] In this case, in the plurality of second semiconductor layers 22, when viewed from the Z-axis direction, the area of the region where each second semiconductor layer 22 overlaps with the multiplication layer 40 is equal to each other. "Equal" includes manufacturing tolerances. The detection target region DA is located within the range where the multiplication layer 40 is located. When viewed from the Z-axis direction, each second semiconductor layer 22 extends in the Y-axis direction more than the edges 41c, 41d of the multiplication layer 40.

[0047] As shown in FIG. 2, the multiplication layer 40 includes a third semiconductor layer 23 and a fourth semiconductor layer 24 that face each other. The third semiconductor layer 23 is provided closer to the first surface 11 side than the fourth semiconductor layer 24. The fourth semiconductor layer 24 is provided closer to the second surface 12 side than the third semiconductor layer 23. The third semiconductor layer 23 is of a second conductivity type. The fourth semiconductor layer 24 is of a first conductivity type.

[0048] In the present embodiment, the multiplication layer 40 further includes a semiconductor region 20 located between the third semiconductor layer 23 and the fourth semiconductor layer 24. The third semiconductor layer 23 and the fourth semiconductor layer 24 face each other with the semiconductor region 20 therebetween and are spaced apart from each other. As a modification of the present embodiment, the multiplication layer 40 may not include the semiconductor region 20. In this modification, the third semiconductor layer 23 and the fourth semiconductor layer 24 are connected to each other.

[0049] The multiplication layer 40 is continuously provided so as to overlap a plurality of second semiconductor layers 22 when viewed from the Z-axis direction. In other words, when viewed from the Z-axis direction, a single region surrounded by the edges 41a, 41b, 41c, 41d of the multiplication layer 40 overlaps a plurality of second semiconductor layers 22. Each of the third semiconductor layer 23 and the fourth semiconductor layer 24 included in the multiplication layer 40 is continuously provided so as to overlap a plurality of second semiconductor layers 22 when viewed from the Z-axis direction. The third semiconductor layer 23 and the fourth semiconductor layer 24 are provided so as to overlap each other when viewed from the Z-axis direction. Both one third semiconductor layer 23 and one fourth semiconductor layer 24 face a plurality of second semiconductor layers 22 in the Z-axis direction.

[0050] In the present embodiment, when viewed from the Z-axis direction, the edges 41a, 41b, 41c, 41d of the multiplication layer 40 coincide with the edges of the third semiconductor layer 23. When viewed from the Z-axis direction, the edges 41a, 41b, 41c, 41d of the multiplication layer 40 coincide with the edges of the fourth semiconductor layer 24. In the present embodiment, each second semiconductor layer 22 includes a portion that does not overlap the multiplication layer 40 when viewed from the Z-axis direction. For example, when viewed from the Z-axis direction, the area of the region where the multiplication layer 40 and the plurality of second semiconductor layers 22 overlap is 80% or more of the area of the region where the multiplication layer 40 is located.

[0051] The semiconductor substrate 10 further includes a fifth semiconductor layer 25. The fifth semiconductor layer 25 surrounds the entire region where the plurality of second semiconductor layers 22 are arranged when viewed in the Z-axis direction. The fifth semiconductor layer 25 forms a part of the first surface 11. The fifth semiconductor layer 25 is surrounded by the semiconductor region 20. The fifth semiconductor layer 25 is in contact with the semiconductor region 20 on a surface other than the surface forming the first surface 11. The fifth semiconductor layer 25 is of the second conductivity type.

[0052] When viewed in the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 overlap each other at least partially. When viewed in the Z-axis direction, the third semiconductor layer 23 and the fifth semiconductor layer 25 overlap each other at least partially. The fifth semiconductor layer 25 corresponds to an absorption layer that absorbs carriers generated outside the detection target region DA.

[0053] The semiconductor substrate 10 further includes a plurality of sixth semiconductor layers 26. Each sixth semiconductor layer 26 is of the first conductivity type. The plurality of sixth semiconductor layers 26 are arranged on the first surface 11. Each sixth semiconductor layer 26 forms a part of the first surface 11. Each sixth semiconductor layer 26 is surrounded by the semiconductor region 20. In the present embodiment, each sixth semiconductor layer 26 is in contact with the semiconductor region 20 on a surface other than the surface forming the first surface 11. Each sixth semiconductor layer 26 is provided between a plurality of adjacent second semiconductor layers 22 when viewed in the Z-axis direction. Each sixth semiconductor layer 26 corresponds to a separator that separates adjacent second semiconductor layers 22 from each other and suppresses the movement of carriers.

[0054] Each sixth semiconductor layer 26 overlaps the third semiconductor layer 23 when viewed in the Z-axis direction. In the Z-axis direction, the thickness of each sixth semiconductor layer 26 is smaller than the thickness of each second semiconductor layer 22. Each sixth semiconductor layer 26 and the third semiconductor layer 23 are spaced apart from each other. For example, in the Z-axis direction, the shortest distance between each sixth semiconductor layer 26 and the third semiconductor layer 23 is, for example, 1 μm or more. A semiconductor region 20 is provided between each sixth semiconductor layer 26 and the third semiconductor layer 23. In the direction along the first surface 11, the width of each sixth semiconductor layer is, for example, 8 μm or less.

[0055] The semiconductor substrate 10 further includes a semiconductor electrode layer 45. When viewed in the Z-axis direction, the semiconductor electrode layer 45 surrounds the entire region where the plurality of second semiconductor layers 22 are arranged and the entire fifth semiconductor layer 25. The semiconductor electrode layer 45 forms part of the first surface 11. The semiconductor electrode layer 45 is surrounded by the semiconductor region 20. The semiconductor electrode layer 45 is in contact with the semiconductor region 20 on a surface other than the surface forming the first surface 11. The semiconductor electrode layer 45 has a first conductivity type. When viewed in the Z-axis direction, the multiplication layer 40 and the semiconductor electrode layer 45 do not overlap. The semiconductor electrode layer 45 is electrically connected to the first semiconductor layer 21.

[0056] The semiconductor substrate 10 is made of, for example, a silicon semiconductor. In this case, the semiconductor substrate 10 contains silicon. In this case, the first conductivity type is P-type and the second conductivity type is N-type. In the semiconductor substrate 10, the first semiconductor layer 21 and the fourth semiconductor layer 24, which are P-type semiconductor layers, are doped with, for example, group III elements as impurities. The impurities in the P-type include at least one selected from, for example, boron, gallium, and indium. The second semiconductor layer 22 and the third semiconductor layer 23, which are N-type semiconductor layers, are doped with, for example, group V elements as impurities. The impurities in the N-type include at least one selected from, for example, phosphorus, arsenic, and antimony.

[0057] The doping of the impurities is performed, for example, by ion implantation or thermal diffusion. In the present embodiment, the plurality of second semiconductor layers 22, third semiconductor layers 23, fourth semiconductor layers 24, fifth semiconductor layers 25, and semiconductor electrode layers 45 are formed by doping the impurities by ion implantation.

[0058] As a modification of this embodiment, the semiconductor substrate 10 may be made of, for example, a compound semiconductor. In this case, the semiconductor substrate 10 may contain indium phosphide. The first conductivity type is N-type, and the second conductivity type is P-type. In the semiconductor substrate 10, the N-type semiconductor layer is doped with, for example, an element of Group IV or Group VI as an impurity. The impurity in the N-type contains, for example, at least one selected from silicon, tin, sulfur, selenium, and tellurium. The P-type semiconductor layer is doped with, for example, an element of Group II as an impurity. The impurity in the P-type contains, for example, at least one selected from beryllium and zinc.

[0059] The amount of the impurity doped in each of the semiconductor region 20, the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, the fourth semiconductor layer 24, the fifth semiconductor layer 25, and the semiconductor electrode layer 45 satisfies, for example, the following relationship indicated by the impurity concentration. The impurity concentration of the first semiconductor layer 21 and the impurity concentration of the fourth semiconductor layer 24 are, for example, equal to or higher than the impurity concentration of the semiconductor region 20, and more preferably higher than the impurity concentration of the semiconductor region 20. The impurity concentration of the first semiconductor layer 21 is, for example, equal to or higher than the impurity concentration of the fourth semiconductor layer 24, and more preferably higher than the impurity concentration of the fourth semiconductor layer 24. The impurity concentration of each second semiconductor layer 22 is, for example, equal to or higher than the impurity concentration of the third semiconductor layer 23, and more preferably higher than the impurity concentration of the third semiconductor layer 23. The impurity concentration of the third semiconductor layer 23 is, for example, equal to or higher than the impurity concentration of the fourth semiconductor layer 24, and more preferably higher than the impurity concentration of the fourth semiconductor layer 24. The impurity concentration of the sixth semiconductor layer 26 is equal to or higher than the impurity concentration of the semiconductor region 20, and more preferably higher than the impurity concentration of the semiconductor region 20. The impurity concentration of the fifth semiconductor layer 25 is, for example, equivalent to that of each second semiconductor layer 22. The impurity concentration of the semiconductor electrode layer 45 is, for example, equivalent to that of the first semiconductor layer 21. The "impurity concentration" means the amount of the doped impurity per unit volume. The impurity concentration is also called the charge carrier concentration or the majority carrier concentration.

[0060] As a modification of this embodiment, the amount of impurities doped in each of the semiconductor region 20, the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, the fourth semiconductor layer 24, the fifth semiconductor layer 25, and the semiconductor electrode layer 45 may be compared by the total amount of impurities in the Z-axis direction instead of the impurity concentration. The total amount of impurities in the Z-axis direction is obtained, for example, by linearly integrating the impurity concentration at an arbitrary position from the first surface 11 in the Z-axis direction. The interval length for performing the line integral is, for example, the thickness of the target region in the Z-axis direction. Hereinafter, the value obtained by this line integral is referred to as the "impurity integrated amount".

[0061] For example, when an arbitrary position from the first surface 11 in the Z-axis direction is "x", the impurity concentration of the third semiconductor layer 23 at the arbitrary position "x" is "f(x)", the impurity concentration of the fourth semiconductor layer 24 at the arbitrary position "x" is "g(x)", the thickness of the third semiconductor layer 23 in the Z-axis direction is "L α ", the thickness of the fourth semiconductor layer 24 in the Z-axis direction is "L β ", the shortest distance between the first surface 11 and the third semiconductor layer 23 in the Z-axis direction is "A", and the shortest distance between the first surface 11 and the fourth semiconductor layer 24 in the Z-axis direction is "B", the following formula (2) is satisfied.

Equation

[0062] That is, the impurity integrated amount of the third semiconductor layer 23 is, for example, equal to or more than the impurity integrated amount of the fourth semiconductor layer 24. More preferably, the impurity integrated amount of the third semiconductor layer 23 is, for example, larger than the impurity integrated amount of the fourth semiconductor layer 24.

[0063] In each of the semiconductor region 20, the first semiconductor layer 21, the second semiconductor layer 22, the third semiconductor layer 23, the fourth semiconductor layer 24, the fifth semiconductor layer 25, and the semiconductor electrode layer 45, the amount of the impurity doped satisfies the following relationship in the above-mentioned impurity integrated amount. The impurity integrated amount of the first semiconductor layer 21 and the impurity integrated amount of the fourth semiconductor layer 24 are, for example, equal to or more than the impurity integrated amount of the semiconductor region 20, and more preferably, larger than the impurity integrated amount of the semiconductor region 20. The impurity integrated amount of the first semiconductor layer 21 is, for example, equal to or more than the impurity integrated amount of the fourth semiconductor layer 24, and more preferably, larger than the impurity integrated amount of the fourth semiconductor layer 24. The impurity integrated amount of each second semiconductor layer 22 is, for example, equal to or more than the impurity integrated amount of the third semiconductor layer 23, and more preferably, larger than the impurity integrated amount of the third semiconductor layer 23. The impurity integrated amount of the sixth semiconductor layer 26 is, for example, equal to or more than the impurity integrated amount of the semiconductor region 20, and more preferably, larger than the impurity integrated amount of the semiconductor region 20. The impurity integrated amount of the fifth semiconductor layer 25 is, for example, equivalent to that of each second semiconductor layer 22. The impurity integrated amount of the semiconductor electrode layer 45 is, for example, larger than that of the first semiconductor layer 21.

[0064] In the present embodiment, as shown in FIGS. 1 and 3, the APD array 1 further includes a plurality of metal layers 30, 31, 32 and a plurality of pad electrodes 33, 34, 35. The plurality of metal layers 30, 31, 32 and the plurality of pad electrodes 33, 34, 35 are all provided on the first surface 11.

[0065] When viewed from the Z-axis direction, the plurality of metal layers 30 cover a part of the plurality of second semiconductor layers 22. The plurality of metal layers 30 are spaced apart from each other. The plurality of metal layers 30 are in contact with different second semiconductor layers 22, respectively. Each metal layer 30 applies a potential to the second semiconductor layer 22 with which it is in contact.

[0066] When viewed from the Z-axis direction, the metal layer 31 surrounds the plurality of second semiconductor layers 22. As shown in FIG. 2, when viewed from the Z-axis direction, the metal layer 31 overlaps with the fifth semiconductor layer 25. The metal layer 31 is continuously provided along the fifth semiconductor layer 25. The metal layer 31 is, for example, in contact with the fifth semiconductor layer 25. For example, a potential may be applied to the fifth semiconductor layer 25 through the metal layer 31. In this case, the fifth semiconductor layer 25 can further absorb carriers generated in the detection target region DA.

[0067] As shown in FIG. 1, when viewed from the Z-axis direction, the metal layer 31 overlaps with the edges 41a, 41b of the multiplication layer 40. The edges 41a, 41b of the multiplication layer 40 are shielded by the metal layer 31. The metal layer 31 corresponds to a shielding member that suppresses the incident of the electromagnetic wave to be detected on the edges 41a, 41b, 41c, 41d of the multiplication layer 40.

[0068] When viewed from the Z-axis direction, the metal layer 32 surrounds the metal layer 31 and the plurality of second semiconductor layers 22. When viewed from the Z-axis direction, the metal layer 32 overlaps with the semiconductor electrode layer 45. The metal layer 32 is continuously provided along the semiconductor electrode layer 45. The metal layer 32 is in contact with the semiconductor electrode layer 45. The potential is applied to the semiconductor electrode layer 45 through the metal layer 32.

[0069] The plurality of pad electrodes 33 are each connected to the metal layer 30. The plurality of pad electrodes 33 are each electrically connected to each second semiconductor layer 22 via the metal layer 30. As shown in FIG. 3, each pad electrode 33 is provided on the first surface 11 and is in contact with the corresponding second semiconductor layer 22 among the plurality of second semiconductor layers 22 via the corresponding metal layer 30 among the plurality of metal layers 30. Each pad electrode 33 corresponds to an output terminal that outputs a detection signal from each second semiconductor layer 22. When viewed from the Z-axis direction, each pad electrode 33 is provided in a range that does not overlap with the multiplication layer 40. The plurality of pad electrodes 33 are arranged in the X-axis direction and are connected to different second semiconductor layers 22. In the present embodiment, each pad electrode 33 corresponds to the cathode of the APD array 1.

[0070] The plurality of pad electrodes 34 are connected to the metal layer 31. In the present embodiment, each pad electrode 34 corresponds to the cathode of the APD array 1. The plurality of pad electrodes 35 are connected to the metal layer 32. In the present embodiment, the pad electrode 35, the metal layer 32, the semiconductor electrode layer 45, and the first semiconductor layer 21 correspond to the anode of the APD array 1.

[0071] As shown in FIG. 2, each APD 15 includes a branching layer 51, an electric field relaxation layer 52, a high electric field layer 53, an electric field control layer 54, and a sensitivity layer 55 formed in the semiconductor substrate 10. The branching layer 51, the electric field relaxation layer 52, the high electric field layer 53, the electric field control layer 54, and the sensitivity layer 55 are arranged in order from the first surface 11 toward the second surface 12.

[0072] The branching layer 51 is composed of the second semiconductor layer 22 and the semiconductor region 20. The branching layer 51 is located in the region from the first surface 11 to the boundary B1 between the semiconductor region 20 on the first surface 11 side and the third semiconductor layer 23. As a modification of the present embodiment, the second semiconductor layer 22 may be in contact with the third semiconductor layer 23. In this case, the branching layer 51 is composed of the second semiconductor layer 22, and the boundary B1 is the boundary between the second semiconductor layer 22 and the third semiconductor layer 23.

[0073] The electric field relaxation layer 52, the high electric field layer 53, and the electric field control layer 54 correspond to the multiplication layer 40. In other words, in the present embodiment, the multiplication layer 40 includes the electric field relaxation layer 52, the high electric field layer 53, and the electric field control layer 54. The electric field relaxation layer 52 relaxes the electric field strength in the branching layer 51. The electric field relaxation layer 52 is composed of the third semiconductor layer 23. The electric field relaxation layer 52 is located in the region from the boundary B1 to the boundary B2 between the semiconductor region 20 and the third semiconductor layer 23 on the second surface 12 side.

[0074] The high electric field layer 53 is a layer to which a higher electric field strength is applied than other semiconductor layers during operation. The high electric field layer 53 corresponds to a carrier multiplication layer that multiplies carriers at a higher electric field strength than other semiconductor layers. The high electric field layer 53 is composed of the semiconductor region 20. The high electric field layer 53 is located in the region from the boundary B2 to the boundary B3 between the semiconductor region 20 and the fourth semiconductor layer 24.

[0075] The electric field control layer 54 controls the electric field strength in the high electric field layer 53. The electric field control layer 54 is composed of the fourth semiconductor layer 24. The electric field control layer 54 is located in the region from the boundary B3 to the boundary B4 between the semiconductor region 20 and the fourth semiconductor layer 24 on the second surface 12 side.

[0076] The multiplication layer 40 is located in the region from the boundary B1 to the boundary B4. As a modification of the present embodiment, when the semiconductor region 20 is not provided between the third semiconductor layer 23 and the fourth semiconductor layer 24, the multiplication layer 40 does not include the semiconductor region 20. In this case, the high electric field layer 53 corresponds to the boundary between the third semiconductor layer 23 and the fourth semiconductor layer 24.

[0077] The sensitivity layer 55 is composed of the semiconductor region 20. The sensitivity layer 55 is located in the region from the boundary B4 to the boundary B5 between the semiconductor region 20 and the first semiconductor layer 21. In the Z-axis direction, the shortest distance L11 between the first semiconductor layer 21 and the fourth semiconductor layer 24 is larger than the shortest distance L12 between the plurality of second semiconductor layers 22 and the third semiconductor layer 23. Therefore, in the Z-axis direction, the thickness of the sensitivity layer 55 is larger than the shortest distance L12 between the plurality of second semiconductor layers 22 and the third semiconductor layer 23. In the Z-axis direction, the thickness of the sensitivity layer 55 may be larger than the thickness of the branching layer 51. In the Z-axis direction, the thickness of the sensitivity layer 55 may be larger than the sum of the thickness of the branching layer 51 and the thickness of the multiplication layer 40. The thickness of the sensitivity layer 55 is, for example, 10 μm or more and 1000 μm or less. The thickness of the sensitivity layer 55 may be 20 μm or more and 80 μm or less.

[0078] When electrons or particles are incident on the sensitivity layer 55, carriers are generated in the sensitivity layer 55. The carriers generated in the sensitivity layer 55 move to the multiplication layer 40. The moving speed of the carriers generated in the sensitivity layer 55 depends on the electric field strength in the sensitivity layer 55. In the multiplication layer 40, the carriers are multiplied. The carriers multiplied in the multiplication layer 40 move to the branching layer 51. The carriers that have moved to the branching layer 51 are output from each second semiconductor layer 22.

[0079] Next, with reference to FIG. 5, the APD array in the modification of the present embodiment will be described. FIG. 5 is a cross-sectional view of the APD array 1A in the modification of the present embodiment. This modification is generally similar or the same as the above-described embodiments and modifications. The APD array 1A is different from the above-described embodiment in that it includes a semiconductor substrate 10A instead of the semiconductor substrate 10. Hereinafter, the differences from the above-described embodiment will be mainly described.

[0080] As shown in FIG. 5, the semiconductor substrate 10A includes a plurality of Junction Termination Extension (JTE) regions 27. Each second semiconductor layer 22 is covered by the junction termination extension region 27. When viewed from the Z-axis direction, the edge 22b of each second semiconductor layer 22 is covered by the junction termination extension region 27. In this modified example, each second semiconductor layer 22 and the semiconductor region 20 are spaced apart from each other. A junction termination extension region 27 is provided between each second semiconductor layer 22 and the semiconductor region 20. Each second semiconductor layer 22 is in contact with the junction termination extension region 27 on a surface other than the surface forming the first surface 11. In other words, the portion of each second semiconductor layer 22 facing the semiconductor region 20 is in contact with the junction termination extension region 27.

[0081] The fifth semiconductor layer 25 is covered by the junction termination extension region 27. When viewed from the Z-axis direction, the edge 25b of the fifth semiconductor layer 25 is covered by the junction termination extension region 27. In this modified example, the fifth semiconductor layer 25 and the semiconductor region 20 are spaced apart from each other. A junction termination extension region 27 is provided between the fifth semiconductor layer 25 and the semiconductor region 20. The fifth semiconductor layer 25 is in contact with the junction termination extension region 27 on a surface other than the surface forming the first surface 11. In other words, the portion of the fifth semiconductor layer 25 facing the semiconductor region 20 is in contact with the junction termination extension region 27.

[0082] In this modified example, each junction termination extension region 27 and the third semiconductor layer 23 are spaced apart from each other. A semiconductor region 20 is provided between each junction termination extension region 27 and the third semiconductor layer 23. As a further modified example of this modified example, each junction termination extension region 27 and the third semiconductor layer 23 may be in contact with each other.

[0083] As a further modified example of this modified example, the plurality of junction termination extension regions 27 may be a continuous single region. In this case, for example, a plurality of second semiconductor layers 22 and fifth semiconductor layers 25 are covered by one junction termination extension region 27.

[0084] Each junction terminal extension region 27 is a semiconductor region of the second conductivity type. The impurity concentration of the junction terminal extension region 27 is lower than the impurity concentration of the second semiconductor layer 22. The impurity integrated amount of the junction terminal extension region 27 is, for example, smaller than the impurity integrated amount of the second semiconductor layer 22.

[0085] Next, referring to FIG. 6, an APD array in a modification of the present embodiment will be described. FIG. 6 is a cross-sectional view of an APD array 1B in a modification of the present embodiment. This modification is generally similar or the same as the above-described embodiments and modifications. The APD array 1B is different from the configuration shown in FIG. 5 in that it includes a semiconductor substrate 10B instead of the semiconductor substrate 10A. Hereinafter, differences from the configuration shown in FIG. 5 will be mainly described.

[0086] As shown in FIG. 6, the semiconductor substrate 10B is different from the semiconductor substrate 10A in that it includes a plurality of junction terminal extension regions 27C instead of the plurality of junction terminal extension regions 27. When viewed from the Z-axis direction, the edge 22b of each second semiconductor layer 22 is covered by the junction terminal extension region 27C. A junction terminal extension region 27C is provided between the edge 22b of each second semiconductor layer 22 and the semiconductor region 20. Each second semiconductor layer 22 is in contact with the semiconductor region 20 at portions other than the edge 22b. For example, at least a part of the surface 22a of each second semiconductor layer 22 facing the first surface 11 is in contact with the semiconductor region 20. The edge 22b of each second semiconductor layer 22 includes the edge of the surface 22a of each second semiconductor layer 22 facing the first surface 11.

[0087] When viewed from the Z-axis direction, the edge 25b of the fifth semiconductor layer 25 is covered by the junction terminal extension region 27C. A junction terminal extension region 27C is provided between the edge 25b of the fifth semiconductor layer 25 and the semiconductor region 20. The portion other than the edge 25b of the fifth semiconductor layer 25 is in contact with the semiconductor region 20. For example, at least a part of the surface 25a of the fifth semiconductor layer 25 facing the first surface 11 is in contact with the semiconductor region 20. The edge 25b of the fifth semiconductor layer 25 includes the edge of the surface 25a of the fifth semiconductor layer 25 facing the first surface 11.

[0088] In this modification example, among the edges 25b of the fifth semiconductor layer 25, a junction termination extension region 27C is provided at the edge 25b on the side of the second semiconductor layer 22, and no junction termination extension region 27C is provided at the edge 25b on the side of the semiconductor electrode layer 45. In a further modification example of this modification example, junction termination extension regions 27C may be provided at both the edge 25b on the side of the second semiconductor layer 22 and the edge 25b on the side of the semiconductor electrode layer 45 in the fifth semiconductor layer 25.

[0089] In this modification example, each junction termination extension region 27C and the third semiconductor layer 23 are spaced apart from each other. A semiconductor region 20 is provided between each junction termination extension region 27C and the third semiconductor layer 23. As a further modification example of this modification example, each junction termination extension region 27C and the third semiconductor layer 23 may be in contact with each other.

[0090] Each junction termination extension region 27C is a semiconductor region of the second conductivity type. The impurity concentration of the junction termination extension region 27C is lower than the impurity concentration of the second semiconductor layer 22. The impurity integrated amount of the junction termination extension region 27C is, for example, smaller than the impurity integrated amount of the second semiconductor layer 22.

[0091] Next, with reference to FIG. 7, an APD array in a modification example of the present embodiment will be described. FIG. 7 is a schematic plan view of an APD array 1C in a modification example of the present embodiment. This modification example is generally similar or the same as the above-described embodiment and modification example. This modification example is different from the above-described embodiment in the positional relationship between a plurality of second semiconductor layers 22 and the multiplication layer 40. Hereinafter, the differences from the above-described embodiment will be mainly described.

[0092] In the semiconductor substrate 10C of the APD array 1C, a plurality of second semiconductor layers 22 are arranged in one row and three or more are arranged in the X-axis direction. In other words, in the APD array 1C, the arrangement of a plurality of second semiconductor layers 22 is two rows or less and three columns or more. In the APD array 1C, a plurality of second semiconductor layers 22 are arranged in one row and eight columns.

[0093] Also in the APD array 1C, the multiplication layer 40 has a rectangular shape. The multiplication layer 40 extends in the X-axis direction. When viewed from the Z-axis direction, in the X-axis direction, a plurality of second semiconductor layers 22 are located between a pair of edges 41a, 41b. In other words, when viewed from the Z-axis direction, a pair of edges 41a, 41b of the multiplication layer 40 are located outside the edge 44a of the second semiconductor layer 44 that is located most outward in the X-axis direction among the plurality of second semiconductor layers 22. Further in other words, when viewed from the Z-axis direction, the multiplication layer 40 is arranged so as to straddle the plurality of second semiconductor layers 22. In this case, when viewed from the Z-axis direction, in the plurality of second semiconductor layers 22, the areas of the regions where each second semiconductor layer 22 overlaps with the multiplication layer 40 are equal to each other. When viewed from the Z-axis direction, each second semiconductor layer 22 extends in the Y-axis direction beyond the edges 41c, 41d of the multiplication layer 40. When viewed from the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 overlap with each other at least in part.

[0094] Next, with reference to FIGS. 8(a) and 8(b), the APD array in a modified example of the present embodiment will be described. FIG. 8(a) is a schematic plan view of the APD array 1D in a modified example of the present embodiment. FIG. 8(b) is a schematic plan view of the APD array 1E in a modified example of the present embodiment. This modified example is generally similar or the same as the above-described embodiments and modified examples. This modified example is different from the above-described embodiment in the positional relationship between the plurality of second semiconductor layers 22 and the multiplication layer 40. Hereinafter, the differences from the configurations shown in FIGS. 8(a) and 8(b) will be mainly described.

[0095] In the APD array 1D, the plurality of second semiconductor layers 22 are arranged in one row and two columns. In other words, in the APD array 1D, the arrangement of the plurality of second semiconductor layers 22 is less than two rows and less than three columns.

[0096] In the APD array 1D, the multiplication layer 40 has a rectangular shape. The multiplication layer 40 extends in the X-axis direction. In the APD array 1D, when viewed from the Z-axis direction, the multiplication layer 40 is surrounded by the fifth semiconductor layer 25. When viewed from the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 do not overlap. In this case, when viewed from the Z-axis direction, in the plurality of second semiconductor layers 22, the areas of the regions where each second semiconductor layer 22 overlaps with the multiplication layer 40 are equal to each other. When viewed from the Z-axis direction, each second semiconductor layer 22 extends in the X-axis direction and the Y-axis direction beyond the edges 41a, 41b, 41c, 41d of the multiplication layer 40.

[0097] In the APD array 1E, the plurality of second semiconductor layers 22 are arranged in two rows and two columns. In other words, in the APD array 1E, the arrangement of the plurality of second semiconductor layers 22 is less than two rows and less than three columns.

[0098] In the APD array 1E, the multiplication layer 40 has a rectangular shape. The multiplication layer 40 extends in the X-axis direction. In the APD array 1E, when viewed from the Z-axis direction, the multiplication layer 40 is surrounded by the fifth semiconductor layer 25. When viewed from the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 do not overlap. In this case, when viewed from the Z-axis direction, in the plurality of second semiconductor layers 22, the areas of the regions where each second semiconductor layer 22 overlaps with the multiplication layer 40 are equal to each other. When viewed from the Z-axis direction, each second semiconductor layer 22 extends in the X-axis direction and the Y-axis direction beyond the edges 41a, 41b, 41c, 41d of the multiplication layer 40.

[0099] Next, with reference to FIG. 9, the APD array in the modified example of the present embodiment will be described. FIG. 9 is a cross-sectional view of the APD array 1F in the modified example of the present embodiment. This modified example is generally similar or the same as the above-described embodiment and modified example. This modified example is different from the above-described embodiment in that the APD array is a back-illuminated type. Hereinafter, the differences from the configuration shown in the above-described embodiment will be mainly described.

[0100] In the APD array 1F, each APD 15 is a back-illuminated type that receives detection light from the second surface 12. In this modification example, the second surface 12 corresponds to the incident surface. The Z-axis is orthogonal to the first surface 11. The APD array 1F includes a semiconductor substrate 10F. The semiconductor substrate 10F has a configuration in which the semiconductor substrate 10 of the APD array 1 shown in FIG. 5 is turned upside down. The APD array 1F may have a configuration in which the semiconductor substrates 10A, 10B, 10C, 10D, and 10E are turned upside down as the semiconductor substrate 10F.

[0101] In the Z-axis direction, the thickness of the first semiconductor layer 21 of the semiconductor substrate 10F is smaller than the thickness of the first semiconductor layer 21 of the semiconductor substrate 10. Only in this respect, the semiconductor substrate 10F is different from the semiconductor substrate 10. For example, the semiconductor substrate 10F is formed by removing a part of the first semiconductor layer 21 of the semiconductor substrate 10. For example, the semiconductor substrate 10F is formed by grinding the first semiconductor layer 21 of the semiconductor substrate 10A in the Z-axis direction.

[0102] In addition to the semiconductor substrate 10F, the APD array 1F includes, for example, a silicon oxide film 91, a light-shielding film 92, a plurality of pad electrodes 93, a plurality of bump electrodes 94, a passivation layer 95, a resin layer 96, solder 97, and a control substrate 98. The second surface 12 of the semiconductor substrate 10F is covered with the silicon oxide film 91. The second surface 12 of the semiconductor substrate 10F may be covered with a silicon nitride film instead of the silicon oxide film 91.

[0103] In this modification example, the silicon oxide film 91 is covered with the light-shielding film 92. The light-shielding film 92 blocks electromagnetic waves other than the electromagnetic wave or particle beam to be detected. The material of the light-shielding film 92 may be selected according to the electromagnetic wave or particle beam to be detected. The material of the light-shielding film 92 contains, for example, aluminum. The light-shielding film 92 transmits high-energy rays to be detected and blocks visible light. As a result, the detection accuracy of high-energy rays is improved. When the object to be detected is visible light, the APD array 1F may not include the light-shielding film 92.

[0104] The plurality of pad electrodes 93 are each provided on the first surface 11 of the semiconductor substrate 10F. Each pad electrode 93 is in contact with the first surface 11 of the semiconductor substrate 10F. The plurality of pad electrodes 93 are each arranged to be in contact with any one of the semiconductor electrode layer 45, the second semiconductor layer 22, and the fifth semiconductor layer 25.

[0105] The plurality of bump electrodes 94 are each provided on a corresponding pad electrode 93. The material of the bump electrode 94 is, for example, nickel or gold. The APD array 1F may be a direct bond instead of the bump electrode 94. The direct bond is, for example, a Cu-Cu direct bond.

[0106] The passivation layer 95 covers the first surface 11 of the semiconductor substrate 10F and the pad electrodes 93 except for the portions where the pad electrodes 93 are in contact with the bump electrodes 94. The material of the passivation layer 95 contains, for example, silicon nitride. The solder 97 electrically connects the control substrate 98 and the bump electrode 94. The resin layer 96 is provided on the control substrate 98 so as to cover the bump electrode 94 and the solder 97.

[0107] The control substrate 98 is electrically connected to the semiconductor substrate 10F through the solder 97, the bump electrode 94, and the pad electrode 93. The control substrate 98 applies a potential to the semiconductor electrode layer 45, the second semiconductor layer 22, and the fifth semiconductor layer 25 through the pad electrode 93. The control substrate 98 acquires and processes detection signals from each APD 15 of the APD array 1F. The control substrate 98 includes a readout circuit that reads out detection signals from each APD 15. The control substrate 98 includes, for example, an ASIC (Application Specific Integrated Circuit) or a PCB (Printed Circuit Board) substrate.

[0108] Next, referring to FIG. 10, the APD array in the modification of this embodiment will be described. FIG. 10 is a schematic plan view of the APD array 1G in the modification of this embodiment. This modification is generally similar or the same as the above-described embodiments and modifications. This modification is different from the APD array 1F in the positional relationship between the plurality of second semiconductor layers 22 and the multiplication layer 40. Hereinafter, the differences from the APD array 1F will be mainly described.

[0109] When the APD array is a back-illuminated type, the plurality of second semiconductor layers 22 may be two-dimensionally arranged in a matrix so as to have three or more columns in both the row direction and the column direction. Referring to FIG. 10, the configuration of the APD array in this case will be described.

[0110] In the APD array 1G, the plurality of second semiconductor layers 22 are arranged in 9 rows and 7 columns. Therefore, in the APD array 1G, the plurality of second semiconductor layers 22 are two-dimensionally arranged in a matrix so as to have three or more columns in both the row direction and the column direction.

[0111] Also in the APD array 1G, the multiplication layer 40 has a rectangular shape. When viewed from the Z-axis direction, the edges 41a, 41b, 41c, 41d of the multiplication layer 40 include a pair of edges 41a, 41b facing each other in the X-axis direction and edges 41c, 41d facing each other in the Y-axis direction.

[0112] In the APD array 1G, when viewed from the Z-axis direction, in the X-axis direction, a plurality of second semiconductor layers 22 are located between a pair of edges 41a and 41b. In the Y-axis direction, the plurality of second semiconductor layers 22 are located between a pair of edges 41c and 41d. In other words, when viewed from the Z-axis direction, the plurality of second semiconductor layers 22 are arranged within the range where the multiplication layer 40 is located. Further in other words, when viewed from the Z-axis direction, all of the edges 41a, 41b, 41c, and 41d of the multiplication layer 40 are located outside the edge 44a of the outermost second semiconductor layer 44 among the plurality of second semiconductor layers 22. Further in other words, when viewed from the Z-axis direction, the multiplication layer 40 is arranged so as to straddle the plurality of second semiconductor layers 22. Also in this case, when viewed from the Z-axis direction, in the plurality of second semiconductor layers 22, the areas of the regions where each second semiconductor layer 22 overlaps with the multiplication layer 40 are equal to each other. When viewed from the Z-axis direction, the multiplication layer 40 and the fifth semiconductor layer 25 overlap with each other at least in part. When viewed from the Z-axis direction, the edges 41a, 41b, 41c, and 41d of the multiplication layer 40 of the APD array 1G overlap with the fifth semiconductor layer 25 over the entire circumference.

[0113] As described above, in the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, the plurality of APDs 15 include a first semiconductor layer 21 of a first conductivity type, a plurality of second semiconductor layers 22 of a second conductivity type, and a multiplication layer 40. Each of the third semiconductor layer 23 and the fourth semiconductor layer 24 of the multiplication layer 40 is continuously provided so as to overlap with the plurality of second semiconductor layers 22 when viewed from the Z-axis direction. In this case, carriers generated by the incidence of an electromagnetic wave or a particle beam to be detected are multiplied by the multiplication layer 40 that is continuously provided so as to overlap with the plurality of second semiconductor layers 22. The carriers multiplied in the multiplication layer 40 are output from each second semiconductor layer 22. According to this configuration, the dead area can be reduced. For this reason, in a simple configuration without a microlens array or the like, the dead area is reduced and a desired electromagnetic wave or particle beam can be detected. According to this configuration, the sensitivity layer can be configured to be relatively wide. For this reason, in particular, detection of an electromagnetic wave or a high-energy ray that requires a relatively wide sensitivity layer can be realized.

[0114] Figs. 11(a) and 11(b) are schematic views showing the configuration of the semiconductor layer in the comparative example. As shown in Fig. 11(a), when a multiplication layer is formed by the second semiconductor layer 22 of the second conductivity type and the semiconductor layer 140 of the first conductivity type for each APD115, there was a variation in gain between the APD115s. As shown in Fig. 11(b), when one semiconductor layer 140 of the first conductivity type is formed for the second semiconductor layers 22 of different conductivity types, the gain seems to be uniform between the APD115s including the second semiconductor layers 22 different from each other. However, in the configuration shown in Fig. 11(b), since the high electric field layer 53 is formed between the second semiconductor layer 22 and the semiconductor layer 140, the electric field is concentrated at the edge 22b of each second semiconductor layer 22, and edge breakdown occurs between each second semiconductor layer 22 and the semiconductor layer 140.

[0115] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, since the multiplication layer 40 is provided separately from the plurality of second semiconductor layers 22, the high electric field layer 53 and the second semiconductor layer 22 are separated from each other. Therefore, the concentration of the electric field in each second semiconductor layer 22 is suppressed, and edge breakdown in each second semiconductor layer 22 is also suppressed.

[0116] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, the multiplication layer 40 is continuously provided so as to overlap with the plurality of second semiconductor layers 22. According to this configuration, the variation in gain in each APD15 can also be suppressed. Figs. 12 and 13 show the evaluation results of the APD array 1. In this evaluation, the laser light was swept in the X-axis direction so as to pass through the four second semiconductor layers 22 arranged in the X-axis direction.

[0117] Fig. 12 shows the output of the APD15 corresponding to each second semiconductor layer 22 according to the irradiation position of the laser light. In Fig. 12, the horizontal axis indicates the irradiation position of the laser, and the vertical axis indicates the output current value. The signals S1 to S2 respectively indicate the outputs from the APD15s corresponding to the second semiconductor layers 22.

[0118] FIG. 13 shows the overall output of the APD array 1 according to the irradiation position of the laser beam. In FIG. 13, the horizontal axis indicates the irradiation position of the laser, and the vertical axis indicates the output current value. The signals S5 each indicate the sum of the outputs from the respective APDs 15. Thus, according to the APD array 1, it was confirmed that the variation in gain among the respective APDs 15 was suppressed and that the operation was performed with a uniform gain.

[0119] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, and 1G, in the Z-axis direction, the shortest distance L11 between the first semiconductor layer 21 and the fourth semiconductor layer 24 is greater than the shortest distance L12 between the plurality of second semiconductor layers 22 and the third semiconductor layer 23. In this case, a relatively wide sensitivity layer 55 is ensured between the first semiconductor layer 21 and the fourth semiconductor layer 24. Therefore, the detection accuracy of electromagnetic waves or particle beams that require a relatively wide sensitivity layer 55 can be improved. For example, near-infrared rays having a wavelength longer than 6000 nm, X-rays having a wavelength shorter than ultraviolet rays, and high-energy particle beams easily pass through the semiconductor substrate. If a relatively wide sensitivity layer 55 is ensured, the detection accuracy of electromagnetic waves having a wavelength of 600 nm to 1200 nm and high-energy rays such as X-rays can also be improved.

[0120] FIG. 14 is a schematic diagram showing the electric field between the semiconductor layers. Each arrow indicates an electric line of force. The electric field strength of the electric field E1 between the surface 22a of each second semiconductor layer 22 and the boundary B1 may be the electric field strength at which carriers multiplied in the multiplication layer 40 are branched and induced. The electric field strength of the electric field E1, that is, the electric field strength of the branching layer 51, is, for example, 10 1 ~10 2 V / cm. If the electric field strength of the electric field E1 exceeds 10 3 V / cm, there is a risk of edge breakdown. The electric field strength of the electric field E2 between the boundary B5 and the boundary B2 may be the electric field strength at which the generated carriers are sufficiently accelerated (drifted). In order to ensure the responsiveness, the electric field strength of the electric field E2, that is, the electric field strength of the sensitivity layer 55, is, for example, 10 2 ~10 4It is about V / cm. The electric field strength of the electric field E3 between the boundary B3 and the boundary B4 may be an electric field strength that multiplies the injected carriers. The electric field strength of the electric field E3, that is, the electric field strength of the high electric field layer 53, is, for example, 10 5 ~10 6 V / cm or so.

[0121] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, the impurity concentration of the third semiconductor layer 23 is higher than the impurity concentration of the fourth semiconductor layer. In this case, during operation, the electric field strength of the electric field E3 between the first semiconductor layer 21 and the fourth semiconductor layer 24 is greater than the electric field strength of the electric field E1 between the first surface 11 and the third semiconductor layer 23. FIG. 15 is a schematic diagram showing the electric field strength in the semiconductor substrate. The relationships of the above-described electric fields E1, E2, and E3 depend on the impurity concentration of the third semiconductor layer 23 and the impurity concentration of the fourth semiconductor layer. If the impurity concentration of the third semiconductor layer 23 is higher than the impurity concentration of the fourth semiconductor layer, the relationship of electric field E3 > electric field E2 > electric field E1 can be obtained. Therefore, the moving speed of the generated carriers is ensured between the first semiconductor layer 21 and the fourth semiconductor layer 24, and a high-speed response can be realized. Edge breakdown between the plurality of second semiconductor layers 22 and the multiplication layer 40 can be further suppressed.

[0122] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, Equation (3) is satisfied.

Equation

[0123] "x" is an arbitrary position from the first surface 11 in the Z-axis direction. "f(x) is the impurity concentration of the third semiconductor layer 23 at an arbitrary position "x". "g(x)" is the impurity concentration of the fourth semiconductor layer 24 at an arbitrary position "x". "L α " is the thickness of the third semiconductor layer 23 in the Z-axis direction. "L β"A" is the thickness of the fourth semiconductor layer 24 in the Z-axis direction. "A" is the shortest distance between the first surface 11 and the third semiconductor layer 23 in the Z-axis direction. "B" is the shortest distance between the first surface 11 and the fourth semiconductor layer 24 in the Z-axis direction. The relationships of the above-described electric fields E1, E2, and E3 depend on the impurity integrated amount of the third semiconductor layer 23 and the impurity integrated amount of the fourth semiconductor layer. If the impurity integrated amount of the third semiconductor layer 23 is higher than the impurity integrated amount of the fourth semiconductor layer, the relationship of electric field E3 > electric field E2 > electric field E1 can be obtained. In this case, between the first semiconductor layer 21 and the fourth semiconductor layer 24, the moving speed of the generated carriers is ensured, and high-speed response can be realized. Between the plurality of second semiconductor layers 22 and the multiplication layer 40, edge breakdown can be further suppressed.

[0124] The semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G include a p-type fifth semiconductor layer 25 that surrounds the entire region where the plurality of second semiconductor layers 22 are arranged when viewed from the Z-axis direction. When viewed from the Z-axis direction, the third semiconductor layer 23 and the fifth semiconductor layer 25 overlap each other at least partially. In this case, the variation in gain in each second semiconductor layer 22 can be further reduced. Further, the movement of carriers generated outside the detection target region DA to the second semiconductor layer 22 can be suppressed.

[0125] In the APD arrays 1A, 1B, when viewed from the Z-axis direction, the edge 22b of each second semiconductor layer 22 is covered by the junction termination extension regions 27, 27C. The junction termination extension regions 27, 27C that cover each second semiconductor layer 22 are p-type semiconductor regions 20 having an impurity concentration lower than the impurity concentration of the second semiconductor layer 22. In this case, the edge breakdown in each second semiconductor layer 22 can be further suppressed.

[0126] In the APD array 1A, the portion of each second semiconductor layer 22 facing the semiconductor region 20 is covered by the junction termination extension region 27. In this case, the edge breakdown in each second semiconductor layer 22 can be further suppressed.

[0127] In the APD arrays 1A and 1B, the junction termination extension regions 27 covering each second semiconductor layer 22 are spaced apart from the multiplication layer 40. In this case, the electric field strength between each second semiconductor layer 22 and the multiplication layer 40 can be made more uniform.

[0128] In the APD arrays 1A and 1B, when viewed from the Z-axis direction, the edge 25b of the fifth semiconductor layer 25 is covered by the junction termination extension regions 27 and 27C. The junction termination extension regions 27 and 27C covering the fifth semiconductor layer 25 are semiconductor regions of the second conductivity type having an impurity concentration lower than the impurity concentration of the fifth semiconductor layer 25. In this case, edge breakdown in the fifth semiconductor layer 25 can be suppressed.

[0129] The semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, and 10G include a sixth semiconductor layer 26 of the first conductivity type. The sixth semiconductor layer 26 is provided between adjacent second semiconductor layers 22 among the plurality of second semiconductor layers 22 when viewed from the Z-axis direction. The impurity concentration of the sixth semiconductor layer 26 is higher than the impurity concentration of the semiconductor region 20. In this case, the movement of carriers between adjacent second semiconductor layers 22 can be suppressed.

[0130] In the Z-axis direction, the thickness of the sixth semiconductor layer 26 may be smaller than the thickness of each second semiconductor layer 22. In this case, edge breakdown between the sixth semiconductor layer 26 and the third semiconductor layer 23 can be suppressed.

[0131] The semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, and 10G contain silicon. The second conductivity type is N-type. In a semiconductor substrate containing silicon, electrons are multiplied about 20 times more easily than holes. Therefore, by providing the multiplication layer 40 for the N-type second semiconductor layer 22, the multiplication factor can be improved.

[0132] The semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G may contain indium phosphide. In this case, the second conductivity type may be P-type. In a semiconductor substrate containing indium phosphide, holes are more easily multiplied than electrons. Therefore, by providing the multiplication layer 40 for the P-type second semiconductor layer 22, the multiplication factor can be improved.

[0133] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, the multiplication layer 40 is provided in a range of 10 μm or less from the first surface 11 in the Z-axis direction. In this case, it has a configuration that is relatively easy to form. In particular, when the multiplication layer 40 is formed by ion implantation, it can be formed relatively easily.

[0134] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, in the direction along the first surface 11, the width W1 of each second semiconductor layer 22 is larger than 10 μm. In this case, the size of each pixel for detection can be ensured.

[0135] In the APD arrays 1, 1A, 1B, 1C, when viewed from the Z-axis direction, the multiplication layer 40 includes a pair of edges 41a, 41b facing each other. A plurality of second semiconductor layers 22 are arranged in three or more in the facing direction of the pair of edges 41a, 41b. When viewed from the Z-axis direction, in the above-mentioned facing direction, the plurality of second semiconductor layers 22 are located between the pair of edges 41a, 41b. In this case, the variation in gain in each second semiconductor layer 22 can be further suppressed.

[0136] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, when viewed from the Z-axis direction, in the plurality of second semiconductor layers 22, the areas of the regions where each second semiconductor layer 22 overlaps with the multiplication layer 40 are equal to each other. In this case, the variation in gain in each second semiconductor layer 22 can be further suppressed.

[0137] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, when viewed from the Z-axis direction, the edges 41a, 41b, 41c, 41d of the multiplication layer 40 overlap with the metal layer 31 as a shielding member. In this case, the generation of carriers outside the detection target region DA can be suppressed.

[0138] In the APD arrays 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G, when viewed from the Z-axis direction, the width W1 of each second semiconductor layer 22 is larger than the shortest distance L1 between adjacent second semiconductor layers 22. In this case, the directions of the electric lines of force from the second semiconductor layer 22 are gathered, and the generated carriers are easily induced in the second semiconductor layer 22.

[0139] As described above, the embodiments and modifications of the present invention have been explained. However, the present invention is not necessarily limited to the above-described embodiments, and various changes are possible without departing from the gist thereof.

[0140] For example, in the semiconductor substrates 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G, instead of the plurality of sixth semiconductor layers 26, another separator may be included. For example, a shallow trench isolation (STI) or a local oxidation of silicon (LOCOS) structure may be formed. In this case, the STI or LOCOS structure is formed at the position of each sixth semiconductor layer 26. However, in this case, the surface of the semiconductor substrate becomes uneven. When a structure in which a plurality of sixth semiconductor layers 26 are formed is used, the uniformity of the electric field strength in the multiplication layer 40 can be further improved compared to the case where the STI or LOCOS structure is used. When the STI or LOCOS structure is formed after the multiplication layer 40 is formed, the uniformity of the electric field strength in the multiplication layer 40 is improved compared to the case where the STI or LOCOS structure is formed before the multiplication layer 40 is formed.

Explanation of Reference Numerals

[0141] 1, 1A, 1B, 1C, 1D, 1E, 1F, 1G…APD array, 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G…semiconductor substrate, 11…first surface, 12…second surface, 20…semiconductor region, 21…first semiconductor layer, 22…second semiconductor layer, 22b, 25b, 41a, 41b, 41c, 41d…edge, 23…third semiconductor layer, 24…fourth semiconductor layer, 25…fifth semiconductor layer, 26…sixth semiconductor layer, 27, 27C…bonding terminal extension region, 40…multiplication layer, 15…APD, L1, L11, L12…shortest distance, W1…width.

Claims

1. A semiconductor substrate having a first surface and a second surface facing each other, and including a semiconductor region provided on the first surface side, The semiconductor substrate has a plurality of avalanche photodiodes arranged along the first surface, The plurality of avalanche photodiodes, A first semiconductor layer of a first conductivity type provided on the second surface side of the semiconductor region, A plurality of second semiconductor layers of a second conductivity type arranged along the first surface and each surrounded by the semiconductor region when viewed from a direction orthogonal to the first surface, A multiplication layer provided in the semiconductor region and provided between the plurality of second semiconductor layers and the first semiconductor layer in a direction orthogonal to the first surface, When viewed from a direction orthogonal to the first surface, the plurality of second semiconductor layers and the multiplication layer are provided within a range where the first semiconductor layer is located, The multiplication layer includes a third semiconductor layer of a second conductivity type and a fourth semiconductor layer of a first conductivity type facing each other, The third semiconductor layer is provided on the first surface side of the fourth semiconductor layer, Each of the third semiconductor layer and the fourth semiconductor layer is continuously provided so as to overlap the plurality of second semiconductor layers when viewed from a direction orthogonal to the first surface, The semiconductor substrate includes a fifth semiconductor layer of a second conductivity type surrounding the entire region where the plurality of second semiconductor layers are arranged when viewed from a direction orthogonal to the first surface, An avalanche photodiode array in which the third semiconductor layer and the fifth semiconductor layer overlap each other at least in part when viewed from a direction orthogonal to the first surface.

2. The impurity concentration of the first semiconductor layer and the impurity concentration of the fourth semiconductor layer are higher than the impurity concentration of the semiconductor region, The impurity concentration of the first semiconductor layer is higher than the impurity concentration of the fourth semiconductor layer, The avalanche photodiode array according to claim 1, wherein the impurity concentration of each of the second semiconductor layers is higher than the impurity concentration of the third semiconductor layer.

3. The avalanche photodiode array according to claim 1 or 2, wherein, in a direction orthogonal to the first surface, the shortest distance between the first semiconductor layer and the fourth semiconductor layer is greater than the shortest distance between the plurality of second semiconductor layers and the third semiconductor layer.

4. The impurity concentration of the third semiconductor layer is higher than the impurity concentration of the fourth semiconductor layer, the avalanche photodiode array according to any one of claims 1 to 3.

5. Let an arbitrary position from the first surface in the direction orthogonal to the first surface be "x", the impurity concentration of the third semiconductor layer at the arbitrary position "x" be "f(x)", the impurity concentration of the fourth semiconductor layer at the arbitrary position "x" be "g(x)", and the thickness of the third semiconductor layer in the direction orthogonal to the first surface be "L α ", and the thickness of the fourth semiconductor layer in the direction orthogonal to the first surface be "L β ", and when the shortest distance between the first surface and the third semiconductor layer in the direction orthogonal to the first surface is "A" and the shortest distance between the first surface and the fourth semiconductor layer in the direction orthogonal to the first surface is "B", 【Number 1】 The avalanche photodiode array according to any one of claims 1 to 4, which satisfies.

6. When viewed from a direction perpendicular to the first surface, the edge of each of the second semiconductor layers is covered by a junction termination extension region, The junction termination extension region covering each of the second semiconductor layers is a semiconductor of a second conductivity type having an impurity concentration lower than the impurity concentration of the second semiconductor layer, the avalanche photodiode array according to any one of claims 1 to 5.

7. The portion of each of the second semiconductor layers facing the semiconductor region is covered by the junction termination extension region, the avalanche photodiode array according to claim 6.

8. The junction termination extension region covering each of the second semiconductor layers is separated from the multiplication layer, the avalanche photodiode array according to claim 6 or 7.

9. When viewed from a direction perpendicular to the first surface, the edge of the fifth semiconductor layer is covered by a junction termination extension region, The junction termination extension region covering the fifth semiconductor layer is a semiconductor of a second conductivity type having an impurity concentration lower than the impurity concentration of the fifth semiconductor layer, the avalanche photodiode array according to any one of claims 1 to 5.

10. The semiconductor substrate includes a sixth semiconductor layer of a first conductivity type provided between the second semiconductor layers adjacent to each other among the plurality of second semiconductor layers when viewed from a direction perpendicular to the first surface, The impurity concentration of the sixth semiconductor layer is higher than the impurity concentration of the semiconductor region, the avalanche photodiode array according to any one of claims 1 to 9.

11. In the direction perpendicular to the first surface, the thickness of the sixth semiconductor layer is smaller than the thickness of each of the second semiconductor layers, the avalanche photodiode array according to claim 10.

12. The semiconductor substrate includes silicon, The second conductivity type is an N-type, the avalanche photodiode array according to any one of claims 1 to 11.

13. The semiconductor substrate includes indium phosphide, The second conductivity type is a P-type, the avalanche photodiode array according to any one of claims 1 to 11.

14. The avalanche photodiode array according to any one of claims 1 to 13, wherein the multiplication layer is provided in a range of 10 μm or less from the first surface in a direction orthogonal to the first surface.

15. The avalanche photodiode array according to any one of claims 1 to 14, wherein the width of each of the second semiconductor layers is greater than 10 μm in a direction along the first surface.

16. When viewed from a direction orthogonal to the first surface, the multiplication layer includes a pair of edges facing each other, three or more of the plurality of second semiconductor layers are arranged in a direction facing the pair of edges, The avalanche photodiode array according to any one of claims 1 to 15, wherein when viewed from a direction orthogonal to the first surface, in the facing direction, the plurality of second semiconductor layers are located between the pair of edges.

17. The avalanche photodiode array according to any one of claims 1 to 16, wherein when viewed from a direction orthogonal to the first surface, in the plurality of second semiconductor layers, the areas of the regions where each of the second semiconductor layers overlaps with the multiplication layer are equal to each other.

18. The avalanche photodiode array according to any one of claims 1 to 17, wherein when viewed from a direction orthogonal to the first surface, the edge of the multiplication layer overlaps with a shielding member.

19. Each of the avalanche photodiodes is a surface incidence type in which detection light is incident from the first surface or a back surface incidence type in which detection light is incident from the second surface, and the avalanche photodiode array according to any one of claims 1 to 19.

20. The avalanche photodiode array according to any one of claims 1 to 19, wherein when viewed from a direction orthogonal to the first surface, a portion of each of the second semiconductor layers that overlaps with the multiplication layer has a rectangular shape extending in a direction along the first surface.

21. The avalanche photodiode array according to any one of claims 1 to 20, wherein when viewed from a direction orthogonal to the first surface, the width of each of the second semiconductor layers is greater than the shortest distance between the adjacent second semiconductor layers.

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