Semiconductor device

Abstract

To provide a semiconductor device with excellent semiconductor characteristics that are particularly useful for a power device.SOLUTION: A semiconductor device includes a crystalline oxide semiconductor layer and at least one electrode electrically connected to the crystalline oxide semiconductor layer. At least one trench is provided on a first surface of the crystalline oxide semiconductor layer. The trench includes a bottom surface, a side surface, and at least one arc portion between the bottom surface and the side surface. The radius of curvature of the arc portion is in the range of 100 nm to 500 nm. The angle between the side surface and the first surface of the crystalline oxide semiconductor layer is 90° or more.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device useful as a power device or the like and a semiconductor system including the same.

Background Art

[0002] Gallium oxide has attracted attention as a next-generation semiconductor material. Gallium oxide is expected as a material capable of realizing a semiconductor device with a large bandgap, high breakdown voltage, and large current, and various studies have been conducted for the purpose of increasing the reverse breakdown voltage and further reducing the forward turn-on voltage.

[0003] In recent years, semiconductor devices having trenches have been studied. As trench-type semiconductor devices of β-Ga2O3, for example, semiconductor devices described in Patent Documents 1 to 3 are disclosed. Further, as trench-type semiconductor devices of α-Ga2O3, for example, semiconductor devices described in Patent Documents 4 and 5 are disclosed.

[0004] However, when a trench is formed in a crystalline oxide semiconductor such as gallium oxide, since it has etching characteristics different from those of other semiconductor materials, it has been difficult to form an arc portion having a curvature radius of 100 nm or more where electric field relaxation can be expected at the bottom of the trench. For example, when crystalline gallium oxide is forcibly etched under conventional dry etching conditions, unevenness is formed on the bottom surface of the trench, or the width inside the trench becomes wider than the opening of the trench, so that the electric field relaxation effect is not sufficiently exhibited, and there are problems such as an increase in on-resistance.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0006] An object of the present invention is to provide a semiconductor device including a trench having excellent semiconductor characteristics.

Means for Solving the Problems

[0007] As a result of intensive studies to achieve the above object, the inventors of the present invention have formed a trench in a crystalline oxide semiconductor layer by using a specific high-pressure dry etching, including a crystalline oxide semiconductor layer and at least one electrode electrically connected to the crystalline oxide semiconductor layer, having at least one trench on a first surface of the crystalline oxide semiconductor layer, the trench including a bottom surface, a side surface, and at least one arc portion between the bottom surface and the side surface, the radius of curvature of the arc portion being in the range of 100 nm to 500 nm, and the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer being 90° or more, and have succeeded in creating a semiconductor device, and have found that such a semiconductor device can solve the above-described conventional problems all at once. In addition, after obtaining the above findings, the inventors of the present invention have further repeated studies and have completed the present invention.

[0008] [1] A semiconductor device including a crystalline oxide semiconductor layer and at least one electrode electrically connected to the crystalline oxide semiconductor layer, having at least one trench on a first surface of the crystalline oxide semiconductor layer, the trench including a bottom surface, a side surface, and at least one arc portion between the bottom surface and the side surface, the radius of curvature of the arc portion being in the range of 100 nm to 500 nm, and the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer being 90° or more. [2] The semiconductor device according to [1], wherein the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer is 150° or less. [3] The semiconductor device according to [1] or [2], wherein the width of the trench becomes narrower toward the bottom surface of the trench. [4] The semiconductor device according to any one of [1] to [3], wherein the side surface of the trench is tapered. [5] The semiconductor device according to [4], wherein the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer is more than 90° and within the range of 135° or less. [6] The semiconductor device according to any one of [1] to [5], wherein the crystalline oxide semiconductor layer contains at least gallium. [7] The semiconductor device according to any one of [1] to [6], wherein the crystalline oxide semiconductor layer has a corundum structure. [8] The semiconductor device according to any one of [1] to [7], wherein the crystalline oxide semiconductor layer contains two or more of the trenches. [9] The semiconductor device according to any one of [1] to [8], wherein the width of the trench is 2 μm or less.

[10] The semiconductor device according to [9], wherein the crystalline oxide semiconductor layer contains four or more of the trenches.

[11] The semiconductor device according to any one of [1] to

[10] , which is a power device.

[12] The semiconductor device according to any one of [1] to

[11] , which is a vertical device.

[13] The semiconductor device according to any one of [1] to

[12] , which is a diode.

[14] The semiconductor device according to any one of [1] to

[12] , which is a transistor.

[15] The semiconductor device according to any one of [1] to

[12] , which is a junction barrier Schottky diode.

[16] A semiconductor system including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of [1] to

[15] . [Effect of the Invention]

[0009] The semiconductor device of the present invention has at least one arc portion between the bottom surface and the side surface of the trench, the radius of curvature of the arc portion is in the range of 100 nm to 500 nm, and it has excellent semiconductor characteristics.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

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Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16-a

Figure 16-b

Mode for Carrying Out the Invention

[0011] The semiconductor device in the embodiment of the present invention includes a crystalline oxide semiconductor layer and at least one electrode electrically connected to the crystalline oxide semiconductor layer, and has at least one trench on the first surface of the crystalline oxide semiconductor layer. The trench includes a bottom surface, a side surface, and at least one arc portion between the bottom surface and the side surface. The radius of curvature of the arc portion is in the range of 100 nm to 500 nm, and the angle formed between the side surface and the first surface of the crystalline oxide semiconductor layer is 90° or more.

[0012] "Radius of curvature" refers to the radius of the contact circle with respect to the curve of the arc portion in the trench cross-section. The "arc portion" includes not only a part of a perfect circle but also a part of an ellipse, and it only needs to be arc-shaped as a whole. For example, it may be a part of a shape where the corner of a polygon is rounded. That is, the arc portion only needs to be a portion having a curved shape in the trench cross-section, and it may be provided at least in part between the side surface and the bottom surface. For example, an example of the arc portion is shown in FIG. 2. The crystalline oxide semiconductor described in FIG. 2 includes an arc portion 7c having two radii of curvature. In FIG. 2, both R1 and R2 are radii of curvature and are in the range of 100 nm to 500 nm. In an embodiment of the present invention, by setting the radius of curvature within such a range, an excellent electric field relaxation effect can be realized, and as a result, the on-resistance can also be reduced. Also, in an embodiment of the present invention, the trench may have an arc portion throughout between the bottom surface 7b and the side surface 7a of the trench. Further, in an embodiment of the present invention, the difference between the radius of curvature R1 of the first arc portion 7ca between the bottom surface 7b and the first side surface 7aa of the trench 7 and the radius of curvature R2 of the second arc portion 7cb between the bottom surface 7b and the second side surface 7ab of the trench is preferably in the range of 0 to 200 nm, and more preferably in the range of 0 to 50 nm. In an embodiment of the present invention, it is most preferable that the radius of curvature R1 of the first arc portion 7ca is equal to the radius of curvature R2 of the second arc portion 7cb.

[0013] The "angle formed between the side surface and the first surface of the crystalline oxide semiconductor layer" refers to the angle formed between the side surface 7a of the trench provided on the first surface 3a side of the crystalline oxide semiconductor layer 3 and the first surface 3a of the crystalline oxide semiconductor layer in the cross-section of the trench 7. In an embodiment of the present invention, it is usually 90° or more. Examples of such an "angle formed between the side surface and the first surface of the crystalline oxide semiconductor layer" include the angles represented by θ (θ1, θ2) in FIGS. 14 and 16-b. In the present invention, by having the angle θ1 formed between the first side surface 7aa of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer 3 and the angle θ2 formed between the second side surface 7ab of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer 3, an excellent electric field relaxation effect can be realized, and as a result, the on-resistance can also be reduced. Further, the upper limit of the "angle formed between the side surface and the first surface of the crystalline oxide semiconductor layer" is not limited to the like as long as it does not impede the object of the present invention, but is preferably 150°. In an embodiment of the present invention, in the cross-section of the trench, it is preferable that the angle (θ1) formed between the first side surface 7aa of the trench 7 and the first surface 3a of the crystalline oxide semiconductor layer is equal to the angle (θ2) formed with the second side surface 7ab of the trench 7.

[0014] The trench is formed in the crystalline oxide semiconductor layer and is not particularly limited as long as it does not inhibit the object of the present invention. The depth of the trench and the like are also not particularly limited, but in the present invention, the depth of the trench in the trench cross-section is usually 200 nm or more, preferably 500 nm or more, and more preferably 1 μm or more. Note that the upper limit of the depth of the trench is not particularly limited, but is preferably 100 μm, and more preferably 10 μm. Also, the width of the trench in the trench cross-section is not particularly limited, but is usually 200 nm or more, preferably 500 nm or more. Note that the upper limit of the width of the trench is not particularly limited, but is preferably 100 μm, and more preferably 10 μm. According to such a trench in a preferable range, more excellent semiconductor characteristics can be exhibited as a semiconductor device such as a power device. Further, in the trench cross-section, as one embodiment of the present invention, an example in which the width of the trench becomes narrower toward the bottom surface is a preferable example. According to such a preferable example, a good interface can be formed and better electrical characteristics can be obtained, which is preferable. Also, it is preferable that the side surface of the trench is tapered and the side surface has a taper angle with respect to the first surface of the crystalline oxide semiconductor layer. Note that the taper angle is the angle formed by the virtual surface (having no taper shape, so the taper angle is 0°) perpendicular to the first surface and the side surface (having a taper shape) of the trench in the trench cross-section. Examples of the taper angle include the angles represented by θ (θ3, θ4) in FIG. 15. In the present invention, the taper angle is preferably in the range of more than 0° and 45° or less. That is, the angle formed by the side surface and the first surface of the crystalline oxide semiconductor layer (for example, θ1, θ2 shown in FIGS. 14 and 16-b) is preferably in the range of more than 90° and 135° or less. By having such a preferable taper angle, a better channel can be formed, and as a result, the on-resistance can be further reduced.

[0015] Also, the electrode may be a known one, and for example, it may be any of a Schottky electrode, an ohmic electrode, a gate electrode, a drain electrode, a source electrode, etc. The electrode may be a known one appropriately set according to the type of the semiconductor device, etc., and examples of the electrode material include D-block metals. Further, the electrode may be, for example, what is called a barrier electrode. The barrier electrode is not particularly limited as long as it forms a Schottky barrier having a predetermined barrier height at the interface with the semiconductor region. The electrode material of the barrier electrode is not particularly limited as long as it can be used as a barrier electrode, and it may be a conductive inorganic material or a conductive organic material. In the present invention, it is preferable that the electrode material is a metal. The metal is not particularly limited, but preferably, for example, at least one metal selected from Groups 4 to 11 of the periodic table. Examples of the metal of Group 4 of the periodic table include titanium (Ti), zirconium (Zr), hafnium (Hf), etc., and among them, Ti is preferable. Examples of the metal of Group 5 of the periodic table include vanadium (V), niobium (Nb), tantalum (Ta), etc. Examples of the metal of Group 6 of the periodic table include one or more metals selected from chromium (Cr), molybdenum (Mo), tungsten (W), etc., and in the present invention, Cr is preferable because semiconductor characteristics such as switching characteristics become better. Examples of the metal of Group 7 of the periodic table include manganese (Mn), technetium (Tc), rhenium (Re), etc. Examples of the metal of Group 8 of the periodic table include iron (Fe), ruthenium (Ru), osmium (Os), etc. Examples of the metal of Group 9 of the periodic table include cobalt (Co), rhodium (Rh), iridium (Ir), etc. Examples of the metal of Group 10 of the periodic table include nickel (Ni), palladium (Pd), platinum (Pt), etc., and among them, Pt is preferable. Examples of the metal of Group 11 of the periodic table include copper (Cu), silver (Ag), gold (Au), etc. Examples of the means for forming the barrier electrode include, for example, known means, and more specifically, for example, a dry method, a wet method, etc.Examples of the dry method include known means such as sputtering, vacuum evaporation, and CVD. Examples of the wet method include screen printing and die coating.

[0016] The crystalline oxide semiconductor layer is not particularly limited as long as it forms a semiconductor region in the semiconductor device. The crystalline oxide semiconductor layer (hereinafter, also simply referred to as the "semiconductor region") is not particularly limited as long as it contains a semiconductor as a main component. However, in the present invention, it is preferable that the semiconductor region contains a crystalline oxide semiconductor as a main component, and it is more preferable that it is an n-type semiconductor region containing an n-type semiconductor as a main component. The crystalline oxide semiconductor preferably has a β-gallia structure or a corundum structure, and more preferably has a corundum structure. Further, the semiconductor region preferably contains at least gallium, more preferably contains a gallium compound as a main component, still more preferably contains an InAlGaO-based semiconductor as a main component, and most preferably contains α-Ga2O3 or its mixed crystal as a main component. Note that the "main component" means that, for example, when the crystalline oxide semiconductor is α-Ga2O3, it is sufficient if α-Ga2O3 is contained at a ratio of 0.5 or more in terms of the atomic ratio of gallium among the metal elements in the semiconductor region. In the present invention, it is preferable that the atomic ratio of gallium among the metal elements in the semiconductor region is 0.7 or more, and more preferably 0.8 or more. Further, the semiconductor region is usually a single-phase region, but may further have a second semiconductor region composed of a different semiconductor phase or other phases as long as the object of the present invention is not inhibited. Further, the semiconductor region is usually in a film shape and may be a semiconductor film. The thickness of the semiconductor film of the semiconductor region is not particularly limited and may be 1 μm or less or 1 μm or more. However, in the present invention, it is preferably 1 μm to 40 μm, and more preferably 1 μm to 25 μm. The withstand voltage of the crystalline oxide semiconductor layer can be increased, for example, by making it a thick film or lowering the carrier concentration. On the other hand, there has been a trade-off problem that the on-resistance also increases by increasing the thickness or lowering the carrier concentration. According to an embodiment of the present invention, a gallium oxide-based crystalline oxide semiconductor layer containing α-Ga2O3 or β-Ga2O3 has a trench including an arc portion having a curvature radius in the range of 100 nm to 500 nm, and the angle formed by the side surface of the trench and the first surface of the crystalline oxide semiconductor layer is within a range exceeding 90° and equal to or less than 135°, so that an electric field relaxation effect can be sufficiently obtained.According to an embodiment of the present invention, since the above-described electric field relaxation effect can be sufficiently obtained, the thickness of the gallium oxide-based crystalline oxide semiconductor layer (including the drift region) can be made thin (for example, 10 μm or less), and even with such a thickness, a semiconductor device with a high breakdown voltage (for example, 3000 V or more) can be realized. Further, according to an embodiment of the present invention, the thickness of the gallium oxide-based crystalline oxide semiconductor layer (including the drift region) can be made even thinner (for example, 2.0 μm or less), and even with such a thickness, a semiconductor device with a high breakdown voltage (for example, 600 V or more) can be realized. Further, in an embodiment of the present invention, the carrier concentration of the gallium oxide-based crystalline oxide semiconductor layer (including the drift region) can be set to 5.0×10. 16 / cm 3 or more, and preferably 3.0×10 17 / cm 3 or more. The thickness of the crystalline oxide layer and the carrier concentration are appropriately adjusted according to the required breakdown voltage. However, in an embodiment of the present invention, as described above, even with a thinner thickness and a higher carrier concentration than in the prior art, a higher breakdown voltage can be achieved, and as a result, the on-resistance can be reduced. Further, the surface area of the semiconductor film is not particularly limited, and it may be 1 mm 2 or more, or it may be 1 mm 2 or less. Note that the crystalline oxide semiconductor is usually a single crystal, but it may be a polycrystal. Further, the semiconductor film may be a single-layer film or a multilayer film. When the semiconductor film is a multilayer film, it is preferable that the multilayer film has a thickness of 40 μm or less, and is a multilayer film including at least a first semiconductor layer and a second semiconductor layer. When a Schottky electrode is provided on the first semiconductor layer, it is also preferable that the carrier concentration of the first semiconductor layer is smaller than the carrier concentration of the second semiconductor layer. In this case, the second semiconductor layer usually contains a dopant, and the carrier concentration of the semiconductor layer (including the first semiconductor layer and the second semiconductor layer) can be appropriately set by adjusting the doping amount.

[0017] The semiconductor film preferably contains a dopant. The dopant is not particularly limited and may be a known one. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium, or p-type dopants. In the present invention, the dopant is preferably Sn, Ge or Si. The content of the dopant is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic % in the composition of the semiconductor film. In the present invention, it is preferable that the dopant used for the first semiconductor layer is germanium, silicon, titanium, zirconium, vanadium or niobium, and the dopant used for the second semiconductor layer is tin, because the semiconductor characteristics can be further improved without impairing the adhesion.

[0018] The semiconductor film is formed, for example, by means such as mist CVD method. More specifically, for example, a raw material solution is atomized to generate atomized droplets (atomization step), the obtained atomized droplets (including mist) are transported to the substrate with a carrier gas (transport step), and then, the atomized droplets are thermally reacted in the film formation chamber to laminate a semiconductor film mainly composed of a crystalline oxide semiconductor on the substrate (film formation step), whereby it is preferably formed.

[0019] (Atomization step) In the atomization step, the raw material solution is atomized, the atomized droplets are suspended, and atomized droplets are generated. The atomization method of the raw material solution is not particularly limited as long as the raw material solution can be atomized and may be a known means. In the present invention, an atomization method using ultrasonic waves is preferable. The atomized droplets obtained by using ultrasonic waves have an initial velocity of zero and float in the air, so they are preferable. For example, instead of spraying like a spray, they can float in the space and be transported as a gas, so there is no damage due to collision energy, which is preferable. The droplet size is not particularly limited and may be droplets of about several mm, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

[0020] (Raw material solution) The raw material solution is not particularly limited as long as it can be atomized and contains a raw material capable of forming a semiconductor region, and it may be an inorganic material or an organic material. However, in the present invention, it is preferable that the raw material is a metal or a metal compound, and it is more preferable that the raw material contains one or more metals selected from gallium, iron, indium, aluminum, vanadium, titanium, chromium, rhodium, nickel, cobalt, zinc, magnesium, calcium, silicon, yttrium, strontium, and barium.

[0021] In the present invention, as the raw material solution, a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or a salt can be preferably used. Examples of the form of the complex include acetylacetonate complex, carbonyl complex, ammine complex, hydride complex, etc. Examples of the form of the salt include organometallic salts (such as metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphate salts, metal halide salts (such as metal chloride salts, metal bromide salts, metal iodide salts, etc.).

[0022] In addition, it is preferable to mix additives such as hydrohalic acids and oxidizing agents into the raw material solution. Examples of the hydrohalic acid include hydrobromic acid, hydrochloric acid, hydroiodic acid, etc. Among them, hydrobromic acid or hydroiodic acid is preferable because a higher-quality film can be obtained. Examples of the oxidizing agent include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), benzoyl peroxide (C6H5CO)2O2, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, organic peroxides such as peracetic acid and nitrobenzene.

[0023] The raw material solution may contain a dopant. By including a dopant in the raw material solution, doping can be performed well. The dopant is not particularly limited as long as it does not inhibit the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants. The concentration of the dopant is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 and may be such, or the concentration of the dopant may be, for example, reduced to a low concentration of about 1×10 17 / cm 3 or less. Further, according to an embodiment of the present invention, the dopant may be contained at a high concentration of about 1×10 20 / cm 3 or more. In an embodiment of the present invention, it is preferable to contain it at a carrier concentration of 1×10 17 / cm 3 or more. Further, as one of the embodiments of the present invention, in a semiconductor device having a breakdown voltage of 600V, the carrier concentration of the gallium oxide-based crystalline oxide semiconductor layer can be set to 1×10 17 / cm 3 or more and 3×10 17 / cm 3 or less.

[0024] The solvent of the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, it is preferable that the solvent contains water, and more preferably, it is water or a mixed solvent of water and alcohol.

[0025] (Transportation step) In the transfer process, the atomized droplets are transferred into the film formation chamber using a carrier gas. The carrier gas is not particularly limited as long as it does not inhibit the object of the present invention. For example, oxygen, ozone, an inert gas such as nitrogen or argon, or a reducing gas such as hydrogen gas or forming gas are preferable examples. Also, the type of carrier gas may be one type, but may also be two or more types, and a dilution gas with a reduced flow rate (for example, a 10-fold dilution gas, etc.) may be further used as the second carrier gas. Further, the supply location of the carrier gas is not limited to only one location, and may be two or more locations. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 1 to 10 L / min. In the case of the dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, and more preferably 0.1 to 1 L / min.

[0026] (Film formation process) In the film formation process, the semiconductor film is formed on the substrate by thermally reacting the atomized droplets in the film formation chamber. The thermal reaction only needs the atomized droplets to react with heat, and the reaction conditions and the like are not particularly limited as long as they do not inhibit the object of the present invention. In this process, the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent, but preferably at a temperature not too high (for example, 1000 °C) or lower, more preferably 650 °C or lower, and most preferably 300 °C to 650 °C. Also, the thermal reaction may be carried out under any atmosphere of vacuum, non-oxygen atmosphere, reducing gas atmosphere, and oxygen atmosphere as long as it does not inhibit the object of the present invention, but it is preferably carried out under a non-oxygen atmosphere or an oxygen atmosphere. Further, it may be carried out under any conditions of atmospheric pressure, increased pressure, and reduced pressure, but in the present invention, it is preferably carried out under atmospheric pressure. Note that the film thickness can be set by adjusting the film formation time.

[0027] (Substrate) The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is also not particularly limited as long as it does not inhibit the object of the present invention, and it may be a known substrate, an organic compound, or an inorganic compound. The shape of the substrate may be any shape and is effective for any shape. For example, plate-like shapes such as flat plates and discs, fibrous shapes, rod-like shapes, cylindrical shapes, prismatic shapes, tubular shapes, spiral shapes, spherical shapes, ring shapes, etc. can be mentioned. However, in the embodiments of the present invention, a substrate is preferred. The thickness of the substrate is not particularly limited in the present invention.

[0028] The substrate is plate-like and is not particularly limited as long as it serves as a support for the semiconductor film. It may be an insulator substrate, a semiconductor substrate, a metal substrate, or a conductive substrate. However, it is preferred that the substrate is an insulator substrate, and it is also preferred that the substrate has a metal film on its surface. Examples of the substrate include a base substrate containing a substrate material having a corundum structure as a main component, a base substrate containing a substrate material having a β-gallia structure as a main component, and a base substrate containing a substrate material having a hexagonal crystal structure as a main component. Here, "main component" means that the substrate material having the specific crystal structure is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, still more preferably 90% or more, and may be 100% with respect to all components of the substrate material.

[0029] The substrate material is not particularly limited as long as it does not inhibit the object of the present invention and may be a known one. Examples of the substrate material having the corundum structure include, for example, α-Al2O3 (sapphire substrate) or α-Ga2O3, and more preferred examples include an a-plane sapphire substrate, an m-plane sapphire substrate, an r-plane sapphire substrate, a c-plane sapphire substrate, and an α-type gallium oxide substrate (a-plane, m-plane, or r-plane). Examples of the underlying substrate mainly composed of a substrate material having a β-gallium structure include, for example, a β-Ga2O3 substrate or a mixed crystal substrate containing Ga2O3 and Al2O3 and having more than 0 wt% and 60 wt% or less of Al2O3. Examples of the underlying substrate mainly composed of a substrate material having a hexagonal crystal structure include, for example, a SiC substrate, a ZnO substrate, and a GaN substrate.

[0030] In the present invention, annealing treatment may be performed after the film formation step. The annealing treatment temperature is not particularly limited as long as it does not inhibit the object of the present invention, and is usually 300°C to 650°C, preferably 350°C to 550°C. The annealing treatment time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. The annealing treatment may be performed in any atmosphere as long as it does not inhibit the object of the present invention, but is preferably in a non-oxygen atmosphere, and more preferably in a nitrogen atmosphere.

[0031] In an embodiment of the present invention, the semiconductor film may be provided directly on the substrate, or the semiconductor film may be provided via other layers such as a buffer layer (buffer layer) or a stress relaxation layer. The formation means of each layer is not particularly limited and may be a known means, but in the embodiment of the present invention, the mist CVD method is preferred.

[0032] Note that, as one of the embodiments of the present invention, it is preferable that the crystalline oxide semiconductor layer contains at least gallium. Further, as one of the preferred embodiments of the present invention, it is preferable that the crystalline oxide semiconductor layer has a corundum structure. In the embodiments of the present invention, after the semiconductor film is peeled off from the substrate or the like using known means, it may be used as the semiconductor region in a semiconductor device, or may be directly used as the semiconductor region in a semiconductor device. Further, as one of the preferred embodiments of the present invention, it is preferable that the crystalline oxide semiconductor layer contains two or more of the trenches. Further, as one of the preferred embodiments of the present invention, it is preferable that the width of the trench is 2 μm or less, and it is more preferable that the crystalline oxide semiconductor layer contains four or more of the trenches. The plurality of trenches are arranged at intervals on the first surface side of the crystalline oxide semiconductor. According to such an embodiment, a semiconductor device more suitable as a power device can be obtained, and more excellent semiconductor characteristics can be obtained. Further, it is more effective for miniaturization of the semiconductor device. Note that the crystalline oxide semiconductor layer has at least one arc portion between the bottom surface and the side surface of the trench, and the radius of curvature of the arc portion is in the range of 100 nm to 500 nm. However, when the crystalline oxide semiconductor layer has two or more arc portions, it is sufficient that the radius of curvature of at least one arc portion is in the range of 100 nm to 500 nm. In the present invention, when the crystalline oxide semiconductor layer has two or more arc portions, it is preferable that the radius of curvature of the two or more arc portions is in the range of 100 nm to 500 nm, and it is more preferable that the radius of curvature of all the arc portions is in the range of 100 nm to 500 nm.

[0033] The trench can be formed, for example, by a high-pressure dry etching method or the like. More specifically, for example, it includes at least etching a crystalline oxide using a plasma-etched etching gas, and an etching method in which the pressure of the etching gas is in the range of 1 Pa or more and 10 Pa or less. In the etching method, it is preferable that the pressure of the etching gas is 2 Pa or more. It is also preferable that the plasma-etched etching gas contains at least a halogen. It is also preferable that the plasma-etched etching gas contains at least gallium. It is also preferable that the etching is performed in an atmosphere of an inert gas. It is also preferable that the inert gas is argon. It is also preferable that the etching is performed in an atmosphere of a halogen gas. It is also preferable that the bias of the plasma of the etching gas is 25 W or more. By using such a preferable high-pressure etching method, the trench can be easily formed.

[0034] Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings, but the present invention is not limited to these embodiments.

[0035] In an embodiment of the present invention, at least one trench 7 is provided on the first surface 3a side of a crystalline oxide semiconductor layer 3 (also referred to as a semiconductor region). The trench 7 includes a bottom surface, a side surface, and at least one arc portion between the bottom surface and the side surface. Further, the crystalline oxide semiconductor layer 3 is electrically connected to an electrode. In an embodiment of the present invention, it can be applied to a semiconductor device including a trench. For example, FIG. 1 shows a junction barrier Schottky diode (JBS) which is one of the embodiments of the present invention. The semiconductor device of FIG. 1 includes a semiconductor region 3, a barrier electrode 2 provided on the semiconductor region and capable of forming a Schottky barrier with the semiconductor region, and a barrier height adjustment region provided between the barrier electrode 2 and the semiconductor region 3 and capable of forming a Schottky barrier having a barrier height greater than the barrier height of the Schottky barrier of the barrier electrode 2 with the semiconductor region 3. Note that the barrier height adjustment region 1 is embedded in a trench 7 provided on the first surface 3a side of the semiconductor region 3. In an embodiment of the present invention, it is preferable that a plurality of trenches 7 and a plurality of barrier height adjustment regions 1 disposed in the plurality of trenches 7 are provided at regular intervals, and it is more preferable that the barrier height adjustment regions are respectively provided between both ends of the barrier electrode and the semiconductor region. With such a preferable aspect, the JBS is configured to be excellent in thermal stability and adhesion, further reduce leakage current, and have excellent semiconductor characteristics such as breakdown voltage. Note that the semiconductor device of FIG. 1 includes an ohmic electrode 4 on the second surface 3b side of the semiconductor region 3. The semiconductor device of FIG. 1 has an arc portion 7c between the bottom surface 7a and the side surface 7b of the trench 7, and the radius of curvature of the arc portion is in the range of 100 nm to 500 nm, which is excellent in an electric field relaxation effect, and as a result, the on-resistance can be lowered.

[0036] The forming means for each layer of the semiconductor device in FIG. 1 is not particularly limited as long as it does not inhibit the object of the present invention, and may be a known means. For example, after film formation by a vacuum evaporation method, a CVD method, a sputtering method, various coating techniques, etc., means for patterning by a photolithography method, or means for directly patterning using a printing technique, etc. can be mentioned.

[0037] FIG. 9 shows an example of a Schottky barrier diode (SBD) according to an embodiment of the present invention. The SBD in FIG. 9 includes an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a dielectric layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. Further, the SBD in FIG. 9 has a trench 7 having the arc portion, and a p-type semiconductor layer 102 is embedded in such a trench 7.

[0038] The materials of the Schottky electrode and the ohmic electrode may be known electrode materials. Examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, or polypyrrole, or mixtures thereof.

[0039] The formation of the Schottky electrode and the ohmic electrode can be performed by known means such as a vacuum evaporation method or a sputtering method. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al are laminated, and patterning using a photolithography technique can be performed on the layer made of Mo and the layer made of Al.

[0040] When a reverse bias is applied to the SBD of FIG. 9, a depletion layer (not shown) spreads well into the n-type semiconductor layer 101a as the crystalline oxide semiconductor layer due to the stress relaxation effect of the arc portion of the trench 7, resulting in a high breakdown voltage SBD. When a forward bias is applied, electrons flow from the ohmic electrode 105b located on the opposite second surface side of the first surface side of the crystalline oxide semiconductor layer to the Schottky electrode 105a located on the first surface side of the crystalline oxide semiconductor layer. The SBD using such a semiconductor structure is excellent for high breakdown voltage and high current, has a fast switching speed, and is also excellent in breakdown voltage and reliability.

[0041] Examples of the material of the dielectric layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO4, AlN, Hf2O3, SiN, SiON, Al2O3, MgO, GdO, SiO2, or Si3N4. By using such an insulator for the insulator layer, the function of semiconductor characteristics at the interface can be well expressed. The dielectric layer 104 is provided between the n-type semiconductor layer 101 and the Schottky electrode 105a. The formation of the insulator layer can be performed by known means such as sputtering, vacuum evaporation, or CVD.

[0042] FIG. 10 shows an example of a trench-type Schottky barrier diode (SBD) including an n-type semiconductor layer 101a as a crystalline oxide semiconductor layer, the n-type semiconductor layer 101a having two or more trenches 7 disposed on the first surface side of the n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a dielectric layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. The trench-type SBD of FIG. 10 has a trench structure including the arc portion. According to such a trench-type SBD, the leakage current can be significantly reduced while maintaining a higher breakdown voltage, and as a result, a significant reduction in on-resistance is also possible.

[0043] FIG. 11 shows an example of a junction barrier Schottky diode (JBS) including an n-type semiconductor layer 101a, an n+-type semiconductor layer 101b, a p-type semiconductor layer 102, a dielectric layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. The JBS in FIG. 11 has a trench 7 having the arc portion, and the p-type semiconductor layer 102 is embedded in the trench 7. According to such a JBS, it is possible to significantly reduce the leakage current while maintaining a higher breakdown voltage than the trench-type SBD in FIG. 10, and as a result, it is also possible to further significantly reduce the on-resistance.

[0044] An example in the case where the semiconductor device of the present invention is a MOSFET is shown in FIG. 12. The MOSFET in FIG. 12 is a trench-type MOSFET, and is an n-type semiconductor layer 131a as a crystalline oxide semiconductor layer, and includes the n-type semiconductor layer 131a including the trench 7, n+-type semiconductor layers 131b and 131c, a gate insulating film 134, and a gate electrode 135a, a source electrode 135b, and a drain electrode 135c.

[0045] An n+-type semiconductor layer 131b having a thickness of, for example, 100 nm to 100 μm is formed on the drain electrode 135c, and an n-type semiconductor layer 131a having a thickness of, for example, 100 nm to 100 μm is formed on the n+-type semiconductor layer 131b. Further, an n+-type semiconductor layer 131c is formed on the n-type semiconductor layer 131a, and a source electrode 135b is formed on the n+-type semiconductor layer 131c.

[0046] In addition, a plurality of trenches 7 having a depth that penetrates the n+ semiconductor layer 131c and reaches halfway through the n-type semiconductor layer 131a are formed as grooves in the n-type semiconductor layer 131a and the n+-type semiconductor layer 131c. Each of the trenches 7 has the arc portion between the bottom surface and the side surface of the trench 7. A gate electrode 135a is embedded and formed in the trench 7 via a gate insulating film 134 having a thickness of, for example, 10 nm to 1 μm.

[0047] In the on-state of the MOSFET in FIG. 12, when a voltage is applied between the source electrode 135b and the drain electrode 135c and a positive voltage is applied to the gate electrode 135a with respect to the source electrode 135b, a channel layer is formed on the side surface of the n-type semiconductor layer 131a, electrons are injected into the n-type semiconductor layer, and it turns on. The off-state is achieved by setting the voltage of the gate electrode to 0V, which causes the channel layer to disappear, the n-type semiconductor layer to be filled with depletion layers, and it turns off.

[0048] Known means can be appropriately used in the manufacture of the MOSFET in FIG. 12. For example, an etching mask is provided in a predetermined region of the n-type semiconductor layer 131a and the n+-type semiconductor layer 131c, and etching is performed by the above-described preferred high-pressure dry etching method to form a groove of the trench 7 with a depth reaching from the surface of the n+-type semiconductor layer 131c to the middle of the n-type semiconductor layer 131a together with the arc portion. Next, using known means such as thermal oxidation method, vacuum evaporation method, sputtering method, CVD method, etc., a gate insulating film 134 with a thickness of, for example, 50 nm to 1 μm is formed on the side surface and bottom surface of the groove of the trench 7. Then, using CVD method, vacuum evaporation method, sputtering method, etc., a gate electrode material such as polysilicon is formed in the groove of the trench 7 to a thickness not exceeding that of the n-type semiconductor layer. And by forming a source electrode 135b on the n+-type semiconductor layer 131c and a drain electrode 135c on the n+-type semiconductor layer 131b respectively using known means such as vacuum evaporation method, sputtering method, CVD method, etc., a power MOSFET can be manufactured. Note that the electrode materials of the source electrode and the drain electrode may be known electrode materials respectively. Examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or mixtures thereof.

[0049] The MOSFET obtained in this way has even better breakdown voltage characteristics than conventional trench MOSFETs. In FIG. 12, an example of a trench-type vertical MOSFET is shown, but the present invention is not limited to this and can be applied to various forms of trench MOSFETs. For example, the depth of the trench 7 in FIG. 12 may be dug down to reach the bottom surface of the n-type semiconductor layer 131a to reduce the series resistance. Another example of a trench MOSFET is shown in FIG. 13.

[0050] FIG. 13 shows an example of a metal-oxide-semiconductor field-effect transistor (MOSFET) including an n-type semiconductor layer 131a, a first n+-type semiconductor layer 131b, a second n+-type semiconductor layer 131c, a p-type semiconductor layer 132, a p+-type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. Note that the p+-type semiconductor layer 132a may be a p-type semiconductor layer or may be the same as the p-type semiconductor layer 132.

[0051] The semiconductor device is particularly useful for power devices. Also, as one embodiment of the present invention, the semiconductor device is preferably a vertical device. Examples of the semiconductor device include, for example, a diode or a transistor (e.g., MESFET, etc.), but among them, a diode is preferred, and a junction barrier Schottky diode (JBS) is more preferred.

[0052] In addition to the above-described matters, the semiconductor device of the present invention can be preferably used as a power module, an inverter, or a converter by using known means, and further, for example, it can be preferably used in a semiconductor system using a power supply device. The power supply device can be produced from or as the semiconductor device by connecting it to a wiring pattern or the like using known means. FIG. 3 shows a power supply system 170 configured using a plurality of the power supply devices 171 and 172 and a control circuit 173. As shown in FIG. 4, the power supply system can be used in a system device 180 by combining an electronic circuit 181 and a power supply system 182. Note that an example of a power circuit diagram of the power supply device is shown in FIG. 5. FIG. 5 shows a power circuit of a power supply device including a power circuit and a control circuit. After switching a DC voltage at a high frequency by an inverter 192 (configured by MOSFETs A to D) and converting it to AC, insulation and voltage conversion are performed by a transformer 193, rectification is performed by a rectifying MOSFET 194 (A to B'), and smoothing is performed by a DCL 195 (smoothing coils L1 and L2) and a capacitor to output a DC voltage. At this time, the output voltage is compared with a reference voltage by a voltage comparator 197, and the inverter 192 and the rectifying MOSFET 194 are controlled by a PWM control circuit 196 so as to obtain a desired output voltage.

Example

[0053] (Example 1) 1. Formation of semiconductor layer 1-1. Film forming apparatus Using FIG. 6, the mist CVD apparatus 19 used in the examples will be described. The film formation apparatus 19 in FIG. 6 includes a carrier gas source 22a that supplies a carrier gas, a flow rate adjustment valve 23a for adjusting the flow rate of the carrier gas sent out from the carrier gas source 22a, a carrier gas (dilution) source 22b that supplies a carrier gas (dilution), a flow rate adjustment valve 23b for adjusting the flow rate of the carrier gas (dilution) sent out from the carrier gas (dilution) source 22b, a mist generation source 24 that houses the raw material solution 24a, a container 25 that contains water 25a, an ultrasonic vibrator 26 attached to the bottom surface of the container 25, a film formation chamber 30, a quartz supply pipe 27 that connects the mist generation source 24 to the film formation chamber 30, and a hot plate (heater) 28 installed in the film formation chamber 30. A substrate 20 is installed on the hot plate 28.

[0054] 1-2. Preparation of the raw material solution An aqueous solution of 0.1M gallium bromide was made to contain 10% hydrobromic acid by volume ratio, and this was used as the raw material solution.

[0055] 1-3. Film formation preparation The raw material solution 24a obtained in 1-2. above was housed in the mist generation source 24. Next, as the substrate 20, a sapphire substrate was placed on the susceptor 21, and the heater 28 was operated to raise the temperature in the film formation chamber 30 to 630°C. Next, the flow rate adjustment valves 23a and 23b were opened, and carrier gas was supplied from the carrier gas supply means 22a and 22b, which are carrier gas sources, into the film formation chamber 30. After sufficiently replacing the atmosphere in the film formation chamber 30 with the carrier gas, the flow rate of the carrier gas was adjusted to 1 L / min, and the flow rate of the carrier gas (dilution) was adjusted to 2 L / min. Nitrogen was used as the carrier gas.

[0056] 1-4. Semiconductor film formation Next, the ultrasonic oscillator 26 was vibrated at 2.4 MHz, and the vibration was propagated through the water 25a to the raw material solution 24a, thereby atomizing the raw material solution 24a to generate a mist. This mist was introduced into the film formation chamber 30 by the carrier gas, and the mist reacted in the film formation chamber 30 at 630 °C under atmospheric pressure, and a semiconductor film was formed on the substrate 20. The film thickness was 4.1 μm, and the film formation time was 105 minutes.

[0057] 1-5. Evaluation When the phase of the film obtained in the above 1-4. was identified using an XRD diffractometer, the obtained film was α-Ga2O3.

[0058] 2. Etching Under the conditions shown in Table 1 below, trenches were formed in the semiconductor film using an ICP-RIE apparatus. All the trenches in the examples had an arc portion, and the radius of curvature of the arc portion was in the range of 100 nm or more and 500 nm or less. A cross-sectional photograph of the trench formed as Example 1 is shown in FIG. 7. As shown in FIG. 7, the radius of curvature of Example 1 was R1 (left side) = 140 nm and R2 (right side) = 160 nm. Also, the side surface of the trench had a taper angle, and the taper angle was 60°. As is clear from FIG. 7, a good trench was formed.

[0059]

Table 1

[0060] (Example 2) Trenches were formed in the same manner as in Example 1 except that etching was performed under the conditions shown in Table 1. A cross-sectional photograph of the obtained trench is shown in FIG. 8. As shown in FIG. 8, the radius of curvature of the arc portion of the trench was R1 (left side) = 125 nm and R2 (right side) = 298 nm. As is clear from FIG. 8, a trench having a high-quality arc portion was formed.

[0061]

Table 2

[0062] (Example 3) A trench was formed in the semiconductor film (also referred to as a crystalline oxide semiconductor layer) in the same manner as in Example 1, except that etching was performed under the conditions shown in Table 2. A cross-sectional photograph of the obtained trench is shown in Fig. 16-a. Also, Fig. 16-b shows an explanatory diagram using the same cross-sectional photograph. The radius of curvature R1 (left side) of the first arc portion 7ca of the trench 7 was 220 nm, and the radius of curvature R2 (right side) of the second arc portion 7cb was also 220 nm. A plurality of trenches 7 were formed in the crystalline oxide semiconductor layer 3, and in each trench 7, a trench 7 having the same radius of curvature for the first arc portion 7ca and the second arc portion 7cb was formed. The width of the trench 7 becomes narrower toward the bottom surface. In the cross-section of the trench, the angle (θ1 shown in Fig. 16-b) formed by the side surface 7a (the first side surface 7aa) of the trench and the first surface 3a of the crystalline oxide semiconductor layer 3 is within a range exceeding 90° and equal to or less than 135°, and the angle (θ2 shown in Fig. 16-b) formed by the side surface 7a (the second side surface 7ab) of the trench and the first surface 3a of the crystalline oxide semiconductor layer 3 is within a range exceeding 90° and equal to or less than 135°. Note that SiO2 shown in Fig. 16-b is a mask, which was provided on the crystalline oxide semiconductor layer 3 to form a trench by etching and was finally removed. Also, when the flow rate of BCl3 was changed to obtain a crystalline oxide semiconductor layer, it was found that a trench having a better arc portion could be obtained by setting it within the range of 50 sccm to 100 sccm.

[0063] According to Examples 1 to 3 of the present invention, in the cross-section of the trench, there is a trench including an arc portion having a radius of curvature within the range of 100 nm to 500 nm, and the angle formed by the side surface of the trench and the first surface of the crystalline oxide semiconductor layer is within a range exceeding 90° and equal to or less than 135°, so that an electric field relaxation effect can be sufficiently obtained. As a result, it becomes possible to reduce the on-resistance of a semiconductor device having a gallium oxide-based crystalline oxide semiconductor layer. Also, according to Example 3, since it is possible to form a trench having arc portions with symmetric radii of curvature in the gallium oxide-based crystalline oxide semiconductor layer, it can be expected to further reduce the on-resistance of the semiconductor device.

[0064] (Comparative Example 1) A trench was formed in the same manner as in Example 1, except that etching was performed under the conditions shown in Table 1. The obtained trench had a convex bottom surface, and a non-quality trench was formed with a corner at the boundary between the bottom surface and the side surface.

[0065] (Comparative Example 2) A trench was formed in the same manner as in Example 1, except that etching was performed under the conditions shown in Table 1. The obtained trench had a reverse-tapered and grooved side surface, and the width inside the trench was wider than that at the opening of the trench. In addition, an arc portion was formed between the bottom surface and the side surface, but the arc portion protruded largely and the radius of curvature was 1 μm or more, resulting in the formation of a non-quality trench.

Industrial Applicability

[0066] The semiconductor device of the present invention can be used in various fields such as semiconductors (e.g., compound semiconductor electronic devices, etc.), electronic component and electrical equipment components, optical and electrophotographic related devices, and industrial members. In particular, it is useful for power devices.

Explanation of Signs

[0067] 1 Barrier height adjustment region 2 Barrier electrode 3 Crystalline oxide semiconductor layer (semiconductor region) 3a First surface 3b Second surface 4 Ohmic electrode 7 Trench 7a Side surface of trench 7aa First side surface of trench 7aa Second side surface of trench 7b Bottom surface of trench 7c Arc portion of trench 7ca First arc portion of trench 7cb Second arc portion of trench 19 Mist CVD apparatus (film forming apparatus) 20 Substrate 21 susceptor 22a carrier gas supply means 22b carrier gas (diluted) supply means 23a carrier gas flow control valve 23b carrier gas (diluted) flow control valve 24 mist generation source 24a raw material solution 25 container 25a water 26 ultrasonic vibrator 27 supply pipe 28 heater 29 exhaust port 30 film forming chamber 101a n-type semiconductor layer 101b n+-type semiconductor layer 102 p-type semiconductor layer 103 metal layer 104 dielectric layer 105a Schottky electrode 105b ohmic electrode 131a n-type semiconductor layer 131b first n+-type semiconductor layer 131c second n+-type semiconductor layer 132 p-type semiconductor layer 132a p+-type semiconductor layer 134 gate insulating film 135a gate electrode 135b source electrode 135c drain electrode 170 power supply system 171 power supply device 172 power supply device 173 control circuit 180 system device 181 electronic circuit 182 power supply system 192 inverter 193 transformer 194 rectifying MOSFET 195 DCL 196 PWM control circuit 197 voltage comparator

Claims

1. A semiconductor device comprising a crystalline oxide semiconductor layer and at least one electrode electrically connected to the crystalline oxide semiconductor layer, having at least one trench on a first surface of the crystalline oxide semiconductor layer, the trench including a bottom surface, a first side surface, a second side surface, a first arc portion between the bottom surface and the first side surface, and a second arc portion between the bottom surface and the second side surface, each of the first arc portion and the second arc portion having a curvature radius of 100 nm or more, a first angle formed by the first side surface and the first surface of the crystalline oxide semiconductor layer, and a second angle formed by the second side surface and the first surface being 90° or more, and a difference between the curvature radius of the first arc portion and the curvature radius of the second arc portion being 0 nm to 200 nm.

2. A semiconductor system comprising the semiconductor device according to Claim 1.

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