Display device

Abstract

To provide a display device.SOLUTION: A display device comprises: at least two flat layers which cover a thin film transistor arranged on an active region of a substrate; a signal link arranged on a non-active region of the substrate; and an outline cover layer overlapped on an upper surface and side surfaces of the signal link, therefore in the display device, damage on the signal link and a protection film on the signal link can be prevented.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] The present invention relates to a display device, and particularly to providing a display device capable of realizing high definition and high resolution.

Background Art

[0002] Video display devices that embody various information on a screen are developing in the direction of being thinner, lighter, portable, and high-performance by the core technology of the information communication era. Therefore, an organic light-emitting display device that can reduce the weight and volume, which are the disadvantages of a cathode ray tube (CRT), has been in the spotlight. This organic light-emitting display device (OLED) is a self-luminous element and has low power consumption, a high response speed, high luminous efficiency, high brightness, and a wide viewing angle. This organic light-emitting display device embodies an image by a large number of sub-pixels arranged in a matrix. Each of the large number of sub-pixels includes a light-emitting element and a pixel circuit including a large number of transistors that independently drive the light-emitting element.

[0003] As such an organic light-emitting display device becomes more high-definition and high-resolution, the load on each signal line and each electrode becomes very large, and the RC (resistance-capacitance) delay that affects the image quality and driving characteristics gradually increases. In particular, there has been a problem that signal delay due to the RC load between the light-emitting element and the transistor occurs, and a driving signal cannot be accurately applied to each sub-pixel.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention is for solving the above problems, and provides a display device capable of realizing high definition and high resolution.

Means for Solving the Problems

[0006] In order to achieve the above object, the organic display device according to the present invention includes a substrate having an active region and a non-active region, a thin film transistor disposed on the active region of the substrate, at least two planarization layers disposed on top of the thin film transistor, a signal link disposed on the non-active region of the substrate, and an outer cover layer overlapping the upper surface and side surfaces of the signal link, whereby high definition and high resolution can be realized and damage to the signal link and the protective film on the signal link can be prevented.

[0007] In some embodiments, the first outer cover layer is spaced apart from the at least two planarization layers. In some embodiments, the at least two planarization layers include a first planarization layer disposed on a protective film covering the thin film transistor and a second planarization layer disposed on the first planarization layer. In some embodiments, the thin film transistor further includes a pixel connection electrode connected to the drain electrode of the thin film transistor and disposed between the first and second planarization layers. In some embodiments, the pixel connection electrode is made of the same material as the drain electrode.

[0008] In some embodiments, each of the signal links includes a lower link made of the same material as the gate electrode of the thin film transistor and on the same plane as the gate electrode, and an upper link made of the same material as the source and drain electrodes of the thin film transistor and connected to the lower link on the same plane as the source and drain electrodes. The first outer cover layer is disposed on the protective film with the same material as the first planarization layer, and the protective film is disposed on the upper link. In some embodiments, the interlayer insulating film disposed between the source and drain electrodes and the gate electrode further includes at least one link contact hole that exposes the lower link, the upper link is connected to the lower link through the at least one link contact hole, and the first outer cover layer overlaps the link contact hole.

[0009] In some embodiments, it further comprises a conductive pad connected to the signal link, a light-emitting element connected to the thin-film transistor, a sealing unit disposed on the light-emitting element, at least one dam disposed between the conductive pad and the light-emitting element, and a second outer cover layer disposed between the at least one dam and the conductive pad. The sealing unit comprises an organic sealing layer, a first inorganic sealing layer, and a second inorganic sealing layer, and the first and second inorganic sealing layers are made of an inorganic insulating material. The second outer cover layer has a line width wider than that of the signal link above the signal link. The signal link is made of the same material as the source and drain electrodes of the thin-film transistor, and the second outer cover layer is made of the same material as the pixel connection electrode in the same layer as the pixel connection electrode.

[0010] In some embodiments, it further comprises a third outer cover layer having a line width wider than that of the second outer cover layer on the second outer cover layer, and the third outer cover layer is made of the same material as the second planarization layer. It further comprises a high-voltage supply line including first and second high-voltage supply lines connected through a line contact hole penetrating the protective film and the first planarization layer. In some embodiments, it further comprises a pixel connection electrode disposed between the first planarization layer and the second planarization layer, the first high-voltage supply line is made of the same material as the source and drain electrodes of the thin-film transistor on the same plane as the source and drain electrodes, and the second high-voltage supply line is made of the same material as the pixel connection electrode on the same plane as the pixel connection electrode.

[0011] In some embodiments, the first outer cover layer includes a number of first outer cover layer portions corresponding to each of a number of signal links within the signal link. In some embodiments, each of the number of first outer cover layer portions has a flat upper surface or a stepped upper surface on the signal link.

[0012] In some embodiments, the display device includes a substrate, a thin film transistor, a conductive pad, a first link, and a first outer cover layer. The substrate has an active region and a non-active region. The thin film transistor is disposed on the active region of the substrate. The conductive pad is disposed in the non-active region of the substrate. The first link is disposed in the non-active region of the substrate and is electrically connected to the conductive pad. The first link includes a first end portion that is electrically connected to an electrode of the thin film transistor in the active region of the substrate and a second end portion that is electrically connected to the first link in the non-active region of the substrate. The first outer cover layer covers an upper surface and one or more side surfaces of the signal link region when the first and second links overlap as viewed from the plane of the substrate.

[0013] In some embodiments, the first link is located in a first layer of the substrate, and the second link is located in a second layer.

[0014] In some embodiments, an interlayer insulating film between the first link and the second link is further provided. The first link and the second link are electrically connected through a hole in the interlayer insulating film.

[0015] In some embodiments, the first link has a first width, the second link has a second width that is wider than the first width in the signal link region when the first and second links overlap, and the first outer cover layer has a third width that is wider than the second width.

[0016] In some embodiments, the first link is made of the same material as the gate electrode of the thin film transistor and on the same layer as the gate electrode, and the second link is made of the same material as the source and drain electrodes of the thin film transistor and on the same layer as the source and drain electrodes. In some embodiments, a planarization layer covering the thin film transistor is further provided, and the first outer cover layer is made of the same material as the planarization layer.

[0017] In some embodiments, a first planarization layer covering the thin film transistor and a pixel connection electrode electrically connected to the drain electrode of the thin film transistor through a hole in the first planarization layer are provided. The first outer cover layer is made of the same material as the pixel connection electrode. In some embodiments, the substrate includes a second planarization layer covering the pixel connection electrode and the first planarization layer, and a second outer cover layer covering the upper surface and the side surface of the first outer cover layer, and the second outer cover layer is made of the same material as the second planarization layer.

[0018] In some embodiments, the display device further includes a light emitting element, a sealing unit, at least one dam, and a second outer cover layer. The light emitting element is disposed in the active region and connected to the thin film transistor. The sealing unit is disposed on the light emitting element. At least one dam is disposed between the conductive pad and the light emitting element. The second outer cover layer is disposed between the at least one dam and the conductive pad.

Advantages of the Invention

[0019] In the present disclosure, the drain electrode of the thin film transistor is connected to the anode electrode of the light emitting element through a pixel connection electrode made of a material with low specific resistance. Thereby, the present invention can reduce the signal delay due to the RC load between the light emitting element and the thin film transistor, and can implement high definition and high resolution.

[0020] Further, in the present disclosure, an outer cover layer overlapping the step portion on the side surface of the signal link and the step portion generated by the link contact hole connecting the signal links is provided. Thereby, the present disclosure can prevent the loss of the protective film covering the signal link, the elution of the signal link, and the chip defect of the conductive material during the etching process for forming the pixel connection electrode.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2A

Figure 2B

Figure 3

Figure 4A

Figure 4B

Figure 5A

Figure 5B

Figure 6A

Figure 6B

Figure 7

Figure 8

[0022] Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

[0023] FIG. 1 is a plan view showing an organic light-emitting display device according to the present invention, and FIGS. 2A and 2B are cross-sectional views showing the organic light-emitting display device taken along lines "I-I'" and "II-II'" in FIG. 1.

[0024] The organic light-emitting display device shown in FIGS. 1, 2A, and 2B is divided into an active area AA provided on a substrate 101 and a non-active area NA disposed around the active area AA.

[0025] A large number of sub-pixels are arranged in a matrix in the active area AA to display an image. Each sub-pixel includes a pixel driving circuit and a light-emitting element 130 connected to the pixel driving circuit.

[0026] The pixel driving circuit includes a switching transistor TS, a driving transistor TD, and a storage capacitor (not shown, Cst). While a structure in which the pixel driving circuit includes two transistors TS and TD and one capacitor C will be described, the present invention is not limited thereto.

[0027] When a scan pulse is supplied to the scan line SL, the switching transistor TS is turned on, and supplies the data signal supplied to the data line DL to the storage capacitor Cst and the gate electrode 102 of the driving transistor TD. For this purpose, as shown in FIG. 1, the switching transistor TS includes a gate electrode GE connected to the scan line SL, a source electrode SE connected to the data line DL, a drain electrode DE connected to the driving transistor, and a semiconductor layer ACT that forms a channel between the source electrode and the drain electrode.

[0028] The driving transistor TD controls the current supplied from the high-voltage (VDD) supply line VL to the light-emitting element 130 in response to the data signal supplied to the gate electrode 102 of the driving transistor TD, thereby adjusting the light emission amount of the light-emitting element 130. Even when the switching transistor TS is turned off, the driving transistor TD supplies a constant current by the voltage charged in the storage capacitor Cst until the data signal of the next frame is supplied, and maintains the light emission of the light-emitting element 130.

[0029] Therefore, as shown in FIGS. 1, 2A, and 2B, the driving transistor TD includes a semiconductor layer 104 disposed on the active buffer layer 114, a gate electrode 102 overlapping the semiconductor layer 104 via a gate insulating film 112, and source and drain electrodes 106 and 108 formed on the interlayer insulating film 116 and in contact with the semiconductor layer 104. In other words, an overlap can refer to two elements that at least partially occupy the same space in a plan view. An overlap does not require direct physical contact between the two elements.

[0030] The semiconductor layer 104 is formed of at least one of an amorphous semiconductor material, a polycrystalline semiconductor material, and an oxide semiconductor material. The semiconductor layer 104 is formed on the active buffer layer 114. Such a semiconductor layer 104 includes a channel region, a source region, and a drain region. The channel region overlaps the gate electrode 102 via the gate insulating film 112 to form a channel region between the source and drain electrodes 106 and 108. The source region is electrically connected to the source electrode 106 through a source contact hole 110S that penetrates the gate insulating film 112 and the interlayer insulating film 116. The drain region is electrically connected to the drain electrode 108 through a drain contact hole 110D that penetrates the gate insulating film 112 and the interlayer insulating film 116. A multi-buffer layer 140 and an active buffer layer 114 are disposed between such a semiconductor layer 104 and the substrate 101. The multi-buffer layer 140 delays the diffusion of moisture and / or oxygen that has penetrated into the substrate 101. The active buffer layer 114 has a function of protecting the semiconductor layer 104 and blocking various defects taken in by the substrate 101.

[0031] At this time, the uppermost layer of the multi-buffer layer 140 in contact with the active buffer layer 114 is formed of a material having etching characteristics different from those of the remaining layers of the multi-buffer layer 140, the active buffer layer 114, the gate insulating film 112, and the interlayer insulating film 116. The uppermost layer of the multi-buffer layer 140 in contact with the active buffer layer 114 is formed of either SiNx or SiOx, and the remaining layers of the multi-buffer layer 140, the active buffer layer 114, the gate insulating film 112, and the interlayer insulating film 116 are formed of the other of SiNx and SiOx. For example, the uppermost layer of the multi-buffer layer 140 in contact with the active buffer layer 114 is formed of SiNx, and the remaining layers of the multi-buffer layer 140, the active buffer layer 114, the gate insulating film 112, and the interlayer insulating film 116 are formed of SiOx.

[0032] The gate electrode 102 is formed on the gate insulating film 112 and overlaps with the channel region of the semiconductor layer 104 through the gate insulating film 112. The gate electrode 102 is formed of a first conductive material that is a single layer or a multilayer made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0033] The source electrode 106 is connected to the source region of the semiconductor layer 104 exposed through the source contact hole 110S that penetrates the gate insulating film 112 and the interlayer insulating film 116. The drain electrode 108 faces the source electrode 106 and is connected to the drain region of the semiconductor layer 104 through the drain contact hole 110D that penetrates the gate insulating film 112 and the interlayer insulating film 116. Such source and drain electrodes 106 and 108 are formed of a second conductive material that is a single layer or a multilayer made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0034] The pixel connection electrode 142 is disposed between the first and second planarization layers 128 and 148. The pixel connection electrode 142 is exposed through a first pixel contact hole 150 that penetrates the protective film 118 and the first planarization layer 128 and is connected to the drain electrode 108. This pixel connection electrode 142 is made of a material with low specific resistance, the same as or similar to the drain electrode 108. The material with low specific resistance refers to a material with low resistivity. Here, the material with low specific resistance may be a metal.

[0035] On the other hand, the high-potential supply line VL arranged in parallel with the data line DL includes first and second high-potential supply lines VL1 and VL2 connected through a line contact hole 180 that penetrates the protective film 118 and the first planarization layer 128. The first high-potential supply line VL1 is arranged on the same plane (for example, in the same layer) with the same material as the source and drain electrodes 106 and 108 of the driving transistor TD, and the second high-potential supply line VL2 is arranged on the same plane with the same material as the pixel connection electrode 142. For example, the second high-potential supply line VL2 and the pixel connection electrode 142 are formed of a conductive substance that is a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof. Here, the conductive substance may sometimes be referred to as the third conductive substance.

[0036] In this way, the high-potential supply line VL of the present invention can reduce the self-resistance of the high-potential supply line VL by including the first and second high-potential supply lines VL2 electrically connected through the line contact hole 180, and the RC time constant is reduced. As a result, it is possible to prevent the transmission of the high-potential voltage (VDD) from the high-potential supply line VL to the source electrode 106 of the driving transistor TD from being delayed, and it becomes possible to implement high resolution and high definition.

[0037] The light-emitting element 130 includes an anode electrode 132, at least one light-emitting stack 134 formed on the anode electrode 132, and a cathode electrode 136 formed on at least one light-emitting stack 134.

[0038] The anode electrode 132 is electrically connected to the pixel connection electrode 142 exposed through the second pixel contact hole 120 that penetrates the second planarization layer 148 disposed on the first planarization layer 128.

[0039] The anode electrode 132 of each sub-pixel is formed to be exposed by the bank 138. Such a bank 138 may be formed of an opaque material (for example, a black member) so as to prevent light interference between adjacent sub-pixels. In this case, the bank 138 includes a light-shielding material composed of at least any one of a color pigment, an organic black pigment, and carbon.

[0040] At least one light-emitting stack 134 is formed on the anode electrode 132 in the light-emitting region provided by the bank 138. At least one light-emitting stack 134 is formed by laminating a hole-related layer, an organic light-emitting layer, and an electron-related layer in this order or in the reverse order on the anode electrode 132. In addition, the light-emitting stack 134 may include first and second light-emitting stacks facing each other with a charge generation layer interposed therebetween. In this case, the organic light-emitting layer in either the first or second light-emitting stack generates blue light, and the organic light-emitting layer in the other of the first and second light-emitting stacks generates yellow-green light, so that white light is generated by the first and second light-emitting stacks. The white light generated by this light-emitting stack 134 is incident on a color filter located above or below the light-emitting stack 134, and a color image can be realized. In addition, without another color filter, each light-emitting stack 134 may generate color light corresponding to each sub-pixel and realize a color image. That is, the light-emitting stack 134 of the red (R) sub-pixel may generate red light, the light-emitting stack 134 of the green (G) sub-pixel may generate green light, and the light-emitting stack 134 of the blue (B) sub-pixel may generate blue light.

[0041] The cathode electrode 136 is formed to face the anode electrode 132 with at least one light-emitting stack 134 interposed therebetween and is connected to a low voltage (VSS) supply line.

[0042] In the non-active region NA, a data pad DP connected to a data line DL, a scan pad SP connected to a scan line SL, and a power supply pad (not shown) connected to each of a low voltage (VSS) supply line and a high voltage (VDD) supply line are arranged. Such data pad DP, scan pad SP, and power supply pad may be arranged in the non-active region NA arranged in at least one of one side and the other side regions of the substrate 101, or may be arranged in non-active regions NA different from each other. On the other hand, the data pad DP, the scan pad SP, and the power supply pad are not limited to the structure of FIG. 1 and can be variously changed according to the design matters of the display device.

[0043] At least one of such data pad DP, scan pad SP, and power supply pad is connected to the corresponding signal line through a signal link. The signal link may include a lower link 122 and an upper link 124 as shown in FIGS. 1, 2A, and 2B. The signal link may be referred to as a "signal link region" here. The signal link includes a region where the lower link 122 and the upper link 124 overlap when viewed from the plane of the substrate 101.

[0044] The lower link 122 extends from either the conductive pad or the signal line, and the upper link 124 extends from the other of the conductive pad and the signal line.

[0045] Such a lower link 122 is exposed through at least one link contact hole 126 penetrating at least one layer of the interlayer insulating film 116 disposed between the source and drain electrodes 106, 108 and the gate electrode 102 and is connected to the upper link 124. The lower link 122 is made of the same material as the gate electrode 102 of the driving transistor TD and is disposed on the same plane (for example, the gate insulating film 112), and the upper link 124 is made of the same material as the source and drain electrodes 106, 108 of the driving transistor TD and is disposed on the same plane (for example, the interlayer insulating film 116).

[0046] On the upper link 124, a protective film 118 made of an inorganic insulating material and an outer cover layer 146 made of the same organic insulating material as the first planarization layer 128 are disposed on the protective film 118 (which may be referred to as the first outer cover layer here).

[0047] The outer cover layer 146 made of an organic insulating material is formed so as to be separated from each of the first and second planarization layers 128 and 148. In other words, "separated from" refers to a configuration in which two components are arranged so as not to physically contact each other. Thereby, it is possible to block moisture and oxygen from the outside from flowing into the light-emitting element 130 through the outer cover layer 146, the first and second planarization layers 128 and 148, and prevent damage to the light-emitting element 130.

[0048] As shown in FIG. 1, the outer cover layer 146 is formed so as to correspond to a number of signal links disposed on the substrate 101 in a one-to-many manner (in other words, one outer cover layer corresponds to two or more signal links), or as shown in FIGS. 3, 4A, and 4B, it is formed so as to correspond to each of the signal links in a one-to-one manner (in other words, one outer cover layer corresponds to one signal link). That is, the signal link can be a conductive path between two components of the display device.

[0049] As shown in FIG. 4A, the outer cover layer 146 is formed to have a flat upper surface at the upper part of the upper link 124, or as shown in FIG. 4B, it is formed to have a stepped upper surface that becomes thinner toward the edge. The outer cover layer 146 having a stepped upper surface can prevent defects generated by the steps of the outer cover layer 146 during subsequent processes of the outer cover layer 146.

[0050] Such an outer cover layer 146 is formed to overlap not only the link contact hole 126 but also the upper surface and side surfaces of the upper link 124. In particular, the outer cover layer 146 is formed to overlap the link contact hole 126 on the protective film 118 that covers the step portions generated by the link contact hole 126 and the step portions generated by the side surfaces of the upper link 124.

[0051] Accordingly, in this embodiment, it is possible to prevent the protective film 118 from flowing out and the upper link 124 from being damaged during subsequent processes of the first planarization layer 128. This will be specifically described in connection with FIGS. 5A, 5B, 6A, and 6B.

[0052] FIGS. 5A and 5B are cross-sectional views showing a comparative example without an outer cover layer, and FIGS. 6A and 6B are cross-sectional views showing an embodiment with an outer cover layer.

[0053] In the comparative example shown in FIGS. 5A and 5B, after the lower link 122, the interlayer insulating film 116, the upper link 124, the protective film 118, and the first planarization layer 128 are formed in sequence, the pixel connection electrode 142 is formed in the active region. At this time, during the dry etching process for forming the pixel connection electrode 142, a part of the protective film 118 corresponding to the step portion generated by the link contact hole 126 flows out. Then, the upper link 124 is exposed through the portion where the protective film 118 has flowed out (region A). A defect occurs in which the exposed upper link 124 is short-circuited with at least one of the conductive materials of the anode electrode 132 and the cathode electrode 136 formed after the pixel connection electrode 142.

[0054] Also, during the dry etching process for forming at least one of the pixel connection electrode 142 and the anode electrode 132, if the loss of the protective film 118 is large (Region B), the upper link 124 below the protective film 118 melts and is lost. In this case, not only does a contact failure occur between the lower link 122 and the upper link 124, but the substance lost from the upper link 124 may move along the wet etching solution to the active region AA during the etching process of the anode electrode 132. In this case, foreign matter defects may occur due to the lost substance that has moved to the active region AA.

[0055] Moreover, during the dry etching process for forming the pixel connection electrode 142, a chip (tip) (Region C) composed of the residual substance 142A of the pixel connection electrode 142 is generated around the upper link 124 (referred to as a tip defect). This residual substance 142A of the pixel connection electrode 142 may move along the etching solution to the active region AA during the etching process of the anode electrode 132. In this case, foreign matter defects may occur due to the residual substance 142A that has moved to the active region AA.

[0056] On the other hand, in the embodiment of the present invention shown in FIGS. 6A and 6B, after the lower link 122, the interlayer insulating film 116, the upper link 124, and the protective film 118 are formed in this order, the first planarization layer 128 and the outer cover layer 146 are formed simultaneously. Thereafter, the pixel connection electrode 142 is formed in the active region AA. During the dry etching process for forming such a pixel connection electrode 142, the outer cover layer 146 covers the protective film 118 on the upper link 124. The outer cover layer 146 covers the protective film 118 of the step portion generated by the link contact hole 126 during the dry etching process for forming the pixel connection electrode 142. Thereby, during the dry etching process of the pixel connection electrode 142, the loss of the protective film 118 can be prevented and the exposure of the upper link 124 can be prevented or reduced. As a result, a short circuit failure between at least one of the conductive materials of the anode electrode 132 and the cathode electrode 136 and the upper link 124, a contact failure between the upper link 124 and the lower link 122, and a foreign matter failure due to at least one of the conductive materials of the upper link 124 and the pixel connection electrode 142 can be prevented or reduced.

[0057] FIG. 7 is a plan view showing an organic light emitting display device according to a second embodiment, and FIG. 8 is a cross-sectional view showing the display device cut along line “IV-IV′” in FIG. 7.

[0058] The display devices shown in FIGS. 7 and 8 have the same components as the display devices shown in FIGS. 1 and 2, except that they include a sealing unit 150, a number of dams 158, and a second outer cover layer 164. Accordingly, detailed descriptions of the same components will be omitted.

[0059] The sealing unit 150 blocks or reduces the intrusion of external moisture and oxygen into the light emitting element 130 that is vulnerable to external moisture and oxygen. For this purpose, the sealing unit 150 includes at least one inorganic sealing layer 152 and at least one organic sealing layer 154. In some embodiments, the structure of the sealing unit 150 in which the first inorganic sealing layer 152, the organic sealing layer 154, and the second inorganic sealing layer 156 are laminated in this order will be described.

[0060] The first inorganic encapsulation layer 152 is formed on the substrate 101 on which the cathode electrode 136 is formed. The second inorganic encapsulation layer 156 is formed on the substrate 101 on which the organic encapsulation layer 154 is formed, and is formed so as to surround the upper surface, lower surface, and side surfaces of the organic encapsulation layer 154 together with the first inorganic encapsulation layer 152. Such first and second inorganic encapsulation layers 152 and 156 minimize or block the intrusion of external moisture and oxygen into the light-emitting stack 134. The first and second inorganic encapsulation layers 152 and 156 are formed of an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Thereby, since the first and second inorganic encapsulation layers 152 and 156 are deposited in a low-temperature atmosphere, damage to the light-emitting stack 134, which is vulnerable to a high-temperature atmosphere during the deposition process of the first and second inorganic encapsulation layers 152 and 156, can be prevented or reduced.

[0061] The organic encapsulation layer 154 serves as a buffer to relieve the stress between layers due to bending of the organic light-emitting display device, and enhances the planarization performance. The organic encapsulation layer 154 is formed on the substrate 101 on which the first inorganic encapsulation layer 152 is formed of a non-photosensitive organic insulating material such as PCL, acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC), or a photosensitive organic insulating material such as photoacrylic. When such an organic encapsulation layer 154 is formed by an inkjet method, a dam 158 is disposed to prevent or reduce the diffusion of the liquid organic encapsulation layer 154 to the edge of the substrate 101. The dam 158 is disposed closer to the edge of the substrate 101 as compared with the organic encapsulation layer 154. Such a dam 158 can prevent or reduce the spread of the organic encapsulation layer 154 to the pad region where the conductive pads disposed at the outermost periphery of the substrate 101 are disposed.

[0062] The second outer cover layer 164 can be disposed in a region that cannot be covered by the outer cover layer 146 shown in FIGS. 1 and 2. For example, the second outer cover layer 164 is disposed between the dam 158, which is a region where a thin film of an organic insulating material (which can be a path for external moisture and humidity movement) cannot be disposed, and the conductive pads SP and DP. In some embodiments, the second outer cover layer 164 is formed instead of the outer cover layer 146. In other embodiments, in addition to the outer cover layer 146, the second outer cover layer 164 is further formed.

[0063] The second outer cover layer 164 is formed in the same mask process as the pixel connection electrode 142. That is, the second outer cover layer 164 can be formed on the protective film 118, which is in the same plane as the pixel connection electrode 142, by a third conductive material (for example, the same material as the pixel connection electrode 142). The second outer cover layer 164 is disposed on the signal link 162 made of a second conductive material (for example, the same material as the source and drain electrodes 106 and 108). The signal link 162 may be a single line that electrically connects a conductive pad (for example, a data pad) to a corresponding signal line. The second outer cover layer 164 has a line width w2 that is wider than the line width w1 of the signal link 162. Since the line width of the second outer cover layer 164 is wider than the line width of the signal link 162, the second outer cover layer 164 is disposed so as to cover the upper portion and the side surface of the signal link 162. Since the protective film 118 can be disposed on the signal link 162, the second outer cover layer 164 can be disposed on the protective film 118. Thereby, during the dry etching process for forming the second outer cover layer 164 and the pixel connection electrode 142, the third conductive material of the second outer cover layer 164 covers the protective film on the signal link. Therefore, in an embodiment, loss of the protective film 118 disposed on the signal link 162, damage to the signal link 162, and chip defects of the third conductive material can be prevented or reduced.

[0064] On such a second outer cover layer 164, a third outer cover layer 166 made of the same material as the second planarization layer 148 is disposed. The third outer cover layer 166 has a wider line width than the second outer cover layer 164 so as to cover the side surface and the upper surface of the second outer cover layer 164. Since such a third outer cover layer 166 is formed with a thickness thinner than that of the second planarization layer 148, the generation of steps due to the third outer cover layer 166 can be minimized. Accordingly, during the pressing process of a signal transmission film (for example, FPC or TCP) on a conductive pad adjacent to the third outer cover layer 166, defective crimping due to the thickness of the third outer cover layer 166 can be prevented or reduced.

[0065] On the other hand, in the first embodiment, the structure including the outer cover layer 146 is described, and in the second embodiment, the structures including the second and third cover layers 164 and 166 are described. However, in other embodiments, all of the outer cover layer 146, the second and third cover layers 164 and 166 may be included.

[0066] In addition, in the present disclosure, the structure in which the outer cover layer 146 is disposed on the upper portions of the signal links 122 and 124 including the link contact holes 126 and the second and third outer cover layers 164 and 166 are disposed on the upper portion of the signal link 162 not including the link contact hole 126 is described. However, the present disclosure is not limited thereto. The second and third outer cover layers 164 and 166 may be disposed on the upper portions of the signal links 122 and 124 including the link contact hole 126, and the outer cover layer 146 may be disposed on the upper portion of the signal link 162 not including the link contact hole 126.

[0067] In addition, in the present disclosure, the structure in which the outer cover layer 146, the second and third outer cover layers 164 and 166 are disposed on the upper portions of the signal links connected to the data pad DP is described. However, they may be disposed on the upper portions of the signal links connected to a scan pad (SP) and / or a power pad.

[0068] Furthermore, the display device related to the present disclosure includes an outer cover layer that overlaps with a step portion on the side surface of the signal link and a step portion generated by a link contact hole that connects the signal links. Therefore, the display device according to the present disclosure can prevent or reduce the loss of the protective film covering the signal link, the elution of the signal link, and the chip defect of the third conductive substance during the etching process for forming the pixel connection electrode.

[0069] In addition, in the present disclosure, although the organic light-emitting display device has been described, it is applicable to any display device including a thin-film transistor.

[0070] The above description is merely illustrative of the present invention, and various modifications may be possible by those having ordinary knowledge in the technical field to which the present invention pertains without departing from the technical idea of the present invention. Therefore, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be interpreted according to the appended claims, and any technology within the equivalent scope should be interpreted as being included in the scope of the present invention.

Explanation of Reference Numerals

[0071] 102 Gate electrode 104 Semiconductor layer 106 Source electrode 108 Drain electrode 122, 124, 162 Signal link 130 Light-emitting element 132 Anode electrode 134 Light-emitting stack 136 Cathode electrode 146, 164, 166 Outer cover layer

Claims

1. A substrate having an active region and a non-active region, a thin film transistor provided in the active region of the substrate, a first planarization layer covering the thin film transistor, a pixel connection electrode provided on the first planarization layer and connected to the thin film transistor, a protective film provided on the pixel connection electrode, an anode electrode connected to the pixel connection electrode, a light emitting element provided on the anode electrode, a cathode electrode provided on the light emitting element, a sealing portion disposed on the light emitting element, a first inorganic sealing layer, a second inorganic sealing layer, and an organic sealing layer disposed between the first and second inorganic sealing layers A sealing portion comprising: a conductive pad provided in the non-active region of the substrate, a signal link in which the conductive pad in the non-active region of the substrate is electrically connected to the thin film transistor in the active region, an outer cover layer covering the vertex and one or more side surfaces of the signal link region, and at least one dam disposed between the conductive pad and the light emitting element Comprising: The outer cover layer contains the same material as the first planarization layer, The outer cover layer is separated from the first planarization layer. A display device.

2. The first inorganic sealing layer and the second inorganic sealing layer cover the at least one dam and are in contact with each other, The display device according to claim 1, wherein the organic sealing layer is confined by the at least one dam.

3. The display device according to claim 1, wherein the pixel connection electrode is electrically connected to the drain electrode of the thin film transistor through a hole in the first planarization layer.

4. The display device according to claim 1, wherein the outer cover layer is separated from the second inorganic sealing layer.

5. The display device according to claim 1, wherein the outer cover layer is separated from the at least one dam.

6. The display device according to claim 1, wherein the at least one dam prevents the organic sealing layer from spreading to the conductive pad.

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