Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device in which electric field concentration at an external terminal is alleviated.SOLUTION: A terminal portion 20 of a semiconductor device includes a second external terminal 20c, an insulating sheet 20b arranged on the second external terminal 20c, and a first external terminal 20a arranged on the insulating sheet 20b, and the second external terminal 20c, the insulating sheet 20b, and the first external terminal 20a are arranged stepwise. In the first external terminal 20a, the closer the rear surface 20a6 of a first end portion 20a3 along the side of the outer end is to the tip, the closer the rear surface other than the first end portion 20a3 is to the front surface side. This reduces the electric field strength at the outer end of the second external terminal 20c.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] A semiconductor device used in a power conversion device is generally configured as follows. First, a semiconductor chip is mounted on a wiring pattern on an insulating substrate by soldering. One end of an external terminal integrally formed with a terminal case is joined to the wiring pattern on the insulating substrate. Between the semiconductor chip and the wiring pattern, between the wiring pattern and the external terminal, or between the semiconductor chip and the external terminal, they are joined using a metal wire or the like, and the inside of the terminal case is filled with a filler and sealed (see Patent Document 1). A metal plate is joined to a metal foil formed on the surface of the insulating substrate opposite to the side on which the semiconductor chip is mounted by soldering. By bringing the outer surface of this metal plate into contact with a heat dissipation fin or the like, the heat generated by the semiconductor chip can be dissipated to the outside.

[0003] In such a semiconductor device, it becomes necessary to increase the insulation strength with respect to the insulating substrate as the voltage to be handled increases. For this reason, it is known that the electric field at a high electric field location can be relaxed by making the upper creepage distance from the edge of the metal coating corresponding to the wiring pattern to the edge of the insulating substrate smaller than the lower creepage distance from the edge of the metal coating corresponding to the metal foil to the edge of the insulating substrate (see Patent Document 2). Further, in addition to making the upper creepage distance smaller than the lower creepage distance, it is known that the insulation performance is improved by field relaxation and defect suppression when an insulator having a dielectric constant lower than that of the sealing filler is filled between the insulating substrate and the metal plate (see Patent Document 3).

[0004] Also, in a semiconductor device having a circuit board in which copper plates are arranged on the upper and lower surfaces of an insulating substrate made of ceramic at positions offset inward from the outer periphery of the insulating substrate, and the end of the upper copper plate is arranged inward of the end of the lower copper plate, and the insulating substrate, the upper copper plate, and the lower copper plate are sealed with resin except for the lower surface of the lower copper plate, it is known that an electric field concentrates at the end of the upper copper plate in contact with the insulating substrate (see Non-Patent Document 1). And, when the circuit board has an insulating substrate made of ceramic, an upper conductor layer which is an electric circuit pattern arranged on the upper surface of the insulating substrate offset inward from the outer periphery of the insulating substrate, and a lower conductor layer which is offset inward from the outer periphery of the insulating substrate in a plan view and extends to the outside of the end of the conductor layer and is arranged on the lower surface of the insulating substrate, and the end of the joint surface between the upper conductor layer and the insulating substrate enters inside the outermost peripheral end of the upper conductor layer, it is known that the electric field can be suppressed (see Patent Document 4).

[0005] Also, it is known to form a curved surface at the end of a recess of an insulating substrate arranged on a base substrate, form a metal layer in this recess, and arrange a circuit-side conductor on the metal layer (see Patent Document 5).

[0006] Also, when a brazing material for joining a surface electrode corresponding to a wiring pattern to an insulating substrate is made to protrude toward the side surface side of the insulating substrate, it is known that the protruding portion shields between the surface electrode and the back electrode of the insulating substrate, so that the electric field strength at the upper end portion of the surface electrode can be relaxed (see Patent Document 6).

[0007] Furthermore, it is also known that when the intersection of the main surface of an insulating substrate and the side surface of a conductive plate arranged on this main surface is coated with an ion gel containing an ionic liquid, the local electric field concentration at the intersection is relaxed and the dielectric breakdown voltage can be improved (see Patent Document 7).

[0008] In addition, there is a device that reduces the electric field concentration at the end of a wiring pattern to which a high voltage is applied within a semiconductor device (see Patent Document 8). According to this semiconductor device, another wiring pattern having a potential between the potential differences between adjacent wiring patterns is disposed between two adjacent wiring patterns having a potential difference among the wiring patterns on which a plurality of sets of semiconductor chips are mounted.

[0009] By the way, some semiconductor devices are provided with external terminals to which a large-capacity capacitor can be externally connected (see Patent Document 9). The capacitor is for smoothing fluctuations in the input DC power supply voltage. The external terminal of the semiconductor device is electrically connected to the electrode of the capacitor by ultrasonic bonding. The electrode of the capacitor has a configuration in which a plate-shaped positive external electrode and a negative external electrode are arranged in parallel with an insulating member interposed therebetween. Thereby, the generation of inductance of the electrode of the capacitor is suppressed, and the resistance value of the joint portion is reduced.

[0010] Also, a power module is known in which a plurality of plate-shaped conductors protrude from the side surface of the power module with an insulating plate interposed therebetween, and the end of the upper conductor coincides with the end of the insulating plate in plan view. In this power module, the tip portions of each DC bus bar connected to the positive electrode and the negative electrode of the smoothing capacitor are electrically connected to the positive electrode side main electrode and the negative electrode side main electrode by brazing material (see Patent Documents 10 and 11).

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

[0012] [Non-Patent Document 1] Yuichiro Hinata et al., Fuji Electric Technical Report, 2016, Vol. 89, no. 4, pp242-246 [Summary of the Invention] [Problems to be Solved by the Invention]

[0013] In any of the conventional semiconductor devices, there is no description about reducing the electric field concentration at the end of the wiring pattern on the circuit board inside the device. However, for the external terminals to which capacitors are connected, since the same high voltage as that of the wiring pattern is applied, there is a problem that the insulating member deteriorates due to the application of the high voltage for a long time at the location where the electric field concentration occurs, resulting in insulation failure.

[0014] The present invention has been made in view of such points, and an object thereof is to provide a semiconductor device in which the electric field concentration at the external terminals is alleviated. [Means for Solving the Problems]

[0015] In an aspect of the present invention, a semiconductor device is provided. This semiconductor device includes a first external terminal having an end portion including a first end portion, a second external terminal having a terrace region in a part of the front surface, and a part region of the front surface excluding the terrace region being disposed to face the back surface of the first external terminal, an insulating sheet disposed between the first external terminal and the second external terminal and disposed adjacent to the terrace region of the second external terminal. The front surface of the first external terminal is flat. The back surface of the end portion of the first external terminal is farther from the second external terminal as it is closer to the tip of the end portion. The first external terminal has second and third end portions that are end portions of both side edges in a direction orthogonal to the direction in which the terrace region of the second external terminal and the first external terminal are disposed in a plan view. The back surfaces of the second end portion and the third end portion of the first external terminal are farther from the second external terminal as they are closer to the tip of the end portion. The sides of the front surface of the second end portion and the third end portion of the first external terminal overlap the end portion of the second external terminal in a plan view. The second external terminal is provided with notches at end portions of the second external terminal at respective positions facing the corners formed by the first end portion, the second end portion, and the third end portion of the first external terminal in a plan view.

[0016] In another aspect of the present invention, there is provided a step of preparing a first external terminal having a front surface and a back surface, the front surface being flat and the back surface of the end portion approaching the front surface side more than the back surface other than the end portion as it approaches the tip; a step of preparing an insulating sheet; a step of preparing a second external terminal having a terrace region on a part of the front surface; a step of disposing the insulating sheet adjacent to the terrace region on the second external terminal; and a step of disposing the first external terminal so that the back surface of the first external terminal faces a part of the front surface region of the second external terminal excluding the terrace region via the insulating sheet. The first external terminal has a first end portion which is one of the end portions, and second and third end portions which are end portions of both side edges facing each other with the first end portion interposed therebetween. The insulating sheet has an insulating region that does not contact the first external terminal in a plan view. The step of preparing the first external terminal includes a step of forming the back surfaces of the second end portion and the third end portion so as to approach the front surface side more than the back surface other than the second end portion and the third end portion as they approach the tips of the second end portion and the third end portion. The step of disposing the first external terminal is a step of overlapping the front surface sides of the second end portion and the third end portion of the first external terminal with the end portion of the second external terminal in a plan view. A method of manufacturing a semiconductor device is provided.

Effect of the Invention

[0017] In the semiconductor device having the above configuration, since the back surface of the end portion of the first external terminal on the side facing the insulating sheet is farther from the second external terminal as it approaches the tip of the end portion, there is an advantage that electric field concentration can be alleviated.

Brief Description of the Drawings

[0018]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

[0019] Hereinafter, embodiments will be described with reference to the drawings. In the drawings, parts denoted by the same reference numerals indicate the same components. Also, each embodiment can be implemented by partially combining a plurality of embodiments within a non-contradictory range.

[0020] [First Embodiment] FIG. 1 is a plan view showing a semiconductor device according to the first embodiment, FIG. 2 is a cross-sectional view taken along the line X1-X1 of FIG. 1, and FIG. 3 is a cross-sectional view showing the connection state between the terminal portion and the capacitor of the semiconductor device according to the first embodiment.

[0021] The semiconductor device 10 according to the first embodiment can be, for example, a power conversion device used in an inverter for driving a three-phase motor. The semiconductor device 10 for such an application has a function of rectifying and smoothing the alternating current supplied from the power source to convert it into direct current, and then converting it back into alternating current for driving the three-phase motor.

[0022] The semiconductor device 10 has a case 12 that forms a rectangular frame. This case 12 has three circuit accommodation parts 14, 16, and 18 along the longitudinal direction. For example, a U-phase drive circuit is accommodated in the circuit accommodation part 14, a V-phase drive circuit is accommodated in the circuit accommodation part 16, and a W-phase drive circuit is accommodated in the circuit accommodation part 18. In FIG. 1, the U-phase drive circuit, V-phase drive circuit, W-phase drive circuit, control terminals, etc. are not shown for simplicity.

[0023] The case 12 is formed by insert molding in which a thermoplastic resin heated and melted is injected into an injection molding die into which various terminals for connecting to external circuits are inserted, integrating the inserted various terminals and the resin. Examples of the thermoplastic resin include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, acrylonitrile butadiene styrene (ABS) resin, etc. The terminals provided in the case 12 include terminal parts 20, 22, 24 for connecting a large-capacity capacitor for stabilizing the input DC voltage, a U-phase output terminal 32, a V-phase output terminal 34, and a W-phase output terminal 36.

[0024] The terminal part 20 has a first external terminal 20a connected to the positive terminal (P terminal) of the capacitor, an insulating sheet 20b, and a second external terminal 20c connected to the negative terminal (N terminal) of the capacitor. The terminal part 22 has a first external terminal 22a connected to the positive terminal (P terminal) of the capacitor, an insulating sheet 22b, and a second external terminal 22c connected to the negative terminal (N terminal) of the capacitor. The terminal part 24 has a first external terminal 24a connected to the positive terminal (P terminal) of the capacitor, an insulating sheet 24b, and a second external terminal 24c connected to the negative terminal (N terminal) of the capacitor.

[0025] Since the terminal portions 20, 22, and 24 have the same structure, in the following description, the terminal portion 20 will be described as a representative. As shown in the cross-sectional view of FIG. 2, the terminal portion 20 has a laminated structure in which an insulating sheet 20b is disposed on the front surface (the upper surface in the figure) of the second external terminal 20c, and the first external terminal 20a is disposed on the front surface of the insulating sheet 20b. In the terminal portion 20, the outer end (the right end in FIG. 2) of the second external terminal 20c is aligned with the surface of the outer wall of the case 12, and the insulating sheet 20b and the first external terminal 20a are sequentially shifted inward from the outer end of the second external terminal 20c, resulting in an overall stepped shape. Here, in the terminal portion 20, in the front surface where the insulating sheet 20b is disposed, a terrace region 20c1 is formed between the outer end and the outer end of the insulating sheet 20b of the second external terminal 20c. The insulating sheet 20b of the terminal portion 20 forms an insulating region 20b1 between the region where the first external terminal 20a is in contact and the terrace region 20c1 on the front surface where the first external terminal 20a is disposed. Since the insulating region 20b1 is an exposed portion exposed to the atmosphere, it is necessary to ensure the creepage insulation distance and the space insulation distance between the terminals, and it is necessary to set it in accordance with the standard according to the rated voltage of the product. Therefore, the length by which the insulating region 20b1 protrudes from the end of the first external terminal 20a needs to be longer as the potential difference applied between the first external terminal 20a and the second external terminal 20c is higher, so that the creepage insulation distance and the space insulation distance can be sufficiently ensured. The front surface of the first external terminal 20a of the terminal portion 20 that protrudes from the case 12 forms an exposed region 20a1.

[0026] As shown in FIG. 3, the terminal portion 20 is a terminal that is electrically connected to the capacitor 38. The capacitor 38 has a first connection terminal 40 extending from the upper surface of the capacitor case, a flexible insulating sheet 42, and a second connection terminal 44. The first connection terminal 40 of the capacitor 38 is bent in the right direction in the figure after coming out of the capacitor case and extends parallel to the upper surface of the capacitor case. The second connection terminal 44 is bent in the left direction in the figure at a position higher than the first connection terminal 40 after coming out of the capacitor case and extends parallel to the upper surface of the capacitor case.

[0027] Next, an example of the connection between the semiconductor device 10 and the capacitor 38 will be described. The first external terminal 20a of the terminal portion 20 of the semiconductor device 10 is joined to the second connection terminal 44 of the capacitor 38 via a flat connecting member 46, and the second external terminal 20c of the terminal portion 20 is directly joined to the first connection terminal 40 of the capacitor 38. Here, as the order of joining the capacitor 38 and the terminal portion 20, first, the tip of the first connection terminal 40 of the capacitor 38 is placed on the terrace region 20c1 of the second external terminal 20c, and the first connection terminal 40 of the capacitor 38 and the second external terminal 20c of the terminal portion 20 are joined by laser welding at the welding site 48. Next, the insulating sheet 42 is bent so as to cover the welding site 48, and the connecting member 46 is placed so as to bridge the upper surface of the second connection terminal 44 of the capacitor 38 and the exposed region 20a1 of the first external terminal 20a. Then, the connecting member 46 and the second connection terminal 44 of the capacitor 38 are joined by laser welding at the welding site 50, and the connecting member 46 and the first external terminal 20a of the terminal portion 20 are joined by laser welding at the welding site 52.

[0028] As a result, between the semiconductor device 10 and the capacitor 38, the conductors of the negative electrode and the positive electrode are arranged in parallel with the insulating sheet 20b and the insulating sheet 42 sandwiched therebetween, and the current flows in opposite directions to each other, so that the inductance at this connection portion is reduced.

[0029] Next, the terminal portion 20 of this semiconductor device 10 will be described in detail. FIG. 4 is a diagram showing the configuration of the terminal portion, (A) is a plan view of the terminal portion, (B) is a bottom view of the terminal portion, FIG. 5 is a cross-sectional view taken along the line X2-X2 of FIG. 4(A), FIG. 6 is a cross-sectional view taken along the line X3-X3 of FIG. 4(A), and FIG. 7 is a diagram showing the electric field relaxation effect.

[0030] As shown in FIGS. 4(A) and 4(B), the terminal portion 20 of the semiconductor device 10 has a laminated structure in which the first external terminal 20a is disposed on the insulating sheet 20b, and the insulating sheet 20b is disposed on the second external terminal 20c. The first external terminal 20a has an exposed region 20a1 at the center of the outer end of its front surface. The insulating sheet 20b has an insulating region 20b1 at the center of the outer end of its front surface that does not contact the first external terminal 20a. The second external terminal 20c has a terrace region 20c1 at the center of the outer end of its front surface.

[0031] The first external terminal 20a has through holes 20a2 on both sides of the exposed region 20a1 along the side of the outer end. The insulating sheet 20b has through holes 20b3 in the extending portions 20b2 extending from the side of the central portion of the outer end on both sides of the insulating region 20b1, and has through holes 20b4 near the side of the inner end that does not overlap the first external terminal 20a in plan view. The second external terminal 20c has a through hole 20c2 at a position that overlaps the through hole 20b3 of the insulating sheet 20b in plan view. These through holes 20a2, 20b3, 20b4, 20c2 are for positioning the first external terminal 20a, the insulating sheet 20b, and the second external terminal 20c in the injection molding die.

[0032] Here, the first external terminal 20a and the second external terminal 20c are made of copper or a copper alloy. The first external terminal 20a has a plate thickness of 0.6 mm or more, and may be 0.8 mm or more and 1.2 mm or less. The insulating sheet 20b is a single sheet or a plurality of laminated sheets, is thinner than the plate thickness of the first external terminal 20a, and has a thickness of 0.05 mm or more. The material of the insulating sheet 20b is selected from one or more types in the group consisting of aramid fiber, glass fiber, ceramic, polyimide, mica, and composite materials of one or more of these materials.

[0033] The first external terminal 20a of the terminal portion 20 has a first end portion 20a3, a second end portion 20a4, and a third end portion 20a5 on three sides surrounding the exposed area 20a1. The first end portion 20a3 is an end portion along the side of the outer end of the first external terminal 20a. The second end portion 20a4 and the third end portion 20a5 are end portions of both side edges in a direction orthogonal to the direction in which the exposed area 20a1 of the first external terminal 20a, the insulating area 20b1 of the insulating sheet 20b, and the terrace area 20c1 of the second external terminal 20c are arranged in a plan view.

[0034] As shown in FIG. 5, the back surface 20a6 of the first end portion 20a3 of the first external terminal 20a is processed. That is, the back surface 20a6 of the first end portion 20a3 is shaped such that it approaches the front surface side from the back surface other than the first end portion 20a3 as it gets closer to the tip of the first end portion 20a3. In the illustrated example, the cross section from the back surface 20a6 to the front surface of the first end portion 20a3 has an R chamfered structure with a radius of curvature fr_R. An alternative structure to this R chamfered structure may be a curved surface formed by press working. Also, the back surface 20a6 of this first end portion 20a3 may have a C chamfered structure instead of the R chamfered structure.

[0035] As shown in FIG. 6, the back surfaces 20a7 and 20a8 of the second end portion 20a4 and the third end portion 20a5 of the first external terminal 20a are processed respectively. That is, the back surface 20a7 of the second end portion 20a4 and the back surface 20a8 of the third end portion 20a5 are shaped such that they approach the front surface side from the back surface other than the second end portion 20a4 and the third end portion 20a5 as they get closer to the tips of the second end portion 20a4 and the third end portion 20a5. In the illustrated example, the back surfaces 20a7 of the second end portion 20a4 and 20a8 of the third end portion 20a5 have an R chamfered structure with a radius of curvature si_R. An alternative structure to this R chamfered structure may be a curved surface formed by press working. Also, the back surfaces 20a7 and 20a8 of this second end portion 20a4 and the third end portion 20a5 may have a C chamfered structure in addition to the R chamfered structure.

[0036] The radius of curvature fr_R of the first end portion 20a3, and the radii of curvature si_R of the second end portion 20a4 and the third end portion 20a5 of the first external terminal 20a are desirably 0.5 mm or more and 1.0 mm or less, and are approximately 40% to 80% of the plate thickness of the first external terminal 20a. The plate thickness of the first external terminal 20a is appropriately determined according to the current capacity of the semiconductor device. Here, the plate thickness of the first external terminal 20a is, for example, 1.2 mm.

[0037] By providing an R chamfer structure for the back surface 20a6 of the first end portion 20a3 on the side of the outer end of the first external terminal 20a, the back surface 20a7 of the second end portion 20a4 on the sides of both ends of the first external terminal 20a, and the back surface 20a8 of the third end portion 20a5, respectively, the electric field concentration at the first end portion 20a3, the second end portion 20a4, and the third end portion 20a5 can be alleviated. That is, as shown in FIG. 7, it can be seen that when the radius of curvature fr_R and the radius of curvature si_R are 60% or more of the plate thickness (1.2 mm) as compared with the case where there is no R chamfer structure, the electric field strength is significantly alleviated.

[0038] Regarding the terminal portion 20 of the semiconductor device 10 according to the first embodiment, the first external terminal 20a has been described as the positive terminal (P terminal) and the second external terminal 20c as the negative terminal (N terminal). However, the first external terminal 20a may be the negative terminal (N terminal) and the second external terminal 20c may be the positive terminal (P terminal).

[0039] [Second Embodiment] FIG. 8 is a diagram showing the configuration of the terminal portion of the semiconductor device according to the second embodiment, (A) is a plan view of the terminal portion, (B) is a bottom view of the terminal portion, FIG. 9 is an enlarged view of part A of FIG. 8(B), FIG. 10 is a diagram showing the state of resin sealing by the case of the terminal portion, and FIG. 11 is a diagram showing the electric field relaxation effect.

[0040] As shown in FIGS. 8(A) and 8(B), the terminal portion 60 of the semiconductor device according to the second embodiment has a stacked structure in which a first external terminal 60a, an insulating sheet 60b, and a second external terminal 60c are arranged in a stepped manner. Although not shown, the back surfaces of the first end portion 60a1, the second end portion 60a2, and the third end portion 60a3 of the first external terminal 60a have an R chamfered structure, similar to the terminal portion 20 of the semiconductor device according to the first embodiment.

[0041] The sides of the front surface of the second end portion 60a2 and the sides of the front surface of the third end portion 60a3 of the first external terminal 60a of the terminal portion 60 overlap the end portions 60c1 and 60c2 of the second external terminal 60c in a plan view. Since the second end portion 60a2 and the third end portion 60a3 of the first external terminal 60a overlap the end portions 60c1 and 60c2 of the second external terminal 60c in a plan view, a larger cross-sectional area of each external terminal can be ensured within a limited width. Therefore, the inductance of the first external terminal 60a and the second external terminal 60c can be reduced, and the power loss can be reduced. The first external terminal 60a has a corner portion 60a4 formed by the first end portion 60a1 and the second end portion 60a2 and a corner portion 60a5 formed by the first end portion 60a1 and the third end portion 60a3. The second external terminal 60c is provided with a notch 60c3 at the position of the end portion 60c1 facing the corner portion 60a4 of the first external terminal 60a and a notch 60c4 at the position of the end portion 60c2 facing the corner portion 60a5 of the first external terminal 60a.

[0042] Since the cutouts 60c3 and 60c4 have a symmetrical shape, the cutout 60c3 will be described here. As shown in FIG. 9, the cutout 60c3 has an arc shape with a radius of curvature ar_R centered at a position facing the corner 60a4 of the first external terminal 60a in a plan view. Also, at the cutout 60c3 of the second external terminal 60c, the corner 60c5 formed by the cutout 60c3 of the second external terminal 60c and the end 60c1 of the second external terminal 60c is rounded in an arc shape by a fillet 60c6 with a radius of curvature fi_R. By providing the cutout 60c3 at the end 60c1 of the second external terminal 60c facing the corner 60a4 of the first external terminal 60a, the creepage distance between the corner 60a4 of the first external terminal 60a and the end 60c1 of the second external terminal 60c can be extended. Similarly, by providing the cutout 60c4 at the end 60c2 of the second external terminal 60c facing the corner 60a5 of the first external terminal 60a, the creepage distance between the corner 60a5 of the first external terminal 60a and the end 60c2 of the second external terminal 60c can be extended.

[0043] The radius of curvature ar_R of the cutout 60c3 is 0.5 mm or more and 1.5 mm or less, and the radius of curvature fi_R of the fillet 60c6 is 0.5 mm or more and 1.5 mm or less. The cutout 60c3 and the fillet 60c6 of the second external terminal 60c are formed by pressing.

[0044] As shown in FIG. 10, in the terminal portion 60, the second end 60a2 and the third end 60a3 of the first external terminal 60a, a part of the insulating sheet 60b, and the ends 60c1 and 60c2 of the second external terminal 60c are sealed by the resin of the case 12. In the illustrated example, the second end 60a2 of the first external terminal 60a and the end 60c1 of the second external terminal 60c are located about 1.5 mm inside from the edge 12a of the case 12, and are resin-sealed including the cutout 60c3 of the second external terminal 60c and the corner 60a4 of the first external terminal 60a. Also, the third end 60a3 of the first external terminal 60a and the end 60c2 of the second external terminal 60c are located about 1.5 mm inside from the edge 12b of the case 12, and are resin-sealed including the cutout 60c4 of the second external terminal 60c and the corner 60a5 of the first external terminal 60a.

[0045] In addition to making the back surfaces of the first end portion 60a1, the second end portion 60a2, and the third end portion 60a3 of the first external terminal 60a have an R chamfer structure, the terminal portion 60 is configured to provide notch portions 60c3 and 60c4 at positions of the end portions 60c1 and 60c2 of the second external terminal 60c that face the corner portions 60a4 and 60a5 of the first external terminal 60a. Thereby, even when the electric field strength cannot be sufficiently reduced only by the R chamfer structure of the first external terminal 60a, the electric field strength can be sufficiently reduced by using the notch portions 60c3 and 60c4 in combination. That is, according to FIG. 11, even when the curvature radius fr_R and the curvature radius si_R of the R chamfer are 0.5 mm, the electric field strength can be reduced as the curvature radius ar_R of the notch portions 60c3 and 60c4 and the curvature radius fi_R of the fillet 60c6 are increased.

[0046] In addition, in the terminal portion 60 of the semiconductor device according to the second embodiment, although the first external terminal 60a has been described as the positive terminal (P terminal) and the second external terminal 60c has been described as the negative terminal (N terminal), the first external terminal 60a may be the negative terminal (N terminal) and the second external terminal 60c may be the positive terminal (P terminal). This is because when the polarities of the first external terminal 60a and the second external terminal 60c were switched to confirm the effect of electric field relaxation, there was no difference due to the polarity.

Explanation of Signs

[0047] 10 Semiconductor device 12 Case 12a, 12b Edge 14, 16, 18 Circuit housing portion 20 Terminal portion 20a First external terminal 20a1 Exposed area 20a2 Through hole 20a3 First end 20a4 Second end 20a5 Third end 20a6, 20a7, 20a8 Back surface 20b Insulating sheet 20b1 Insulating region 20b2 Extension 20b3, 20b4 Through-hole 20c Second external terminal 20c1 Terrace area 20c2 Through-hole 22 Terminal part 22a First external terminal 22b Insulating sheet 22c Second external terminal 24 Terminal part 24a First external terminal 24b Insulating sheet 24c Second external terminal 32 U-phase output terminal 34 V-phase output terminal 36 W-phase output terminal 38 Capacitor 40 First connection terminal 42 Insulating sheet 44 Second connection terminal 46 Connecting member 48, 50, 52 Welding parts 60 Terminal part 60a First external terminal 60a1 First end 60a2 Second end 60a3 Third end 60a4, 60a5 Corner parts 60b Insulating sheet 60c Second external terminal 60c1, 60c2 Ends 60c3, 60c4 Notches 60c5 Corner 60c6 Fillet

Claims

1. a first external terminal having an end portion including a first end portion; a second external terminal having a terrace region on a part of a front surface, and a part region of the front surface excluding the terrace region being disposed to face the back surface of the first external terminal; an insulating sheet disposed between the first external terminal and the second external terminal and disposed adjacent to the terrace region of the second external terminal; the front surface of the first external terminal is flat; the back surface of the end portion of the first external terminal is farther from the second external terminal as it is closer to the tip of the end portion; the first external terminal has second and third end portions which are end portions of both sides in a direction orthogonal to the direction in which the terrace region of the second external terminal and the first external terminal are disposed in a plan view, and the back surfaces of the second end portion and the third end portion are farther from the second external terminal as they are closer to the tip of the end portion; the sides of the front surface of the second end portion and the sides of the front surface of the third end portion of the first external terminal overlap with the end portion of the second external terminal in a plan view; the second external terminal is provided with notches at the end portions at positions respectively facing the corners formed by the first end portion, the second end portion, and the third end portion of the first external terminal in a plan view; a semiconductor device.

2. The semiconductor device according to claim 1, wherein the insulating sheet includes an insulating region that does not contact the first external terminal between the first end portion and the terrace region of the second external terminal in a plan view.

3. The cross section from the back surface to the front surface of the end portion of the first external terminal has an R chamfered structure, and the radius of curvature of the R chamfered structure is 60% or more and 80% or less of the thickness of the first external terminal. The semiconductor device according to claim 1 or 2.

4. The semiconductor device according to any one of claims 1 to 3, wherein the thickness of the first external terminal is 0.6 mm or more and 1.2 mm or less.

5. The semiconductor device according to claim 3, wherein the R chamfered structure of the first external terminal has a radius of curvature of 0.5 mm or more and 1.0 mm or less.

6. The semiconductor device according to claim 1, wherein the notch of the second external terminal is resin-sealed.

7. The semiconductor device according to claim 1, wherein the notch of the second external terminal is a semi-circle having a radius of curvature of 0.5 mm or more and 1.5 mm or less in a plan view.

8. In the semiconductor device according to claim 7, the corner formed by the notch portion and the end portion of the second external terminal is a fillet arc shape having a curvature radius of 0.5 mm or more and 1.5 mm or less in plan view.

9. In the semiconductor device according to claim 1, a part of the second external terminal, a part of the insulating sheet, the second end portion and the third end portion of the first external terminal are resin-sealed.

10. In the semiconductor device according to claim 1, the thickness of the insulating sheet is thinner than the thickness of the first external terminal.

11. The insulating sheet is a single sheet or a plurality of laminated sheets, In the semiconductor device according to claim 10, the material of the insulating sheet is selected from one or more of the group consisting of aramid fiber, glass fiber, ceramic, polyimide, mica, and a composite material of one or more of these materials.

12. In the semiconductor device according to claim 1, the first external terminal is a negative electrode and the second external terminal is a positive electrode, or the first external terminal is a positive electrode and the second external terminal is a negative electrode.

13. A step of preparing a first external terminal having a front surface and a back surface, the front surface being flat, and the back surface of the end portion approaching the front surface side from the back surface other than the end portion as it approaches the tip; A step of preparing an insulating sheet; A step of preparing a second external terminal having a terrace region on a part of the front surface; A step of disposing the insulating sheet adjacent to the terrace region on the second external terminal; A step of disposing the first external terminal so that the back surface of the first external terminal faces a part of the front surface of the second external terminal excluding the terrace region via the insulating sheet; comprising The first external terminal has a first end portion which is one of the end portions, and second end portions and third end portions which are the end portions of both sides facing each other with the first end portion interposed therebetween, The insulating sheet has an insulating region that does not contact the first external terminal in plan view, The step of preparing the first external terminal includes a step of forming the back surfaces of the second end portion and the third end portion so as to approach the front surface side from the back surface other than the second end portion and the third end portion as they approach the tips of the second end portion and the third end portion, The step of disposing the first external terminal is a step of overlapping the side of the front surface of the second end portion and the side of the front surface of the third end portion of the first external terminal with the end portion of the second external terminal in plan view. A method of manufacturing a semiconductor device.

14. The method of manufacturing a semiconductor device according to claim 13, wherein the step of preparing the first external terminal includes a step of forming the back surface of the end portion of the first external terminal by pressing.

15. The method of manufacturing a semiconductor device according to claim 13, wherein the step of preparing the second external terminal includes a step of forming notches at the end portions of the second external terminal at positions where the second external terminal faces the corner portions formed by the first end portion, the second end portion, and the third end portion of the first external terminal in a plan view.

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