Electronic control device

Abstract

To appropriately inhibit a memory region from being pressed in a multi-core configuration in which a microcomputer has multiple cores.SOLUTION: An electronic control device 1 includes a microcomputer 2 having multiple cores, an operating system 3 that defines interruption process identification information for identifying an interruption process, a priority level of an interruption process, and interruption destination information indicating a core in which an interruption process is executed, and an interruption process unit 4 that, when an interruption request is started in the microcomputer, determines whether an interruption condition is established or not established on the basis of whether or not an interruption regarding the started interruption request is defined on the operating system side, and, when determining that the interruption condition is established, identifies an execution core for an interruption request having the same content but a different execution destination core, on the basis of interruption destination core information and performs the interruption process.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an electronic control device.

Background Art

[0002] A vehicle is equipped with a plurality of electronic control units (hereinafter referred to as ECUs (Electronic Control Units)). The ECU is equipped with a microcomputer (hereinafter referred to as a microcontroller), and with the increasing demand for higher functionality and reliability of vehicles, multi-core processing has advanced due to an increase in the number of cores (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When an interrupt request is raised by the INTC (Interrupt Controller) inside the microcontroller, it is determined whether the interrupt condition is satisfied or not in the ISR (interrupt service routine) module inside the BSW (Basic SoftWare) based on the interrupt vector and priority defined by the OS (Operating System). When the BSW determines that the interrupt condition is satisfied, it performs interrupt processing, and when it determines that the interrupt condition is not satisfied, it performs error processing.

[0005] As described above, when the number of cores of the microcontroller increases, the problem of memory area compression becomes apparent. In particular, for interrupt processing with the same content but different execution destination cores, the OS definition and ISR processing are distinguished for each core. The above problem did not occur in conventional microcontrollers with a small number of cores, but there is a problem that the memory area in the microcontroller will be compressed in the future due to an increase in the number of cores.

[0006] The present invention has been made in view of the above circumstances, and an object thereof is to provide an electronic control device capable of appropriately avoiding compression of a memory area in a microcomputer even when the number of cores increases in a multi-core configuration in which the microcomputer has a plurality of cores.

Means for Solving the Problems

[0007] According to the invention described in claim 1, a microcomputer (2) having a plurality of cores, interrupt processing specifying information for specifying interrupt processing, a priority of the interrupt processing, and an interrupt destination core information indicating a core on which the interrupt processing is executed An operating system (3) to be defined, and when an interrupt request is raised in the microcomputer, it is determined whether or not the interrupt of the raised interrupt request is defined on the operating system side, and when it is determined that the interrupt condition is satisfied, for interrupt requests having the same content but only different execution destination cores, an interrupt processing unit (4) that specifies an execution core based on the interrupt destination core information and performs interrupt processing.

[0008] When it is determined that the interrupt condition is satisfied, the execution core is specified based on the interrupt destination core information for interrupt requests having the same content but only different execution destination cores, and interrupt processing is performed. For interrupt processing having the same content but only different execution destination cores, it is possible to eliminate the process of securing a memory area for each core. Thereby, even when the number of cores increases in a multi-core configuration in which the microcomputer has a plurality of cores, compression of the memory area in the microcomputer can be appropriately avoided.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described with reference to the drawings. As shown in FIG. 1, an electronic control unit 1 is arranged in an ECU mounted on a vehicle. The electronic control unit 1 includes a microcomputer 2, an OS 3, and a BSW 4 (corresponding to an interrupt processing unit). The microcomputer 2 has a configuration having a CPU, a ROM, a RAM, an I / O, etc., and executes software processing by executing a computer program stored in a non-transitory tangible storage medium by the CPU, and controls the operation of the electronic control unit 1 by hardware processing by a dedicated electronic circuit. The microcomputer 2 has a multi-core configuration having a plurality of cores. The microcomputer 2 wakes up an interrupt request by the INTC.

[0011] The OS 3 defines an interrupt vector (corresponding to interrupt processing specific information) for specifying interrupt processing, the priority of the interrupt processing, and interrupt destination core information indicating the core on which the interrupt processing is executed. For example, when the target of the interrupt processing is "core 0", "core 0" is defined as the interrupt destination core information, and when the target of the interrupt processing is "core 1", "core 1" is defined as the interrupt destination core information. The OS 3 realizes real-time performance in units of μs.

[0012] When an interrupt request is raised in the INTC of the microcontroller 2, BSW4 determines whether the interrupt condition is satisfied or not based on whether the interrupt of the raised interrupt request is defined on the OS3 side. When the interrupt of the raised interrupt request is defined on the OS3 side, BSW4 determines that the interrupt condition is satisfied; when the interrupt of the raised interrupt request is not defined on the OS3 side, BSW4 determines that the interrupt condition is not satisfied. When BSW4 determines that the interrupt condition is satisfied, it acquires interrupt destination core information, and for interrupt requests with the same content but different execution destination cores, it identifies the execution core based on the interrupt destination core information and performs interrupt processing. On the other hand, when BSW4 determines that the interrupt condition is not satisfied, it acquires interrupt destination core information, and for interrupt requests with the same content but different execution destination cores, it performs error processing based on the interrupt destination core information.

[0013] Next, the operation of the above-described configuration will be described with reference to FIGS. 2 to 6. As shown in FIG. 2, when an interrupt request is raised in the INTC of the microcontroller 2 (S1), the electronic control unit 1 defines an interrupt vector, a priority, and interrupt destination information (S2). The electronic control unit 1 determines whether the interrupt condition is satisfied or not based on whether the interrupt of the raised interrupt request is defined on the OS3 side (S3).

[0014] When the interrupt of the raised interrupt request is defined on the OS3 side and the electronic control unit 1 determines that the interrupt condition is satisfied (S3: YES), it acquires the interrupt destination information (S4). The electronic control unit 1 identifies the execution core based on the acquired interrupt destination information and performs interrupt processing (S5). On the other hand, when the interrupt of the raised interrupt request is not defined on the OS3 side and the electronic control unit 1 determines that the interrupt condition is not satisfied (S3: NO), it acquires the interrupt destination information (S6). The electronic control unit 1 performs error processing based on the acquired interrupt destination information (S7).

[0015] As shown in FIG. 3, when interrupt requests with the same content but different execution destination cores are raised and the targets of interrupt processing are "core 0" and "core 1", by defining "core 0" and "core 1" as interrupt destination information, if the memory usage per interrupt processing is, for example, "22 bytes", it is only necessary to secure a memory area of "22 bytes" for one processing. Also, if the memory usage per error processing is, for example, "15 bytes", it is only necessary to secure a memory area of "15 bytes" for one processing.

[0016] Taking the conventional configuration as a comparison target, it will be described with reference to FIGS. 4 to 6. As shown in FIG. 4, the electronic control device 11 to be compared includes a microcomputer 12, an OS 13, and a BSW 14. Different from the above-described OS 3, the OS 13 does not define interrupt destination core information.

[0017] In this case, as shown in FIG. 5, when an interrupt request is raised in the INTC of the microcomputer 2 in the electronic control device 11 (S11), it defines an interrupt vector and a priority (S12). The electronic control device 1 determines whether the interrupt condition is satisfied or not based on whether the interrupt of the raised interrupt request is defined on the OS 3 side (S13).

[0018] When the electronic control device 11 determines that the interrupt condition is satisfied (S13: YES), it performs interrupt processing (S14). On the other hand, when the electronic control device 1 determines that the interrupt condition is not satisfied (S13: NO), it performs error processing (S15). In this case, since the electronic control device 11 does not define interrupt destination information indicating the core where the interrupt processing is executed, steps S13 to S15 are performed for the number of cores.

[0019] As shown in FIG. 6, when an interrupt request having the same content but different execution destination cores is raised and the targets of interrupt processing are "core 0" and "core 1", if the memory usage per interrupt processing is, for example, "22 bytes", a memory area obtained by multiplying the "22 bytes" for one process by the number of cores (in this case, "2") is required, which causes compression of the memory area. Also, if the memory usage per error processing is, for example, "15 bytes", a memory area obtained by multiplying the "15 bytes" for one process by the number of cores is required, which causes compression of the memory area.

[0020] As described above, according to the present embodiment, the following operational effects can be obtained. In the electronic control device 1, when it is determined that an interrupt condition is satisfied, for interrupt requests having the same content but different execution destination cores, the execution core is specified based on the interrupt destination core information and interrupt processing is performed. It is possible to eliminate the process of securing a memory area for each core for interrupt processing having the same content but different execution destination cores. Thereby, even when the number of cores increases in the multi-core configuration in which the microcomputer 2 has a plurality of cores, it is possible to appropriately avoid compression of the memory area in the microcomputer 2.

[0021] Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and further other combinations and forms including only one element, more, or less thereof are also within the scope and spirit of the present disclosure.

[0022] The control unit and its method described in the present disclosure may be implemented by a dedicated computer configured by a processor and a memory programmed to execute one or more functions embodied by a computer program. Alternatively, the control unit and its method described in the present disclosure may be implemented by a dedicated computer provided by configuring a processor with one or more dedicated hardware logic circuits. Or, the control unit and its method described in the present disclosure may be implemented by one or more dedicated computers configured by a combination of a processor and a memory programmed to execute one or more functions and a processor configured by one or more hardware logic circuits. Further, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions to be executed by a computer.

Explanation of Signs

[0023] In the drawings, 1 is an electronic control unit, 2 is a microcomputer, 3 is an OS, and 4 is a BSW (interrupt processing unit).

Claims

1. A microcomputer (2) having a plurality of cores, An operating system (3) that defines interrupt processing specific information for specifying interrupt processing, the priority of the interrupt processing, and interrupt destination core information indicating the core on which the interrupt processing is executed, When an interrupt request is raised in the microcomputer, it determines whether the interrupt of the raised interrupt request is defined on the operating system side, and when it determines that the interrupt condition is satisfied, it specifies the execution core based on the interrupt destination core information for interrupt requests having the same content but only different execution destination cores, and an interrupt processing unit (4) that performs interrupt processing with the specified core as the interrupt destination. An electronic control device comprising:

2. The electronic control device according to claim 1, wherein when the interrupt processing unit determines that the interrupt condition is not satisfied, it performs error processing based on the interrupt destination core information for interrupt requests having the same content but only different execution destination cores.

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