Display device

Abstract

To reduce the number of transistors connected to a capacity element.SOLUTION: A display device includes a capacity element and one transistor. One electrode of the capacity element is connected to wiring and the other electrode of the capacity element is connected to a gate of the transistor. A clock signal is input to the wiring and the clock signal is input to the gate of the transistor through the capacity element. A conductive state of the transistor is controlled by a signal synchronizing with the clock signal and the transistor is set to an on period and an off period repeatedly. Thus, deterioration in the transistor can be suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Semiconductor device, display device, liquid crystal display device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device and a display device having a driver circuit formed on the same substrate as a pixel portion, The present invention relates to a liquid crystal display device, a driving method for the device, or an electronic device having the device. Regarding. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single crystal semiconductors are used to form a pixel region. The technology of configuring driving circuits such as gate drivers on a substrate is expected to contribute greatly to reducing costs and improving reliability. Development is underway actively to contribute significantly to the

[0003] However, transistors made of non-single crystal semiconductors have a higher threshold voltage and When the degradation of this transistor progresses, the driver circuit stops working. This causes a problem that the image cannot be displayed due to the difficulty in adjusting the brightness. The present invention discloses a shift register configuration that can suppress the degradation of transistors. In Patent Document 1, one electrode of the capacitance element is connected to a wiring to which a clock signal is input, The other electrode of the capacitance element is connected to the gates of the two transistors. The potential of the capacitor is increased or decreased in synchronization with the clock signal. Using this combination, a signal synchronized with the clock signal is generated at the gates of the two transistors. Then, a signal synchronized with this clock signal is used to control the on and off of the transistor. Then, the period during which the transistor is on and the period during which the transistor is off are repeated, so that deterioration of the transistor can be suppressed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in Patent Document 1, since the other electrode of the capacitive element is connected to the gates of two transistors, there is a problem that the parasitic capacitance of the node connected to the capacitive element increases. For this reason, there is a problem that the potential of the H level of the signal synchronized with the clock signal becomes low. In this case, when the threshold voltage of the transistor increases, there is a problem that the time when the transistor cannot turn on becomes earlier. That is, there is a problem that the life of the shift register becomes short. Or, since the parasitic capacitance connected to the capacitive element is large, there is a problem that the capacitance value of the capacitive element must be increased. For this reason, since it is necessary to increase the area where one electrode and the other electrode of the capacitive element overlap, there is a problem that the layout area of the capacitive element becomes large.

[0006] Or, in Patent Document 1, since it is necessary to increase the area of the capacitive element, there is a problem that one electrode and the other electrode are likely to be short-circuited by dust or the like. As a result, there are problems such as a decrease in yield and an increase in cost.

[0007] ​​​​​​​​​​​ Alternatively, in Patent Document 1, since it is necessary to increase the capacitance value of the capacitive element, there is a problem that the delay or distortion of the signal (for example, a clock signal or an inverted clock signal) supplied to the capacitive element becomes large. Or, there is a problem that the power consumption becomes large. Or, since it is necessary to use a circuit having a large current driving ability as a circuit that outputs a signal supplied to the capacitive element, there is a problem that an external circuit (hereinafter also referred to as an external circuit) becomes large. Or, there is a problem that the display device becomes large. Or, in Patent Document 1, there is a period during which the gate of the pull-up transistor Tu is in a floating state. Therefore, the potential of the gate of the pull-up transistor Tu is not stabilized, and noise or the like occurs. Therefore, there is a problem that the shift register malfunctions.

[0008] In view of the above problems, it is an object to reduce the number of transistors connected to the capacitive element. Or, it is an object to reduce the parasitic capacitance of the transistor connected to the capacitive element. Or, it is an object to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is an object to reduce the layout area. Or, it is an object to extend the lifespan. It is an object to reduce the delay or distortion of the signal. Or, it is an object to reduce the power consumption. Or, it is an object to reduce the influence of noise. Or, it is an object to suppress or mitigate the deterioration of the transistor. Or, it is an object to suppress malfunction. Or, it is an object to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, since it is necessary to use a circuit having a large current driving ability as a circuit that outputs a signal supplied to the capacitive element, there is a problem that an external circuit (hereinafter also referred to as an external circuit) becomes large. Or, there is a problem that the display device becomes large. Or, since it is necessary to use a circuit having a large current driving ability as a circuit that outputs a signal supplied to the capacitive element, there is a problem that an external circuit (hereinafter also referred to as an external circuit) becomes large. Or, there is a problem that the display device becomes large.

[0009] Or, in Patent Document 1, there is a period during which the gate of the pull-up transistor Tu is in a floating state. Therefore, the potential of the gate of the pull-up transistor Tu is not stabilized, and noise or the like occurs. Therefore, there is a problem that the shift register malfunctions. Or, in Patent Document 1, there is a period during which the gate of the pull-up transistor Tu is in a floating state. Therefore, the potential of the gate of the pull-up transistor Tu is not stabilized, and noise or the like occurs. Therefore, there is a problem that the shift register malfunctions. Or, in Patent Document 1, there is a period during which the gate of the pull-up transistor Tu is in a floating state. Therefore, the potential of the gate of the pull-up transistor Tu is not stabilized, and noise or the like occurs. Therefore, there is a problem that the shift register malfunctions.

[0010] In view of the above problems, it is an object to reduce the number of transistors connected to the capacitive element. Or, it is an object to reduce the parasitic capacitance of the transistor connected to the capacitive element. Or, it is an object to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is an object to reduce the layout area. Or, it is an object to extend the lifespan. It is an object to reduce the delay or distortion of the signal. Or, it is an object to reduce the power consumption. Or, it is an object to reduce the influence of noise. Or, it is an object to suppress or mitigate the deterioration of the transistor. Or, it is an object to suppress malfunction. Or, it is an object to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is an object to reduce the parasitic capacitance of the transistor connected to the capacitive element. Or, it is an object to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is an object to reduce the layout area. Or, it is an object to extend the lifespan. It is an object to reduce the delay or distortion of the signal. Or, it is an object to reduce the power consumption. Or, it is an object to reduce the influence of noise. Or, it is an object to suppress or mitigate the deterioration of the transistor. Or, it is an object to suppress malfunction. Or, it is an object to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is an object to extend the lifespan. It is an object to reduce the delay or distortion of the signal. Or, it is an object to reduce the power consumption. Or, it is an object to reduce the influence of noise. Or, it is an object to suppress or mitigate the deterioration of the transistor. Or, it is an object to suppress malfunction. Or, it is an object to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is an object to reduce the power consumption. Or, it is an object to reduce the influence of noise. Or, it is an object to suppress or mitigate the deterioration of the transistor. Or, it is an object to suppress malfunction. Or, it is an object to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is an object to reduce the influence of noise. Or, it is an object to suppress or mitigate the deterioration of the transistor. Or, it is an object to suppress malfunction. Or, it is an object to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is an object to suppress or mitigate the deterioration of the transistor. Or, it is an object to suppress malfunction. Or, it is an object to prevent a short circuit between one electrode and the other electrode of the capacitive element. An object is to solve the above problems. Or, an object is to reduce the current driving ability of an external circuit. Also an object is to reduce the size of an external circuit. Or, an object is to reduce the size of a display device. Note that the description of these problems does not prevent the existence of other problems.

Means for Solving the Problems

[0011] It has a capacitive element and one transistor. One electrode of the capacitive element is connected to a wiring, and the other electrode of the capacitive element is connected to the gate of the transistor. A clock signal is input to the wiring, so the clock signal is input to the gate of the transistor via the capacitive element. And the conduction state of the transistor is controlled by a signal synchronized with the clock signal, and the transistor repeats a period of being on and a period of being off. Thus, deterioration of the transistor can be suppressed.

[0012] An exemplary aspect of the present invention has a driving circuit and a pixel. The pixel has a liquid crystal element. The driving circuit has a first transistor, a second transistor, a third transistor, a fourth transistor, and a capacitive element. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A first terminal of the second transistor is electrically connected to the second wiring. A second terminal of the second transistor is electrically connected to the gate of the first transistor. The gate of the second transistor is electrically connected to the first wiring. A first terminal of the third transistor is electrically connected to a third wiring. And a second terminal of the third transistor is electrically connected to a fourth wiring. The second terminal of the transistor is electrically connected to the gate of the first transistor, and the The first terminal of the fourth transistor is electrically connected to the third wiring, and the fourth The second terminal of the transistor is electrically connected to the gate of the third transistor, and the The gate of the fourth transistor is electrically connected to the gate of the first transistor, One electrode of the capacitor element is electrically connected to the first wiring, and the other electrode of the capacitor element is electrically connected to the gate of the third transistor, which is a liquid crystal display device.

[0013] Note that switches can be of various forms. Examples include electrical switches and mechanical switches. That is, any device that can control the flow of current is acceptable and is not limited to a specific type. For example, as a switch, a transistor (e.g., bipolar transistor, MOS transistor, etc.), a diode (e.g., PN diode, PIN diode, Schottky diode, MIM (Metal Insulator Metal) diode, MIS (Metal Insulator Semicon ductor) diode, a transistor connected in diode configuration, etc.) can be used. Alternatively, a logic circuit combining these can be used as a switch.

[0014] Examples of mechanical switches include switches using MEMS (Micro-Electro-Mechanical System) technology, such as a digital micromirror device (DMD).

[0015] Note that both N-channel transistors and P-channel transistors are used to form CMOS. An S-shaped switch may be used as the switch.

[0016] When it is explicitly described that A and B are connected, it shall include the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and shall also include those other than the connection relationship shown in the figure or the text. For example, in the case where A and B are electrically connected, one or more elements (for example, switches, transistors, capacitor elements, inductors, resistance elements, diodes, etc.) that enable the electrical connection between A and B may be connected between A and B. Alternatively, in the case where A and B are functionally connected, one or more circuits (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplification circuits (circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplification circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) that enable the functional connection between A and B may be connected between A and B. For example, even if another circuit is sandwiched between A and B, when the signal output from A is transmitted to B, A and B are considered to be functionally connected.

[0017] ​​​​​​​​​​​​​​​​

[0018] In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, when they are connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, when they are functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, when they are connected without another element or another circuit sandwiched between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected. In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, when they are connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, when they are functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, when they are connected without another element or another circuit sandwiched between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected. In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, when they are connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, when they are functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, when they are connected without another element or another circuit sandwiched between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected. In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). In addition, when it is explicitly described that A and B are electrically connected, it includes the case where A and B are electrically connected (that is, when they are connected with another element or another circuit sandwiched between A and B), the case where A and B are functionally connected (that is, when they are functionally connected with another circuit sandwiched between A and B), and the case where A and B are directly connected (that is, when they are connected without another element or another circuit sandwiched between A and B). That is, when it is explicitly described that they are electrically connected, it is considered to be the same as when it is only explicitly described that they are connected.

[0019] In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). In addition, a display element, a display device having the display element, a light-emitting element, and a light-emitting device having the light-emitting element can use various forms and have various elements. For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). For example, as the display element, the display device, the light-emitting element, or the light-emitting device, there are EL (electroluminescence) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electronic ink, electrophoretic elements, grating light valves (GLVs), plasma displays (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic displays, carbon nanotubes, etc., and can have a display medium in which contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic action. In addition, as a display device using an EL element, there is an EL display, and as a display device using an electron-emitting element, there is a field emission display (FED). ) and SED (Surface-conduction Electron-emitter Disply) type flat panel displays, etc., display devices using liquid crystal elements, and as for display devices using liquid crystal elements, there are liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), electronic ink, and as for display devices using electrophoretic elements, there is electronic paper.

[0020] Note that a liquid crystal element is an element that controls light transmission or non-transmission by the optical modulation action of liquid crystal, and is composed of a pair of electrodes and liquid crystal. Note that the optical modulation action of liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Note that as liquid crystal elements, there are nematic liquid crystals, cholesteric liquid crystals, smectic liquid crystals, discotic liquid crystals, thermotropic liquid crystals, lyotropic liquid crystals, low molecular weight liquid crystals, high molecular weight liquid crystals, polymer dispersed liquid crystals (PDLC), ferroelectric liquid crystals, antiferroelectric liquid crystals, main chain liquid crystals, side chain type high molecular weight liquid crystals, plasma addressed liquid crystals (PALC), banana type liquid crystals, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment), ASV (Advanced Super View) mode, ASM (Axially Symmetric aligned Mic) mode, ​​​​​​​ro-cell) mode, OCB (Optical Compensated Bire fringence) mode, ECB (Electrically Controlle d Birefringence) mode, FLC (Ferroelectric Li quid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, PDLC (Polymer Disperse d Liquid Crystal) mode, guest - host mode, blue Phase) mode, etc. can be used. However, it is not limited to this, and various types of liquid crystal elements can be used.

[0021] In addition, for display devices that require a light source, such as liquid crystal displays (transmissive liquid crystal displays , transflective liquid crystal displays, reflective liquid crystal displays, direct - view liquid crystal displays, projection type liquid crystal displays), display devices using a grating light valve (GLV), display devices using a digital micromirror device (DMD), etc., as the light source, electroluminescence, cold cathode tubes, hot cathode tubes, LEDs, laser light sources, mercury lamps, etc. can be used . However, it is not limited to this, and various types of light sources can be used .

[0022] In addition, as the transistor, various forms of transistors can be used. Therefore , there is no limitation on the type of transistor used. For example, thin - film transistors (TFTs) having an amorphous semiconductor film represented by amorphous silicon, polycrystalline silicon, microcrystalline (also called microcrystal, nanocrystal, semi - amorphous) silicon, etc. can be used . ​can be achieved.

[0023] When producing microcrystalline silicon, by using a catalyst (such as nickel), the crystallinity can be further improved, and it becomes possible to manufacture transistors with good electrical characteristics. In this case, without performing laser irradiation, just by applying heat treatment, it is also possible to improve the crystallinity. As a result, a part of the source driver circuit (such as an analog switch) and the gate driver circuit (scanning line drive circuit) can be integrally formed on the substrate. Furthermore, when laser irradiation is not performed for crystallization, it is possible to suppress the unevenness of the crystallinity of silicon. Therefore, it is possible to display an image with improved image quality.

[0024] However, it is possible to produce polycrystalline silicon or microcrystalline silicon without using a catalyst (such as nickel).

[0025] Alternatively, transistors can be formed using a semiconductor substrate, an SOI substrate, etc. With these, variations in characteristics, size, shape, etc. are small, the current supply ability is high, and transistors with small sizes can be manufactured. When using these transistors, it is possible to achieve low power consumption of the circuit or high integration of the circuit.

[0026] Alternatively, transistors having a compound semiconductor or oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, SnO can be used, and further, thin film transistors in which these compound semiconductors or oxide semiconductors are thinned can be used. With these, the manufacturing temperature can be lowered, for example, it is possible to manufacture transistors at room temperature. As a result, it becomes possible to directly form a transistor on a substrate with low heat resistance, such as a plastic substrate or a film substrate. In addition to using these compound semiconductors or oxide semiconductors for the channel portion of the transistor, they can also be used for other applications. For example, these compound semiconductors or oxide semiconductors can be used as resistive elements, pixel electrodes, and electrodes with translucency. Furthermore, since they can be deposited or formed simultaneously with the transistor, the cost can be reduced. Moreover, it is possible to use transistors formed by inkjet or printing methods. By these means, it becomes possible to manufacture at room temperature, at low vacuum, or on a large substrate.

[0027] Since it is possible to manufacture without using a mask (reticle), the layout of the transistor can be easily changed. Furthermore, since there is no need to use a resist, the material cost can be reduced and the number of processes can be decreased. Moreover, since the film is applied only to the necessary parts, the material is not wasted and the cost can be reduced compared to the manufacturing method of etching after depositing the film over the entire surface.

[0028] In addition, it is possible to use transistors having an organic semiconductor or a carbon nanotube. By these means, it becomes possible to form a transistor on a substrate that can be bent. A semiconductor device using such a substrate can be made resistant to shock.

[0029] Furthermore, transistors with various structures can be used. For example, MOS transistors, junction transistors, bipolar transistors, etc. can be used as the transistor. ​​​​It becomes possible. By using MOS transistors, the size of the transistors can be reduced. It becomes possible. Therefore, a large number of transistors can be mounted. By using bipolar transistors, a large current can be passed. Therefore, the circuit can be operated at high speed.

[0030] Note that MOS transistors, bipolar transistors, etc. may be mixed and formed on one substrate. As a result, low power consumption, miniaturization, high-speed operation, etc. can be realized.

[0031] In addition, various transistors can be used.

[0032] Note that transistors can be formed using various substrates. The type of substrate is not limited to a specific one. As the substrate, for example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a stainless steel substrate, a substrate having stainless steel foil, etc. can be used.

[0033] Note that the configuration of the transistor can take various forms and is not limited to a specific configuration. For example, a multi-gate structure with two or more gate electrodes can be applied. In the multi-gate structure, since the channel regions are connected in series, a configuration in which a plurality of transistors are connected in series is formed.

[0034] As another example, a structure in which gate electrodes are arranged above and below the channel can be applied. Note that by configuring the gate electrodes to be arranged above and below the channel, a configuration in which a plurality of transistors are connected in parallel is formed.

[0035] A structure in which a gate electrode is disposed above the channel region, a gate electrode below the channel region A structure in which, a normal stagger structure, an inverse stagger structure, a structure in which the channel region is divided into a plurality of regions A structure in which the channel regions are connected in parallel, or a configuration in which the channel regions are connected in series is also applicable. Further, a structure in which a source electrode or a drain electrode overlaps with the channel region (or a part thereof) is also applicable. Alternatively, a structure provided with an LDD region can be applied.

[0036] Note that various types of transistors can be used and can be formed using various substrates. Therefore, all of the circuits necessary to realize a predetermined function can be formed on the same substrate. For example, all of the circuits necessary to realize a predetermined function can be formed using various substrates such as a glass substrate, a plastic substrate, a single crystal substrate, or an SOI substrate. Alternatively, a part of the circuits necessary to realize a predetermined function may be formed on a certain substrate, and another part of the circuits necessary to realize a predetermined function may be formed on another substrate. That is, all of the circuits necessary to realize a predetermined function do not have to be formed using the same substrate. For example, a part of the circuits necessary to realize a predetermined function is formed by transistors on a glass substrate, and another part of the circuits necessary to realize a predetermined function is formed on a single crystal substrate, and an IC chip composed of transistors formed using the single crystal substrate is connected to the glass substrate by COG (Chip On Glass), and the IC chip is disposed on the glass substrate. Alternatively, the IC chip can be connected to the glass substrate by TAB (Tape Automate On Glass) and the IC chip is disposed on the glass substrate. It is also possible to connect it to the glass substrate using a printed circuit board or a bonding method. Alternatively, circuits with high drive voltages and high drive frequencies consume large amounts of power. Therefore, the circuits for such parts are not formed on the same substrate. Instead, for example, The circuit for that part is formed on a single crystal substrate, and an IC chip composed of that circuit is used. This can prevent an increase in power consumption.

[0037] A transistor is defined as a transistor having at least three terminals including a gate, a drain, and a source. A channel region is provided between the drain region and the source region. A current can be passed through the drain region, the channel region, and the source region. The source and drain depend on the transistor structure and operating conditions, so it is unclear which is the source and which is the drain. Therefore, it is difficult to determine whether the source or drain is the same. In some cases, the region that functions as a source or drain is not called a source or drain. In some cases, they are referred to as the first terminal and the second terminal. They may be referred to as the first electrode and the second electrode. Or, they may be referred to as the first region and the second region. There is a match.

[0038] A transistor has at least three terminals including a base, an emitter, and a collector. In this case, the emitter and the collector are connected to the first terminal and the second terminal. It may be written as 2 terminals, etc.

[0039] Semiconductor devices include semiconductor elements (transistors, diodes, thyristors, etc.). It also refers to devices that have circuits that can function by utilizing the characteristics of semiconductors. The whole may be referred to as a semiconductor device. Or, a device having a semiconductor material is called a semiconductor device as well.

[0040] Note that a display device refers to a device having display elements. Note that the display device may include a plurality of pixels including the display elements Note that the display device may include a peripheral drive circuit for driving a plurality of pixels. Note that the peripheral drive circuit for driving a plurality of pixels may be formed on the same substrate as the plurality of pixels Note that the display device may include a peripheral drive circuit arranged on the substrate by wire bonding, bumping, etc., that is, an IC chip connected by so-called chip-on-glass (COG) Note that the display device may include an IC chip, a resistor element, a capacitor element, an inductor, a transistor, etc. connected by a flexible printed circuit (FPC). Note that the display device may include a printed wiring board (PWB) to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, etc. are attached, connected via a flexible printed circuit (FPC), etc. Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate. Note that the display device may include an illumination device, a housing, an audio input / output device, a light sensor, etc. Note that the illumination device may have a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc. Note that a light-emitting device refers to a device having a light-emitting element, etc. As a display element, the emission Note that the display device may include a printed wiring board (PWB) to which an IC chip, a resistor element, a capacitor element, an inductor, a transistor, etc. are attached, connected via a flexible printed circuit (FPC), etc. Note that the display device may include an optical sheet such as a polarizing plate or a retardation plate. Note that the display device may include an illumination device, a housing, an audio input / output device, a light sensor, etc. Note that the illumination device may have a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc.

[0041] Note that the illumination device may have a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc. Note that the illumination device may have a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc. Note that the illumination device may have a backlight unit, a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, a light source (LED, cold cathode tube, etc.), a cooling device (water-cooled, air-cooled), etc.

[0042] Note that a light-emitting device refers to a device having a light-emitting element, etc. As a display element, the emission When the light emitting device has a light element, the light emitting device is a specific example of a display device.

[0043] The reflecting device is a device having a light reflecting element, a light diffractive element, a light reflecting electrode, etc. It is said.

[0044] Note that the liquid crystal display device refers to a display device having a liquid crystal element. There are direct-view, projection, transmissive, reflective, and semi-transmissive types.

[0045] In addition, a driving device refers to a device that has semiconductor elements, electric circuits, and electronic circuits. For example, a transistor that controls the input of a signal from a source signal line to a pixel (selection transistor) (sometimes called a transistor for switching, etc.) and supplies a voltage or current to the pixel electrode. The transistors that supply a voltage or current to the light-emitting element are Furthermore, a circuit for supplying a signal to the gate signal line (a gate driver, A circuit that supplies signals to the source signal lines (sometimes called a source line driver circuit, etc.) A pixel driver (sometimes called a pixel driver or a source line driver circuit) is an example of a driver device.

[0046] In addition, the present invention is applicable to display devices, semiconductor devices, lighting devices, cooling devices, light-emitting devices, reflecting devices, driving devices, etc. For example, a display device may include a semiconductor device and a light emitting device. Alternatively, the semiconductor device may include a display device and a driving device. This may be the case.

[0047] Note that it is not explicitly stated that B is formed on A, or that B is formed on A. In the case of the above, it is not limited to B being formed directly on A. If not, that is, it shall also include the case where another object is interposed between A and B. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers , etc.).

[0048] Therefore, for example, when it is explicitly described that layer B is formed on (or above) layer A, it includes the case where layer B is formed directly in contact with layer A, and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed on layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed directly in contact with layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed directly in contact with layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed directly in contact with layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer.

[0049] Furthermore, the same applies when it is explicitly described that B is formed above A. It is not limited to the case where B is directly in contact with A, and it shall also include the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that B is formed above A, it includes the case where B is directly in contact with A and the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that B is formed above A, it includes the case where B is directly in contact with A and the case where another object is interposed between A and B. Therefore, for example, when it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer. When it is described that layer B is formed above layer A, it includes the case where layer B is formed directly in contact with layer A and the case where another layer (for example, layer C or layer D, etc.) is formed directly in contact with layer A and layer B is formed directly in contact with that layer. Note that another layer (for example, layer C or layer D, etc.) may be a single layer or a multi - layer.

[0050] In addition, when it is explicitly described that B is formed on A, on A, or above A, the case where B is formed obliquely above shall also be included. When it is explicitly described that B is formed on A, on A, or above A, the case where B is formed obliquely above shall also be included. When it is explicitly described that B is formed on A, on A, or above A, the case where B is formed obliquely above shall also be included.

[0051] In addition, the same applies to the case where B is under A or below A.

[0052] In addition, for those explicitly described as singular, it is desirable to be singular. However, it is not limited to this, and it is also possible to be plural. Similarly, for those explicitly described as plural, it is desirable to be plural. However, it is not limited to this, and it is also possible to be singular. In addition, for those explicitly described as plural, it is desirable to be plural. However, it is not limited to this, and it is also possible to be singular. However, it is not limited to this, and it is also possible to be singular.

[0053] In addition, in the figures, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. However, it is not necessarily limited to that scale.

[0054] In addition, the figures schematically show ideal examples and are not limited to the shapes or values shown in the figures. For example, it is possible to include variations in shape due to manufacturing techniques, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations. For example, it is possible to include variations in shape due to manufacturing techniques, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations. In addition, the figures schematically show ideal examples and are not limited to the shapes or values shown in the figures. For example, it is possible to include variations in shape due to manufacturing techniques, variations in shape due to errors, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations. However, it is not necessarily limited to that scale.

[0055] In addition, technical terms are often used for the purpose of describing specific embodiments or examples, etc., and are not limited to this. However, it is not limited to this.

[0056] In addition, words that are not defined (including scientific and technical words such as technical terms or academic terms) can be used as having a meaning equivalent to the general meaning understood by those of ordinary skill in the art. Words defined by a dictionary, etc. are preferably interpreted in a meaning that does not conflict with the background of the related technology. In addition, words that are not defined (including scientific and technical words such as technical terms or academic terms) can be used as having a meaning equivalent to the general meaning understood by those of ordinary skill in the art. Words defined by a dictionary, etc. are preferably interpreted in a meaning that does not conflict with the background of the related technology. In addition, words that are not defined (including scientific and technical words such as technical terms or academic terms) can be used as having a meaning equivalent to the general meaning understood by those of ordinary skill in the art. Words defined by a dictionary, etc. are preferably interpreted in a meaning that does not conflict with the background of the related technology. However, it is not limited to this.

[0057] In addition, terms such as first, second, third, etc. are used to describe various elements, members, regions, layers, areas separately from others. Therefore, terms such as first, second, third, etc. do not necessarily indicate an order or importance of the elements, parts, etc. Therefore, terms such as first, second, third, etc. do not necessarily indicate an order or importance of the elements, parts, etc. It does not limit the number of materials, regions, layers, areas, etc. Further, for example, "first" can be replaced with "second", "third", etc. It is possible to replace "second" or "third", etc.

Advantages of the Invention

[0058] The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or droop of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the deterioration of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller. It is possible to reduce the number of transistors connected to the capacitive element. Or, it is possible to reduce the parasitic capacitance of the transistors connected to the capacitive element. Or, it is possible to increase the potential of the H level of the signal synchronized with the clock signal. Or, it is possible to reduce the layout area. Or, it is possible to extend the lifespan. It is possible to reduce the delay or droop of the signal. Or, it is possible to reduce the power consumption. Or, it is possible to reduce the influence of noise. Or, it is possible to suppress or mitigate the deterioration of the transistors. Or, it is possible to suppress malfunction. Or, it is possible to prevent a short circuit between one electrode and the other electrode of the capacitive element. Or, it is possible to reduce the current driving ability of the external circuit. Or, it is possible to reduce the size of the external circuit. Or, it is possible to make the display device smaller. The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or droop of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the deterioration of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller. The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or droop of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the deterioration of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller. The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or droop of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the deterioration of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller. The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or droop of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the deterioration of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller. The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or droop of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the deterioration of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller. The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or droop of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the deterioration of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller. The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or droop of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the deterioration of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller. The number of transistors connected to the capacitive element can be reduced. Or, the parasitic capacitance of the transistors connected to the capacitive element can be reduced. Or, the potential of the H level of the signal synchronized with the clock signal can be increased. Or, the layout area can be reduced. Or, the lifespan can be extended. The delay or droop of the signal can be reduced. Or, the power consumption can be reduced. Or, the influence of noise can be reduced. Or, the deterioration of the transistors can be suppressed or mitigated. Or, malfunction can be suppressed. Or, a short circuit between one electrode and the other electrode of the capacitive element can be prevented. Or, the current driving ability of the external circuit can be reduced. Or, the size of the external circuit can be reduced. Or, the display device can be made smaller.

Brief Description of the Drawings

[0059]

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Embodiments for Carrying Out the Invention

[0060] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, this embodiment is not to be construed as being limited to the described content. In the configurations described below, the same reference numerals are used to denote the same components among different drawings, and detailed descriptions of the same parts or parts having the same function are omitted.

[0061] Note that the content described in one embodiment (even a part of the content) can be applied to, combined with, or replaced with the content described in another part (even a part of the content) in the same embodiment, and / or the content described in one or more other embodiments (even a part of the content). That is, operations such as application, combination, or replacement can be performed.

[0062] Note that the content described in the embodiments refers to the content described using various drawings in each embodiment, or the content described using the text described in the specification. That is, it is the content described using the text described in the specification.

[0063] Note that the figure (which may be only a part) described in a certain embodiment can be combined with another part of that figure, the figure (which may be only a part) described in that embodiment, and / or one or more other figures (which may be only a part) described in one or more other embodiments to form even more figures.

[0064] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. Note that the semiconductor device can be represented as a drive circuit or a flip-flop.

[0065] First, an example of the semiconductor device of this embodiment will be described with reference to FIG. 1(A). The semiconductor device in FIG. 1(A) includes a circuit 100, transistors 101, 102, 103, 104, a capacitor element 105, and a capacitor element 106. The transistors 101 to 104 are each assumed to be N-channel type, and are turned on when the potential difference (Vgs) between the gate and the source exceeds the threshold voltage (Vth). However, it is not limited to this, and the transistors 101 to 104 can each be P-channel type. A P-channel type transistor is turned on when the potential difference (Vgs) between the gate and the source is lower than the threshold voltage (Vth).

[0066] The connection relationship of the semiconductor device in FIG. 1(A) will be described. The first terminal of the transistor 101 is connected to the wiring 123B, and the second terminal of the transistor 101 is connected to the wiring 121. The first terminal of the transistor 102 is connected to the gate of the transistor 101, the second terminal of the transistor 102 is connected to the wiring 121, and the gate of the transistor 102 is connected to wiring 123C. The first terminal of transistor 103 is connected to wiring 122A and continued, and the second terminal of transistor 103 is connected to the gate of transistor 101 . The first terminal of transistor 104 is connected to wiring 122B, and the second terminal of transistor 104 is connected to the gate of transistor 103. One electrode of capacitor element 105 is connected to the gate of transistor 101, and the other electrode of capacitor element 105 is connected to wiring 12 1. One electrode of capacitor element 106 is connected to wiring 123, and the other electrode of capacitor element 106 is connected to the gate of transistor 103.

[0067] Note that the connection point of the gate of transistor 101, the first terminal of transistor 102, the second terminal of transistor 103, or the gate of transistor 104 is indicated as node A. Then the connection point of the gate of transistor 103, the second terminal of transistor 104, or the other electrode of capacitor element 106 is indicated as node B. However, it is possible to indicate node A and node B as wiring.

[0068] Note that it is possible to indicate wiring 121, wiring 123A, wiring 123B, wiring 123C, wiring 122A, and wiring 1 22B as terminals.

[0069] An example of what can be input to each wiring (wiring 121, wiring 122A - 122B, wiring 123A - 123C) will be described. However, the content described below is an example and is not limited to this. To each wiring, in addition to what is described below, various other things can be input, and each wiring can be in a floating state (hereinafter, floating state). is also possible.

[0070] As an example, it is assumed that a signal S1 is output from the wiring 121. Therefore, the wiring 121 can function as a signal line. In particular, when the wiring 121 is connected to a pixel or when the wiring 121 is arranged to extend into the pixel portion, the wiring 121 can function as a gate line, a scanning line, or a capacitance line. The signal S1 is an output signal of the semiconductor device and is often a digital signal having an H level and an L level, and can function as an output signal, a selection signal, a gate signal, or a scanning signal.

[0071] As an example, it is assumed that a voltage V1 is supplied to the wirings 122A to 122B. Therefore, the wirings 122A to 122B can function as power supply lines. The voltage V1 is often a value approximately equal to the L level of the signal S1 and can function as a ground voltage, a power supply voltage, or a negative power supply voltage. However, it is not limited to this, and a signal such as a clock signal can be input to the wirings 122A to 122B. In this case, the wirings 12 2A to 122B can function as signal lines or clock signal lines. Also it is possible for different voltages or different signals to be input to the wirings 122A to 122B .

[0072] Note that "approximately" includes various errors such as errors due to noise, errors due to process variations, errors due to variations in the device fabrication process and / or measurement errors.

[0073] As an example, it is assumed that a signal S2 is input to the wirings 123A to 123C. Therefore, Wires 123A to 123C can function as signal lines. Signal S2 is often a digital signal that repeats between H level and L level at a constant period and can function as a clock signal (CK). However, it is not limited to this, and a power supply voltage can be supplied to wires 123A to 123C. In this case, wires 123A to 12 3C can function as power supply lines. Alternatively, different voltages or different signals can be input to wires 123A to 123B.

[0074] In this embodiment, as an example, let the potential of the L level of the signal be V1 and the potential of the H level of the signal be V2, and assume that V2 > V1. However, it is not limited to this.

[0075] Note that voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential). Therefore, it is possible to interchangeably refer to voltage, potential, and potential difference as potential, voltage, and voltage difference, respectively.

[0076] An example of the functions of circuit 100, transistors 101 to 104, capacitor element 105, and capacitor element 106 will be described. However, the content described below is an example and is not limited to this. Circuit 100 and each element can have various functions in addition to the functions described below, and it is also possible that they do not have the functions described below.

[0077] Circuit 100 has a function of controlling the potential or state of node A and a function of controlling the potential or state of wire 121. For example, circuit 100 has a function of increasing the potential of node A or wire 12 1, a function of decreasing the potential of node A or wire 12 1, and / or has a function of floating node A or wiring 121. Trans The transistor 101 has a function of raising the potential of wiring 12 1 in response to a signal (e.g., signal S2) input to wiring 123B. The transistor 102 has a function of controlling the timing at which wiring 121 and node A are electrically connected in response to a signal (e.g., signal S2) input to wiring 123C, and functions as a switch. The transistor 103 controls the timing at which wiring 122A and node A are electrically connected in response to the potential of node B, and functions as a switch. The transistor 104 has a function of controlling the timing at which wiring 122B and node B are electrically connected in response to the potential of node A, and functions as a switch. The capacitor element 105 has a function of raising the potential of node A in response to the potential of wiring 126 and / or a function of holding the potential difference between the gate of transistor 101 and the second terminal. The capacitor element 106 has a function of controlling the potential of node B in response to a signal (e.g., signal S2) input to wiring 123A.

[0078] Next, the operation of the semiconductor device in FIG. 1(A) will be described with reference to FIGS. 1(B), 2(A) to (E). FIG. 1(B) is an example of a timing chart for explaining the operation of the semiconductor device, and has periods T1, T2, T3, T4, and T5. In FIG. 1(B), signal S1, signal S2, the potential Va of node A, and the potential Vb of node B are shown. FIG. 2(A) shows a schematic diagram of the operation of the semiconductor device in FIG. 1(A) in period T1. FIG. 2(B) shows a schematic diagram of the operation of the semiconductor device in FIG. 1(A) in period T2. FIG. 2(C) shows a schematic diagram of the operation of the semiconductor device in FIG. 1(A) in period T3. FIG. 2(D) shows ​​​​​​​​​​​​​Fig. 1(A) shows a schematic diagram of the operation of the semiconductor device during period T4. Fig. 2(E) shows a schematic diagram of the operation of the semiconductor device during period T 5 of Fig. 1(A).

[0079] Note that when the potential of node A rises, the semiconductor device sequentially performs the operations in period T1, period T2 operation, and the operation in period T3. After that, until the potential of node A rises again the semiconductor device sequentially repeats the operations in period T4 and period T5 .

[0080] First, in period T1, signal S2 becomes the L level. Then, since transistor 102 turns off nodes A and 121 are in a non-conductive state. At the same time, the potential of node B decreases due to the capacitive coupling of capacitor element 106. When the potential of node B at this time is lower than the sum (V1 + V th106) of the potential of wiring 122A (V1) and the threshold voltage (Vth106) of transistor 103 transistor 103 turns off. Thus, wiring 122A and node A are in a non-conductive state. On the other hand, circuit 100 starts to raise the potential of node A. When the potential of node A reaches the sum (V1 + Vth104) of the potential of wiring 122B (V1) and the threshold voltage (Vth104) of transistor 1 04, transistor 104 turns on. Then, wiring 122B and node B become conductive. Thus voltage V1 is supplied from wiring 122B to node B, so the potential of node B becomes V1 . As a result, transistor 103 remains off, so wiring 122A and node A remain in a non-conductive state. Similarly, when the potential of node A reaches the sum (V1 + Vth101) of the potential of wiring 123B (V1) and the threshold voltage (Vth101) of transistor 101 and ​ Meanwhile, transistor 101 turns on. Then, wiring 123B and wiring 121 become conductive. Therefore, the signal S2 at the L level is supplied from wiring 123B to wiring 121. As a result, the potential of wiring 121 becomes approximately equal to the potential of wiring 123B (the L level of signal S2, or V1). After that, when the circuit 100 raises the potential of node A to a certain value (for example, equal to or higher than V1 + Vth101 and equal to or lower than V2) and then stops supplying a signal to node A, the circuit 100 and node A become non-conductive. Therefore, node A becomes a floating state, and the potential of node A is

[0081] maintained at a high value. At this time, the potential difference between node A and wiring 121 is held in the capacitive element 105. Note that during period T1, the circuit 100 can supply voltage V1 or a signal at the L level to wiring 121. Alternatively, the circuit 100 can make the circuit

[0082] 100 and wiring 121 non-conductive by not supplying a signal or the like to wiring 121. Thus, the circuit 100 can make wiring 121 a floating state. Next, during period T2, since the potential of node A is maintained at a high value, transistor 104 remains on. Therefore, wiring 122B and node B remain conductive, and the potential of node B remains at V1. As a result, transistor 103 remains off, so wiring 122A and node A remain non-conductive. Similarly, The voltage level rises to the H level. Then, since the wiring 123B and the wiring 121 remain in a conductive state, the potential of the wiring 121 starts to rise. At the same time, since the transistor 102 turns on, the node A and the wiring 121 become conductive. However, when the potential of the wiring 121 rises to a value (V2 - Vth 102) obtained by subtracting the threshold voltage (Vth102) of the transistor 102 from the potential of the wiring 123C (V2), the transistor 102 turns off. Therefore, the wiring 121 and the node A become non-conductive. Here, the capacitor element 105 remains holding the potential difference between the wiring 1 21 and the node A during the period T1. Therefore, when the potential of the wiring 121 rises, the potential of the node A rises to V2 + Vth101 + α (α is a positive number) due to the capacitive coupling of the capacitor element 105. This is a so-called bootstrap operation. Therefore, the potential of the wiring 121 rises until it becomes equal to the potential of the wiring 123B (the H level of the signal S2, or V1).

[0083] Note that in the period T2, since the circuit 100 often does not supply a signal or the like to the node A, the circuit 100 and the node A often become non-conductive. Thus, the circuit 100 often makes the node A in a floating state.

[0084] Note that in the period T2, since the circuit 100 often does not supply a signal or the like to the wiring 121, the circuit 100 and the wiring 121 often become non-conductive.

[0085] Next, in the period T3, after the signal S2 decreases from the H level to the L level, the circuit 100 decreases the potential of the node A so as to be V1. Therefore, when the potential of the node A reaches the potential of the wiring ​Until the sum (V1 + Vth101) of the potential (V1) of 123B and the threshold voltage (Vth101) of transistor 101 is reached, transistor 101 is on. Therefore, the L level signal S2 of the bell is supplied from wiring 123B to wiring 121, so the potential of wiring 121 decreases to the potential (V1) of wiring 123B. Similarly, until the potential of node A becomes the sum (V1 + Vth104) of the potential (V1) of wiring 122B and the threshold voltage (Vth104) of transistor 104, transistor 104 is on. Therefore, since voltage V 1 is supplied from wiring 122B to node B, the potential of node B remains at V1. As a result, since transistor 103 remains off, wiring 122A and node A remain non-conductive. At this time, the potential difference between the potential of wiring 123A (the L level of signal S2, or V1) and the potential of wiring 122B (V1) is held in capacitor element 106.

[0086] Note that in period T3, circuit 100 can supply voltage V1 or an L-level signal to wiring 121. Or, by not supplying a signal or the like to wiring 121, circuit 100 and wiring 121 can be made non-conductive. Thus, circuit 100 can make wiring 121 in a floating state.

[0087] Next, in period T4, signal S2 rises from the L level to the H level. At this time, since the potential of node A remains at V1, transistors 101 and 104 remain off. Therefore, since node B remains in a floating state, the potential of node B rises due to the capacitive coupling of capacitor element 106. When the potential of node B becomes the potential (V1) of wiring 122A ​​​​​​​Higher than the sum (V1 + Vth103) with the threshold voltage (Vth103) of transistor 103 If it becomes higher, transistor 103 turns on. Then, wiring 122A and node A become conductive. Therefore, since voltage V1 is supplied from wiring 122A to node A, the potential of node A is maintained at V1. At the same time, since transistor 102 turns on, wiring 121 and node A become conductive. At this time, voltage V1 is supplied to node A from wiring 122 A. Therefore, voltage V1 is supplied from wiring 122A to wiring 121, and the potential of wiring 121 is maintained at V1.

[0088] Note that in period T4, circuit 100 can supply voltage V1, an L-level signal, etc. to node A. Or, circuit 100 can make circuit 100 and node A non-conductive by not supplying a signal, etc. to node A. And, circuit 100 can make node A in a floating state.

[0089] Note that in period T5, circuit 100 can supply voltage V1, an L-level signal, etc. to wiring 121. Or, circuit 100 can make circuit 100 and wiring 121 non-conductive by not supplying a signal, etc. to wiring 121. Then, circuit 100 can make wiring 121 in a floating state.

[0090] Next, in period T5, signal S2 decreases from the H level to the L level. At this time, since the potential of node A remains at V1, transistors 101 and 104 remain off. Therefore, the potential of node B decreases due to the capacitive coupling of capacitive element 106. This is the case. If the potential of node B becomes lower than the sum (V1 + Vth103) of the potential of wiring 122A (V1) and the threshold voltage (V th103) of transistor 103, transistor 10 3 turns off. Thus, wiring 122A and node A are in a non-conductive state. Similarly, since transistor 102 turns off, wiring 121 and node A are in a non-conductive state. At this time, if circuit 100 supplies an L-level signal or voltage V1 to node A and wiring 121, the potential of node A and the potential of wiring 121 are maintained at V1. However, if circuit 100 does not supply an L-level signal or voltage V1 or the like to node A and wiring 121, node A and wiring 121 are in a floating state, so the potential of node A and the potential of wiring 121 are maintained at V1. In the semiconductor device of FIG. 1(A), compared with the conventional technology, the number of transistors connected to the other electrode of the capacitive element 106 can be reduced. Therefore, the parasitic capacitance connected to the other electrode of the capacitive element 106, that is, the parasitic capacitance of node B, can be reduced. Note that the parasitic capacitance refers to the combined capacitance such as the gate capacitance of a transistor, the parasitic capacitance between the gate and source of a transistor, the parasitic capacitance between the gate and drain of a transistor, and / or the wiring capacitance. However, it is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitive element 106.

[0091] In the semiconductor device of FIG. 1(A), compared with the conventional technology, the number of transistors connected to the other electrode of the capacitive element 106 can be reduced. Therefore, the parasitic capacitance connected to the other electrode of the capacitive element 106, that is, the parasitic capacitance of node B, can be reduced. Note that the parasitic capacitance refers to the combined capacitance such as the gate capacitance of a transistor, the parasitic capacitance between the gate and source of a transistor, the parasitic capacitance between the gate and drain of a transistor, and / or the wiring capacitance. However, it is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitive element 106. In addition, in the semiconductor device of FIG. 1(A), since the parasitic capacitance of node B can be reduced, the capacitance value of the capacitive element 106 can be made smaller than that of the conventional technology. Therefore, the capacitive element is not limited to this, and a plurality of transistors can be connected to the other electrode of the capacitive element 106.

[0092] Alternatively, in the semiconductor device of FIG. 1(A), since the parasitic capacitance of node B can be reduced, the capacitance value of the capacitive element 106 can be made smaller than that of the conventional technology. Therefore, the capacitive element Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent short - circuiting between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of a signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of an external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on - resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Or, in the semiconductor device of Fig. 1(A), in period T2, before the transistor 102 turns off, the node A and the wiring 121 often become conductive. Therefore, since the potential of node A decreases, the gate voltages of the transistor 101 and the transistor 104 can be reduced. Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent short - circuiting between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of a signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of an external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent short - circuiting between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of a signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of an external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent short - circuiting between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of a signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of an external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced. Since the area where one electrode of the capacitor 106 overlaps with the other electrode can be reduced, the layout area of the capacitor element 106 can be reduced. As a result, it is possible to prevent short - circuiting between one electrode and the other electrode of the capacitor element 106 due to dust or the like. Therefore, the yield can be improved or the cost can be reduced. Or, since the load on the wiring 123A can be reduced, the distortion or delay of a signal (for example, signal S2) input to the wiring 123A can be reduced. Or, since the current driving ability of an external circuit that supplies a signal to the wiring 123A can be reduced, the size of the external circuit can be reduced.

[0093] Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on - resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on - resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on - resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on - resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on - resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on - resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced. Or, in the semiconductor device of Fig. 1(A), since the parasitic capacitance of node B can be reduced, the amplitude voltage of node B when the potential of the wiring 123A changes can be increased. Thus, in period T4, the potential of node B can be made higher than in the prior art, and the Vgs of the transistor 103 can be increased. That is, since the on - resistance of the transistor 103 can be reduced, it becomes easier to maintain the potential of node B at V1 in period T4. Or, since the channel width (W) of the transistor 103 can be reduced, the layout area can be reduced.

[0094] Or, in the semiconductor device of Fig. 1(A), in period T2, before the transistor 102 turns off, the node A and the wiring 121 often become conductive. Therefore, since the potential of node A decreases, the gate voltages of the transistor 101 and the transistor 104 can be reduced. Or, in the semiconductor device of Fig. 1(A), in period T2, before the transistor 102 turns off, the node A and the wiring 121 often become conductive. Therefore, since the potential of node A decreases, the gate voltages of the transistor 101 and the transistor 104 It can be lowered. As a result, the characteristics of transistor 101 and transistor 104 Deterioration can be suppressed. Or, transistor 101 and transistor 104 Can be prevented from being destroyed. Or, as a transistor, a transistor with a gate insulating film Thinned to improve mobility can be used. When using such a transistor The channel width (W) of the transistor can be reduced. Therefore, The layout area can be reduced.

[0095] Or, in the semiconductor device of FIG. 1(A), all transistors can be of N-channel type or all Transistors can be of P-channel type. Therefore, compared with a CMOS circuit The number of processes can be reduced, the yield can be improved, or the cost can be reduced. In particular, when All transistors are of N-channel type, as the semiconductor layer of the transistor, an amorphous semiconductor, Microcrystalline semiconductor, organic semiconductor, or oxide semiconductor can be used. Therefore, The number of processes can be reduced, the yield can be improved, or the cost can be reduced, etc. However, it is not limited to this, and the semiconductor device of FIG. 1(A) can be configured by a CMOS circuit Combining P-channel type transistors and N Channel type transistors.

[0096] Or, in the semiconductor device of FIG. 1(A), in at least one of period T4 and period T5 Transistors 101 to 104 are turned off. Therefore, since the transistor does not stay on throughout one operation period, Deterioration of transistor characteristics such as an increase in threshold voltage or a decrease in mobility can be suppressed.

[0097] In particular, when using a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor as the semiconductor layer of the transistor, the characteristic degradation of the transistor becomes remarkable. However, in the semiconductor device of FIG. 1(A), since the characteristic degradation of the transistor can be suppressed, a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor can be used as the semiconductor layer of the transistor. However, it is not limited thereto, and a polycrystalline semiconductor or single crystal semiconductor can be used as the semiconductor layer.

[0098] Note that it is possible to indicate that period T2 is a selection period and the other periods (period T1, period T3, period T4, and period T5) are non-selection periods. Or, it is possible to indicate that period T1, period T2, period T3, period T4, and period T5 are a set period, an output period, a reset period, a first non-selection period, and a second non-selection period, respectively.

[0099] Note that the channel width (W) of transistor 101 can be larger than the channel width of transistor 102, transistor 103, and / or transistor 104. Or, among the transistors included in the semiconductor device, the channel width of transistor 101 can be the largest. In this case, since the on-resistance of transistor 101 becomes smaller, the rise time and fall time of the signal output from wiring 121 (for example, signal S1) become shorter. Therefore, in period T2, the timing at which transistor 102 turns off becomes earlier. Thus, it is possible to suppress the potential of node A from decreasing too much and the semiconductor device from malfunctioning. However, it is not limited thereto, and the channel width of transistor 101 ​is smaller than any one of the channel widths of transistors 102 to 104 or any one of the channel widths of the transistors included in the semiconductor device. It is possible.

[0100] Note that when referring to the channel width of a transistor, it can be rephrased as the W / L (L: channel length) ratio of the transistor. It is possible.

[0101] Note that the L-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be lower than V1. In this case, a reverse bias can be applied to the transistor, so that the characteristic degradation of the transistor can be mitigated. In particular, since the time during which transistor 102 is on is long, the L-level potential of the signal input to wiring 123C is preferably lower than V1. However, it is not limited thereto, and the L-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be higher than V1. It is possible. It is possible. In particular, since the time during which transistor 102 is on is long, the L-level potential of the signal input to wiring 123C is preferably lower than V1. However, it is not limited thereto, and the L-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be higher than V1. It is possible. It is possible.

[0102] Note that the H-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be lower than V2. In this case, the Vgs of the transistor becomes small, so that the characteristic degradation of the transistor can be suppressed. In particular, since the time during which transistor 102 is on is long, the H-level potential of the signal input to wiring 123C is preferably lower than V2. However, it is not limited thereto, and the H-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be higher than V2. It is possible. It is possible. In particular, since the time during which transistor 102 is on is long, the H-level potential of the signal input to wiring 123C is preferably lower than V2. However, it is not limited thereto, and the H-level potential of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be higher than V2. It is possible. It is possible.

[0103] The amplitude of the signal input to wiring 123A, wiring 123B, and / or wiring 123C The voltage can be smaller than V2 - V1. In particular, since the time for transistor 103 to turn on is long, it is preferable to make the amplitude of the signal input to wiring 123A smaller than V2 - V1. Thus, the Vgs of transistor 103 can be reduced, and deterioration of the characteristics of transistor 103 can be suppressed. However, it is not limited to this. The amplitude voltage of the signal input to wiring 123A, wiring 123B, and / or wiring 123C can be larger than V2 - V1.

[0104] It is possible to input a signal to wiring 122A and / or wiring 122B. In this way, since voltage V1 can be omitted, the number of power supplies can be reduced. Or, since a reverse bias can be applied to the transistor, deterioration of the characteristics of the transistor can be mitigated. In particular, to wiring 122A, a signal that becomes an L level during the period when transistor 103 turns on (for example, period T1, period T3, period T5) can be input. As an example, there is an inverted signal of signal S2 (hereinafter, also referred to as an inverted clock signal). To wiring 122B, a signal that becomes an L level during the period when transistor 104 turns on (for example, period T3, period T4, period T5) can be input.

[0105] It is possible to supply a voltage (for example, voltage V2 ) to wiring 123A, wiring 123B, and / or wiring 123C. By doing so, the semiconductor device can function as an inverter circuit , or a buffer circuit.

[0106] ​​Note that, as shown in Fig. 3(A), since the same voltage (e.g., voltage V1) is often supplied to wiring 122A and wiring 122B, it is possible to share wiring 122A and wiring 122B. For this reason, the first terminal of transistor 103 and the first terminal of transistor 104 are connected to wiring 122. Wiring 122 corresponds to wiring 122A or wiring 122B, and the same as these wirings can be input to wiring 122.

[0107] Note that sharing a plurality of wirings means connecting elements or circuits connected to the plurality of wirings to the same wiring. Or it means connecting the plurality of wirings to each other.

[0108] Note that, as shown in Fig. 3(B), since the same signal (e.g., signal S2) is often input to wirings 123A to 123C, it is possible to share wirings 123A to 123C. For this reason, the first terminal of transistor 101, the gate of transistor 102, and one electrode of capacitor element 106 are connected to wiring 123. Wiring 123 corresponds to wirings 123A to 123C, and the same as these wirings can be input to wiring 123. However, it is not limited to this, and it is possible to share only any two or more of wirings 123A to 123C.

[0109] Note that, similar to Fig. 3(B), in Fig. 3(A) as well, it is possible to share wirings 123A to 123C.

[0110] Note that, as shown in Fig. 3(C), by combining Fig. 3(A) and Fig. 3(B), wiring 122 ​​​​​​​​​​​​​It is possible to share A and wiring 122B, and further share wirings 123A to 123C. For example, the first terminal of transistor 103 and the first terminal of transistor 104 are connected to wiring 122, and the first terminal of transistor 101, the gate of transistor 102 and one electrode of capacitor element 106 can be connected to wiring 123.

[0111] In addition, as shown in Fig. 3(D), the gate of transistor 104 can be connected to wiring 121. By connecting the gate of transistor 104 to wiring 121, when transistor 104 is turned on, the gate voltage becomes V1, which is lower than the gate voltage (V1 + Vth101 + α) when transistor 104 in Fig. 1(A) is turned on. Therefore, breakdown of transistor 104 or deterioration of the characteristics of transistor 104 can be suppressed.

[0112] Similar to Fig. 3(D), in Figs. 3(A) to 3(C) as well, the gate of transistor 104 can be connected to wiring 121.

[0113] In addition, as shown in Fig. 3(E), the second terminal of transistor 103 can be connected to wiring 121. By connecting the second terminal of transistor 103 to wiring 121, during period T4, voltage V1 is supplied from wiring 122A to wiring 121, so it becomes easier to maintain the potential of wiring 121 at V1.

[0114] Similar to Fig. 3(E), in Figs. 3(A) to 3(D) as well, the second terminal of transistor 103 can be connected to wiring 121. ​​​

[0115] Note that, as shown in Fig. 4(A), it is possible to omit the capacitor element 105. In this case , the parasitic capacitance between the gate of the transistor 101 and the second terminal can be used as the capacitor element 105 .

[0116] Note that, in Fig. 4(A), when the parasitic capacitance between the gate of the transistor 101 and the second terminal is used as the capacitor element 105, in the transistor 101, the parasitic capacitance between the gate and the second terminal is preferably larger than the parasitic capacitance between the gate and the first terminal . Therefore, in the transistor 101, the overlapping area between the conductive layer functioning as the gate electrode and the conductive layer functioning as the source electrode or the drain electrode is preferably larger on the second terminal side than on the first terminal side. However, it is not limited thereto .

[0117] Note that, similar to Fig. 4(A), in Figs. 3(A) to 3(E) as well, it is possible to omit the capacitor element 105 .

[0118] Note that, as shown in Fig. 4(B), it is possible to use a MOS capacitor as the capacitor element 105 . In an example of Fig. 4(B), a transistor 105a is used as the capacitor element 105 . The transistor 105a is of the N-channel type. The first terminal and the second terminal of the transistor 105a are connected to the wiring 121, and the gate of the transistor 105a is connected to the node A. By doing so, during the periods (periods T1 and T2) when it is necessary to function as a capacitor element, since the potential of the node A is high, the gate capacitance of the transistor 105a can be increased. On the other hand, during the periods when it is not necessary to function as a capacitor element (for example T1 and period T2), since the potential of the node A is high, the gate capacitance of the transistor 105a can be increased. On the other hand, during the periods when it is not necessary to function as a capacitor element (for example ), ​​During periods T3, T4, and T5, the potential of the node A is low, so that the transistor 105 However, this is not limited to this, and the gate capacitance of the transistor 1 can be reduced. Alternatively, the first of the transistors 105a may be a P-channel type. One of the first terminal and the second terminal may be in a floating state. The gate of the transistor 105a is connected to the wiring 121, and the first and second terminals of the transistor 105a are connected to the wiring 121. The terminal of the transistor 105a can be connected to the node A. The channel region may be doped.

[0119] As in FIG. 4B, in FIGS. 3A to 3E and 4A, the capacitance element A transistor 105a is used as 105, and a first terminal and a second terminal of the transistor 105a are connected to each other. The terminal of the transistor 105a is connected to the wiring 121, and the gate of the transistor 105a is connected to the node A. It is possible.

[0120] As shown in FIG. 4C, a MOS capacitor can be used as the capacitor element 106. In the example of FIG. 4C, a transistor 106a is used as the capacitor 106. The transistor 106a is an N-channel type. The second terminal of the transistor 106a is connected to a node B, and the gate of the transistor 106a is connected to a wiring 123A. However, the present invention is not limited to this, and the transistor 106a is a P-channel type. Alternatively, one of the first terminal and the second terminal of the transistor 106a may be , or may be floating. Alternatively, the gate of transistor 106a may be connected to node B and a first terminal and a second terminal of the transistor 106a are connected to the wiring 123A. It is possible. Or, impurities can be added to the channel region of the transistor 106a. It is possible.

[0121] Similar to FIG. 4(C), in FIGS. 3(A) to (E) and FIGS. 4(A) to (B) as well, the transistor 106a is used as the capacitive element 106, and the first terminal and the second terminal of the transistor 106a are connected to the node B, and the gate of the transistor 106a can be connected to the wiring 123A. It is possible.

[0122] As shown in FIG. 4(D), it is possible to replace the transistor 103 with the diode 103a. The diode 103a corresponds to the transistor 103. And the diode 103a has a function of reducing the potential of the node A when the potential of the node B is lower than the potential of the node A, and a function of making the nodes A and B non-conductive when the potential of the node B is higher than the potential of the node A. One terminal of the diode 103a (hereinafter also referred to as the input terminal or the anode) is connected to the node A, and the other terminal of the diode 103a (hereinafter also referred to as the output terminal or the cathode) is connected to the node B. One terminal of the diode 103a (hereinafter (hereinafter also referred to as the output terminal or the cathode) is connected to the node B.

[0123] In FIG. 4(D), when replacing the transistor 103 with the diode 103a it is possible to supply the voltage V2 to the wiring 122B. Or, it is possible to input the inverted signal of the signal S2 (for example, the inverted clock signal) to the wiring 123A. It is possible to input the inverted signal of the signal S2 (for example, the inverted clock signal) to the wiring 123A.

[0124] Similar to FIG. 4(D), in FIGS. 3(A) to (E) and FIGS. 4(A) to (C) as well, replace the transistor 103 with the diode 103a, and one terminal of the diode 103a is connected to node A, and the other terminal of diode 103a is connected to node B, which is possible.

[0125] As shown in FIG. 4(E), it is possible to replace transistor 104 with diode 104a. In an example of FIG. 4(E), an example is shown in the case where not only transistor 104 but also transistor 103 is replaced with a diode. Diode 104a corresponds to transistor 104. And diode 104a has a function of raising the potential of node B when the potential of node A is higher than the potential of B, and a function of making nodes A and B in a non-conductive state when the potential of node A is lower than the potential of node B. One terminal of diode 104a is connected to node A, and the other terminal of diode 104a is connected to node B. connected to node B.

[0126] Similar to FIG. 4(E), in FIGS. 3(A) to (E) and FIGS. 4(A) to (D) as well, it is possible to replace transistor 104 with diode 104a, and one terminal of diode 104a is connected to node A, and the other terminal of diode 104a is connected to node B, which is possible.

[0127] As shown in FIG. 4(F), it is possible to use a diode-connected transistor as the diode. Diode-connected transistor 103 and diode connected transistor 104 respectively correspond to diode 103a and diode 104a. The first terminal of transistor 103 is connected to node B, and the second terminal and gate of transistor 103 are connected to node A. The first terminal and gate of transistor 104 ​​​​​​One end is connected to node A, and the second terminal of transistor 104 is connected to node B. However, without being limited thereto, the gate of transistor 103 can be connected to node B, and the gate of transistor 104 can be connected to node B.

[0128] Similar to FIG. 4(F), in FIGS. 3(A) to (E) and FIGS. 4(A) to (E) as well, the first terminal of transistor 103 can be connected to node B, the second terminal of transistor 103 can be connected to node A, and the gate of transistor 103 can be connected to node A. Or, the first terminal of transistor 104 can be connected to node A, the second terminal of transistor 104 can be connected to node B, and the gate of transistor 104 can be connected to node A. However, without being limited thereto, the gate of transistor 103 can be connected to node B, and the gate of transistor 104 can be connected to node B.

[0129] As shown in FIG. 5(A), it is possible to newly add diode 107. When an L-level signal is input to wiring 123A, diode 107 has a function of reducing the potential of node B, and when an H-level signal is input to wiring 123A, it has a function of making wiring 12 3A and node B in a non-conducting state. One terminal of diode 107 is connected to node B, and the other terminal of diode 107 is connected to wiring 123A. However, without being limited thereto, the other terminal of diode 107 can be connected to a wiring different from wiring 123A.

[0130] Similar to FIG. 5(A), in FIGS. 3(A) to (E) and FIGS. 4(A) to (F) as well,​​ A new diode 107 is added, and one terminal of the diode 107 is connected to node B , and the other terminal of the diode 107 can be connected to the wiring 123A.

[0131] In addition, as shown in Fig. 5(B), a newly added transistor 107a with a diode connection can be added. The transistor 107a with a diode connection corresponds to the diode 1 07 and is of the N-channel type. The first terminal of the transistor 107a is connected to the wiring 123 A, and the second terminal and the gate of the transistor 107a are connected to the node B. . However, it is not limited to this, and the transistor 107a can be of the P-channel type. Or the gate of the transistor 107a can be connected to the wiring 123A. is possible.

[0132] In addition, similar to Fig. 5(B), in Figs. 3(A) to (E), Figs. 4(A) to (F), and Fig. 5(A) , a newly added transistor 107a can be added, and the first terminal of the transistor 107a is connected to the wiring 123A, and the second terminal and the gate of the transistor 107a are connected to the node B. However, it is not limited to this, and the gate of the transistor 107a can be connected to the node B.

[0133] In addition, as shown in Fig. 5(C), the transistor 102 can be omitted.

[0134] In addition, similar to Fig. 5(C), in Figs. 3(A) to (E), Figs. 4(A) to (F), and Fig. 5(A) to (B), the transistor 102 can also be omitted.

[0135] Note that, as shown in FIG. 5(D), circuit 100 can be omitted.

[0136] Note that, similar to FIG. 5(D), in FIGS. 3(A) to (E), FIGS. 4(A) to (F), and FIG. 5(A) to (C) as well, circuit 100 can be omitted.

[0137] Note that, as shown in FIG. 5(E), transistors 101, 102, transistors 103, and transistor 104 can be replaced with transistors 101p, 102p, transistors 103p, and transistor 104p. Transistors 101p to 104p correspond to transistors 101 to 104 respectively and are assumed to be P-channel type.

[0138] Note that in FIG. 5(E), the potential relationships are often opposite to those of the semiconductor device in FIG. 1(A). For example, voltage V2 is supplied to wirings 122A to 122B, and the inverted signal of signal S2 can be input to wirings 123A to 123B. Similarly, the inverted signal of signal S1

[0139] is often output from wiring 121. Note that in FIG. 5(E), circuit 100 often has a function of reducing the potential of node A during period T1. Or, circuit 100 often has a function of

[0140] raising the potential of node A to V2 during period T3. Note that, similar to FIG. 5(E), in FIGS. 3(A) to (E), FIGS. 4(A) to (F), and FIG. 5(A) to (D) as well, P-channel transistors can be used as transistors 101 to 104.

[0141] (Embodiment 2) In this embodiment, an example of a semiconductor device will be described. The semiconductor device of this embodiment is a specific example of the semiconductor device described in Embodiment 1. In particular, in this embodiment, the specific example of circuit 100 will be described. Note that the content described in Embodiment 1 can be applied to the semiconductor device of this embodiment.

[0142] A specific example of circuit 100 will be described with reference to FIG. 6(A). However, FIG. 6(A) is merely an example and is not limited thereto. As circuit 100, various circuits other than FIG. 6(A) can be used. Note that the same parts as in FIG. 1(A) are denoted by the same reference numerals, and the description thereof will be omitted.

[0143] Circuit 100 includes transistor 131, transistor 132, transistor 133, transistor 134, and transistor 135. Transistors 131 to 135 are each assumed to be N-channel type. However, transistors 131 to 135 can be P-channel type.

[0144] The connection relationship of the transistors included in circuit 100 will be described. The first terminal of transistor 131 is connected to wiring 125, the second terminal of transistor 131 is connected to node A, and the gate of transistor 131 is connected to wiring 125. The first terminal of transistor 132 is connected to wiring 125, the second terminal of transistor 132 is connected to node A, and the gate of transistor 132 is connected to wiring 124A. The first terminal of transistor 133 is connected to wiring 122E, the second terminal of transistor 133 is connected is made, and the gate of transistor 133 is connected to wiring 124B. The first terminal of transistor 134 is connected to wiring 122C, and the second terminal of transistor 134 is connected to node A is continued, and the gate of transistor 134 is connected to wiring 126. The first terminal of transistor 135 is connected to wiring 122D, and the second terminal of transistor 135 is connected to wiring 121 is connected, and the gate of transistor 135 is connected to wiring 126.

[0145] An example of something (such as a signal, voltage, or current) that can be input to wirings 122C to 122E, wirings 124A to 124B, wiring 125, and wiring 126 will be described. However, the content described below is an example and is not limited thereto. In addition to the things described below, various things can be input to each wiring, and each wiring can be in a floating state (hereinafter, a floating state). is possible. Let it be assumed that a voltage V1 is supplied to wirings 122C to 122E in the same manner as to wirings 122A and 122B. Therefore, wirings 122C to 122E can function as power supply lines. However, it is not limited to this, and any signal such as a clock signal can be input to wirings 122C to 122E. In this case, wirings 122C to 122E can function as signal lines. Or, different voltages can be supplied to wirings 122C to 122E. is possible.

[0146] Let it be assumed that a voltage V1 is supplied to wirings 122C to 122E, just as to wirings 122A and 122B. Thus, wirings 122C to 122E can function as power supply lines. However, it is not limited to this, and any signal, such as a clock signal, can be input to wirings 122C to 122E. In this case, wirings 122C to 122E can function as signal lines. Or, different voltages can be supplied to wirings 122C to 122E. is possible. However, it is not limited to this, and any signal such as a clock signal can be input to wirings 122C to 122E. In this case, wirings 122C to 122E can function as signal lines. Or, different voltages can be supplied to wirings 122C to 122E. is possible. In this case, wirings 122C to 122E can function as signal lines. Or, different voltages can be supplied to wirings 122C to 122E. is possible.

[0147] As an example, let it be assumed that a signal S3 is input to wirings 124A to 124B. Thus, wirings 124A to 124B can function as signal lines. Signal S3 is, In many cases, it is a signal that is the inverted signal of signal S2 or a signal whose phase is approximately 180° shifted from that of signal S2, and it can function as an inverted clock signal (CKB). However, it is not limited to this, and it is possible to supply voltage to wirings 124A to 124B. In this case, wirings 124A to 124B can function as power supply lines. Or, it is possible to input different signals to wirings 124A to 124B. Often, it can function as an inverted clock signal (CKB). However, it is not limited to this. Rather, it is not limited to this, and it is possible to supply voltage to wirings 124A to 124B. In this case, wirings 124A to 124B can function as power supply lines. Or, it is possible to input different signals to wirings 124 A to 124B.

[0148] As an example, it is assumed that signal S4 is input to wiring 125. Therefore, wiring 12 5 can function as a signal line. Signal S4 is often a digital signal having an L level and an H level, and functions as a start signal (SP), a transmission signal from another row (stage), or a signal for selecting another row. However, it is not limited to this, and it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line. However, it is not limited to this. Rather, it is possible to supply voltage to wiring 125. In this case, wiring 125 can function as a power supply line.

[0149] As an example, it is assumed that signal S5 is input to wiring 126. Therefore, wiring 12 6 can function as a signal line. Signal S5 is often a digital signal having an L level and an H level, and functions as a reset signal (RE) or a signal for selecting another row. However, it is not limited to this. Rather, it is possible to supply voltage to wiring 126. In this case, wiring 126 can function as a power supply line. However, it is not limited to this. Rather, it is possible to supply voltage to wiring 126. In this case, wiring 126 can function as a power supply line.

[0150] An example of the functions of transistors 131 to 135 will be described. However, the content described below is an example and is not limited thereto. Transistors 131 to 135 are described below. However, the content described below is an example and is not limited thereto. Transistors 131 to 135 are described below. ​In addition to the functions described above, it is also possible to have various other functions, or not to have the functions described below. This is also possible.

[0151] Transistor 131 has the function of raising the potential of node A in response to a signal (e.g., signal S4) input to wiring 125, and functions as a diode. Transistor 132 has the function of controlling the timing at which wiring 125 and node A conduct in response to a signal (e.g., signal S3) input to wiring 124A, and functions as a switch. Transistor 1 has the function of controlling the timing at which wiring 122E and wiring 121 conduct in response to a signal (e.g., signal S3) input to wiring 124B, and functions as a switch. Transistor 133 has the function of controlling the timing at which wiring 122E and wiring 121 conduct in response to a signal (e.g., signal S3) input to wiring 124B, and functions as a switch. Transistor 134 has the function of controlling the timing at which wiring 122C and node A conduct in response to a signal (e.g., signal S5) input to wiring 126, and functions as a switch. Transistor 134 has the function of controlling the timing at which wiring 122C and node A conduct in response to a signal (e.g., signal S5) input to wiring 126, and functions as a switch. Transistor 135 has the function of controlling the timing at which wiring 122D and wiring 121 conduct in response to a signal (e.g., signal S5) input to wiring 126, and functions as a switch. Transistor 135 has the function of controlling the timing at which wiring 122D and wiring 121 conduct in response to a signal (e.g., signal S5) input to wiring 126, and functions as a switch. has the function of controlling the timing at which wiring 122D and wiring 121 conduct in response to a signal (e.g., signal S5) input to wiring 126, and functions as a switch. functions as such.

[0152] Next, the operation of the semiconductor device in Fig. 6(A) will be described with reference to Fig. 6(B), Figs. 7(A) to (C), and Figs. 8(A) to (B). Fig. 6(B) is an example of a timing chart for explaining the operation of the semiconductor device, and has a period T1, a period T2, a period T3, a period T4, and a period T5. Fig. 7(A) shows a schematic diagram of the operation of the semiconductor device in Fig. 6(A) during period T1. Fig. 7(B) shows a schematic diagram of the operation of the semiconductor device in Fig. 6(A) during period T2. Fig. 7(C) shows a schematic diagram of the operation of the semiconductor device in Fig. 6(A) during period T3. Fig. 7(C) shows a schematic diagram of the operation of the semiconductor device in Fig. 6(A) during period T3. Fig. 8(A) shows a schematic diagram of the operation of the semiconductor device of Fig. 6(A) in period T4. Fig. 8( B) shows a schematic diagram of the operation of the semiconductor device of Fig. 6(A) in period T5. Note that the parts common to the operation of the semiconductor device of Fig. 1( A) are not described again for simplicity.

[0153] First, in period T1, since signal S5 is at the L level, transistor 134 and transistor 135 turn off. Thus, wiring 122C and node A are in a non-conductive state, and wiring 122D and wiring 121 are in a non-conductive state. At the same time, since signals S3 and S4 become at the H level, transistors 131, 132, and transistor 133 turn on. Then, wiring 125 and node A become conductive, and wiring 122E and wiring 121 become conductive. Therefore, the signal (H-level signal S 4) input to wiring 125 is supplied from wiring 125 to node A, so the potential of node A starts to rise. Furthermore, since wiring 122E and wiring 121 are in a conductive state, voltage V1 is supplied from wiring 122E to wiring 121. After that, when the potential of node A rises to a value (V1 - Vth131) obtained by subtracting the threshold voltage (Vth131) of transistor 131 from the H-level potential (V1) of signal S4, transistor 131 turns off. Similarly, when the potential of node A rises to a value (V1 - Vth132) obtained by subtracting the threshold voltage (Vth132) of transistor 132 from the H-level potential (V1) of signal S3, transistor 132 turns off. When transistors 131 and 132 turn off, no charge is supplied to node A. Therefore, the potential of node A becomes a high value (at least V1 + Vth101 or more). When it rises to a value (V1 - Vth132), transistor 132 turns off. When transistors 131 and 132 turn off, no charge is supplied to node A. Therefore, the potential of node A becomes a high value (at least V1 + Vth101 or more). ) while remaining maintained at, node A becomes floating. Here, for convenience, when the potential of node A becomes V1 - Vth131, it is assumed that transistor 131 and transistor 132 turn off . Therefore, wiring 125 and node A become non-conductive. At this time, the potential of node A remains at V1 - Vth131, and node A becomes floating.

[0154] Next, in period T2, since signal S4 becomes the L level, transistor 131 remains off . And since signal S3 becomes the L level, transistor 132 remains off and transistor 133 turns off. Therefore, wiring 125 and node A remain non-conductive , and wiring 122E and wiring 121 become non-conductive. At this time, since signal S5 remains at the L level, transistor 134 and transistor 135 remain off . Therefore, wiring 122C and node A remain non-conductive, and wiring 122D and the wiring 121 remain non-conductive.

[0155] Next, in period T3, since signal S4 remains at the L level, transistor 131 remains off . And since signal S5 becomes the H level, transistor 134 and transistor 135 turn on. Then, wiring 122C and node A become conductive, and the wiring 122D and wiring 121 become conductive. Therefore, voltage V1 is supplied from wiring 122C to node A, so the potential of node A decreases to V1. Similarly, voltage V1 is supplied from wiring 122D to wiring 121, so the potential of wiring 121 decreases to V1 . At the same time, since signal S3 becomes the H level, transistor 132 and transistor Stage 133 is turned on. Then, wiring 125 and node A are in a conducting state, and wiring 12 2E and wiring 121 are in a conducting state. Thus, an L-level signal S4 is supplied to node A , and the potential of node A decreases to V1. Similarly, since voltage V1 is supplied to wiring 121 , the potential of wiring 121 decreases to V1.

[0156] Next, in period T4, since signal S4 remains at the L level, transistor 131 remains off . And since signal S5 becomes the L level, transistor 134 and transistor 135 turn off. Thus, wiring 122C and node A are in a non-conducting state, and wiring 122D and wiring 121 are in a non-conducting state. At this time, since signal S4 becomes the L level , transistor 132 and transistor 133 turn off. Thus, wiring 125 and node A are in a non-conducting state, and wiring 122E and wiring 121 are in a non-conducting state.

[0157] Next, in period T5, since signal S4 remains at the L level, transistor 131 remains off . And since signal S5 remains at the L level, transistor 134 and transistor 135 remain off. Thus, wiring 122C and node A remain in a non-conducting state , and wiring 122D and wiring 121 remain in a non-conducting state. At this time, since signal S4 becomes the H level, transistor 132 and transistor 133 turn on . Then, wiring 125 and node A are in a conducting state, and wiring 122E and wiring 121 are in a conducting state. Thus, an L-level signal S4 is supplied from wiring 125 to node A, so the potential of node A is maintained at V1. Similarly, voltage V1 is supplied from wiring 122E to wiring 121 Since it is supplied to, the potential of the wiring 121 is maintained at V1.

[0158] In the semiconductor device of FIG. 6(A), in periods T4 and T5, an L-level signal or the voltage V1 is supplied to node A, so that the noise of node A can be reduced. Therefore, maloperation can be prevented.

[0159] Alternatively, in the semiconductor device of FIG. 6(A), in period T1, since both the transistor 131 and the transistor 132 are turned on, the potential of node A can be raised quickly. Alternatively, the channel width of transistor 131, or the channel width of transistor 132 can be made smaller .

[0160] Note that the channel width of transistor 131 can be larger than the channel width of transistor 134, or the channel width of transistor 103. Similarly, the channel width of transistor 13 2 can be larger than the channel width of transistor 134, or the channel width of transistor 103. This is because, in period T2, it is preferable that the potential of node A rises faster, and in period T3, it is preferable that the potential of node A decreases slower . That is, in period T2, if the potential of node A rises quickly, the drive frequency can be improved, the through-current can be suppressed, and the power consumption can be reduced. On the other hand, in period T 3, if the potential of node A decreases slowly, the on-time of transistor 101 becomes longer so that the fall time of the signal (for example, signal S1) output from the wiring 121 can be shortened . Therefore, a transistor having a function of raising the potential of node A in period T2 The channel width of the transistor that decreases the potential of node A during period T3 is preferably larger than the channel width of the transistor. However, it is not limited thereto, and the channel width of transistor 1 31 can be smaller than the channel width of transistor 134 or the channel width of transistor 103. Similarly, the channel width of transistor 132 can be smaller than the channel width of transistor 134 or the channel width of transistor 103.

[0161] In addition, the sum of the channel width of transistor 131 and the channel width of transistor 134 can be larger than the channel width of transistor 134 or the channel width of transistor 103. This is because, during period T2, the H-level signal S4 is supplied from wiring 12 5 to node A through two transistors connected in parallel, namely transistor 13 1 and transistor 132. However, it is not limited thereto, and the sum of the channel width of transistor 131 and the channel width of transistor 134 can be smaller than the channel width of transistor 134 or the channel width of transistor 103.

[0162] In addition, the channel width of transistor 134 can be smaller than the channel width of transistor 133. Similarly, the channel width of transistor 132 can be smaller than the channel width of transistor 133. Similarly, the channel width of transistor 103 can be smaller than the channel width of transistor 102. This is because the load of wiring 1 21 (for example, wiring resistance, parasitic capacitance, connected transistors, etc.) is at node A ​​​​​​​​​This is because it is often greater than the load of Therefore, the channel width of the transistor having the function of supplying a signal or voltage to node A is preferably smaller than the channel width of the transistor that supplies a signal or voltage to wiring 121. However, it is not limited to this, and the channel width of transistor 134 can be larger than the channel width of transistor 133. Similarly, the channel width of transistor 132 can be larger than the channel width of transistor 133. Similarly, the channel width of transistor 103 can be larger than the channel width of transistor 102. It is possible for the channel width of transistor 103 to be larger than the channel width of transistor 132. This is because transistor 103 has the function of maintaining the potential of node A at V1 during period T4, while transistor 132 has the function of maintaining the potential of node A at V1 during period T5. Specifically, in period T4, the signal (for example, signal S2) input to wiring 123B becomes the H level. At this time, if the potential of node A rises and transistor 101 turns on, the potential of wiring 121 will rise. Therefore, transistor 103 is required to maintain the potential of node A at V1 and keep transistor 101 off, so the channel width of transistor 103 is preferably large. On the other hand, in period T5, the signal (for example, signal S2) input to wiring 123B becomes the L level, so even if transistor 101 turns on, the potential of wiring 121 will not rise. That is, even if the potential of node A rises or decreases from V1, wiring 12

[0163] ​​​​​​​​​​​​​​The potential of 1 does not increase. Therefore, the necessity of reducing the on-resistance of transistor 132 is low, so it is preferable that the channel width of transistor 132 is small. However, this is not limited thereto, and the channel width of transistor 103 can be smaller than the channel width of transistor 132. This is because transistor 132 has the function of raising the potential of node A during period T1. By increasing the channel width of transistor 132, the potential of node A can be raised faster.

[0164] Note that the channel width of transistor 102 can be smaller than the channel width of transistor 133. This is because if the channel width of transistor 102 is increased too much, the potential of node A will decrease too much during period T2, causing the semiconductor device to malfunction. Specifically, both transistor 102 and transistor 133 have the function of maintaining the potential of wiring 1 21 at V1. However, during period T2, until the potential of wiring 121 rises from the potential of wiring 123C (V1) by the threshold voltage (Vth102) of transistor 102 to the value (V1 - Vth102), transistor 102 is on. Therefore, in order to prevent the potential of node A from decreasing too much during period T2, it is preferable that the channel width of transistor 102 is small. On the other hand, the channel width of transistor 133 is preferably large in order to maintain the potential of wiring 121 at V1. However, this is not limited thereto, and the channel width of transistor 102 can be larger than the channel width of transistor 133. This is because during period T4, signal S2 is at the H level. This is because when it turns into a loop, the potential of wiring 121 is likely to increase. Therefore, by increasing the channel width of transistor 102, the increase in the potential of wiring 121 can be more easily suppressed.

[0165] Note that, similar to Embodiment 1, the L-level potential of the signal input to wiring 124A, wiring 124B, wiring 125, and / or wiring 126 can be lower than V1. In particular, since transistors 132 and 133 are on for a long time, the L-level potential of the signal input to wiring 124A and wiring 124B is preferably lower than V1.

[0166] Note that, similar to Embodiment 1, the H-level potential of the signal input to wiring 124A, wiring 124B, wiring 125, or wiring 126 can be lower than V2. In particular, since transistors 132 and 133 are prone to deterioration, the H-level potential of the signal input to wiring 124A and wiring 124B is preferably lower than V2.

[0167] Note that, similar to Embodiment 1, it is possible to input a signal to wiring 122C, wiring 122D, or wiring 122E. For example, to wiring 122C, it is possible to input a signal that becomes an L level during the period when transistor 134 is on (for example, period T3). Examples thereof include signal S2 or signal S4. To wiring 122D, it is possible to input a signal that becomes an L level during the period when transistor 135 is on (for example, period T3). Examples thereof include signal S2 or signal S4. To wiring 122E, it is possible During the period when transistor 133 is turned on (for example, period T1, period T3, period T5), a signal at the L level can be input. As an example, there are signal S2, signal S3, etc. There is.

[0168] In addition, in FIG. 13(C), as an example, the first terminal of transistor 103 is connected to wiring 124B and the first terminal of transistor 104 is connected to wiring 126, and the first terminal of transistor 1 33 is connected to wiring 123A, the first terminal of transistor 134 is connected to wiring 1 23A, and the first terminal of transistor 135 is connected to wiring 123A is shown. However, it is not limited to this, and the first terminal of transistor 103 can be connected to wiring 12 4A or wiring 125. Or, the first terminal of transistor 133, the first terminal of transistor 134, or the first terminal of transistor 135 can be connected to wiring 121, wiring 123B, wiring 123C, or wiring 126. There is. It is possible. There is.

[0169] In addition, similar to Embodiment 1, voltage (for example, voltage V1 or voltage V2) can be supplied to wiring 124A, wiring 124B, and / or wiring 126. By doing so, the semiconductor device can function as an inverter circuit or a buffer circuit. There is. Thus, the semiconductor device can function as an inverter circuit or a buffer circuit. There is.

[0170] In addition, as shown in FIG. 9(A), since the same signal (for example, signal S3) is input to wiring 124A and wiring 124B, it is possible to share wiring 124A and wiring 124B. Therefore, the gates of transistor 132 and transistor 133 are There is. It is connected to wiring 124. Wiring 124 corresponds to wiring 124A or wiring 124B, and it is possible to input something similar to these wirings.

[0171] Note that FIG. 9(C) shows a configuration when FIGS. 3(C) and 9(A) are combined. For example, the first terminal of transistor 101, the gate of transistor 102, and one electrode of capacitor element 106 are connected to wiring 123. The gate of transistor 132 and the gate of transistor 133 are connected to wiring 124. The first terminal of transistor 103, the first terminal of transistor 104, the first terminal of transistor 133, the first terminal of transistor 134, and the first terminal of transistor 135 are connected to wiring 122.

[0172] Note that as shown in FIG. 9(C), the gate of transistor 131 can be connected to wiring 127. As an example, voltage V2 is supplied to wiring 127, and it can function as a power supply line. However, it is not limited to this, and various things such as current, voltage, and signal can be input to wiring 127. For example, the signal input to wiring 127 preferably becomes high level during period T1 and low level during period T2, so it is possible to input signal S3 to wiring 127. In this case, wiring 127 can be connected to wiring 124A or wiring 124B and can function as a signal line.

[0173] Note that in FIG. 9(C), the gate of transistor 131 is shown as being connected to wiring 127, but it is not limited to this. For example, the first terminal of transistor 131 can be connected to wiring 127. ​​​​​​​​​​​​​​Subsequently, the gate of transistor 131 can be connected to wiring 125.

[0174] Similar to FIG. 9(C), in FIGS. 9(A) to (B) as well, the gate of transistor 131 can be connected to wiring 127.

[0175] Note that, as shown in FIG. 10(A), transistor 131 can be omitted. Even if transistor 131 is omitted, in period T1, transistor 132 turns on so that the potential of node A rises.

[0176] Similar to FIG. 10(A), in FIGS. 9(A) to (C) as well, transistor 131 can be omitted.

[0177] Note that, as shown in FIG. 10(B), transistor 132 can be omitted. Even if transistor 132 is omitted, in period T5, node A becomes floating, so the potential of node A is maintained at V1.

[0178] Similar to FIG. 10(B), in FIGS. 9(A) to (C) and FIG. 10(A) as well, transistor 132 can be omitted.

[0179] Note that, as shown in FIG. 10(C), transistor 134 and transistor 135 can be omitted. Or, either transistor 134 or transistor 135 can be omitted. Even if transistor 134 is omitted, in period T3, transistor 132 turns on so that the potential of node A decreases to V1. Similarly, even if transistor 135 is omitted, in period T3, transistor 133 turns on Therefore, the potential of the wiring 121 decreases to be V1.

[0180] Similar to FIG. 10(C), in FIGS. 9(A) to (C) and FIGS. 10(A) to (B), it is also possible to omit the transistor 134 and the transistor 135.

[0181] As shown in FIG. 11(A), it is possible to omit the transistor 133. When the transistor 133 is omitted, in the period T5, since the wiring 121 becomes a floating state, the potential of the wiring 121 is maintained at V1.

[0182] Similar to FIG. 11(A), in FIGS. 9(A) to (C) and FIGS. 10(A) to (C), it is also possible to omit the transistor 133.

[0183] As shown in FIG. 11(B), it is possible to omit the transistor 102. When the transistor 102 is omitted, in the period T4, since the wiring 121 becomes a floating state, the potential of the wiring 121 is maintained at V1.

[0184] Similar to FIG. 11(B), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), and FIG. 11 (A), it is also possible to omit the transistor 102.

[0185] As shown in FIG. 11(C), it is possible to omit the transistor 103, the transistor 104, and the capacitor element 106. Even when the transistor 103, the transistor 104, and the capacitor element 106 are omitted, in the period T4, since the wiring 121 becomes a floating state, the potential of the wiring 121 is maintained at V1.

[0186] Note that, similar to FIG. 11(C), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), and FIGS. 11 (A) to (B) as well, the transistor 103, the transistor 104, and the capacitor element 1 06 can be omitted.

[0187] Note that, as shown in FIG. 12(A), the transistor 133 can be replaced with a diode 133a. The diode 133a corresponds to the transistor 133. The diode 133a has a function of reducing the potential of the wiring 121 when an L-level signal is input to the wiring 124B, and a function of making the wiring 124B and the wiring 121 non-conductive when an H-level signal is input to the wiring 124B. One terminal of the diode 133a (hereinafter also referred to as the input terminal or the anode) is connected to the wiring 121, and the other terminal of the diode 133a (hereinafter also referred to as the output terminal or the cathode) is connected to the wiring 124B.

[0188] Note that, in FIG. 12(A), when the transistor 133 is replaced with the diode 133a, it is possible to input the signal S2 to the wiring 124B. Therefore, it is possible to connect the wiring 124B to the wirings 123A to 123C and share the wiring 124B and the wirings 123A to 123C.

[0189] Note that, similar to FIG. 12(A), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), and FIGS. 11 (A) to (C) as well, the transistor 133 can be replaced with the diode 133a, and one terminal of the diode 133a can be connected to the wiring 121, and the other terminal of the diode 133a can be connected to the wiring 124B.

[0190] ​​​​Note that, as shown in FIG. 12(B), the transistor 133 can be diode-connected. The diode-connected transistor 133 corresponds to the diode 133a. The first terminal of the transistor 133 is connected to the wiring 124B, the second terminal of the transistor 133 is connected to the wiring 121, and the gate of the transistor 133 is connected to the wiring 121. However, it is not limited thereto, and the gate of the transistor 133 can be connected to the wiring 124B.

[0191] Note that, similar to FIG. 12(B), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), FIGS. 11(A) to (C), and FIG. 12(A) as well, the first terminal of the transistor 133 can be connected to the wiring 124B, the second terminal of the transistor 133 can be connected to the wiring 121, and the gate of the transistor 133 can be connected to the wiring 121. However, it is not limited thereto, and the gate of the transistor

[0192] 133 can be connected to the wiring 124B. Note that, as shown in FIG. 12(C), the transistor 134 can be replaced with the diode 134a, and the transistor 135 can be replaced with the diode 135a. The diode 134a corresponds to the transistor 134, and the diode 135a corresponds to the transistor 135. When an L-level signal is input to the wiring 126, the diode 134a has a function of reducing the potential of the node A, and when an H-level signal is input to the wiring 126, it has a function of making the wiring 126 and the When an H-level signal is input to wiring 126, it has a function of making wiring 126 and wiring 121 non-conductive. One terminal of diode 134a (hereinafter also referred to as the input terminal or the anode) is connected to node A, and the other terminal of diode 134a (hereinafter also referred to as the output terminal or the cathode) is connected to wiring 126. One terminal of diode 135a (hereinafter also referred to as the input terminal or the anode) is connected to wiring 121, and the other terminal of diode 135a ( hereinafter also referred to as the output terminal or the cathode) is connected to wiring 126.

[0193] In addition, in FIG. 12(C), when transistors 134 and 135 are replaced with diodes, for example, an inverted signal of signal S5 can be input to wiring 126.

[0194] In addition, in FIG. 12(C), it is possible to replace only one of transistors 134 and 135 with a diode.

[0195] Similar to FIG. 12(C), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), FIGS. 11(A ) to (C), and FIGS. 12(A) to (B), it is also possible to replace transistor 134 with diode 1 34a, with one terminal of diode 134a connected to node A and the other terminal of diode 134a connected to wiring 126. Or, it is possible to replace transistor 135 with diode 135a, with one terminal of diode 135a connected to wiring 12 1 and the other terminal of diode 135a connected to wiring 126.

[0196] In addition, as shown in FIG. 13(A), transistors 134 and 135 are di The diode-connected transistor 134 and the diode The diodes 134a and 135a are connected to the diodes 134a and 135a. A first terminal of the transistor 134 is connected to the wiring 126. The second terminal of transistor 34 is connected to node A, and the gate of transistor 134 is connected to node A. The first terminal of the transistor 135 is connected to the wiring 126. A second terminal of the transistor 135 is connected to the wiring 121, and a gate of the transistor 135 is , and is connected to the wiring 121. However, this is not limited thereto. , and the gate of the transistor 135 can be connected to the wiring 126. It is possible to connect to 6.

[0197] As in FIG. 13(A), FIGS. 9(A) to (C), 10(A) to (C), and 11(A) 12(A) to (C), the first terminal of the transistor 134 is A second terminal of the transistor 134 is connected to the wiring 126, and a second terminal of the transistor 134 is connected to the node A. The gate of the transistor 134 can be connected to the node A. A first terminal of the transistor 135 is connected to the wiring 126, and a second terminal of the transistor 135 is connected to the wiring 1 21, and the gate of the transistor 135 can be connected to the wiring 121. However, the present invention is not limited to this. The gate of the transistor 134 is connected to the wiring 126. The gate of the transistor 135 may be connected to the wiring 126. It is Noh.

[0198] As shown in FIG. 13B, a transistor 137 and a transistor 138 are newly added. can be added. Transistors 137 and 138 shall be of the N-channel type. However, it is not limited thereto, and transistors 137 and transistor 138 can be of the P-channel type. The first terminal of transistor 137 is connected to wiring 122F, and the second terminal of transistor 137 is connected to wiring 121 and the gate of transistor 137 is connected to wiring 128. The first terminal of transistor 138 is connected to wiring 122G, the second terminal of transistor 138 is connected to node A and the gate of transistor 138 is connected to wiring 128. As an example, a signal S6 is input to wiring 128. Therefore, wiring 128 can function as a signal line . Signal S6 is often a digital signal having an H level and an L level and can function as, for example, a full-stage reset signal. As an example, a voltage V1 is supplied to wiring 122F and wiring 122G. Therefore, wiring 122F and wiring 122G can function as power supply lines. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. Note that in FIG. 13(B), signal S6 can become an H level during the period before the semiconductor device starts operating. Or, the semiconductor device shown in FIG. 13(B) shifts 22F, and wiring 122G can function as a power supply line. And it is possible to share wiring 122A to 122G. In this case, the first terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. terminal of transistor 137 and the first terminal of transistor 138 can be connected to wiring 122 as shown in FIG. 11(B). However, various things such as current, voltage, and signal can be input to wiring 128, wiring 122F, and wiring 122G. Note that in FIG. 13(B), signal S6 can become an H level during the period before the semiconductor device starts operating. Or, the semiconductor device shown in FIG. 13(B) shifts It is possible to input various things such as current, voltage, and signal to wiring 128, wiring 122F, and wiring 122G.

[0199] Note that in FIG. 13(B), signal S6 can be at the H level during the period before the semiconductor device starts operating. Or, the semiconductor device shown in FIG. 13(B) shifts to the H level. Or, the semiconductor device shown in FIG. 13(B) shifts When used in a register, signal S6 can become H level during the period before the shift register starts scanning, or during the period after the shift register finishes scanning. Therefore, as signal S6, it is possible to use the start pulse of the shift register, or the output signal of the last stage of the shift register, etc. However, an example of this embodiment is not limited to this. In addition, in FIG. 13(B), it is possible to newly add only one of transistor 137 and transistor 138. Note that, similar to FIG. 13(B), in FIGS. 9(A) to (C), FIGS. 10(A) to (C), FIGS. 11(A

[0200] ), FIGS. 12(A) to (C), and FIG. 13(A), it is also possible to newly add transistor 137, connect the first terminal of transistor 137 to wiring 122F, connect the second terminal of transistor 137 to wiring 121, and connect the gate of transistor 137 to wiring 1

[0201] 28. Or, it is possible to newly add transistor 138, connect the first terminal of transistor 138 to wiring 122G, connect the second terminal of transistor 138 to node A, and connect the gate of transistor 138 to wiring 128. ) to (C), FIGS. 12(A) to (C), and FIG. 13(A), it is also possible to newly add transistor 137, connect the first terminal of transistor 137 to wiring 122F, connect the second terminal of transistor 137 to wiring 121, and connect the gate of transistor 137 to wiring 1 28. Or, it is possible to newly add transistor 138, connect the first terminal of transistor 138 to wiring 122G, connect the second terminal of transistor 138 to node A, and connect the gate of transistor 138 to wiring 128. 28. Or, it is possible to newly add transistor 138, connect the first terminal of transistor 138 to wiring 122G, connect the second terminal of transistor 138 to node A, and connect the gate of transistor 138 to wiring 128. connect the first terminal of transistor 138 to wiring 122G, connect the second terminal of transistor 138 to node A, and connect the gate of transistor 138 to wiring 128. is possible. In addition, in FIG. 13(B), it is possible to newly add only one of transistor 137 and transistor 138.

[0202] (Embodiment 3) In this embodiment, an example of a shift register will be described. The shift register of this embodiment can have the semiconductor devices of Embodiment 1 and Embodiment 2. Note that it is possible to indicate the shift register as a semiconductor device or a gate driver. Note that the actual The content described in Embodiment 1 and Embodiment 2 can be applied to the shift register of this embodiment. It is applicable.

[0203] First, an example of the shift register will be described with reference to FIG. 14(A). The shift register 220 is connected to wirings 201_1 to 201_N (N is a natural number), wiring 202, wiring 203, wiring 204, wiring 205, and wiring 206.

[0204] Wiring 202 corresponds to wiring 123 (wiring 123A to 123C) or wiring 124 (wiring 124A to 124B) described in Embodiment 1 and Embodiment 2, and can function as a signal line or a clock signal line. And it is assumed that a signal GS2 is input to wiring 202 from circuit 221. The signal GS2 corresponds to signal S2 or signal S3 described in Embodiment 1 and Embodiment 2, and can function as a clock signal.

[0205] Wiring 203 corresponds to wiring 123 (wiring 123A to 123C) or wiring 124 (wiring 124A to 124B) described in Embodiment 1 and Embodiment 2, and can function as a signal line or a clock signal line. And it is assumed that a signal GS3 is input to wiring 203 from circuit 221. The signal GS3 corresponds to signal S2 or signal S3 described in Embodiment 1 and Embodiment 2, and can function as an inverted clock signal.

[0206] Wiring 204 corresponds to wiring 122 (wiring 122A to 122G) described in Embodiment 1 and Embodiment 2, and can function as a power supply line. And wiring 20 ​​​​​​​​​ Let voltage V1 be supplied to 4 from circuit 221.

[0207] Wiring 205 corresponds to wiring 125 described in Embodiment 1 and Embodiment 2, and can function as a signal line. A signal GS4 is input to wiring 205 from circuit 221. Signal GS4 corresponds to signal S4 described in Embodiment 1 and Embodiment 2, and can function as a start signal (hereinafter, start pulse) or a vertical synchronization signal.

[0208] Wiring 206 corresponds to wiring 126 described in Embodiment 1 and Embodiment 2, and can function as a signal line. A signal GS5 is input to wiring 206 from circuit 221. Signal GS5 corresponds to signal S5 described in Embodiment 1 and Embodiment 2, and can function as a reset signal.

[0209] However, it is not limited to this, and various things such as signals, voltages, or currents can be input to wirings 202 to 206, and each wiring can be in a floating state.

[0210] As shown in FIG. 6(C), as signal S2 or signal S3, an unbalanced clock signal can be used. In this case, as an example, signal S3 can have a phase shifted by 180° with respect to signal S2. By doing so, when the semiconductor device of the present embodiment is used as a shift register, it is possible to prevent the selection signal of a certain stage from overlapping with the selection signals of the previous and subsequent stages.

[0211] The wirings 201_1 to 201_N correspond to the wiring 121 described in Embodiment 1 and Embodiment 2, and can function as gate lines or scanning lines. And from the wirings 201_1 to 201_N, signals GS1_1 to GS1_N are output respectively. The signals GS1_1 to GS1_N correspond to the signal S1 described in Embodiment 1 and Embodiment 2, and can function as output signals, selection signals, scanning signals, or gate signals.

[0212] As shown in FIG. 14(B), the signals GS1_1 to GS1_N become H level in order from the signal GS1_1. For example, assume that the signal GS1_i - 1 (i is any one of 1 to N) becomes H level. Then, when the signals GS2 and GS3 are inverted, the signal GS1_i - 1 becomes L level and the signal GS1_i becomes H level. Then, when the signals GS2 and GS3 are inverted again, the signal GS1_i becomes L level and the signal GS1_i + 1 becomes H level. Thus, the signals GS1_1 to GS1_N become H level in order. In other words, the wirings 201_1 to 201_N are selected in order.

[0213] The circuit 221 supplies a signal, voltage, etc. to the shift register 220 and has a function of controlling the shift register 220, and can function as a control circuit, a controller, or the like. In the present embodiment, the circuit 211 supplies the signal GS2, the signal GS3, the voltage V1, the signal GS4, and the signal GS5 to the wiring 202, the wiring 203, the wiring 204, the wiring 205, and the wiring 206 respectively. However, it is not limited to this, and the shift register 220 can also supply signals, currents, voltages, etc. to various other circuits and control these circuits. ​ It is capable. For example, circuit 221 can supply signals or voltages to circuits such as signal line driving circuits, scanning line driving circuits, and / or pixels, and control these circuits.

[0214] Circuit 221 has, as an example, circuit 222, circuit 223, etc. Circuit 222 has a function of generating power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, and a reference voltage, and can function as a power supply circuit or a regulator. Circuit 223 has a function of generating various signals such as a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a video signal, and can function as a timing generator. However, it is not limited thereto. Circuit 221 can also have various circuits or various elements in addition to circuit 222 and circuit 223. For example, circuit 221 can have an oscillator, a level shift circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, an operational amplifier, a shift register, a look-up table, a coil, a transistor, a capacitive element, a resistive element, and / or a frequency divider, etc.

[0215] Next, an example of the shift register 220 will be described with reference to FIG. 15. The shift register in FIG. 15 has a plurality of flip-flops 200_1 to 200_N (N is a natural number). The flip-flops 200_1 to 200_N respectively correspond to the semiconductor devices described in Embodiment 1 and Embodiment 2. In FIG. 15, as an example, the configuration when the semiconductor device in FIG. 9(B) is used as a flip-flop is shown.

[0216] The connection relationship of the shift register will be described. First, as an example, the flip-flop 20 the connection relationship of 0_i will be described. In the flip-flop 200_i, the wiring 121 , the wiring 122, the wiring 123, the wiring 124, the wiring 126, and the wiring 127 are respectively the wiring 2 01_i, the wiring 204, the wiring 202, the wiring 203, the wiring 201_i-1, the wiring 201_i +1. However, in many cases, the connection destinations of the wiring 123 and the wiring 124 are reversed between the odd-stage flip-flop and the even-stage flip-flop. For example, in the odd-stage flip-flop, assume that the wiring 123 is connected to the wiring 202 and the wiring 124 is connected to the wiring 2 03. In this case, in the even-stage flip-flop, the wiring 123 is connected to the wiring 2 03 and the wiring 124 is connected to the wiring 202. On the other hand, in the odd-stage flip-flop , assume that the wiring 123 is connected to the wiring 203 and the wiring 124 is connected to the wiring 202 . In this case, in the even-stage flip-flop, the wiring 123 is connected to the wiring 202 and the wiring 124 is connected to the wiring 203. In addition, in the flip-flop 200_1, the wiring 125 is connected to the wiring 205.

[0217] In addition, in the flip-flop 200_N, the wiring 126 is connected to the wiring 206.

[0218] In addition, in the flip-flop 200_N, the wiring 126 is connected to the wiring 206.

[0219] Next, an example of the operation of the shift register in FIG. 15 will be described with reference to the timing chart of FIG. 14(B). Note that the description of the parts common to the operations of the semiconductor devices of Embodiment 1 and Embodiment 2 will be omitted. will be omitted.

[0220] The operation of flip-flop 200_i will be described. First, when signal GS1_i-1 becomes H level it becomes a bell. Then, flip-flop 200_i starts operating in period T1, and signal G S1_i becomes L level. After that, signals GS2 and GS3 are inverted. Then, flip-flop 200_i starts operating in period T2, and signal GS1_i becomes H level Signal GS1_i is input as a reset signal to flip-flop 200_i-1 and as a start signal to flip-flop 200_i+1. Therefore , flip-flop 200_i-1 starts operating in period T3, and flip-flop 200_i+1 starts operating in period T1. After that, signals GS2 and signal GS3 are inverted again. Then, flip-flop 200_i+1 starts operating in period T2, and signal GS1_i+1 becomes H level. Signal GS1_i+1 is input as a reset signal to flip-flop 200_i. Therefore, flip-flop 200_i starts operating in period T3, and signal GS1_i becomes L level. After that, until signal GS1_i-1 becomes H level again, flip-flop 200_i repeats the operation in period T4 and the operation in period T5 every time signals GS2 and signal GS3 are inverted. Signal GS1_i+1 is input as a reset signal to flip-flop 200_i. Therefore, flip-flop 200_i starts operating in period T3, and signal GS1_i becomes L level. After that, until signal GS1_i-1 becomes H level again, flip-flop 200_i repeats the operation in period T4 and the operation in period T5 every time signals GS2 and signal GS3 are inverted. 0_i starts operating in period T3, so signal GS1_i becomes L level. After that, until signal GS1_i-1 becomes H level again, flip-flop 200_i repeats the operation in period T4 and the operation in period T5 every time signals GS2 and signal GS3 are inverted. until signal GS1_i-1 becomes H level again, flip-flop 200_i repeats the operation in period T4 and the operation in period T5 every time signals GS2 and signal GS3 are inverted. operation.

[0221] Note that in flip-flop 200_1, instead of the output signal of the previous-stage flip-flop , signal GS4 is input from an external circuit via wiring 205. Therefore, when signal GS4 becomes H level, flip-flop 200_1 starts operating in period T1.

[0222] In the flip-flop 200_N, instead of the output signal of the flip-flop in the next stage the signal GS5 is input from the external circuit via the wiring 206. Therefore, when the signal GS5 becomes H level, the flip-flop 200_N starts operating in the period T3.

[0223] By using the semiconductor devices of Embodiment 1 and Embodiment 2 in the shift register of the present embodiment the same advantages as those of the semiconductor device can be obtained.

[0224] Note that the wiring 206 can be omitted. In this case, as an example, as the flip-flop 200_N, a configuration in which the transistors 134 and 135 shown in FIG. 10(C) are omitted can be used.

[0225] Note that in the flip-flops 200_1 to 200_N, when a signal is used instead of the voltage V1 the wiring 204 can be omitted.

[0226] Note that the signal GS4 can be input to the wiring 206 in the same manner as the wiring 205. In this case, by connecting the wiring 206 to the wiring 205, it is possible to share the wiring 205 and the wiring 206. Or, the signal GS2 can be input to the wiring 206 in the same manner as the wiring 202. In this case, by connecting the wiring 206 to the wiring 202 it is possible to share the wiring 206 and the wiring 202. Or, the signal GS3 can be input to the wiring 206 in the same manner as the wiring 203. In this case, by connecting the wiring 206 to the wiring 203, it is possible to share the wiring 206 and the wiring 203. ​​Or, the voltage V1 can be input to the wiring 206 in the same manner as the wiring 204. In this case, by connecting the wiring 206 to the wiring 204, it is possible to share the wiring 206 and the wiring 2 04.

[0227] Note that when a configuration that requires the signal S6 as shown in FIG. 13(B) is used for the flip-flops 200_1 to 200_N, it is possible to add the wiring 207 as shown in FIG. 16. The signal GS6 is input to the wiring 207. The signal GS6 corresponds to the signal S6 described in the second embodiment and can function as a full-stage reset signal. Thus, the wiring 207 corresponds to the wiring 128 in FIG. 13(B) and can function as a signal line. However, it is not limited to this, and by sharing the wiring 207 with another wiring, the number of wirings, or the number of signals or power supply voltages can be reduced. For example, the signal GS4 can be input to the wiring 207 in the same manner as the wiring 205. Therefore, by connecting the wiring 207 to the wiring 205, it is possible to share the wiring 207 and the wiring 205. Or, the signal GS5 can be input to the wiring 207 in the same manner as the wiring 206. Therefore, by connecting the wiring 207 to the wiring 206, it is possible to share the wiring 207 and the wiring 206. Or, the output signal S1_N of the flip-flop 200_N can be input to the wiring 207. Therefore, by connecting the wiring 207 to the wiring 201_N, it is possible to share the wiring 207 and the wiring 201_N.

[0228] However, it is not limited to this, and by sharing the wiring 207 with another wiring, the number of wirings, or the number of signals or power supply voltages can be reduced. For example, the signal GS4 can be input to the wiring 207 in the same manner as the wiring 205. Therefore, by connecting the wiring 207 to the wiring 205, it is possible to share the wiring 207 and the wiring 205. Or, the signal GS5 can be input to the wiring 207 in the same manner as the wiring 206. Therefore, by connecting the wiring 207 to the wiring 206, it is possible to share the wiring 207 and the wiring 206. Or, the output signal S1_N of the flip-flop 200_N can be input to the wiring 207. Therefore, by connecting the wiring 207 to the wiring 201_N, it is possible to share the wiring 207 and the wiring 201_N. However, it is not limited to this, and by sharing the wiring 207 with another wiring, the number of wirings, or the number of signals or power supply voltages can be reduced. For example, the signal GS4 can be input to the wiring 207 in the same manner as the wiring 205. Therefore, by connecting the wiring 207 to the wiring 205, it is possible to share the wiring 207 and the wiring 205. Or, the signal GS5 can be input to the wiring 207 in the same manner as the wiring 206. Therefore, by connecting the wiring 207 to the wiring 206, it is possible to share the wiring 207 and the wiring 206. Or, the output signal S1_N of the flip-flop 200_N can be input to the wiring 207. Therefore, by connecting the wiring 207 to the wiring 201_N, it is possible to share the wiring 207 and the wiring 201_N. Or, the signal GS5 can be input to the wiring 207 in the same manner as the wiring 206. Therefore, by connecting the wiring 207 to the wiring 206, it is possible to share the wiring 207 and the wiring 206. Or, the output signal S1_N of the flip-flop 200_N, which is the output signal of the flip-flop 200_N, can be input to the wiring 207. Therefore, by connecting the wiring 207 to the wiring 201_N, it is possible to share the wiring 207 and the wiring 201_N.

[0229] ​​​​In addition, when the flip-flops 200_1 to 200_N are configured to require the voltage V2 as shown in Fig. 9(C), it is possible to newly add wiring. The voltage V2 is supplied to the wiring. The wiring corresponds to the wiring 127 in Fig. 9(C) and can function as a power supply line. When a configuration that requires the voltage V2 is used, it is possible to newly add wiring. The voltage V2 is supplied to the wiring. The wiring corresponds to the wiring 127 in Fig. 9(C) and can function as a power supply line. When a configuration that requires the voltage V2 is used, it is possible to newly add wiring. The voltage V2 is supplied to the wiring. The wiring corresponds to the wiring 127 in Fig. 9(C) and can function as a power supply line. When a configuration that requires the voltage V2 is used, it is possible to newly add wiring. The voltage V2 is supplied to the wiring. The wiring corresponds to the wiring 127 in Fig. 9(C) and can function as a power supply line.

[0230] In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the deterioration of the characteristics of the transistor, a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop. When this is the case, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line. In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the deterioration of the characteristics of the transistor, a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop. When this is the case, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line. In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the deterioration of the characteristics of the transistor, a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop. When this is the case, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line. In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the deterioration of the characteristics of the transistor, a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop. When this is the case, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line. In addition, as described in Embodiment 1 and Embodiment 2, in order to suppress the deterioration of the characteristics of the transistor, a signal with an L-level potential lower than V1, a signal with an H-level potential lower than V2, or a signal with an amplitude voltage smaller than V2-V1 is input to the flip-flop. When this is the case, it is possible to newly add wiring. A signal is input to the wiring, and the wiring can function as a signal line.

[0231] As shown in Fig. 17(A), the shift register can include circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 can have the function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 can have the function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in Fig. 17(A), the shift register can include circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 can have the function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 can have the function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in Fig. 17(A), the shift register can include circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 can have the function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 can have the function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in Fig. 17(A), the shift register can include circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 can have the function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 can have the function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in Fig. 17(A), the shift register can include circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 can have the function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 can have the function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in Fig. 17(A), the shift register can include circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 can have the function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 can have the function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in Fig. 17(A), the shift register can include circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 can have the function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 can have the function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in Fig. 17(A), the shift register can include circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 can have the function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 can have the function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. As shown in Fig. 17(A), the shift register can include circuits 212, 213, 214, 215, and / or 216. Circuits 212 to 216 can have the function of increasing (or decreasing) the amplitude voltage or the input voltage of the input signal and outputting it, and can function as a level shift circuit. Or, circuits 212 to 216 can have the function of inverting and outputting the input signal, and can function as an inverter circuit or a buffer circuit. Wiring 202 is connected to the flip-flop via circuit 212. Wiring 203 is connected to the flip-flop via circuit 213. Wiring 204 is connected to the flip-flop via circuit 214. Wiring 205 is connected to the flip-flop via circuit 215. Wiring 206 is connected to the flip-flop via circuit 216. This allows a small amplitude signal to be input to the shift register. Therefore, the driving voltage of the external circuit can be reduced, thereby reducing the cost of the external circuit. This makes it possible to reduce power consumption, etc.

[0232] In FIG. 17A, the shift register is any one of the circuits 212 to 216. , or two or more.

[0233] As shown in FIG. 17B, the shift register has circuits 211_1 to 211_N. The circuits 211_1 to 211_N have a function of increasing the current capability of the input signal. The function of increasing the amplitude voltage of the input signal or the function of inverting the input signal is provided. It can function as a fader circuit, a level shift circuit, or an inverter circuit. The circuits 211_1 to 211_N are respectively connected to the flip-flops 200_1 to 200_N and the wiring For example, the circuit 211_i is a flip-flop. The flip-flop 200 is connected between the flip-flop 200_i and the wiring 201_i. The signal GS1_i, which is the output signal of the ._i, is output from the wiring 201_i via the circuit 211_i. In this way, the drive voltage of each flip-flop can be reduced, resulting in reduced power consumption. It is possible to reduce the number of flip-flops and suppress the deterioration of the transistor characteristics. By reducing the channel width of the transistor (particularly the transistor 101) included in the chip, This allows the layout area to be reduced.

[0234] In the example of FIG. 17B, the flip-flop 200_i-1 receives a reset signal and Thus, the signal GS1_i is input via the circuit 211_i. Therefore, in the flip-flop 200_i-1, during the period T3, the period during which the transistor 101 is turned on becomes longer so that the fall time of the signal GS_i-1, which is the output signal of the flip-flop 200_i-1, can be shortened. On the other hand, to the flip-flop 200_i+1, as a start signal, the signal GS1_i is input without passing through the circuit 211_i. Therefore, in the flip-flop 200_i+1, during the period T1, the potential of the node A can be raised quickly so that the drive frequency can be improved. However, it is not limited to this. To the flip-flop 200_i-1, as a reset signal, the signal GS1_i can be input without passing through the circuit 211 _i. Or, to the flip-flop 200_i+1, as a start signal, the signal GS1_i can be input via the circuit 211_i. In the shift register of FIG. 14(A), the signals S1_1 to S1_N were shifted by 1 / 2 cycles of the signal S2 or 1 / 2 cycle of the signal S3 at a time. However, it is not limited to this. The signals S1_1 to S1_N can be shifted by 1 / 2×M (M is a natural number) cycles of the signal S2 or 1 / 2×M cycles of the signal S3 at a time. That is, in the signals S1_1 to S1_N, the period during which the signal of a certain row becomes the H level and the period during which the signal of another row becomes the H level can overlap. To achieve this, it is possible to input a 2×M-phase clock signal to the shift register.

[0235] Regarding a specific example, it will be described with reference to the shift register of FIG. 24. In FIG. 24, there is a flip-flop

[0236] For a specific example, it will be described with reference to the shift register of FIG. 24. In FIG. 24, there is a flip-flop ​​​​​​​Only the rops 200_i+1 to 200_i+2M+1 are shown. Flip-flop 200_i The wirings 123 of flip-flops 200_i+1 to 200_i+M are each connected to the wirings 203_1 to 203_M, and the wirings 124 of flip-flops 200_i+1 to 200_i+M are each connected to the wirings 204_ 1 to 204_M. The wirings 123 of flip-flops 200_i+M+1 to 200_i+2M are each connected to the wirings 204_1 to 204_M, and the wirings 123 of flip-flops 20 0_i+M+1 to 200_i+2M are each connected to the wirings 203_1 to 203_M and the wiring 125 of flip-flop 200_i+1 is connected to the wiring 121 of flip-flop 200_i. The wiring 12 6 of flip-flop 200_i+1 is connected to the wiring 121 of flip-flop 200_i+M+1. Note that the wirings 20 3_1 to 203_M correspond to the wiring 203. The wirings 204_1 to 204_M correspond to the wiring 2 04. As shown in FIG. 25(A), signals GS2_1 to GS2_M are respectively input to the wirings 203_1 to 203_M. Signals GS3_1 to GS3_M are respectively input to the wirings 204_1 to 204_M. The signals GS2_1 to GS2_M are M clock signals whose phases are shifted by 1 / 2 M periods each and correspond to the signal GS2. The signals GS3_1 to GS3_M are inverted signals of the signals GS2_1 to GS2_M and correspond to the signal GS3. In this way, it becomes possible to shift by 1 / 2×M (M is a natural number) periods of the signal S2 or 1 / 2 ×M periods of the signal S3 each. Note that in FIG. 24, the wiring 125 of flip-flop 200_i+1 may be connected to any one of the wirings 121 of flip-flops 200_i-M+1 to 200_i-1.

[0237] Note that in FIG. 24, the wiring 125 of flip-flop 200_i+1 may be connected to any one of the wirings 121 of flip-flops 200_i-M+1 to 200_i-1. ​​​ This is possible. By doing so, in flip-flop 200_i+1, the timing at which transistor 131 turns on can be advanced, so the timing at which the potential of node A rises can be advanced. Therefore, the drive frequency can be increased. Or, since the channel width of transistor 131 or transistor 132 can be reduced, the layout area can be reduced. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+M+2 to 200_i+2M. By doing so, in flip-flop 200_i+1, the timing at which transistor 101 turns off can be delayed, so the fall time of signal S1_i+1 can be shortened. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+2 to 200_i+M. By doing so, the pulse widths of signals S1_1 to S1_N can be made smaller than half the period of the clock signal. Thus, the drive frequency can be increased while reducing power consumption. In FIG. 24, it is preferable that M≦4. More preferably, it is preferable that M≦2. This is because when the shift register of FIG. 23 is used in the scanning line drive circuit of a display device, if M is too large, a plurality of types of video signals will be written to the pixels.

[0238] In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+M+2 to 200_i+2M. By doing so, in flip-flop 200_i+1, the timing at which transistor 101 turns off can be delayed, so the fall time of signal S1_i+1 can be shortened. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+M+2 to 200_i+2M. By doing so, in flip-flop 200_i+1, the timing at which transistor 101 turns off can be delayed, so the fall time of signal S1_i+1 can be shortened. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+M+2 to 200_i+2M. By doing so, in flip-flop 200_i+1, the timing at which transistor 101 turns off can be delayed, so the fall time of signal S1_i+1 can be shortened. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+M+2 to 200_i+2M. By doing so, in flip-flop 200_i+1, the timing at which transistor 101 turns off can be delayed, so the fall time of signal S1_i+1 can be shortened. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+M+2 to 200_i+2M. By doing so, in flip-flop 200_i+1, the timing at which transistor 101 turns off can be delayed, so the fall time of signal S1_i+1 can be shortened.

[0239] In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+2 to 200_i+M. By doing so, the pulse widths of signals S1_1 to S1_N can be made smaller than half the period of the clock signal. Thus, the drive frequency can be increased while reducing power consumption. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+2 to 200_i+M. By doing so, the pulse widths of signals S1_1 to S1_N can be made smaller than half the period of the clock signal. Thus, the drive frequency can be increased while reducing power consumption. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+2 to 200_i+M. By doing so, the pulse widths of signals S1_1 to S1_N can be made smaller than half the period of the clock signal. Thus, the drive frequency can be increased while reducing power consumption. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+2 to 200_i+M. By doing so, the pulse widths of signals S1_1 to S1_N can be made smaller than half the period of the clock signal. Thus, the drive frequency can be increased while reducing power consumption. In FIG. 24, the wiring 126 of flip-flop 200_i+1 can be connected to any one of the wirings 121 of flip-flops 200_i+2 to 200_i+M. By doing so, the pulse widths of signals S1_1 to S1_N can be made smaller than half the period of the clock signal. Thus, the drive frequency can be increased while reducing power consumption.

[0240] In FIG. 24, it is preferable that M≦4. More preferably, it is preferable that M≦2. This is because when the shift register of FIG. 23 is used in the scanning line drive circuit of a display device, if M is too large, a plurality of types of video signals will be written to the pixels. In FIG. 24, it is preferable that M≦4. More preferably, it is preferable that M≦2. This is because when the shift register of FIG. 23 is used in the scanning line drive circuit of a display device, if M is too large, a plurality of types of video signals will be written to the pixels. In FIG. 24, it is preferable that M≦4. More preferably, it is preferable that M≦2. This is because when the shift register of FIG. 23 is used in the scanning line drive circuit of a display device, if M is too large, a plurality of types of video signals will be written to the pixels. When the period during which an illegal video signal is input to the pixel becomes long and the display quality deteriorates This is because there is. As an example, FIG. 25(B) shows a timing chart in the case where M = 2 as an example.

[0241] (Embodiment 4) In this embodiment, an example of a semiconductor device and a shift register having the semiconductor device will be described. Note that the contents described in Embodiments 1 to 3 can be applied to the semiconductor device and the shift register of this embodiment

[0242] First, the semiconductor device of this embodiment will be described with reference to FIG. 19(A). Note that the parts common to FIG. 1(A) are denoted by the same reference numerals, and the description thereof will be omitted

[0243] The semiconductor device in FIG. 19(A) includes a circuit 100, a transistor 101, a transistor 102, a transistor 103, a transistor 104, a capacitor element 105, a capacitor element 106, and a transistor 301. Transistor 301 corresponds to transistor 101 and has the same function as transistor 101. Transistor 301 is an N-channel type However, transistor 301 can be a P-channel type

[0244] The first terminal of transistor 301 is connected to wiring 123D, the second terminal of transistor 301 is connected to wiring 311, and the gate of transistor 301 is connected to node A

[0245] Wiring 123D corresponds to wirings 123A to 123C, and it is assumed that signal S2 is input thereto ​​​​​​Therefore, similarly to FIG. 3(D), it is possible to share wiring 123D with wirings 123A to 123C. In this case, the first terminal of transistor 301 is connected to wiring 123. Assume that signal S7 is output from wiring 311. Signal S7 corresponds to signal S1.

[0246] Next, the operation of the semiconductor device in FIG. 19(A) will be described with reference to the timing chart in FIG. 19(B). Note that the description of the parts common to the operation in FIG. 1(A) will be omitted.

[0247] First, in period T1, the potential of node A starts to rise. Then, similarly to transistor 101, when the potential of node A reaches the sum (V1 + Vth301) of the potential of wiring 123D (V1) and the threshold voltage (Vth301) of transistor 301, transistor 301 turns on. Then, wiring 123D and wiring 311 become conductive. Therefore, since the L-level signal S2 is supplied from wiring 123D to wiring 311, the potential of wiring 311 decreases to V1.

[0248] Next, in period T2, since the potential of node A becomes V1 + Vth101 + α, transistor 301 remains on. Then, wiring 123D and wiring 311 remain conductive. Therefore, since the H-level signal S2 is supplied from wiring 123D to wiring 311, the potential of wiring 311 rises to V2.

[0249] Next, in period T3, the potential of node A starts to decrease to V1. Similarly to transistor 101, when the potential of node A reaches the potential of wiring 123D (V1) and the threshold voltage of transistor 301 ​​​​​​​​​​Until the sum (V1 + Vth301) with the threshold voltage (Vth301) is reached, the transistor 301 is on. Therefore, since the L-level signal S1 is shared from the wiring 123D to the wiring 311, the potential of the wiring 311 decreases to become V1. After that, when the potential of the node A decreases to V1 + Vth301, the transistor 301 turns off.

[0250] During the period T4 and the period T5, since the potential of the node A is maintained at V1, the transistor 3 01 remains off. Therefore, the wiring 123D and the wiring 311 remain in a non-conductive state.

[0251] In the semiconductor device of FIG. 19(A), the wiring 121 and the wiring 311 can output signals at the same timing. Therefore, one of the signal S1 output from the wiring 121 and the signal S7 output from the wiring 311 can be used to drive a load such as a gate line or a pixel, and the other signal can be used as a signal for driving another circuit such as a transfer signal. By doing so, another circuit can be driven without being affected by signal smear, delay, etc. caused by driving a load or the like.

[0252] Note that a capacitive element can be connected between the gate of the transistor 301 and the second terminal. The capacitive element corresponds to the capacitive element 105.

[0253] Note that, as shown in FIG. 20(A), it is possible to add the transistor 301 to the semiconductor device of FIG. 6(A).

[0254] Note that, as shown in FIG. 20(B), the transistor 302, the transistor 303, and / or ​​​It is possible to add transistor 304. Transistors 302, 303, and 304 each correspond to transistor 134, transistor 102, and transistor 133 and have similar functions. The first terminal of transistor 302 is connected to wiring 122H, the second terminal of transistor 302 is connected to wiring 331, and the gate of transistor 302 is connected to wiring 126. The first terminal of transistor 303 is connected to wiring 331, the second terminal of transistor 303 is connected to node A, and the gate of transistor 303 is connected to wiring 123E. The first terminal of transistor 304 is connected to wiring 122I, the second terminal of transistor 304 is connected to wiring 331, and the gate of transistor 304 is connected to wiring 124C. However, it is not limited to this, and it is possible to add only one or two of transistors 302, 303, and 304.

[0255] In addition, in FIG. 20(B), since the same signal (signal S2) as that of wirings 123A to 123C is input to wirings 123D and 123E, it is possible to share wirings 123D and 123E with wirings 123A to 123C. In this case, the first terminal of transistor 301 and the gate of transistor 303 can be connected to wiring 123.

[0256] In addition, in FIG. 20(B), since the same voltage (voltage V1) as that of wirings 122A to 122E is supplied to wirings 122H and 122I, it is possible to share wirings 122H and 122I with wirings 122A to 122E. In this case, transistor 3 ​ The first terminal of 02 and the first terminal of transistor 304 are connected to wiring 122. This is possible.

[0257] In addition, in FIG. 20(B), transistor 302 can be replaced with a diode or a transistor connected in diode form, similar to transistor 135. Also, transistor 304 can be replaced with a diode or a transistor connected in diode form, similar to transistor 133. This is possible.

[0258] Next, an example of a shift register having the semiconductor device described above will be described with reference to FIG. 21. Note that the content described in Embodiment 3 will be omitted from the description. Alternatively, the parts common to FIGS. 14 and 21 are denoted by the same reference numerals and the description thereof will be omitted.

[0259] The shift register includes a plurality of flip-flops 320_1 to 320_N. Flip-flops 320_1 to 320_N correspond to flip-flops 200_1 to 200_N in FIG. 14. Alternatively, flip-flops 320_1 to 320_N correspond to the semiconductor devices in FIGS. 19(A), 20(A), or 20(B). FIG. 21 shows an example in the case of using the semiconductor device in FIG. 20(A) as an example.

[0260] In flip-flop 320_i, wiring 311 is connected to wiring 321_i. Then, wiring 126 is connected to wiring 321_i - 1.

[0261] Signals GS7_1 to GS7_N are respectively output from wirings 321_1 to 321_N. Assume that. The signals GS7_1 to GS7_N correspond to the signal S7 and can function as transfer signals, output signals , selection signals, scanning signals, or gate signals.

[0262] Next, the operation of the shift register in FIG. 21 will be described with reference to the timing chart of FIG. 14(B). Refer to and explain.

[0263] The operation of the flip-flop 320_i will be described. First, the signal GS7_i-1 becomes the H level. Then, the flip-flop 320_i starts operating in the period T2, and the signals GS1_i and GS7_i become the L level. After that, the signals GS2 and GS 3 are inverted. Then, the flip-flop 320_i starts operating in the period T2, and the signals GS1_i and GS7_i become the H level. The signal GS1_i is input as a reset signal to the flip flop 320_i-1, and the signal GS7_i is input as a start signal to the flip flop 320_i+1. Therefore, the flip-flop 3 20_i-1 starts operating in the period T3, and the flip-flop 320_i+1 starts operating in the period T1. After that, the signals GS2 and GS3 are inverted again. Then, the flip-flop 320_i+1 starts operating in the period T2, and the signal GS 1_i+1 becomes the H level. The signal GS1_i+1 is input as a set signal to the flip-flop 320_i. Therefore, the flip-flop 320_i starts operating in the period T3, and the signals GS1_i and GS7_i become the L level. After that, until the signal GS7_i-1 becomes the H level again, the flip-flop 320_i is the signal ​​​​​Each time GS2 and signal GS3 are inverted, the operations in period T4 and the operations in period T5 are repeated. Repeat.

[0264] In the shift register of this embodiment, since signals GS7_1 to GS7_N are used as start signals, the delay times of signals S1_1 to S1_N can be shortened. This is because signals GS7_1 to GS7_N are not input to gate lines, pixels, etc., and thus have less delay or distortion compared to signals S1_1 to S1_N. 1 to S1_N. 12.

[0265] Alternatively, in the shift register of this embodiment, since signals GS1_1 to GS1_N are used as reset signals, in the operation of each flip-flop in period T3, the time that transistor 101 is turned on can be lengthened. Therefore, the fall times of signals S1_1 to S1_1 and signals GS7_1 to GS7_N can be shortened. 20. 22.

[0266] Note that signals GS1_1 to GS1_N can be input as start signals to the flip-flops in the next stage. For example, signal GS1_i can be input as a start signal to flip-flop 320_i + 1. 28. 30.

[0267] Note that signals GS7_1 to GS7_N can be input as reset signals to the flip-flops in the previous stage. For example, signal GS7_i can be input as a reset signal to flip-flop 320_i - 1. 36. 38.

[0268] (Embodiment 5) In this embodiment, an example of a display device will be described.

[0269] First, referring to FIG. 22(A), an example of the system block of the liquid crystal display device will be described. The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_ 2, a pixel section 5364, a circuit 5365, and a lighting device 5366. In the pixel section 5364, a plurality of wirings 5371 are arranged extending from the circuit 5362, and a plurality of wirings 5372 are arranged extending from the circuit 5363_1 and the circuit 5363_2. And in the intersection regions of the plurality of wirings 5 371 and the plurality of wirings 5372, pixels 5367 each having a display element such as a liquid crystal element are arranged in a matrix.

[0270] The circuit 5361 has a function of outputting signals or voltages, etc. to the circuit 5362, the circuit 5363_1, the circuit 5 363_2, and the circuit 5365 according to the video signal 5360, and can function as a controller, a control circuit, a timing generator, or a regulator, etc.

[0271] As an example, the circuit 5361 outputs signals such as a start signal (SSP) for a signal line driving circuit, a clock signal (SCK) for a signal line driving circuit, an inverted clock signal (SCKB) for a signal line driving circuit, data (DATA) for a video signal, and a latch signal (LAT) to the circuit 5362. The circuit 5362 has a function of outputting a video signal to the plurality of wirings 5372 according to these signals and functions as a signal line driving circuit.

[0272] When a video signal is input to the plurality of wirings 5371, the plurality of wirings 5371 can function as signal lines, video signal lines, or source lines, etc.

[0273] The circuit 5361 outputs signals such as, for example, a start signal (GSP) for a scanning line driving circuit, a clock signal (GCK) for a scanning line driving circuit, and a clock signal (GCKB) for an inverted scanning line driving circuit to the circuits 5363_1 and 5363_2. The circuits 5363_1 and 5363_2 have a function of outputting scanning signals to a plurality of wirings 5371 in response to these signals and function as scanning line driving circuits. When scanning signals are input to the plurality of wirings 5372, the plurality of wirings 5372 can function as signal lines, scanning lines, gate lines, or the like. Since the same signals are input from the circuit 5361 to the circuits 5363_1 and 5363_2, the scanning signals output from the circuit 5363_1 to the plurality of wirings 5367 and the scanning signals output from the circuit 5363_2 to the plurality of wirings 5367 are often at substantially the same timing. Therefore, the loads driven by the circuits 5363_1 and 5363_2 can be reduced. Thus, the display device can be made larger. Or, the display device can be made high-definition. Or, since the channel widths of the transistors included in the circuits 5363_1 and 5363_2 can be reduced, a narrow-bezel display device can be obtained. The circuit 5361 outputs a backlight control signal (BLC) to the circuit 5365, for example. The circuit 5365 has a function of controlling the amount or time of power supplied to the lighting device 5366 in response to the backlight control signal (BLC) to control the luminance (or average luminance) of the lighting device 5366 and functions as a power supply circuit.

[0274]

[0275]

[0276] ​​​​​​​​​​​​​​​

[0277] Note that it is possible to omit either the circuit 5363_1 or the circuit 5363_2.

[0278] Note that it is possible to newly arrange wirings such as capacitance lines, power supply lines, and scanning lines in the pixel section 5364. And the circuit 5361 can output signals or voltages or the like to these wirings. Or, a circuit similar to the circuit 5363_1 or the circuit 5363_2 can be newly added, and this newly added circuit can output signals such as scanning signals to the newly added wirings.

[0279] Note that the pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in FIG. 22(B), since the display element emits light, the circuit 5365 and the lighting device 5366 can be omitted. And, in order to supply power to the display element, it is possible to arrange a plurality of wirings 5373 that can function as power supply lines in the pixel section 5364. The circuit 5361 can supply a power supply voltage called voltage (ANO) to the wiring 5373. This wiring 5373 can be connected separately for each color element of the pixel, or can be commonly connected to all pixels.

[0280] Note that in FIG. 22(B), as an example, the circuit 5361 shows an example in the case of supplying different signals to the circuit 5363_1 and the circuit 5363_2. The circuit 5361 outputs signals such as a start signal (GSP1) for the scanning line drive circuit, a clock signal (GCK1) for the scanning line drive circuit, and a clock signal (GCKB1) for the inverted scanning line drive circuit to the circuit 5363_1. Thus, circuit 5361 outputs signals such as a start signal for the scanning line driving circuit (GSP2), a clock signal for the scanning line driving circuit (GCK2), and an inverted clock signal for the scanning line driving circuit (GCKB2) to circuit 5363_2. In this case, circuit 5363_1 scans only the wirings of the odd rows among the plurality of wirings 5372, and circuit 5363_2 can scan only the wirings of the even rows among the plurality of wirings 5372. Therefore, since the driving frequencies of circuit 5363_1 and circuit 5363_2 can be reduced, power consumption can be reduced. Or, the area where one stage of flip-flops can be laid out can be increased. Therefore, the display device can be made high-definition. Or, the display device can be made large. Note that, similar to FIG. 22(B), in FIG. 22(A) as well, circuit 5361 can supply separate signals to circuit 5363_1 and circuit 5363_2. Next, an example of the configuration of the display device will be described with reference to FIGS. 23(A), (B), (C), (D), and (E). In FIG. 23(A), circuits having a function of outputting signals to pixel section 5364 (for example, circuit 5362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, since the number of external components is reduced, cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the number of wirings between substrate 5380 and external components can be reduced. Thus, the number of external components is reduced, so cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the number of wirings between substrate 5380 and external components can be reduced. Or, the area where one stage of flip-flops can be laid out can be increased. Therefore, the display device can be made high-definition. Or, the display device can be made large. Note that, similar to FIG. 22(B), in FIG. 22(A) as well, circuit 5361 can supply separate signals to circuit 5363_1 and circuit 5363_2. Next, an example of the configuration of the display device will be described with reference to FIGS. 23(A), (B), (C), (D), and (E).

[0281] Note that, similar to FIG. 22(B), in FIG. 22(A) as well, circuit 5361 can supply separate signals to circuit 5363_1 and circuit 5363_2. Next, an example of the configuration of the display device will be described with reference to FIGS. 23(A), (B), (C), (D), and (E).

[0282] Next, an example of the configuration of the display device will be described with reference to FIGS. 23(A), (B), (C), (D), and (E). In FIG. 23(A), circuits having a function of outputting signals to pixel section 5364 (for example, circuit 5362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, since the number of external components is reduced, cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the number of wirings between substrate 5380 and external components can be reduced.

[0283] In FIG. 23(A), circuits having a function of outputting signals to pixel section 5364 (for example, circuit 5362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, since the number of external components is reduced, cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the number of wirings between substrate 5380 and external components can be reduced. In FIG. 23(A), circuits having a function of outputting signals to pixel section 5364 (for example, circuit 5362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, since the number of external components is reduced, cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the number of wirings between substrate 5380 and external components can be reduced. In FIG. 23(A), circuits having a function of outputting signals to pixel section 5364 (for example, circuit 5362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, since the number of external components is reduced, cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the number of wirings between substrate 5380 and external components can be reduced. In FIG. 23(A), circuits having a function of outputting signals to pixel section 5364 (for example, circuit 5362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, since the number of external components is reduced, cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the number of wirings between substrate 5380 and external components can be reduced. In FIG. 23(A), circuits having a function of outputting signals to pixel section 5364 (for example, circuit 5362, circuit 5363_1, and circuit 5363_2, etc.) are formed on the same substrate 5380 as pixel section 5364. And circuit 5361 is formed on a substrate different from pixel section 5364. Thus, since the number of external components is reduced, cost reduction can be achieved. Or, since the number of signals or voltages input to substrate 5380 is reduced, the number of wirings between substrate 5380 and external components can be reduced. The number of connections can be reduced. Therefore, it is possible to improve reliability or yield. It can be done.

[0284] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate can be mounted on an FPC (Flexible Printed Circuit) by the TAB (Tape Automated Bonding) method. Or, the substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method. Printed Circuit) by the TAB (Tape Automated Bonding) method. Printed Circuit) by the TAB (Tape Automated Bonding) method. Or, the substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method. The substrate can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method. It can be mounted on the same substrate 5380 as the pixel portion 5364 by the COG (Chip on Glass) method.

[0285] When the circuit is formed on a substrate different from the pixel portion 5364, a transistor using a single crystal semiconductor can be formed on the substrate. Therefore, the circuit formed on the substrate can obtain merits such as an improvement in driving frequency, an improvement in driving voltage, and a reduction in variation of output signals. A transistor using a single crystal semiconductor can be formed on the substrate. Therefore, the circuit formed on the substrate can obtain merits such as an improvement in driving frequency, an improvement in driving voltage, and a reduction in variation of output signals. A transistor using a single crystal semiconductor can be formed on the substrate. Therefore, the circuit formed on the substrate can obtain merits such as an improvement in driving frequency, an improvement in driving voltage, and a reduction in variation of output signals. It can obtain merits such as an improvement in driving frequency, an improvement in driving voltage, and a reduction in variation of output signals.

[0286] In many cases, signals, voltages, currents, etc. are input from an external circuit via the input terminal 5381. In many cases, signals, voltages, currents, etc. are input from an external circuit via the input terminal 5381.

[0287] In FIG. 23(B), circuits with low driving frequencies (for example, circuit 5363_1, circuit 5363_ 2) are formed on the same substrate 5380 as the pixel portion 5364. And circuits 5361 and circuit 5362 are formed on a substrate different from the pixel portion 5364. Thus, since it becomes possible to configure the circuit formed on the substrate 5380 with transistors having a small mobility, it becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like as the semiconductor layer of the transistor. Therefore, the size of the display device can be increased and the number of processes can be reduced. Since it becomes possible to configure the circuit formed on the substrate 5380 with transistors having a small mobility, it becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like as the semiconductor layer of the transistor. Since it becomes possible to configure the circuit formed on the substrate 5380 with transistors having a small mobility, it becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like as the semiconductor layer of the transistor. Since it becomes possible to configure the circuit formed on the substrate 5380 with transistors having a small mobility, it becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like as the semiconductor layer of the transistor. Therefore, the size of the display device can be increased and the number of processes can be reduced. It is possible to achieve reduction, cost reduction, or improvement in yield, etc.

[0288] As shown in Fig. 23(C), a part of circuit 5362 (circuit 5362a) is formed on the same substrate 5380 as pixel section 53 64, and the remaining circuit 5362 (circuit 5362b) can be formed on a substrate different from pixel section 5 364. Circuit 5362a is often a circuit (for example, a shift register, a selector, a switch, etc.) that can be constituted by transistors with low mobility. And circuit 5362b is often a circuit (for example, a shift register, a latch circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, etc.) that is preferably constituted by transistors with high mobility and small characteristic dispersion. By doing so, as in Fig. 23(B), it becomes possible to use a non-single crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or an oxide semiconductor, etc. as the semiconductor layer of the transistor, and further reduction of external components can be achieved. In Fig. 23(D), circuits having a function of outputting a signal to pixel section 5364 (for example, circuit 5 362, circuit 5363_1, and circuit 5363_2, etc.), and circuits having a function of controlling these circuits (for example, circuit 5361) are formed on a substrate different from pixel section 5364. Thus, it becomes possible to form the pixel section and its peripheral circuits on separate substrates,

[0289] so that improvement in yield can be achieved.

[0290] In Fig. 23(E), a part of circuit 5361 (circuit 5361a) is formed on the same substrate 5380 as pixel section 5364, and the remaining circuit 5361 (circuit 5361b) is different from pixel section 5364. It is formed on a substrate. Circuit 5361a is composed of transistors with low mobility. There are many cases where it has circuits (such as switches, selectors, level shift circuits, etc.) that can be configured. And circuit 5361b preferably has circuits (such as shift registers, timing generators, oscillators, regulators, or analog buffers, etc.) that are configured using transistors with high mobility and small variations. There are many cases.

[0291] Note that as circuit 5363_1 and circuit 5363_2, the semiconductor devices of Embodiments 1 to 4, or a shift register can be used. In this case, when circuit 5363_ 1 and circuit 5363_2 are formed on the same substrate as the pixel portion, it is possible to make the polarities of all the transistors formed on the substrate N-channel type or P-channel type. Thus, it is possible to reduce the number of processes, improve the yield, or reduce the cost. In particular, by making the polarities of all the transistors N-channel type, it becomes possible to use a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor, etc. as the semiconductor layer of the transistor. Therefore, it is possible to achieve an increase in the size of the display device, a reduction in cost, or an improvement in yield, etc.

[0292] Note that transistors using a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor, etc. as the semiconductor layer often cause characteristic degradation such as an increase in the threshold voltage or a decrease in mobility. However, the semiconductor devices or shift registers of Embodiments 1 to 4 can suppress the characteristic degradation of the transistors, so the life of the display device can be extended.

[0293] Note that, as a part of the circuit 5362, the semiconductor devices of Embodiments 1 to 4, or a shift register can be used. For example, the circuit 5362a shown in FIG. 23(C) can have the semiconductor devices of Embodiments 1 to 4, or a shift register.

[0294] (Embodiment 6) In this embodiment, a layout diagram of a shift register (hereinafter also referred to as a top view) will be described. In this embodiment, as an example, the layout diagram of the shift register in FIG. 15 will be described. Note that the content described in this embodiment can also be applied to the semiconductor devices, shift registers, or display devices of Embodiments 1 to 5, in addition to the shift register in FIG. 15. It should be noted that the layout diagram of this embodiment is an example and is not limited thereto.

[0295] The layout diagram of this embodiment will be described with reference to FIGS. 30 and 31. FIG. 30 shows an example of a layout diagram of a part of the shift register, and FIG. 31 shows, as an example, a layout diagram of the flip-flop 200_i.

[0296] The transistors, capacitive elements, or wirings shown in FIGS. 30 and 31 are composed of a conductive layer 401, a semi- conductor layer 402, a conductive layer 403, a conductive layer 404, and a contact hole 405. However, it is not limited thereto, and another conductive layer, insulating film, or another contact hole can be newly formed. For example, it is possible to newly add a contact hole for connecting the conductive layer 401 and the conductive layer 403.

[0297] ​​​​The conductive layer 401 can include a portion that functions as a gate electrode or a wiring. Half The semiconductor layer 402 can include a portion that functions as a semiconductor layer of a transistor. The conductive layer 403 can include a portion that functions as a wiring, a source, or a drain. The conductive layer 404 can include a portion that functions as a transparent electrode, a pixel electrode, or a wiring. The contact hole 405 can be used to connect the conductive layer 401 and the conductive layer 404, or to connect the conductive layer 403 and the conductive layer 404.

[0298] In an example of FIG. 30, the wiring 202 has an opening 411, and the wiring 203 has an opening 412. In this way, by the wiring 202 and the wiring 203 having openings, the parasitic capacitance can be reduced. Or, the breakdown of the transistor caused by electrostatic breakdown can be suppressed. However, it is not limited to this, and similar to the wiring 204, the opening 411 , or the opening 412 can be omitted. Or, an opening can be provided in the wiring 204 in the same way as the wiring 202 or the wiring 203.

[0299] In an example of FIG. 30, by providing an opening in a part of the intersection of the wiring 202 or the wiring 203 and another wiring, the crosstalk capacitance of the wiring can be reduced. Therefore, noise reduction, or reduction of signal delay or distortion, etc. can be achieved.

[0300] In an example of FIG. 30, on a part of the conductive layer 403 included in the wiring 204, the conductive layer 404 is formed. And the conductive layer 404 is connected to the conductive layer 4 03 through the contact hole 405. In this way, the wiring resistance can be reduced, so the reduction of voltage drop , or the delay or attenuation of the signal can be reduced. However, it is not limited to this, and the conductive layer 404 and the contact hole 405 can be omitted. Or , similar to the wiring 204, in the wiring 202 or the wiring 203, a part of the conductive layer 403 has a conductive layer 404 formed thereon, and the conductive layer 404 can be connected to the conductive layer 403.

[0301] Here, in an example of FIG. 30, the wiring widths of the wiring 202, the wiring 203, and the wiring 2 04 are respectively shown as the wiring width 421, the wiring width 422, and the width 423. And the openings the width of 411, the length of the opening 411, the width of the opening 412, and the length of the opening 412 are respectively , shown as the width 424, the length 425, the width 426, and the length 427.

[0302] The signals input to the wiring 202 and the wiring 203 are often signals inverted from each other. Therefore, it is preferable that the wiring resistance or parasitic capacitance of the wiring 202 is set to be approximately equal to the wiring resistance or parasitic capacitance of the wiring 203. Accordingly, it is preferable that the wiring 202 includes a portion approximately equal to the wiring width 422. Or, the opening 411 preferably includes a portion approximately equal to the width 426 or the length 427 of the opening 412. However, it is not limited to this, and the wiring width 421, the wiring width 422, the width 424 of the opening 411, the length 425 of the opening 411, or the length 427 of the opening 412 can be set to various values. For example, assume that the cross-capacitance between the wiring 202 and other wirings is larger than the cross-capacitance between the wiring 203 and other wirings. In this case, by reducing the wiring resistance of the wiring 202, the delay or attenuation of the signals input to the wiring 202 and the wiring 203 can be approximately reduced. It is possible to set them to be equal. For this purpose, the wiring 202 can include a portion larger than the wiring width 42 2. Or, the opening 411 can include a portion smaller than the width 426 of the opening 412. Or, the opening 411 can include a portion shorter than the length 427 of the opening 4 12. On the other hand, when the mutual capacitance between the wiring 202 and other wirings is smaller than the mutual capacitance between the wiring 203 and other wirings, the wiring 202 can include a portion smaller than the wiring width 422. Or, the opening 411 can include a portion larger than the width 426 of the opening 412. Or, the opening 411 can include a portion longer than the length 427 of the opening 412. 12. If the mutual capacitance between the wiring 202 and other wirings is smaller than the mutual capacitance between the wiring 203 and other wirings, the wiring 202 can include a portion smaller than the wiring width 422. Or, the opening 411 can include a portion larger than the width 426 of the opening 412. Or, the opening 411 can include a portion longer than the length 427 of the opening 412. 12. 12. Or, the opening 411 can include a portion larger than the width 426 of the opening 412. Or, the opening 411 can include a portion longer than the length 427 of the opening 412. 12.

[0303] When the wiring 204 does not have an opening, the wiring 204 preferably includes a portion having a wiring width 421 or smaller than the wiring width 42 2. This is because the wiring 204 does not have an opening, so the wiring resistance of the wiring 204 is small. However, it is not limited to this, and the wiring 2 04 can include a portion larger than the wiring width 421 or the wiring width 422. 2.

[0304] In an example of FIG. 31, in the capacitor elements 105 and 106, one electrode is formed by the conductive layer 401, and the other electrode is formed by the conductive layer 403. By doing so, the capacitance value per unit area can be increased, so that the layout area can be reduced. However, it is not limited to this, and it is possible to arrange the semiconductor layer 402 between the conductive layer 401 and the conductive layer 403. By doing so, it is possible to suppress the short circuit between the conductive layer 401 and the conductive layer 403. Or, the capacitor element 401 and the conductive layer 403 can be short-circuited. By doing so, the capacitance value per unit area can be increased, so that the layout area can be reduced. However, it is not limited to this, and it is possible to arrange the semiconductor layer 402 between the conductive layer 401 and the conductive layer 403. By doing so, it is possible to suppress the short circuit between the conductive layer 401 and the conductive layer 403. Or, the capacitor element 401 and the conductive layer 403 can be short-circuited. By doing so, the capacitance value per unit area can be increased, so that the layout area can be reduced. However, it is not limited to this, and it is possible to arrange the semiconductor layer 402 between the conductive layer 401 and the conductive layer 403. By doing so, it is possible to suppress the short circuit between the conductive layer 401 and the conductive layer 403. Or, the capacitor element 401 and the conductive layer 403 can be short-circuited. By doing so, the capacitance value per unit area can be increased, so that the layout area can be reduced. However, it is not limited to this, and it is possible to arrange the semiconductor layer 402 between the conductive layer 401 and the conductive layer 403. By doing so, it is possible to suppress the short circuit between the conductive layer 401 and the conductive layer 403. Or, the capacitor element 401 and the conductive layer 403 can be short-circuited. By doing so, the capacitance value per unit area can be increased, so that the layout area can be reduced. However, it is not limited to this, and it is possible to arrange the semiconductor layer 402 between the conductive layer 401 and the conductive layer 403. By doing so, it is possible to suppress the short circuit between the conductive layer 401 and the conductive layer 403. Or, the capacitor element 105 or the capacitive element 106 can be a MOS capacitor.

[0305] In an example of FIG. 31, in transistors 101, 103, 104, 131, 132, 133, 134, and 135, the overlapping area of the conductive layer 401 of the second terminal and the conductive layer 403 is preferably smaller than the overlapping area of the conductive layer 401 of the first terminal and the conductive layer 403. By doing so, the gate of the transistor 101 or the noise of the wiring 201_i can be reduced. Or, since the concentration of the electric field on the second terminal can be suppressed, the deterioration or destruction of the transistor can be suppressed. Note that a semiconductor layer 402 can be formed in the overlapping portion of the conductive layer 401 and the conductive layer 403. By doing so, the parasitic capacitance between the conductive layer 401 and the conductive layer 403 can be reduced, so that noise can be reduced. For the same reason, a semiconductor layer 402 or a conductive layer 403 can be formed in the overlapping portion of the conductive layer 401 and the conductive layer 404. Note that the conductive layer 404 can be formed on a part of the conductive layer 401, and the conductive layer 401 can be connected to the conductive layer 404 through the contact hole 405. By doing so,

[0306] the wiring resistance can be lowered. Or, the conductive layer 403 and the conductive layer 404 can be formed on a part of the conductive layer 401, the conductive layer 401 is connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 is connected to another contact hole 405. the wiring resistance can be reduced. Or, the conductive layer 403 and the conductive layer 404 can be formed on a part of the conductive layer 401, the conductive layer 401 is connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 is connected to another contact hole 405. the wiring resistance can be reduced. Note that a semiconductor layer 402 or a conductive layer 403 can be formed in the overlapping portion of the conductive layer 401 and the conductive layer 404. This is possible.

[0307] Note that the conductive layer 404 can be formed on a part of the conductive layer 401, and the conductive layer 401 can be connected to the conductive layer 404 through the contact hole 405. By doing so, the wiring resistance can be lowered. Or, the conductive layer 403 and the conductive layer 404 can be formed on a part of the conductive layer 401, the conductive layer 401 is connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 is connected to another contact hole 405. the wiring resistance can be reduced. Or, the conductive layer 403 and the conductive layer 404 can be formed on a part of the conductive layer 401, the conductive layer 401 is connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 is connected to another contact hole 405. and the conductive layer 404, and the conductive layer 401 is connected to the conductive layer 404 through the contact hole 405, and the conductive layer 403 is connected to another contact hole 405. This is possible. It can be connected to the conductive layer 404. By doing so, the wiring resistance can be further reduced.

[0308] Note that the conductive layer 404 is formed on a part of the conductive layer 403, and the conductive layer 403 can be connected to the conductive layer 404 through the contact hole 405. By doing so, the wiring resistance can be reduced.

[0309] Note that the conductive layer 401 or the conductive layer 403 is formed under a part of the conductive layer 404, and the conductive layer 404 can be connected to the conductive layer 401 or the conductive layer 403 through the contact hole 405. By doing so, the wiring resistance can be reduced.

[0310] Note that when the capacitor element 105 is omitted, as described in the first embodiment, the parasitic capacitance between the gate and the second terminal of the transistor 101 can be made larger than the parasitic capacitance between the gate and the first terminal of the transistor 101. An example of the layout diagram of the transistor 101 in this case is shown in FIG. 18. In an example of FIG. 18, the width of the conductive layer 403 that can function as the first electrode of the transistor 101 is shown as width 431, and the width of the conductive layer 403 that can function as the second electrode of the transistor 101 is shown as width 432. Then, the width 431 can be larger than the width 432. By doing so, as described in the first embodiment, the parasitic capacitance between the gate and the second terminal of the transistor 101 can be made larger than the parasitic capacitance between the gate and the first terminal of the transistor 101. However, it is not limited to this.

[0311] (Embodiment 7) In this embodiment, an example of a signal line driving circuit will be described. Note that the signal line driving circuit can be referred to as a semiconductor device or a signal generation circuit.

[0312] An example of the signal line driving circuit will be described with reference to FIG. 26(A). The signal line driving circuit has a plurality of circuits 502_1 to 502_N (N is a natural number), a circuit 500, and a circuit 501. And the circuits 502_1 to 502_N each have a plurality of transistors 503_1 to 503_k (k is a natural number). The transistors 503_1 to 503_k are assumed to be N-channel type. However, it is not limited thereto, and the transistors 503_1 to 503_k can be P-channel type or can be CMOS type switches.

[0313] The connection relationship of the signal line driving circuit will be described by taking the circuit 502_1 as an example. The first terminals of the transistors 503_1 to 503_k are connected to the wiring 505_1. The second terminals of the transistors 503_1 to 503_k are each connected to the wirings S1 to Sk. The gates of the transistors 503_1 to 503_k are each connected to the wirings 504_1 to 504_k. For example, the first terminal of the transistor 503_1 is connected to the wiring 505_1, the second terminal of the transistor 503_1 is connected to the wiring S1, and the gate of the transistor 503_1 is connected to the wiring 504_1.

[0314] The circuit 500 has a function of supplying signals to the circuits 502_1 to 502_N via the wirings 504_1 to 504_k and can function as a shift register, a decoder, or the like. ​​​​​​​​​​​​This is the case. This signal is often a digital signal and can function as a selection signal. And the wirings 504_1 to 504_k can function as signal lines.

[0315] The circuit 501 has a function of outputting a signal to the circuits 502_1 to 502_N and can function as a video signal generation circuit or the like. For example, the circuit 501 supplies a signal to the circuit 502_1 via the wiring 505_1. At the same time, it supplies a signal to the circuit 502_2 via the wiring 505_2. This signal is often an analog signal and can function as a video signal. And the wirings 505_1 to 505_N can function as signal lines.

[0316] The circuits 502_1 to 502_k have a function of selecting to which wiring the output signal of the circuit 501 is output and can function as a selector circuit. For example, the circuit 502_1 has a function of selecting to which of the wirings S1 to Sk the signal output by the circuit 501 to the wiring 505_1 is output.

[0317] The transistors 503_1 to 503_N each have a function of controlling the conduction state between the wiring 505_1 and the wirings S1 to Sk according to the output signal of the circuit 500 and function as switches.

[0318] Next, the operation of the signal line driving circuit in FIG. 26(A) will be described with reference to the timing chart in FIG. 26(B). In FIG. 26(B), the signal 514_1 input to the wiring 504_1, the signal 514_2 input to the wiring 504_2, and the signal 514 input to the wiring 504_k are shown. ​​​​​​​​​​_k, the signal 515_1 input to the wiring 505_1, and the letter An example of 515_2 input to the wiring 505_2 is shown.

[0319] Note that one operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The one gate selection period refers to the period during which the pixels belonging to a certain row are selected and a video signal can be written to the pixels. That is what is meant by the period.

[0320] Note that the one gate selection period is divided into a period T0, a period T1, and up to a period Tk. The period T0 is a period for simultaneously applying a precharge voltage to the pixels belonging to the selected row, and can function as a precharge period. The periods T1 to Tk are each a period for writing a video signal to the pixels belonging to the selected row, and can function as a writing period. That's it.

[0321] For the sake of convenience, the operation of the signal line driving circuit will be described by taking the operation of the circuit 502_1 as an example.

[0322] First, in the period T0, the circuit 500 outputs a signal of H level to the wirings 504_1 to 504_k. Then, since the transistors 503_1 to 503_k turn on, the wirings 50 5_1 and the wirings S1 to Sk become conductive. At this time, since the circuit 501 supplies the precharge voltage Vp to the wiring 505_ 1, the precharge voltage Vp is output to the wirings S1 to Sk through the transistors 503_1 to 503_k, respectively. And the pre charge voltage Vp is written to the pixels belonging to the selected row, so the pixels belonging to the selected row are precharged.

[0323] Next, in period T1, circuit 500 outputs a signal of H level to wiring 504_1. Then, since transistor 503_1 turns on, wiring 505_1 and wiring S1 become conductive state. And wiring 505_1 and wiring S2~Sk become non-conductive state. At this time , assuming that circuit 501 outputs signal Data(S1) to wiring 505_1, signal Data(S1) is output to wiring S1 via transistor 503_1. In this way , signal Data(S1) is written to the pixels belonging to the selected row among the pixels connected to wiring S1.

[0324] Next, in period T2, circuit 500 outputs a signal of H level to wiring 504_2. Then, since transistor 503_2 turns on, wiring 505_2 and wiring S2 become conductive state. And wiring 505_1 and wiring S1 become non-conductive state, and wiring 505_1 and wiring S3~Sk remain in non-conductive state. At this time, if circuit 501 outputs signal Data (S2) to wiring 505_1, signal Data(S2) is output to wiring S2 via transistor 503_2. In this way, signal Data(S2) is written to the pixels belonging to the selected row among the pixels connected to wiring S2.

[0325] After that, until period Tk, circuit 500 outputs signals of H level to wiring 504_1~504_k in order. So, similar to period T1 and period T2, from period T3 to period Tk, circuit 5 00 outputs signals of H level to wiring 504_3~504_k in order. Therefore, transistors 503_3~503_k turn on in order, so transistors 503_1~503 _N is turned on in sequence. Therefore, the signals output from the circuit 501 are output to the wirings S1 to Sk in sequence. In this way, it becomes possible to write signals to the pixels belonging to the selected row in sequence.

[0326] Since the signal line driving circuit of the present embodiment has a circuit that functions as a selector, the number of signals , or the number of wirings can be reduced. Or, before writing the video signal to the pixel (during period T 0), a voltage for performing precharge is written to the pixel, so the writing time of the video signal can be shortened. Therefore, it is possible to increase the size of the display device and increase the definition of the display device . However, it is not limited to this, and it is possible to omit period T0 and not perform precharge on the pixel .

[0327] Note that if k is too large, the writing time to the pixel becomes short, so there may be a case where the writing of the video signal to the pixel is not completed within the time. Therefore, it is preferable that k ≤ 6 . More preferably, it is preferable that k ≤ 3. Even more preferably, it is preferable that k = 2 .

[0328] In particular, when the color elements of the pixel are divided into n (n is a natural number) pieces, it is possible to set k = n . For example, when the color elements of the pixel are divided into three: red (R), green (G), and blue (B) , it is possible to set k = 3. In this case, one gate selection period is divided into period T0, period T1 , period T2, and period T3. And in period T1, period T2, and period T3, respectively , it is possible to write the video signal to the red (R) pixel, the green (G) pixel, and the blue (B) pixel . However, it is not limited to this, and the order of period T1, period T2, and period T3 can be set arbitrarily .

[0329] In particular, when a pixel is divided into n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or auxiliary pixels), k = n can be set. For example, when a pixel is divided into two sub-pixels, k = 2 is possible. In this case, one gate selection period is divided into period T0, period T1, and period T2. Then, in period T1, a video signal can be written to one of the two sub-pixels, and in period T2, a video signal can be written to the other of the two sub-pixels. When divided, k = 2 is possible. In this case, one gate selection period is divided into period T0, period T1, and period T2. Then, in period T1, a video signal can be written to one of the two sub-pixels, and in period T2, a video signal can be written to the other of the two sub-pixels. When divided, k = 2 is possible. In this case, one gate selection period is divided into period T0, period T1, and period T2. Then, in period T1, a video signal can be written to one of the two sub-pixels, and in period T2, a video signal can be written to the other of the two sub-pixels. When divided, k = 2 is possible. In this case, one gate selection period is divided into period T0, period T1, and period T2. Then, in period T1, a video signal can be written to one of the two sub-pixels, and in period T2, a video signal can be written to the other of the two sub-pixels. When divided, k = 2 is possible. In this case, one gate selection period is divided into period T0, period T1, and period T2. Then, in period T1, a video signal can be written to one of the two sub-pixels, and in period T2, a video signal can be written to the other of the two sub-pixels. When divided, k = 2 is possible. In this case, one gate selection period is divided into period T0, period T1, and period T2. Then, in period T1, a video signal can be written to one of the two sub-pixels, and in period T2, a video signal can be written to the other of the two sub-pixels.

[0330] Since the driving frequencies of circuit 500 and circuits 502_1 to 502_N are often low, circuit 500 and circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Further, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of circuit 500 and circuits 502_1 to 502_N are often low, circuit 500 and circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Further, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of circuit 500 and circuits 502_1 to 502_N are often low, circuit 500 and circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Further, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of circuit 500 and circuits 502_1 to 502_N are often low, circuit 500 and circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Further, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of circuit 500 and circuits 502_1 to 502_N are often low, circuit 500 and circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Further, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced. Since the driving frequencies of circuit 500 and circuits 502_1 to 502_N are often low, circuit 500 and circuits 502_1 to 502_N can be formed on the same substrate as the pixel portion. In this way, the number of connections between the substrate on which the pixel portion is formed and the external circuit can be reduced, so that the yield can be improved or the reliability can be improved. Further, as shown in FIG. 23(C), by forming the scanning line driving circuit on the same substrate as the pixel portion, the number of connections to the external circuit can be further reduced.

[0331] As circuit 500, the semiconductor device or shift register of Embodiments 1 to 4 can be used. In this case, the polarities of all the transistors included in circuit 500 can be made N-channel type or P-channel type. Therefore, the number of manufacturing steps can be reduced, the yield can be improved, or the cost can be reduced. As circuit 500, the semiconductor device or shift register of Embodiments 1 to 4 can be used. In this case, the polarities of all the transistors included in circuit 500 can be made N-channel type or P-channel type. Therefore, the number of manufacturing steps can be reduced, the yield can be improved, or the cost can be reduced. As circuit 500, the semiconductor device or shift register of Embodiments 1 to 4 can be used. In this case, the polarities of all the transistors included in circuit 500 can be made N-channel type or P-channel type. Therefore, the number of manufacturing steps can be reduced, the yield can be improved, or the cost can be reduced. As circuit 500, the semiconductor device or shift register of Embodiments 1 to 4 can be used. In this case, the polarities of all the transistors included in circuit 500 can be made N-channel type or P-channel type. Therefore, the number of manufacturing steps can be reduced, the yield can be improved, or the cost can be reduced.

[0332] Note that not only circuit 500 but also the polarities of all the transistors included in circuits 502_1 to 502_N can be made N-channel type or P-channel type. Therefore, circuit 5 Note that not only circuit 500 but also the polarities of all the transistors included in circuits 502_1 to 502_N can be made N-channel type or P-channel type. Therefore, circuit 5 00, and when circuits 502_1 to 502_N are formed on the same substrate as the pixel portion, the number of processes can be reduced, the yield can be improved, or the cost can be reduced. In particular, by making the polarity of all transistors N-channel type, as the semiconductor layer of the transistor, a non-single crystal semiconductor, microcrystalline semiconductor, organic semiconductor, or oxide semiconductor can be used. Therefore, the driving frequencies of circuit 500 and circuits 502_1 to 502_N are often low .

[0333] (Embodiment 8) In this embodiment, the configuration and operation of pixels applicable to a liquid crystal display device will be described.

[0334] FIG. 27(A) is a diagram showing an example of a pixel configuration applicable to a liquid crystal display device. Pixel 508 0 has a transistor 5081, a liquid crystal element 5082, and a capacitor element 5083. The gate of transistor 5081 is electrically connected to wiring 5085. The first terminal of transistor 508 1 is electrically connected to wiring 5084. The second terminal of transistor 5081 is electrically connected to the first terminal of liquid crystal element 5082. The second terminal of liquid crystal element 5082 is connected to wiring 5087 electrically. The first terminal of capacitor element 5083 is electrically connected to the first terminal of liquid crystal element 5082. The second terminal of capacitor element 5083 is electrically connected to wiring 5086 .

[0335] Wiring 5084 can function as a signal line. The signal line is a wiring for transmitting a signal voltage input from outside the pixel to pixel 5080. Wiring 5085 can function as a scanning line . The scanning line is for controlling the on / off of transistor 5081 It is a wiring. The wiring 5086 can function as a capacitance line. The capacitance line is a wiring for applying a predetermined voltage to the second terminal of the capacitance element 5083. The transistor 5081 can function as a switch. The capacitance element 5083 can function as a holding capacitance . The holding capacitance is a capacitance element for allowing the signal voltage to continue to be applied to the liquid crystal element 5 even when the switch is off. The wiring 5087 can function as a counter electrode. The counter electrode is a wiring for applying a predetermined voltage to the second terminal of the liquid crystal element 5082 . Note that the functions that each wiring can have are not limited to this, and it can have various functions. For example, by changing the voltage applied to the capacitance line , the voltage applied to the liquid crystal element can also be adjusted. Note that since the transistor 5081 only needs to function as a switch, the polarity of the transistor 5081 can be P-channel type or N-channel type.

[0336] Fig. 27(B) is a diagram showing an example of a pixel configuration applicable to a liquid crystal display device. The pixel configuration example shown in Fig. 27(B ) is the same configuration as the pixel configuration example shown in Fig. 27(A), except that the wiring 5087 is omitted , and the second terminal of the liquid crystal element 5082 and the second terminal of the capacitance element 5083 are electrically connected . The pixel configuration example shown in Fig. 27(B) is applicable particularly when the liquid crystal element is in the horizontal electric field mode (including the IPS mode, FFS mode, etc.). This is because when the liquid crystal element is in the horizontal electric field mode, the second terminal of the liquid crystal element 5082 and the second terminal of the capacitance element 5083 Since they can be formed on the same substrate, it is easy to electrically connect the second terminal of the liquid crystal element 5082 and the second terminal of the capacitor element 5 083. By adopting the pixel configuration shown in FIG. 27(B), the wiring 5087 can be omitted, so that the manufacturing process can be simplified and the manufacturing cost can be reduced. The pixel configurations shown in FIGS. 27(A) and 27(B) can be arranged in a matrix. By doing so, a display section of the liquid crystal display device is formed, and various images can be displayed. FIG. 27(C) is a diagram showing a circuit configuration when the pixel configurations shown in FIG. 27(A) are arranged in a matrix. The circuit configuration shown in FIG. 27(C) is a diagram showing four pixels extracted from among a plurality of pixels included in the display section. And, a pixel located at the i-th column and j-th row (i, j

[0337] are natural numbers) is denoted as pixel 5080_i,j, and the wiring 5084_i, the wiring 5085_j, and the wiring 5086_j are electrically connected to the pixel 5080_i,j, respectively. Similarly, for the pixel 5080_i+1,j, it is electrically connected to the wiring 5084_i+1, the wiring 5 085_j, and the wiring 5086_j. Similarly, for the pixel 5080_i,j+ 1, it is electrically connected to the wiring 5084_i, the wiring 5085_j+1, and the wiring 5086_j+1. Similarly, for the pixel 5080_i+1,j+1, it is electrically connected to the wiring 5084_i +1, the wiring 5085_j+1, and the wiring 5086_j+1. Each wiring can be shared by a plurality of pixels belonging to the same column or row. In the pixel configuration shown in FIG. 2 7(C), the wiring 5087 is a counter electrode, and the counter electrode is for all pixels. Note that, for the pixel 5080_i+1,j, it is electrically connected to the wiring 5084_i+1, the wiring 5 085_j, and the wiring 5086_j. Similarly, for the pixel 5080_i,j+ 1, it is electrically connected to the wiring 5084_i, the wiring 5085_j+1, and the wiring 5086_j+1. Similarly, for the pixel 5080_i+1,j+1, it is electrically connected to the wiring 5084_i +1, the wiring 5085_j+1, and the wiring 5086_j+1. Each wiring can be shared by a plurality of pixels belonging to the same column or row. In the pixel configuration shown in FIG. 2 7(C), the wiring 5087 is a counter electrode, and the counter electrode is for all pixels. Note that, in the pixel configuration shown in FIG. 27(C), the wiring 5087 is a counter electrode, and the counter electrode is for all pixels. Since it is common in [context not specified], for wiring 5087, notation by natural number i or j will not be used. In addition, since it is also possible to use the pixel configuration shown in FIG. 27(B), even in the configuration where wiring 5087 is described, wiring 5087 is not essential and can be omitted by sharing with other wiring or the like.

[0338] The pixel configuration shown in FIG. 27(C) can be driven in various ways. In particular, by being driven by a method called AC driving, deterioration (burn-in) of the liquid crystal element can be suppressed. FIG. 27(D) is a diagram showing the voltage timing chart applied to each wiring in the pixel configuration shown in FIG. 27(C) when dot inversion driving, which is one type of AC driving, is performed. By performing dot inversion driving, flicker (flutter) visually recognized when AC driving is performed can be suppressed. In FIG. 27(D), signals 5185_j input to wiring 5085_j, signals 5185_j+1 input to wiring 5085_j+1, signals 5184_i input to wiring 5084_i, signals 5184_i+1 input to wiring 5084_i+1, and voltage 5186 supplied to wiring 5086 are shown. In the pixel configuration shown in FIG. 27(C), the switch in the pixel electrically connected to wiring 5085_j becomes in a selected state (on state) during the j-th gate selection period within one frame period, and becomes in a non-selected state (off state) during other periods. And after the j-th gate selection period, the (j + 1)-th gate selection period is provided. By performing sequential scanning in this way, all pixels become in a selected state in order within one frame period. The timing chart shown in FIG. 27(D) is as follows.

[0339] In the pixel configuration shown in FIG. 27(C), the switch in the pixel electrically connected to wiring 5085_j is in a selected state (on state) during the j-th gate selection period within one frame period, and is in a non-selected state (off state) during other periods. And after the j-th gate selection period, the (j + 1)-th gate selection period is provided. By performing sequential scanning in this way, all pixels become in a selected state in order within one frame period. By doing so, within one frame period, all pixels will be sequentially in a selected state. The timing In the timing chart, when the voltage is in a high state (high level), the switch in the corresponding pixel becomes in a selected state, and when the voltage is in a low state (low level), it becomes in an unselected state. Note that this is the case when the transistor in each pixel is of the N-channel type. When a P-channel type transistor is used, the relationship between the voltage and the selected state is opposite to that in the case of the N-channel type.

[0340] In the timing chart shown in FIG. 27(D), during the j-th gate selection period in the k-th frame (k is a natural number), a positive signal voltage is applied to the wiring 5084_i used as a signal line, and a negative signal voltage is applied to the wiring 5084_i + 1. Then, during the j + 1-th gate selection period in the k-th frame, a negative signal voltage is applied to the wiring 5084_i, and a positive signal voltage is applied to the wiring 5 084_i + 1. Thereafter, for each signal line, signals with inverted polarities are alternately applied for each gate selection period. As a result, in the k-th frame a positive signal voltage is applied to the pixel 5080_i,j, a negative signal voltage is applied to the pixel 5080_i + 1,j, a negative signal voltage is applied to the pixel 5080_i,j + 1, and a positive signal voltage is applied to the pixel 5080_i + 1,j + 1, respectively. And in the k + 1-th frame, for each pixel, a signal voltage with a polarity opposite to the signal voltage written in the k-th frame is written. As a result, in the k + 1-th frame, a negative signal voltage is applied to the pixel 5080_i,j, a positive signal voltage is applied to the pixel 5080_i + 1,j, a positive signal voltage is applied to the pixel 5080_i,j + 1, and a negative signal voltage is applied to the pixel 5080_i + 1,j + 1, respectively. In this way, in the same frame, adjacent pixels have different polarities ​​ A signal voltage of a certain polarity is applied, and in each pixel, the signal voltage is inverted in polarity every frame. This driving method is dot inversion driving. By dot inversion driving, while suppressing the deterioration of the liquid crystal element, flicker that is visually recognized when the entire or a part of the displayed image is uniform can be reduced. Note that the voltage applied to all the wirings 5086 including the wirings 5086_j and 5086_j+1 can be set to a constant voltage. Note that in the timing chart of the wiring 5084, the notation of the signal voltage indicates only the polarity, but actually, various signal voltage values can be taken at the displayed polarity. Here, although the case of inverting the polarity for each dot (one pixel) has been described, it is not limited to this, and the polarity can also be inverted for a plurality of pixels at a time. For example, by inverting the polarity of the signal voltage written every two gate selection periods, the power consumption for writing the signal voltage can be reduced . In addition, the polarity can be inverted for each column (source line inversion), or the polarity can be inverted for each row (gate line inversion). Note that it is sufficient that a constant voltage is applied to the second terminal of the capacitive element 5083 in the pixel 5080 during one frame period. Here, since the voltage applied to the wiring 5085 used as the scanning line is at a low level for most of the one frame period and a substantially constant voltage is applied , the connection destination of the second terminal of the capacitive element 5083 in the pixel 5080 can be the wiring 5 085. FIG. 27(E) is a diagram showing an example of a pixel configuration applicable to a liquid crystal display device. The pixel configuration shown in FIG. 27(E), when compared with the pixel configuration shown in FIG. 27(C), has wirings .

[0341] Note that it is sufficient that a constant voltage is applied to the second terminal of the capacitive element 5083 in the pixel 5080 during one frame period. Here, since the voltage applied to the wiring 5085 used as the scanning line is at a low level for most of the one frame period and a substantially constant voltage is applied to it, the connection destination of the second terminal of the capacitive element 5083 in the pixel 5080 can be the wiring 5 085. FIG. 27(E) is a diagram showing an example of a pixel configuration applicable to a liquid crystal display device. The pixel configuration shown in FIG. 27(E), when compared with the pixel configuration shown in FIG. 27(C), has wirings . 085. FIG. 27(E) is a diagram showing an example of a pixel configuration applicable to a liquid crystal display device. The pixel configuration shown in FIG. 27(E), when compared with the pixel configuration shown in FIG. 27(C), has wirings . 5086 is omitted, and the second terminal of the capacitive element 5083 in the pixel 5080 is electrically connected to the wiring 5085 in the previous row. Specifically, in the range shown in FIG. 27(E), the second terminals of the capacitive elements 5083 in the pixels 5080_i,j+1 and 5080_i+1,j+1 are electrically connected to the wiring 5085_j. Thus, by electrically connecting the second terminal of the capacitive element 5083 in the pixel 5080 to the wiring 5085 in the previous row, the wiring 5086 can be omitted. As a result, the aperture ratio of the pixel can be improved. Note that the connection destination of the second terminal of the capacitive element 5083 may be the wiring 5085 in another row instead of the wiring 5085 in the previous row. Note that the driving method of the pixel configuration shown in FIG. 27(E) can be the same as the driving method of the pixel configuration shown in FIG. 27(C). In addition, by using the capacitive element 5083 and the wiring electrically connected to the second terminal of the capacitive element 5083, the voltage applied to the wiring 5084 used as the signal line can be reduced. The pixel configuration and driving method in this case will be described with reference to FIGS. 27(F) and 27(G). The pixel configuration shown in FIG. 27(F) is characterized in that, compared with the pixel configuration shown in FIG. 27(A), the number of wirings 5086 per pixel column is two, and the electrical connection between the second terminal of the capacitive element 5083 in the pixel 5080 is performed alternately with adjacent pixels. The two wirings 5086 are respectively referred to as wiring 5086-1 and wiring 5086-2. Specifically, in the range shown in FIG. 27(F), the second terminal of the capacitive element 5083 in the pixel 5080_i,j is electrically connected to the wiring 5086-1_j.

[0342] Note that the capacitive element 5083 and the wiring electrically connected to the second terminal of the capacitive element 5083 can be used to reduce the voltage applied to the wiring 5084 used as the signal line. The pixel configuration and driving method in this case will be described with reference to FIGS. 27(F) and 27(G). The pixel configuration shown in FIG. 27(F) is characterized in that, compared with the pixel configuration shown in FIG. 27(A), the wiring 5086 is two per pixel column, and the electrical connection between the second terminal of the capacitive element 5083 in the pixel 5080 is performed alternately with adjacent pixels. Note that the two wirings 5086 are respectively referred to as wiring 5086-1 and wiring 5086-2. Specifically, in the range shown in FIG. 27(F), the second terminal of the capacitive element 5083 in the pixel 5080_i,j is electrically connected to the wiring 5086-1_j. ​ The second terminal of the capacitive element 5083 in pixel 5080_i+1,j is electrically connected to wiring 5086-2 _j, and the second terminal of the capacitive element 5083 in pixel 5080_i,j+1 is electrically connected to wiring 5086-2_j+1, and the second terminal of the capacitive element 5083 in pixel 5080_i+1,j+1 is electrically connected to wiring 5086-1_j+1. Note that in FIG. 27(G), the signal 5185_j input to wiring 5085_j, the signal 5185_j+1 input to wiring 50 85_j+1, the signal 5184_i input to wiring 5084_i, the signal 5184_i+1 input to wiring 5084_i+1, wiring 5086- 1_j, the signal 5186-1_j input to wiring 5086-1_j, the signal 5186-2_j input to wiring 5086-2_j, the signal 5186-1_j+1 input to wiring 5086-1_j+1, and the signal 5186-2_j+1 input to wiring 5086-2_j+1 are shown.

[0343] And, for example, as shown in FIG. 27(G), when a positive-polarity signal voltage is written to pixel 5080_i, j in the k-th frame, wiring 5086-1_j is set to a low level during the j-th gate selection period, and after the end of the j-th gate selection period, it is changed to a high level and maintained at the high level throughout one frame period. After a negative-polarity signal voltage is written to the j-th gate selection period in the (k+1)-th frame, it is changed to a low level . In this way, after a positive-polarity signal voltage is written to the pixel, by changing the voltage of the wiring electrically connected to the second terminal of the capacitive element 5083 in the positive direction, the voltage applied to the liquid crystal element can be changed by a predetermined amount in the positive direction. That is, the voltage applied to the pixel is increased by that amount when the positive-polarity signal voltage is written to the pixel. Since the signal voltage to be impressed can be reduced, the power consumption for signal writing can be reduced. When a signal voltage with a negative polarity is written during the j-th gate selection period after the signal voltage with a negative polarity is written into the pixel, by changing the voltage of the wiring electrically connected to the second terminal of the capacitor element 5083 in the negative direction, the voltage applied to the liquid crystal element can be changed by a predetermined amount in the negative direction. Thus, similar to the case of a positive polarity, the signal voltage to be written into the pixel can be reduced. That is, the wiring electrically connected to the second terminal of the capacitor element 5083 is preferably different wiring for the pixel to which a signal voltage with a positive polarity is applied and the pixel to which a signal voltage with a negative polarity is applied in the same row of the same frame. FIG. 27(F) shows an example where the wiring 5086-1 is electrically connected to the pixel to which a signal voltage with a positive polarity is written in the k-th frame, and the wiring 5086-2 is electrically connected to the pixel to which a signal voltage with a negative polarity is written in the k-th frame. However, this is just an example. For example, in the case of a driving method where pixels to which a signal voltage with a positive polarity is written and pixels to which a signal voltage with a negative polarity is written appear every two pixels, the electrical connections of the wiring 5086-1 and the wiring 5086-2 are preferably made alternately every two pixels accordingly. Furthermore, when a signal voltage with the same polarity is written into all the pixels in one row (gate line inversion) is also conceivable. In that case, one wiring 5086 per row is sufficient. That is, also in the pixel configuration shown in FIG. 27(C), a driving method for reducing the signal voltage to be written into the pixel, as described with reference to FIGS. 27(F) and 27(G), can be used.

[0344] ​​​​​​​​​​​​​​​Next, a pixel configuration and a driving method thereof that are particularly preferable when the liquid crystal element is in a vertical alignment (VA) mode typified by an MVA mode or a PVA mode will be described. The VA mode has excellent characteristics such as no rubbing process being required during manufacturing, little light leakage during black display, and a low driving voltage. However, it also has a problem that the image quality deteriorates (the viewing angle is narrow) when the screen is viewed obliquely. To widen the viewing angle of the VA mode, as shown in FIGS. 28(A) and 28 (B), it is effective to adopt a pixel configuration in which a pixel has a plurality of sub-pixels. The pixel configurations shown in FIGS. 28(A) and 28(B) represent an example in the case where pixel 5080 includes two sub-pixels (sub-pixel 5080-1, sub-pixel 5080-2). Note that the number of sub-pixels in one pixel is not limited to two, and various numbers of sub-pixels can be used. The larger the number of sub-pixels, the wider the viewing angle can be. The plurality of sub-pixels can have the same circuit configuration as each other. Here, it will be described on the assumption that all sub-pixels are the same as the circuit configuration shown in FIG. 27( A). Note that the first sub-pixel 5080-1 has a transistor 5081-1, a liquid crystal element 5082-1, and a capacitor element 5083-1, and the connection relationships thereof shall conform to the circuit configuration shown in FIG. 27(A). Similarly, the second sub-pixel 5080-2 has a transistor 5081-2, a liquid crystal element 5082-2, and a capacitor element 5083-2, and the connection relationships thereof shall conform to the circuit configuration shown in FIG. 27(A). The pixel configuration shown in FIG. 28(A) has two wirings (wiring 5085-1, wiring 5085-2) serving as scanning lines for the two sub-pixels constituting one pixel, and serves as a signal line for use As described above. Note that the first sub-pixel 5080-1 has a transistor 5081-1, a liquid crystal element 5082-1, and a capacitor element 5083-1, and the connection relationships thereof shall conform to the circuit configuration shown in FIG. 27(A). Similarly, the second sub-pixel 5080-2 has a transistor 5081-2, a liquid crystal element 5082-2, and a capacitor element 5083-2, and the connection relationships thereof shall conform to the circuit configuration shown in FIG. 27(A). The second sub-pixel 5080-2 has a transistor 5081-2, a liquid crystal element 5082-2, and a capacitor element 5083-2, and the connection relationships thereof shall conform to the circuit configuration shown in FIG. 27(A). shall conform to the circuit configuration shown in FIG. 27(A).

[0345] The pixel configuration shown in FIG. 28(A) has two wirings (wiring 5085-1, wiring 5085-2) serving as scanning lines for the two sub-pixels constituting one pixel, and serves as a signal line for use It has one wiring 5084 and one wiring 5086 used as a capacitance line, representing a configuration. That is. Thus, by sharing the signal line and the capacitance line among two sub-pixels, the opening ratio can be improved, and furthermore, the signal line driving circuit can be made simple. As a result, the manufacturing cost can be reduced, and the number of connection points between the liquid crystal panel and the driving circuit IC can be reduced. This can improve the yield. The pixel configuration shown in Fig. 28(B) has one wiring 5085 used as a scanning line for two sub-pixels that make up one pixel, two wirings 5084 (wiring 5084-1, wiring 5084-2) used as signal lines, and one wiring 50 86 used as a capacitance line. This represents a configuration. Thus, by sharing the scanning line and the capacitance line among two sub-pixels, the opening ratio can be improved, and furthermore, the total number of scanning lines can be reduced. Therefore, even in a high-definition liquid crystal panel, the gate line selection period per pixel can be made sufficiently long, and an appropriate signal voltage can be written to each pixel.

[0346] Figs. 28(C) and 28(D) are examples schematically showing the electrical connection states of the elements after replacing the liquid crystal elements with the shapes of the pixel electrodes in the pixel configuration shown in Fig. 28(B). In Figs. 28(C) and 28(D), electrode 5088-1 represents the first pixel electrode, and electrode 5088-2 represents the second pixel electrode. In Fig. 28(C), the first pixel electrode 5088-1 corresponds to the first terminal of the liquid crystal element 5082-1 in Fig. 28(B), and the second pixel electrode 5088-2 corresponds to the first terminal of the liquid crystal element 5082-2 in Fig. 28(B). That is, the first pixel electrode 5088-1 is the source of the transistor 5081-1. In Figs. 28(C) and 28(D), electrode 5088-1 represents the first pixel electrode, and electrode 5088-2 represents the second pixel electrode. In Fig. 28(C), the first pixel electrode 5088-1 corresponds to the first terminal of the liquid crystal element 5082-1 in Fig. 28(B), and the second pixel electrode 5088-2 corresponds to the first terminal of the liquid crystal element 5082-2 in Fig. 28(B). That is, the first pixel electrode 5088-1 is the source of the transistor 5081-1. In Fig. 28(C), the first pixel electrode 5088-1 corresponds to the first terminal of the liquid crystal element 5082-1 in Fig. 28(B), and the second pixel electrode 5088-2 corresponds to the first terminal of the liquid crystal element 5082-2 in Fig. 28(B). That is, the first pixel electrode 5088-1 is the source of the transistor 5081-1. In Fig. 28(C), the first pixel electrode 5088-1 corresponds to the first terminal of the liquid crystal element 5082-1 in Fig. 28(B), and the second pixel electrode 5088-2 corresponds to the first terminal of the liquid crystal element 5082-2 in Fig. 28(B). That is, the first pixel electrode 5088-1 is the source of the transistor 5081-1. In Fig. 28(C), the first pixel electrode 5088-1 corresponds to the first terminal of the liquid crystal element 5082-1 in Fig. 28(B), and the second pixel electrode 5088-2 corresponds to the first terminal of the liquid crystal element 5082-2 in Fig. 28(B). That is, the first pixel electrode 5088-1 is the source of the transistor 5081-1. or is electrically connected to one of the drains, and the second pixel electrode 5088-2 is connected to one of the source or drain of the transistor 5 081-2. On the other hand, in FIG. 28(D), the connection relationship between the pixel electrode and the transistor is reversed. That is, the first pixel electrode 50 88-1 is electrically connected to one of the source or drain of the transistor 5081-2, and the second pixel electrode 5088-2 is electrically connected to one of the source or drain of the transistor 5081-1.

[0347] By alternately arranging the pixel configurations as shown in FIGS. 28(C) and 28(D) in a matrix, a special effect can be obtained. An example of such a pixel configuration and its driving method is shown in FIGS. 28(E) and 28(F). The pixel configuration shown in FIG. 28(E) has a configuration corresponding to the portions of pixels 5 080_i,j and pixel 5080_i+1,j+1 shown in FIG. 28(C), and the portions corresponding to pixels 5080_i+1,j and pixel 5080_i,j+1 are configured as shown in FIG. 28(D). In this configuration, when driven as shown in the timing chart of FIG. 28(F), in the j-th gate selection period of the k-th frame, a positive-polarity signal voltage is written to the first pixel electrode of pixel 5080_i,j and the second pixel electrode of pixel 5080_i+1,j, and a negative-polarity signal voltage is written to the second pixel electrode of pixel 5080_i,j and the first pixel electrode of pixel 508 0_i+1,j. Further, in the (j+1)-th gate selection period of the k-th frame, a positive-polarity signal voltage is written to the second pixel electrode of pixel 5080_i,j+1 and the first pixel electrode of pixel 5080_i+1,j+1, and the first pixel electrode of pixel 5080_i,j+1 and the second pixel electrode of pixel 5080_i+1,j+1 As shown in the timing chart of FIG. 28(F), when driven, in the j-th gate selection period of the k-th frame, a positive-polarity signal voltage is written to the first pixel electrode of pixel 5080_i,j and the second pixel electrode of pixel 5080_i+1,j, and a negative-polarity signal voltage is written to the second pixel electrode of pixel 5080_i,j and the first pixel electrode of pixel 508 0_i+1,j. Further, in the (j+1)-th gate selection period of the k-th frame, a positive-polarity signal voltage is written to the second pixel electrode of pixel 5080_i,j+1 and the first pixel electrode of pixel 5080_i+1,j+1, and a positive-polarity signal voltage is written to the first pixel electrode of pixel 5080_i,j+1 and the second pixel electrode of pixel 5080_i+1,j+1 and a positive-polarity signal voltage is written to the second pixel electrode of pixel 5080_i,j+1 and the first pixel electrode of pixel 5080_i+1,j+1, and a positive-polarity signal voltage is written to the first pixel electrode of pixel 5080_i,j+1 and the second pixel electrode of pixel 5080_i+1,j+1 electrode.​​​​​​ A negative-polarity signal voltage is written to the electrode. In the (k + 1)-th frame, the polarity of the signal voltage is reversed at each pixel. By doing so, while realizing a drive equivalent to dot inversion drive in a pixel configuration including sub-pixels, the polarity of the voltage applied to the signal line can be made the same within one frame period, so that the power consumption for writing the signal voltage of the pixel can be significantly reduced. Note that the voltage applied to all of the wirings 5086 including the wirings 5086_j and 5086_j+1 can be set to a constant voltage. Note that FIG. 27(F) shows the signal 5185_j input to the wiring 5085_j, the signal 5185_j+1 input to the wiring 5085_j+1, the signal 5184-1_i input to the wiring 5084-1_i, the signal 5184-2_i input to the wiring 5084-2_i, the signal 5184-1_i+1 input to the wiring 5084-1_i+1, the signal 5184-2_i+1 input to the wiring 5084-2_i+1, and the voltage 5186 supplied to the wiring 5186. Furthermore, by the pixel configuration and its driving method shown in FIGS. 28(G) and 28(H), the magnitude of the signal voltage written to the pixel can be reduced. This is because the capacitance lines electrically connected to the plurality of sub-pixels included in each pixel are made different for each sub-pixel. That is, by the pixel configuration and its driving method shown in FIGS. 28(E) and 28(F), for sub-pixels in which the same polarity is written within the same frame, the capacitance lines are made common within the same row, and for sub-pixels in which different polarities are written within the same frame, the capacitance lines are made different within the same row. Then, when the writing of each row is completed, each capacitance line

[0348] ​​​​​​​​​​​​​​​​The voltage is changed in the positive direction for the sub-pixels where the signal voltage with positive polarity is written and in the negative direction for the sub-pixels where the signal voltage with negative polarity is written, so that the magnitude of the signal voltage written into the pixel can be reduced. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. The first pixel electrode of the pixel 5080_i+1,j and the wiring 5086-2_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i+1,j and the wiring 5086-1_j are electrically connected via a capacitive element. The first pixel electrode of the pixel 5080_i,j+1 and the wiring 5086-2_j+1 are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j+1 and the wiring 5086-1_j+1 are electrically connected via a capacitive element. The first pixel electrode of the pixel 5080_i+1,j+1 and the wiring 5086-1_j+1 are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i+1,j+1 and the wiring 5086-2_j+1 are electrically connected via a capacitive element. However, this is just an example. For example, in the case of a driving method where pixels with a signal voltage of positive polarity and pixels with a signal voltage of negative polarity appear every two pixels, the electrical connections of the wiring 5086-1 and the wiring 5086-2 should also be alternated every two pixels accordingly. Furthermore, in the case where the same polarity of signal voltage is written in all the pixels in one row (gate line inversion) is also conceivable. In that case, the wiring 5086 is provided for each row. is written, the magnitude of the signal voltage written into the pixel can be reduced. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. Specifically, the wiring 5086 used as the capacitance line is provided in two lines (wiring 5086-1, wiring 5086-2) for each row, and the first pixel electrode of the pixel 5080_i,j and the wiring 5086-1_j are electrically connected via a capacitive element, and the second pixel electrode of the pixel 5080_i,j and the wiring 5086-2_j are electrically connected via a capacitive element. However, this is just an example. For example, in the case of a driving method where pixels with a signal voltage of positive polarity and pixels with a signal voltage of negative polarity appear every two pixels, the electrical connections of the wiring 5086-1 and the wiring 5086-2 should also be alternated every two pixels accordingly. However, this is just an example. For example, in the case of a driving method where pixels with a signal voltage of positive polarity and pixels with a signal voltage of negative polarity appear every two pixels, the electrical connections of the wiring 5086-1 and the wiring 5086-2 should also be alternated every two pixels accordingly. However, this is just an example. For example, in the case of a driving method where pixels with a signal voltage of positive polarity and pixels with a signal voltage of negative polarity appear every two pixels, the electrical connections of the wiring 5086-1 and the wiring 5086-2 should also be alternated every two pixels accordingly. However, this is just an example. For example, in the case of a driving method where pixels with a signal voltage of positive polarity and pixels with a signal voltage of negative polarity appear every two pixels, the electrical connections of the wiring 5086-1 and the wiring 5086-2 should also be alternated every two pixels accordingly. Furthermore, in the case where the same polarity of signal voltage is written in all the pixels in one row (gate line inversion) is also conceivable. In that case, the wiring 5086 is provided for each row. One may be sufficient. That is, even in the pixel configuration shown in FIG. 28(E), a driving method for reducing the signal voltage written to the pixel, as described using FIGS. 28(G) and 28(H), can be used. Note that in FIG. 27(H), the signal 518 5_j input to the wiring 5085_j, the signal 5185_j+1 input to the wiring 5085_j+1, the signal 5184-1_ i input to the wiring 5084-1_i, the signal 5184-2_i input to the wiring 5084-2_i, the signal 5184 -1_i+1 input to the wiring 5084-1_i+1, the signal 5184-2_i+1 input to the wiring 50 84-2_i+1, the signal 5186-1_j input to the wiring 5086-1_j, the signal 5186-2_j input to the wiring 5086-2_j are shown, the signal 5186-1_j+1 input to the wiring 5086-1_j+1, and the signal 5186-2 _j+1 input to the wiring 5086-2_j+1.

[0349] By combining the pixel of the present embodiment with the semiconductor device, shift register, or display device of Embodiments 1 to 7, various advantages can be obtained. For example when using a pixel having a sub-pixel structure, the number of signals required to drive the display device increases, so the number of gate lines or source lines may increase. As a result, the number of connections between the substrate on which the pixel portion is formed and the external circuit may increase significantly. However, even if the number of gate lines increases, as shown in Embodiment 5, it is possible to form the scanning line driving circuit on the same substrate as the pixel portion. Therefore, a pixel having a sub-pixel structure can be used without significantly increasing the number of connections between the substrate on which the pixel portion is formed and the external circuit. Or, the source Even if the number of S lines increases, by using the signal line driving circuit of Embodiment 7, the number of source lines can be reduced. Therefore, pixels having a sub-pixel structure can be used without significantly increasing the number of connections between the substrate on which the pixel portion is formed and the external circuit.

[0350] Alternatively, when a signal is input to the capacitance line, the number of connections between the substrate on which the pixel portion is formed and the external circuit may increase significantly. Therefore, it is possible to supply a signal to the capacitance line by using the semiconductor device or the shift register of Embodiments 1 to 4. The semiconductor device or the shift register of Embodiments 1 to 4 can be formed on the same substrate as the pixel portion. Therefore, a signal can be input to the capacitance line without significantly increasing the number of connections between the substrate on which the pixel portion is formed and the external circuit.

[0351] Alternatively, when AC driving is used, t...

Claims

1. A gate driver includes a first clock signal line, a second clock signal line, a power supply line, a gate line, a first transistor, and a second transistor, One of the source electrode or drain electrode of the first transistor is always electrically connected to the first clock signal line through a first conductive layer that intersects the second clock signal line, The other of the source electrode or drain electrode of the first transistor is always electrically connected to the gate line, One of the source electrode or drain electrode of the second transistor is always electrically connected to the power supply line, The other of the source electrode or drain electrode of the second transistor is always electrically connected to the gate line, A second conductive layer having a function as the first clock signal line has a region in contact with the first conductive layer at a first contact hole, The second conductive layer has a region in contact with a third conductive layer having a region disposed above the second conductive layer at a second contact hole having a larger area in plan view than the first contact hole, The first contact hole and the second contact hole are disposed in the gate driver, A display device.

2. A gate driver includes a first clock signal line, a second clock signal line, a power supply line, a gate line, a first transistor, and a second transistor, One of the source electrode or drain electrode of the first transistor is always electrically connected to the first clock signal line through a first conductive layer that intersects the second clock signal line, The other of the source electrode or drain electrode of the first transistor is always electrically connected to the gate line, One of the source electrode or drain electrode of the second transistor is always electrically connected to the power supply line, The other of the source electrode or drain electrode of the second transistor is always electrically connected to the gate line, A second conductive layer having a function as the first clock signal line has a region in contact with the first conductive layer at a first contact hole, The second conductive layer has a region in contact with a third conductive layer having a region disposed above the second conductive layer at a second contact hole having a larger area in plan view than the first contact hole, The fourth conductive layer having the function as the second clock signal line and intersecting with the first conductive layer does not overlap with the third conductive layer. The first contact hole and the second contact hole are disposed in the gate driver. A display device.

3. In claim 2, The fourth conductive layer has a plurality of stacked conductive layers. A display device.

4. The gate driver has a first clock signal line, a second clock signal line, a power supply line, a gate line, a first transistor, and a second transistor. One of the source electrode or the drain electrode of the first transistor is always in conduction with the first clock signal line through a first conductive layer intersecting with the second clock signal line. The other of the source electrode or the drain electrode of the first transistor is always in conduction with the gate line. One of the source electrode or the drain electrode of the second transistor is always in conduction with the power supply line. The other of the source electrode or the drain electrode of the second transistor is always in conduction with the gate line. The second conductive layer having the function as the first clock signal line has a region in contact with the first conductive layer at the first contact hole. The second conductive layer has a region in contact with a third conductive layer disposed above the second conductive layer in a second contact hole having a larger area in plan view than the first contact hole. The fifth conductive layer having the function as the power supply line has a region in contact with a sixth conductive layer disposed above the fifth conductive layer in a third contact hole having a larger area in plan view than the first contact hole. The first contact hole, the second contact hole, and the third contact hole are disposed in the gate driver. A display device.

5. The gate driver has a first clock signal line, a second clock signal line, a power supply line, a gate line, a first transistor, and a second transistor. One of the source electrode or the drain electrode of the first transistor is always in conduction with the first clock signal line through a first conductive layer intersecting with the second clock signal line. The other of the source electrode or the drain electrode of the first transistor is always in conduction with the gate line. One of the source electrode or the drain electrode of the second transistor is always in conduction with the power supply line. The other of the source electrode or the drain electrode of the second transistor is always in conduction with the gate line. The second conductive layer having a function as the first clock signal line has a region in contact with the first conductive layer at the first contact hole. The second conductive layer has a region in contact with a third conductive layer having a region disposed above the second conductive layer in a second contact hole having a larger area in plan view than the first contact hole. The fourth conductive layer having a function as the second clock signal line and intersecting the first conductive layer does not have an overlap with the third conductive layer. The fifth conductive layer having a function as the power supply line has a region in contact with a sixth conductive layer disposed above the fifth conductive layer in a third contact hole having a larger area in plan view than the first contact hole. The first contact hole, the second contact hole, and the third contact hole are disposed in the gate driver. A display device.

6. In claim 5, The fourth conductive layer has a plurality of stacked conductive layers. A display device.

7. In any one of claims 4 to 6, The fifth conductive layer has a plurality of stacked conductive layers. A display device.

8. In any one of claims 4 to 7, The sixth conductive layer has a plurality of stacked conductive layers. A display device.

9. In any one of claims 1 to 8, The gate line is always in conduction with the gate of the transistor included in the pixel. A display device.

10. In any one of claims 1 to 8, The second conductive layer has a region extending along a first direction. The third conductive layer has a region extending along the first direction. A display device.

11. In any one of claims 1 to 10, The second conductive layer has a plurality of stacked conductive layers. A display device.

12. In any one of claims 1 to 11, The third conductive layer has a plurality of stacked conductive layers. A display device.

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