Communication system and FPGA

Abstract

To achieve both high-speed data communication processing and reduced wiring.SOLUTION: A communication system 1 includes a plurality of nodes (2) communicatively connected via a network 6, and each of the node includes an FPGA 7. At least one of the FPGAs 7 includes a CPU unit 8 and at least one logic unit 9. The logic unit 9 includes a communication logic unit 9B configured to receive data from the network 6 and transmit data to the network 6. The communication logic unit 9B is configured to selectively transmit data to the network 6 without going through the CPU unit 8, and selectively send data to the CPU unit 8.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a communication system and an FPGA (field-programmable gate array: integrated circuit).

Background Art

[0002] Conventionally, a communication system including a master node and a plurality of slave nodes controlled by the master node, and performing data communication between the master node and each slave node is known (for example, Patent Documents 1 and 2).

[0003] In the communication system of Patent Document 1, each node is connected to other nodes by a two-wire bus, and each slave node is communicably connected to one or more peripheral devices, configured to read data from the peripheral devices and / or write data thereto. Each node includes a node transceiver including a control circuit, and the transmission and reception operations of the node transceiver are controlled by the control circuit.

[0004] In the communication system of Patent Document 2, each node (control unit (master), slider unit (first slave), head unit (second slave)) is connected to other nodes by a LAN cable compliant with the Ethernet communication standard. Each slave node has a CPU, and the CPU executes processing of signals input and output in various elements attached to the slave node.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the above prior art, the transmission and reception processing of data and signals in the master node and slave nodes is performed by a control circuit or a CPU. Therefore, the time required for data communication processing is long, and data communication cannot be performed in a short cycle. In order to process the transmission and reception of predetermined data that needs to be communicated in a short cycle, a board without a CPU may be separately prepared, and a dedicated communication line for performing data communication in a shorter cycle may be provided separately from the communication line for performing data communication in a normal cycle. This makes it possible to shorten the transmission and reception processing for predetermined data and communicate in a short cycle. However, with such a configuration, since the number of boards and communication lines increases, it becomes difficult to apply the communication system to a device such as a small robot where the wiring space inside the housing is small.

[0007] In view of the above background, an object of the present invention is to provide a communication system and an FPGA that can achieve both high-speed data communication processing and wiring reduction.

Means for Solving the Problem

[0008] A certain aspect of the present invention for solving the above problems is a communication system (1) having a plurality of nodes (2) communicably connected via a network (6), each node including an FPGA (7), at least one of the FPGAs including a CPU section (8) and at least one logic section (9), the logic section including a communication logic section (9B) configured to receive data from the network and transmit data to the network, the communication logic section being configured to selectively transmit data to the network without passing through the CPU section and selectively send data to the CPU section.

[0009] According to this aspect, since the communication logic section selectively transmits data to the network without passing through the CPU section, the time required for data transmission and reception processing is shortened, enabling high-speed data communication processing. Also, since high-speed data communication processing is possible, there is no need to separately provide a dedicated line for high-speed communication, and wiring reduction is possible.

[0010] In the communication system of the above aspect, it is preferable that the communication logic unit is configured to transmit data generated aperiodically to the network via the CPU unit.

[0011] According to this aspect, the aperiodically generated data that needs to be processed by the CPU unit is transmitted to the network after being processed by the CPU unit.

[0012] In the communication system of the above aspect, it is preferable that the communication logic unit is configured to transmit data generated periodically to the network without passing through the CPU unit.

[0013] According to this aspect, the periodically generated data that does not need to be processed by the CPU unit is received and transmitted in a short time.

[0014] In the communication system of the above aspect, it is preferable that the node includes a master node (2M) and a plurality of slave nodes (2S), and the FPGA of the master node includes the communication logic unit.

[0015] According to this aspect, the data communicated between the slave nodes is received and transmitted in a short time without being processed by the CPU unit of the master node when passing through the master node.

[0016] In the communication system of the above aspect, it is preferable that at least one of the FPGAs includes a plurality of the logic units (9), and the communication logic unit is configured to communicate selectively with another one (9A, 9C) of the logic units without passing through the CPU unit.

[0017] According to this aspect, the communication logic unit provided in one FPGA communicates with other logic units without going through the CPU unit, thereby reducing the time required for data transmission and reception processing within the FPGA and enabling high-speed data communication processing. Further, since high-speed data communication processing becomes possible, in order for this FPGA to communicate with other FPGAs at high speed, there is no need to separately provide a dedicated line for high-speed communication in addition to a normal communication line, and wiring can be saved.

[0018] In order to solve the above problems, an aspect of the present invention is an FPGA (7) including a CPU unit (8) and a plurality of logic units (9), wherein the logic unit includes a communication logic unit (9B) capable of receiving data from a network and transmitting data to the network, and the communication logic unit and another one (9A, 9C) of the logic units are configured to communicate selectively without going through the CPU unit.

[0019] According to this aspect, the communication logic unit and other logic units communicate without going through the CPU unit, thereby reducing the time required for data transmission and reception processing within the FPGA and enabling high-speed data communication processing. Further, since high-speed data communication processing becomes possible, when the FPGA communicates with an external device, there is no need to separately provide a dedicated line for high-speed communication in addition to a normal communication line, and wiring can be saved.

[0020] In the FPGA according to the above aspect, it is preferable that the communication logic unit is configured to communicate data generated aperiodically with another one of the logic units via the CPU unit.

[0021] According to this aspect, aperiodically generated data that requires processing by the CPU unit is transmitted to the network after being processed by the CPU unit.

[0022] In the FPGA according to the above aspect, it is preferable that the communication logic unit is configured to communicate data generated periodically with another one of the logic units without going through the CPU unit.

[0023] According to this aspect, data that is periodically generated and does not require processing by the CPU unit is received and transmitted in a short time. This enables high-speed communication processing of data.

Advantages of the Invention

[0024] According to the above aspects, it is possible to provide a communication system and an FPGA that can achieve both high-speed communication processing of data and wiring reduction.

Brief Description of the Drawings

[0025]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Modes for Carrying Out the Invention

[0026] Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings.

[0027] ≪First Embodiment≫ First, the first embodiment of the present invention will be described with reference to FIGS. 1 to 8. FIG. 1 is a schematic configuration diagram of a communication system 1 according to the first embodiment. As shown in FIG. 1, the communication system 1 includes one node constituting a master unit 2M, a plurality of units 2 (nodes) each constituting a slave unit 2S (2S1, 2S2), and a network 6 composed of communication lines connecting these units 2. The master unit 2M means a master node, and the slave unit 2S means a slave node.

[0028] The network 6 is a ring-type network that connects a plurality of units 2 in a ring shape by communication lines, and data is transmitted in one direction on the communication lines. That is, the plurality of units 2 are communicably connected in a ring shape and are communicably connected via a ring-type network 6 that communicates in one direction of the ring. In the present embodiment, for simplicity, the communication system 1 has two slave units 2S, but the communication system 1 may have three or more slave units 2S.

[0029] Note that the ring-type network 6 means a logical communication configuration and does not necessarily have a physical ring-type configuration. In addition, being communicably connected includes not only those physically connected via communication lines but also those wirelessly connected.

[0030] Each slave unit 2S includes an FPGA 7 (field-programmable gate array: integrated circuit). The FPGA 7 includes a programmable logic part composed of a ROM and an SRAM (not shown). The FPGA 7 includes a CPU part 8 that realizes the function of the CPU by configuring the configuration data stored in the ROM in the logic part. The FPGA 7 also includes a plurality of logic parts 9 (9A, 9C) that realize a predetermined function by configuring the configuration data in the logic part.

[0031] Further, each slave unit 2S includes an A / D converter 13 and a motor driver 14 as hardware for realizing a predetermined function for hardware such as the sensor 11 and the motor 12.

[0032] The first slave unit 2S1 is connected to the sensor 11 via a communication line, processes the data detected by the sensor 11, and transmits it to the network 6. That is, the first slave unit 2S1 is a unit 2 that receives data from a connected external device as input data, processes the input data, and outputs it to the network 6. The first slave unit 2S1 includes an A / D converter 13 as hardware, and includes a data acquisition logic unit 9A and a communication logic unit 9B as the logic unit 9.

[0033] The second slave unit 2S2 is connected to the motor 12 via a communication line (power line), and controls the operation of the motor 12 based on the data received from the network 6. That is, the second slave unit 2S2 is a unit 2 that receives data from the network 6 as input data, processes the input data, and outputs it to an external device. The second slave unit 2S2 includes a motor driver 14 as hardware, and includes a communication logic unit 9B and a control logic unit 9C as the logic unit 9.

[0034] In the figure, various logic units 9 are simply shown as logic omitting "unit", and the data acquisition logic unit 9A is further shown as simply acquisition logic omitting "data". A system that executes a predetermined operation is configured by the communication system 1, the sensor 11, and the motor 12. The system may be an industrial robot, a humanoid robot, a mobile body, a working machine, an actuator, etc., or may be a part of them.

[0035] The master unit 2M includes an FPGA 7 having a CPU section 8 and a communication logic section 9B, and controls the overall operation of the communication system 1. The master unit 2M causes the CPU section 8 to read program data stored in the ROM, and transmits data to the network 6 in order to control the slave unit 2S so that the system executes a predetermined operation defined by the program. When receiving control command data from the master unit 2M, the slave unit 2S executes an operation according to the command.

[0036] Hereinafter, the functions or operations of each section of the FPGA 7 will be described, which means that the FPGA 7 is programmed to function or operate in that manner.

[0037] The master unit 2M and the slave unit 2S form data into a predetermined structure and transmit it to the network 6. The data is formed into the structure of a packet, for example, in the present embodiment, and is transmitted to the network 6.

[0038] FIG. 2 is a diagram showing an example of the data structure. As shown in FIG. 2, the data packet is composed of a frame including a header, a data section, a trailer, and a CRC in order from the head. The header is composed of a code, a packet start (SODP), a relay count (HOP), and a self-node ID (SID). The trailer is composed of a packet end (EODP), a free buffer size (FBC), a destination ID (DID), and a packet priority (PRI).

[0039] The data section has no limit in size (bytes), and may be configured as a single block including all the data necessary for a series of instructions, or may be limited to a predetermined size and be one of the data divided into a plurality of parts when the data necessary for a series of instructions is larger than the predetermined size. The position of the CRC is arbitrary. For example, the trailer and the CRC may be in reverse positions. Alternatively, the CRC may be omitted. That is, a normal packet is configured by adding at least a header and a trailer to the data. Such data is generated aperiodically.

[0040] Alternatively, the data packet may not include a data portion. In this case, for example, instead of the trailer having a packet priority (PRI), it may be good to have data such as pin numbers, time stamps, alive confirmation data, etc. Such data is regular and generated periodically.

[0041] The destination ID (DID) of the trailer includes information on whether the destination is the CPU section 8 or the logic section 9 in addition to the information of the destination node. For the first data (hereinafter referred to as variable data) generated aperiodically, the information of the CPU section 8 of the destination node is given to the destination ID (DID). For the second data (hereinafter referred to as regular data) generated periodically, the information of the logic section 9 of the destination node is given to the destination ID (DID). The data packet is generated by the communication logic section 9B of each FPGA 7.

[0042] Referring to FIG. 1 again, the A / D converter 13 converts the analog data detected by the sensor 11 into digital data. The motor driver 14 includes a FET (Field effect transistor), and controls the current flowing through the motor 12 by applying the command voltage supplied from the control logic section 9C of the FPGA 7 to the gate electrode. Typically, when the motor 12 is driven by the second slave unit 2S2, the detection of the sensor 11 varies.

[0043] The CPU section 8 of the master unit 2M generates command data for at least one slave unit 2S according to a program or in response to an external command. The CPU section 8 of the first slave unit 2S1 receives the detection data of the sensor 11 acquired by the data acquisition logic section 9A and treats it as transmission data for at least one unit 2, that is, generates data. The data received by the CPU section 8 from the data acquisition logic section 9A is variable data generated aperiodically.

[0044] The communication logic unit 9B receives necessary data such as data and the destination ID from the corresponding CPU unit 8, generates a data packet including the received data, and transmits the data packet to the network 6. The data received by the communication logic unit 9B from the CPU unit 8 is variable data generated aperiodically.

[0045] As will be described in detail later, the communication logic unit 9B of the first slave unit 2S1 may receive data from the data acquisition logic unit 9A. The data received by the communication logic unit 9B from the data acquisition logic unit 9A is regular data generated periodically.

[0046] The communication logic unit 9B of each FPGA 7 generates a data packet with a packet structure from the data received from the corresponding CPU unit 8 or data acquisition logic unit 9A.

[0047] The data acquisition unit of the first slave unit 2S1 is programmed to acquire the data of the sensor 11 when the value of the sensor 11 changes, and send the acquired data to the CPU unit 8 as variable data. In addition, the data acquisition unit of the first slave unit 2S1 acquires the data of the sensor 11 at a predetermined period, and sends the acquired data to the communication logic unit 9B as regular data.

[0048] The communication logic unit 9B of each FPGA 7 receives a data packet from the network 6 and identifies the destination ID of the received data packet. If the destination ID is not the local node (local unit), the communication logic unit 9B transmits the received data packet to the network 6 without going through the CPU unit 8. On the other hand, if the destination ID is the local node, the communication logic unit 9B sends the data of the received data packet to the CPU unit 8 or another logic unit 9.

[0049] When the destination ID of the received data packet is the local node (the second slave unit 2S2) and the CPU unit 8 (i.e., when the data is variable data), the communication logic unit 9B of the second slave unit 2S2 sends the data of the received data packet to the CPU unit 8. When the destination ID of the received data packet is the local node and the logic unit 9 (i.e., when the data is fixed data), the communication logic unit 9B of the second slave unit 2S2 sends the data of the received data packet to the control logic unit 9C without passing through the CPU unit 8.

[0050] Next, with reference to FIGS. 3 and 4, the data flow will be described. FIGS. 3 and 4 show the data flow when the first slave unit 2S1 acquires variable data from the sensor 11 and this data is used for controlling the motor 12.

[0051] FIG. 3 is a diagram showing the flow of variable data in the communication system 1 according to the embodiment. As shown in FIG. 3, the detection data detected by the sensor 11 is (1) input from the sensor 11 to the A / D converter 13, converted from an analog signal to a digital signal, and then (2) acquired by the data acquisition logic unit 9A. Since the detection data is variable data, (3) the data is sent from the data acquisition logic unit 9A to the CPU unit 8, processed by the CPU unit 8, and then (4) sent to the communication logic unit 9B, where it is converted into the format of a data packet. Since the detection data is variable data, the CPU unit 8 of the second slave unit 2S2 is set as the destination ID. Thereafter, the detection data in packet format is (5) sent from the communication logic unit 9B of the first slave unit 2S1 to the network 6.

[0052] The detection data transmitted to the network 6 is received by the communication logic unit 9B of the second slave unit 2S2. Since the transmission destination ID of the data packet is the own node (the second slave unit 2S2) and it is the CPU unit 8, the data received by the (6) communication logic unit 9B is sent to the CPU unit 8. After the data is processed by the CPU unit 8, it is sent to the (7) control logic unit 9C. After the data is converted into a predetermined gate voltage (an example of a control amount) by the control logic unit 9C, it is sent to the (8) motor driver 14, and after being converted into a drive current by the motor driver 14, it is supplied to the (9) motor 12.

[0053] FIG. 7 is a diagram showing the data flow of the communication system 101 according to the comparative example. In the communication system 101 according to the comparative example, data flows as follows. That is, the detection data detected by the sensor 11 is input from the (1) sensor 11 to the A / D converter 13, and after being converted from an analog signal to a digital signal, it is acquired by the (2) data acquisition logic unit 9A. The detection data is sent from the (3) data acquisition logic unit 9A to the CPU unit 8, and after being processed by the CPU unit 8, it is sent to the (4) communication logic unit 9B, and is converted into the form of a data packet in the communication logic unit 9B. The transmission destination ID of the detection data is set to the master unit 2M. Thereafter, the detection data in the packet form is transmitted from the (5) communication logic unit 9B of the first slave unit 2S1 to the network 6.

[0054] The detection data transmitted to the network 6 is received by the communication logic unit 9B of the second slave unit 2S2. The data received by the communication logic unit 9B is checked for the destination ID via the (6) CPU unit 8. Since the destination ID of the data packet is not the local node (the second slave unit 2S2), it is transmitted to the (7) master unit 2M via the network 6. The detection data transmitted to the network 6 is received by the communication logic unit 9B of the master unit 2M. In the master unit 2M, the (8) detection data is sent to the CPU unit 8. After being processed as determined by the CPU unit 8, it is sent to the (9) communication logic unit 9B, where it is converted into the format of a data packet. The second slave unit 2S2 is set as the destination ID of the detection data. Thereafter, the detection data in packet format is transmitted to the network 6 from the (10) communication logic unit 9B of the first slave unit 2S1.

[0055] The detection data transmitted to the network 6 is received by the communication logic unit 9B of the first slave unit 2S1. The data received by the communication logic unit 9B is checked for the destination ID via the (11) CPU unit 8. Since the destination ID of the data packet is not the local node (the first slave unit 2S1), it is transmitted to the (12) master unit 2M via the network 6. The detection data transmitted to the network 6 is received by the communication logic unit 9B of the second slave unit 2S2. In the second slave unit 2S2, the (13) detection data is sent to the CPU unit 8. After being processed as determined by the CPU unit 8, it is sent to the (14) control logic unit 9C. The data is converted into a predetermined gate voltage (an example of a control amount) by the control logic unit 9C, and then sent to the (15) motor driver 14. After being converted into a drive current by the motor driver 14, it is supplied to the (16) motor 12.

[0056] Returning to FIG. 3, in the present embodiment, when the base point of the ring-shaped network 6 is the master unit 2M, the first slave unit 2S1 is located upstream of the second slave unit 2S2. Therefore, the detection data of the sensor 11 is received by the second slave unit 2S2 without passing through the master unit 2M. When the first slave unit 2S1 is located downstream of the second slave unit 2S2, the detection data of the sensor 11 is received by the second slave unit 2S2 after passing through the master unit 2M.

[0057] In the master unit 2M, when the destination ID of the data packet is the own node (master unit 2M), the data is sent from the communication logic unit 9B to the CPU unit 8. On the other hand, when the destination ID of the data packet is not the own node, the data is sent from the communication logic unit 9B to the second slave unit 2S2 via the network 6 without passing through the CPU unit 8.

[0058] That is, the communication logic unit 9B selectively sends data to the network 6 without passing through the CPU unit 8 and selectively sends data to the CPU unit 8. Since the communication logic unit 9B selectively sends data to the network 6 without passing through the CPU unit 8 in this way, the time required for data transmission and reception processing is shortened, and high-speed data communication processing becomes possible. In addition, since high-speed data communication processing becomes possible, there is no need to separately provide a dedicated line for high-speed communication, and wiring can be saved. This point will be described later with reference to FIG. 6.

[0059] In particular, since the FPGA 7 of the master node includes such a communication logic unit 9B, data communicated between slave nodes is received and transmitted in a short time without being processed by the CPU unit 8 of the master node when passing through the master node.

[0060] In this embodiment, only one master unit 2M and two slave units 2S are provided on the network 6. In other embodiments of the present invention, three or more slave units 2S may be provided on the network 6. For example, when a third slave unit is provided on the downstream side of the second slave unit 2S2 and the first slave unit 2S1 transmits data having the third slave unit as the destination ID to the network 6, the data flow is as follows. The data transmitted by the communication logic unit 9B of the first slave unit 2S1 is received by the communication logic unit 9B of the second slave unit 2S2. Since the destination ID of the data is not the own node (the second slave unit 2S2), the communication logic unit 9B transmits the data to the third slave unit via the network 6 without passing through the CPU unit 8.

[0061] In this way, the communication logic unit 9B of the slave unit 2S also selectively transmits data to the network 6 without passing through the CPU unit 8 and selectively sends data to the CPU unit 8. As a result, the time required for data transmission and reception processing in the slave unit 2S is shortened.

[0062] FIG. 4 is a diagram showing the flow of regular data in the communication system 1 according to the embodiment. As shown in FIG. 4, the detection data detected by the sensor 11 is (1) input from the sensor 11 to the A / D converter 13 and converted from an analog signal to a digital signal, and then (2) acquired by the data acquisition logic unit 9A. Since the detection data is regular data, (3) it is sent from the data acquisition logic unit 9A to the communication logic unit 9B without passing through the CPU unit 8, and is converted into the form of a data packet in the communication logic unit 9B. Since the detection data is regular data, the control logic unit 9C of the second slave unit 2S2 is set as the destination ID. Thereafter, the detection data in packet form is (4) transmitted from the communication logic unit 9B of the first slave unit 2S1 to the network 6.

[0063] The detection data transmitted to the network 6 is received by the communication logic unit 9B of the second slave unit 2S2. Since the transmission destination ID of the data packet is the own node and it is the control logic unit 9C, (5) the data received by the communication logic unit 9B is sent to the control logic unit 9C without passing through the CPU unit 8. After the data is converted into a predetermined gate voltage in the control logic unit 9C, (6) it is sent to the motor driver 14, and after being converted into a drive current by the motor driver 14, (7) it is supplied to the motor 12.

[0064] When the first slave unit 2S1 is located downstream of the second slave unit 2S2 in the network 6, the detection data of the sensor 11 passes through the communication logic unit 9B of the master unit 2M. On the other hand, the detection data is transmitted to the network 6 from the communication logic unit 9B toward the second slave unit 2S2 without passing through the CPU unit 8 of the master unit 2M.

[0065] In the data acquisition logic unit 9A of the first slave unit 2S1, in the example of FIG. 3, the data is sent to the CPU unit 8, and in the example of FIG. 4, the data is transmitted to the network 6 without passing through the CPU unit 8. That is, the communication logic unit 9B of the first slave unit 2S1 selectively transmits the data to the network 6 without passing through the CPU unit 8 and selectively sends the data to the CPU unit 8. This also shortens the time required for the data transmission and reception process for the regular data, enabling high-speed data communication processing.

[0066] Also, in the first slave unit 2S1, the data acquisition logic unit 9A sends the regular data to the communication logic unit 9B without passing through the CPU unit 8 and sends the variable data to the communication logic unit 9B through the CPU unit 8. That is, the data acquisition logic unit 9A and the communication logic unit 9B are configured to communicate selectively without passing through the CPU unit 8.

[0067] Also, the communication logic unit 9B of the second slave unit 2S2 sends fixed data to the control logic unit 9C without going through the CPU unit 8, and sends variable data to the control logic unit 9C through the CPU unit 8. That is, the communication logic unit 9B and the control logic unit 9C are configured to communicate selectively without going through the CPU unit 8.

[0068] In this way, the communication logic unit 9B transmits the variable data generated aperiodically to the network 6 through the CPU unit 8. That is, the aperiodically generated data that needs to be processed by the CPU unit 8 is transmitted to the network 6 after being processed by the CPU unit 8.

[0069] Also, the communication logic unit 9B transmits the fixed data generated periodically to the network 6 without going through the CPU unit 8. That is, the periodically generated data that does not need to be processed by the CPU unit 8 is received and transmitted in a short time.

[0070] In this way, in one FPGA 7, since the two logic units 9 are configured to communicate selectively without going through the CPU unit 8, the time required for data transmission and reception processing within the FPGA 7 is shortened, and high-speed data communication processing becomes possible. Also, since high-speed data communication processing becomes possible, when the FPGA 7 communicates with an external device, there is no need to separately provide a dedicated line for high-speed communication in addition to the normal communication line, and wiring can be saved.

[0071] FIG. 8 is a time chart showing the data flow by the communication system 101 according to the comparative example. In the conventional communication system 101 according to the comparative example, the communication logic unit 9B of the master unit 2M transmits operation request data (described as Act request in the figure) that requests a predetermined operation such as a data transmission request to the logic unit 9 of each slave unit 2S. The CPU unit 8 of each slave unit 2S that has received the operation request data generates operation data (described as Act in the figure) such as drive data of the motor 12 and detection data of the sensor 11, and transmits the generated operation data to the CPU unit 8 of the master unit 2M. The CPU unit 8 of the master unit 2M processes the received operation data.

[0072] Also, the CPU unit 8 of the master unit 2M generates predetermined control command data (described as Cmd in the figure), which is variable data, according to the software, and transmits the generated control command data to the logic unit 9 of each slave unit 2S. The CPU unit 8 of each slave unit 2S that has received the control command data performs processing according to the control command. The processing in the CPU unit 8 requires a longer time than the processing in the logic unit 9. Therefore, there is a lot of processing in the CPU unit 8 of each unit, and the data processing efficiency of the entire communication system 101 is not high.

[0073] FIG. 5 is a time chart showing the data flow by the communication system 1 according to the embodiment. As shown in FIG. 5, the communication logic unit 9B of the master unit 2M transmits operation request data (described as Act request in the figure) that requests a predetermined operation such as a data transmission request to the logic unit 9 of each slave unit 2S. Also, the communication logic unit 9B of the master unit 2M periodically transmits fixed-form data (described as Common in the figure) to each slave unit 2S. The logic unit 9 of the slave unit 2S that has received it transmits predetermined fixed-form data in response thereto, such as a time stamp and alive confirmation data, to the logic unit 9 of the master unit 2M. Since these data communications are performed between logics, the processing load on the FPGA 7 is low, and the time required for data generation, transmission, and reception processing is short.

[0074] The CPU unit 8 of the master unit 2M generates predetermined control command data (denoted as Cmd in the figure), which is variable data, according to software, and transmits the generated control command data to the CPU unit 8 of the first slave unit 2S1 that drives the motor 12. The CPU unit 8 of the first slave unit 2S1 that has received the control command data performs processing according to the control command. Also, after driving the motor 12 based on the control command, the CPU unit 8 of the first slave unit 2S1 generates operation data of the motor 12 (denoted as Act in the figure) and transmits the generated operation data to the CPU unit 8 of the master unit 2M. The CPU unit 8 of the master unit 2M processes the received operation data. The processing in the CPU unit 8 requires a longer time compared to the processing in the logic unit 9.

[0075] On the other hand, in the second slave unit 2S2 that acquires the detection data of the sensor 11, when there is no change in the value of the sensor 11, the master unit 2M does not need to receive operation data (denoted as Act in the figure) including the detection data of the sensor 11. That is, it is sufficient to receive the operation data when there is a change in the value of the sensor 11. Therefore, the CPU unit 8 of the second slave unit 2S2 is configured not to send the operation data of the sensor 11 when there is no change in the value of the sensor 11, and to send the operation data when there is a change in the value of the sensor 11. That is, the CPU unit 8 of the second slave unit 2S2 is programmed to operate in an event-driven manner that operates when an event occurs. As a result, in addition to reducing the processing of the CPU unit 8 of the second slave unit 2S2, the processing of the CPU unit 8 of the master unit 2M is also reduced. Thereby, it is possible to improve the data processing efficiency of the entire communication system 1. Also, even if more slave units 2S are provided on the network 6, it is suppressed that the processing amount of the CPU unit 8 of the master unit 2M reaches the limit.

[0076] FIG. 6 is an explanatory diagram for explaining the effects of the communication system 1, where (A) shows the present invention and (B) shows a comparative example. Note that FIG. 6 shows an example in which the communication systems 1 and 101 are applied to a robotic arm, and the X-axis and Y-axis represent the joints of the robotic arm.

[0077] As shown in FIG. 6(B), in the conventional communication system 101 according to the comparative example, the master unit 2M, the first slave unit 2S1, and the second slave unit 2S2 are connected to each other by a ring-shaped network 6. Data communication is performed at a predetermined control cycle (for example, 1 ms). In addition, separately from these units 2, a dedicated short-cycle substrate 107 is prepared to communicate and process the detection data of the sensor 11 that should perform data communication at a shorter control cycle (for example, 50 μs). This substrate 107 was connected to other units 2 by a dedicated communication line 106 separate from the ring-shaped network 6.

[0078] On the other hand, in the present invention, high-speed data communication processing becomes possible, and the data processing efficiency of the entire communication system 1 is improved. As a result, as shown in FIG. 6(A), the second slave unit 2S2 undertakes the function of the short-cycle substrate 107, and it becomes possible to perform data communication processing using only the ring-shaped network 6. Thereby, it is not necessary to separately provide a dedicated communication line 106 for high-speed communication, and wiring reduction becomes possible.

[0079] ≪Second Embodiment≫ Next, a second embodiment of the present invention will be described with reference to FIG. 9. Note that the same or similar elements as those in the first embodiment are denoted by the same reference numerals, and redundant descriptions are omitted. The same applies to the following embodiments.

[0080] FIG. 9 is a schematic configuration diagram of the communication system 1 according to the second embodiment. As shown in FIG. 9, in the communication system 1 of the present embodiment, the FPGA 7 of the master unit 2M includes a plurality of communication logic units 9B. Hereinafter, these communication logics are referred to as a first communication logic unit 9B1 and a second communication logic unit 9B2.

[0081] The first communication logic unit 9B1 is communicably connected to a plurality of slave units 2S by a ring-type network 6 and constitutes a first segment. Although not shown, the second communication logic unit 9B2 is communicably connected to a plurality of slave units 2S by a ring-type network 6 and constitutes a second segment having the same configuration as the first segment.

[0082] In other embodiments, the FPGA 7 of the master unit 2M may include three or more communication logics, and the communication system 1 may include three or more segments by a ring-type network 6.

[0083] The first slave unit 2S1 includes a plurality of A / D converters 13 and acquires detection data of a plurality of sensors 11. Correspondingly, the FPGA 7 of the first slave unit 2S1 includes a plurality of data acquisition logic units 9A. Hereinafter, these data acquisition logics are referred to as a first data acquisition logic and a second data acquisition logic unit 9A2. The FPGA 7 of the first slave unit 2S1 includes one communication logic unit 9B, but may include a plurality of communication logic units 9B as in the master unit 2M.

[0084] The second data acquisition logic unit 9A2 of the first slave unit 2S1 sends the detection data of the sensor 11 received from the A / D converter 13 to the communication logic unit 9B without passing through the CPU unit 8. The first data acquisition logic unit 9A1 sends the variable data among the detection data of the sensor 11 received from the A / D converter 13 to the CPU unit 8 and sends the fixed data to the communication logic unit 9B. Thus, the communication logic unit 9B of the first slave unit 2S1 selectively transmits data to the network 6 without passing through the CPU unit 8 and selectively transmits data to the network 6 through the CPU unit 8. Also, the first data acquisition logic unit 9A1 of the first slave unit 2S1 selectively communicates with the communication logic unit 9B without passing through the CPU unit 8.

[0085] By configuring the FPGA 7 of the first slave unit 2S1 in this way, the time required for data transmission and reception processing is shortened, enabling high-speed data communication processing.

[0086] The first communication logic unit 9B1 and the second communication logic unit 9B2 of the master unit 2M communicate with the CPU unit 8. Also, the first communication logic unit 9B1 and the second communication logic unit 9B2 communicate with each other selectively without going through the CPU unit 8. As a result, the time required for data transmission and reception processing within the FPGA 7 is shortened, enabling high-speed data communication processing.

[0087] <<Third Embodiment>> Next, a third embodiment of the present invention will be described with reference to FIG. 10. FIG. 10 is a schematic configuration diagram of a communication system 1 according to the third embodiment. As shown in FIG. 10, the communication system 1 of this embodiment is common to the second embodiment in that the FPGA 7 of the master unit 2M includes a plurality of communication logic units 9B. On the other hand, the first slave unit 2S1 has the same configuration as that of the first embodiment and operates in the same manner as the first embodiment.

[0088] The first communication logic unit 9B1 and the second communication logic unit 9B2 of the master unit 2M selectively communicate with the CPU unit 8 and selectively communicate with each other without going through the CPU unit 8. The first communication logic unit 9B1 and the second communication logic unit 9B2, for example, send out the regular data received from the corresponding slave unit 2S to each other without going through the CPU unit 8, and send the variable data received from the corresponding slave unit 2S to the CPU unit 8. As a result, the time required for data transmission and reception processing within the FPGA 7 is shortened, enabling high-speed data communication processing.

[0089] With the above description of the specific embodiments completed, the present invention is not limited to the above embodiments and modifications, and can be widely modified and implemented. For example, the number of slave units 2S and the types of hardware are not limited to those described above. In addition, the specific configurations, arrangements, quantities, etc. of each member and part can be appropriately changed without departing from the spirit of the present invention. Also, some or all of the configurations of the above embodiments may be combined with each other. On the other hand, not all of the components shown in the above embodiments are necessarily essential, and they can be appropriately selected.

Explanation of Reference Numerals

[0090] 1: Communication system 2: Unit (node) 2M: Master unit (master node) 2S: Slave unit (slave node) 2S1: First slave unit 2S2: Second slave unit 6: Network 7: FPGA 8: CPU section 9: Logic section 9A: Data acquisition logic section 9A1: First data acquisition logic section 9A2: Second data acquisition logic section 9B: Communication logic section 9B1: First communication logic section 9B2: Second communication logic section 9C: Control logic section

Claims

1. A communication system having a plurality of nodes communicably connected via a network, each node including an FPGA, at least one of the FPGAs including a CPU section and at least one logic section, the logic section including a communication logic section configured to receive data from the network and transmit data to the network, the communication logic section being configured to transmit data to the network selectively without passing through the CPU section and to selectively send data to the CPU section, a communication system.

2. The communication system according to claim 1, wherein the communication logic section is configured to transmit data generated aperiodically to the network via the CPU section.

3. The communication system according to claim 1, wherein the communication logic section is configured to transmit data generated periodically to the network without passing through the CPU section.

4. the nodes including a master node and a plurality of slave nodes, the FPGA of the master node including the communication logic section, the communication system according to any one of claims 1 to 3.

5. at least one of the FPGAs including a plurality of the logic sections, the communication logic section being configured to communicate selectively with another one of the logic sections without passing through the CPU section, the communication system according to any one of claims 1 to 3.

6. An FPGA including a CPU section and a plurality of logic sections, the logic section including a communication logic section capable of receiving data from a network and transmitting data to the network, the communication logic section and another one of the logic sections being configured to communicate selectively without passing through the CPU section, an FPGA.

7. The FPGA according to claim 6, wherein the communication logic section is configured to communicate data generated aperiodically with another one of the logic sections via the CPU section.

8. The FPGA according to claim 6 or 7, wherein the communication logic section is configured to communicate data generated periodically with another one of the logic sections without passing through the CPU section.

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