Imaging apparatus

Abstract

To provide an imaging apparatus having an image processing function and capable of high-speed operation.SOLUTION: In an imaging apparatus having an additional function such as image processing, image data acquired in an imaging operation is binarized in a pixel unit, and product-sum operation is performed by using the binarized data. A memory circuit is provided in the pixel portion, and holds a weighting coefficient used for the product-sum operation. Therefore, the calculation can be performed without reading the weighting coefficient from the outside every time, and the power consumption can be reduced. In addition, by laminating the pixel circuit, the memory circuit, and the like, the product-sum operation circuit, and the like, the wiring length between the circuits can be reduced, and low-power consumption operation and high-speed operation can be performed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, an operation method thereof, or a manufacturing method thereof.

[0003] Note that in this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a storage device, a display device, an imaging device, and an electronic device may include a semiconductor device.

Background Art

[0004] Techniques for configuring a transistor using an oxide semiconductor thin film formed on a substrate have attracted attention. For example, Patent Document 1 discloses an imaging device configured to use a transistor having an extremely low off-current with an oxide semiconductor in a pixel circuit.

[0005] In addition, Patent Document 2 discloses a technique for adding an arithmetic function to an imaging device.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] In imaging devices mounted on mobile devices and the like, the function of being able to acquire high-resolution images has become widespread. In the next generation, it is required to further equip imaging devices with more intelligent functions.

[0008] Image data (analog data) acquired by an imaging device is converted into digital data, and after being taken out externally, image processing is performed as needed. If such processing can be performed within the imaging device, the cooperation with external devices will be faster, and the convenience for the user will be improved. Also, the load and power consumption of peripheral devices and the like can be reduced.

[0009] In addition, when imparting functions to an imaging device, it is preferable to stack elements such as increasing circuits. For example, by providing a plurality of circuits so as to overlap the pixel circuit, an increase in area can be suppressed, and a highly functional and small-sized imaging device can be formed. Also, between the stacked circuits, the wiring length can be shortened, and high-speed and low-power consumption operation can be realized.

[0010] Therefore, one of the objects of one aspect of the present invention is to provide an imaging device capable of performing image processing. Or, one of the objects is to provide a highly functional and small-sized imaging device. Or, one of the objects is to provide an imaging device capable of performing high-speed operation. Or, one of the objects is to provide an imaging device with low power consumption. Or, one of the objects is to provide a highly reliable imaging device. Or, one of the objects is to provide a novel imaging device or the like. Or, one of the objects is to provide a driving method for the above imaging device. Or, one of the objects is to provide a novel semiconductor device or the like.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not necessarily have to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0012] One aspect of the present invention relates to an imaging device having an image processing function and capable of high-speed operation.

[0013] One aspect of the present invention is an imaging device having a plurality of pixel blocks, wherein each pixel block has a first layer and a second layer, the first layer has an area overlapping with the second layer, the pixel block has a plurality of pixel circuits and a plurality of first storage circuits in the first layer, and a plurality of product-sum operation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer, and the pixel circuits and the first storage circuits are imaging devices having transistors having metal oxides in the channel formation region.

[0014] Another aspect of the present invention is an imaging device having a plurality of pixel blocks, wherein each pixel block has a first layer, a second layer, and a third layer, the first layer is located between the second layer and the third layer, or the third layer is located between the first layer and the second layer, the first to third layers have areas overlapping with each other, the pixel block has a plurality of pixel circuits in the first layer, a plurality of product-sum operation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer, and a plurality of first storage circuits in the third layer, and the pixel circuits and the first storage circuits are imaging devices having transistors having metal oxides in the channel formation region.

[0015] The product-sum operation circuit, the first binarization circuit, and the second binarization circuit preferably have transistors having silicon in the channel formation region.

[0016] The number of pixel circuits is the same as that of the first binarization circuits, and a pixel circuit can be electrically connected to one first binarization circuit.

[0017] One first binarization circuit can be electrically connected to a plurality of product-sum operation circuits.

[0018] One first memory circuit can be electrically connected to a plurality of product-sum operation circuits.

[0019] The number of product-sum operation circuits is the same as that of the second binarization circuits, and one product-sum operation circuit can be electrically connected to one second binarization circuit.

[0020] The drive circuit of the pixel circuit and the drive circuit of the first memory circuit can be provided in the second layer.

[0021] Furthermore, it may have a second memory circuit, the input terminal of the second memory circuit is electrically connected to a plurality of second binarization circuits, and the output terminal of the second memory circuit is electrically connected to a plurality of product-sum operation circuits.

[0022] Furthermore, it may have a third memory circuit and a third binarization circuit, and the third memory circuit may be electrically connected to a plurality of product-sum operation circuits via the third binarization circuit.

[0023] The second memory circuit, the third memory circuit, and the third binarization circuit can be provided in the second layer.

[0024] The metal oxide preferably has In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0025] The first memory circuit has memory cells, and the memory cells may have capacitors having ferroelectric layers.

Advantages of the Invention

[0026] By using one aspect of the present invention, it is possible to provide an imaging device capable of performing image processing. Or, it is possible to provide a highly functional and compact imaging device. Or, it is possible to provide an imaging device capable of high-speed operation. Or, it is possible to provide an imaging device with low power consumption. Or, it is possible to provide a highly reliable imaging device. Or, it is possible to provide a novel imaging device or the like. Or, it is possible to provide a driving method for the above imaging device. Or, it is possible to provide a novel semiconductor device or the like.

Brief Description of the Drawings

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[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used between different drawings for the same part or parts having the same function, and the repeated description thereof may be omitted. Note that the hatching of the same elements constituting the drawings may be appropriately omitted or changed between different drawings.

[0029] Also, even if an element is shown as a single element on a circuit diagram, the element may be composed of a plurality of elements as long as there is no functional inconvenience. For example, transistors operating as switches may be connected in series or in parallel in some cases. Also, a capacitor may be divided and arranged at a plurality of positions.

[0030] Also, one conductor may have a plurality of functions such as wiring, electrodes, and terminals, and in this specification, a plurality of names may be used for the same element. Also, even if the elements are shown as being directly connected on a circuit diagram, actually, the elements may be connected via one or a plurality of conductors, and such a configuration is also included in the category of direct connection in this specification.

[0031] (Embodiment 1) In this embodiment, an imaging device, which is an aspect of the present invention, will be described with reference to the drawings.

[0032] One aspect of the present invention is an imaging device having additional functions such as image processing. The imaging device binarizes analog data (image data) acquired in an imaging operation in a pixel unit, and performs a sum-of-products operation using the binarized data. A storage circuit is provided in the pixel unit to hold weight coefficients (also called weight data or filters) used in the sum-of-products operation. Therefore, the operation can be performed without repeatedly reading the weight coefficients from the outside, and power consumption can be reduced.

[0033] Also, in the imaging device according to one aspect of the present invention, by laminating a pixel circuit, a storage circuit, etc. and a sum-of-products operation circuit, etc., the wiring length between circuits can be shortened, and low-power consumption operation and high-speed operation can be performed. In addition, a highly functional and compact imaging device can be provided.

[0034] <Imaging Device> FIG. 1 is a perspective view for explaining an imaging device according to one aspect of the present invention. The imaging device has a layer 10 and a layer 20. The layer 10 can be provided on the layer 20. The imaging device has a pixel unit 11 in which a pixel circuit, a storage circuit, etc. are provided. The pixel unit 11 has elements provided in the layer 10 and elements provided in the layer 20.

[0035] A pixel circuit and a storage circuit can be provided in the layer 10. In the layer 20, a drive circuit for the circuits included in the layer 10, an arithmetic circuit for data acquired by the circuits included in the layer 10, a data conversion circuit, a storage circuit, etc. can be provided. For example, in the layer 20, an arithmetic unit 21, a load driver 31 and a column driver 32 for driving the pixel circuit, a load driver 33 and a column driver 34 for driving the storage circuit, etc. can be provided. Also, in the layer 20, circuits 35, 36, etc. having a data selection function, a holding function, a conversion function, a readout function, etc. may be provided as necessary.

[0036] The circuit in layer 10 and the circuit in layer 20 can be electrically connected by electrodes, wirings, etc. that penetrate layer 10. Note that some of the above-described circuits can also be provided in a layer opposite to the above description or outside the imaging device.

[0037] FIG. 2A is a diagram for explaining the details of the pixel section 11. The pixel section 11 has a plurality of pixel blocks 12 arranged in a matrix. Further, the pixel block 12 has 3×3 pixel blocks 13. Further, the pixel block 13 has 3×3 pixels 14. That is, the pixel block 12 has 9×9 pixels 14. The pixel 14 has a pixel circuit 15 and a memory circuit 16.

[0038] In one aspect of the present invention, various operations and the like are performed on the premise that the pixel block 13 has 3×3 pixels 14, but the number of pixels is not limited to the above, and for example, it can be 2×2, 4×4, 5×5, 25×25, etc. Alternatively, the number of pixels 14 in the horizontal direction and the vertical direction may be different. Also, some of the pixel blocks 13 can be shared by adjacent pixel blocks 12. Also, some of the pixels 14 can be shared by adjacent pixel blocks 13. Note that the number of pixel blocks 13 included in the pixel block 12 can also be changed as appropriate.

[0039] The pixel 14 shown in FIG. 2A is an example in which the pixel circuit 15 and the memory circuit 16 are arranged side by side in layer 10, but as shown in FIG. 2B, the pixel circuit 15 may be provided on top of the memory circuit 16. Alternatively, as shown in FIG. 2C, the memory circuit 16 may be provided on top of the pixel circuit 15.

[0040] FIG. 3 is a diagram for explaining the components of the pixel block 13. The pixel block 13 has 3×3 pixels 14. Therefore, the pixel block 13 has nine pixel circuits 15 and nine memory circuits 16 in layer 10. Also, in a region (layer 20) overlapping with the pixel circuit 15 or the memory circuit 16, a plurality of binarization circuits 22, a plurality of product-sum operation circuits 23, and a plurality of binarization circuits 24 are provided as the operation unit 21.

[0041] The binarization circuits 22 are provided in the same number as the pixel circuits 15, that is, nine. The binarization circuits 22 are provided at positions having an area overlapping with the pixel circuits 15. FIG. 4 is a diagram showing the connection relationship between the pixel circuits 15 and the binarization circuits 22. One pixel circuit 15 is electrically connected to one binarization circuit 22 having an overlapping area.

[0042] The binarization circuit 22 is a circuit that determines and binarizes the image data (analog data) acquired by the pixel circuit 15 with a preset threshold value. For example, a comparator can be used.

[0043] A plurality of product-sum operation circuits 23 are provided in one pixel block 13. In this embodiment, an example of providing six product-sum operation circuits 23 is shown. Note that the number of product-sum operation circuits 23 can be appropriately increased or decreased according to the purpose. The input terminals of the product-sum operation circuits 23 are electrically connected to the storage circuit 16 and the binarization circuits 22.

[0044] FIG. 5 is a diagram showing the connection relationship between the product-sum operation circuit 23, the storage circuit 16, and the binarization circuit 22. Note that, in order to clearly show the connection relationship, nine binarization circuits 22 are extracted and illustrated.

[0045] The pixel block 13 has nine storage circuits 16, each of which has a plurality of memory cells. A 1-bit weight coefficient can be written in advance in each of the plurality of memory cells. Each of the nine storage circuits 16 is electrically connected to each of the six product-sum operation circuits 23. Therefore, a 9-bit weight coefficient can be supplied to each of the product-sum operation circuits 23. Since a weight coefficient can be supplied from one storage circuit 16 to six product-sum operation circuits 23, here, as long as at least 1 bit of weight coefficient is written in one storage circuit 16, this operation can be performed.

[0046] Each of the binarization circuits 22 can output image data converted into 1 bit. Each of the nine binarization circuits 22 is electrically connected to each of the six multiplication-and-addition circuits 23. Since image data can be supplied from one binarization circuit 22 to the six multiplication-and-addition circuits 23, 9-bit image data is supplied to each of the multiplication-and-addition circuits 23.

[0047] FIG. 6A is a diagram for briefly explaining the configuration and operation of the multiplication-and-addition circuit 23. The multiplication-and-addition circuit 23 can be configured to have, for example, nine multipliers 23a and one adder 23b. Each multiplier 23a receives the image data (X1 to X9) converted into 1 bit by the binarization circuit 22 and the 1-bit weight coefficients (W1 to W9) read from the storage circuit 16, performs a multiplication operation, and outputs 1-bit data to the adder 23b. The adder 23b adds the data input from each multiplier 23a and outputs the result to the binarization circuit 24. Here, since the data output from the adder 23b (multiplication-and-addition circuit 23) takes values from 0 to 9, it becomes 4-bit data.

[0048] FIG. 6B is a diagram for explaining the binarization circuit 24. Six binarization circuits 24, which is the same number as the multiplication-and-addition circuits 23, are provided. Also, as shown in FIGS. 6A, 6B, and 7, one binarization circuit 24 is electrically connected to one multiplication-and-addition circuit 23. As shown in FIGS. 6A and 6B, the data input to the binarization circuit 24 is 4-bit digital data corresponding to 0 to 9. The binarization circuit 24 outputs 1 when it determines that the input data is 5 or more, and outputs 0 when it determines that the input data is 4 or less. That is, the binarization circuit 24 is a circuit having a function of converting 4-bit data into 1 bit.

[0049] Also, as shown in FIG. 7, 6-bit operation data can be output from one pixel block 13. FIG. 8 is a diagram for explaining the reading of the operation data from the pixel block 12 (pixel blocks 13[1,1] to 13[3,3]).

[0050] The six binarization circuits 24 included in the pixel block 13 each have a selection transistor 24S that controls the output. The gates of the six selection transistors 24S are electrically connected to a wiring RSEL (wiring RSEL[0], wiring RSEL[1], wiring RSEL[2]). The wiring RSEL is shared by the pixel blocks 13 provided in the row direction. Also, the six output lines OUT (OUT[0] to OUT[5]) to which the six binarization circuits 24 are electrically connected are shared by the pixel blocks 13 provided in the column direction.

[0051] A readout circuit 40 is electrically connected to the six output lines OUT. The readout circuit 40 has switches 40S, 41S, and 42S that are respectively electrically connected to the six output lines OUT of each column.

[0052] The switches 40S to 42S each have a plurality of transistors. The gate of the transistor included in the switch 40S is electrically connected to the wiring CSEL[0]. The gate of the transistor included in the switch 41S is electrically connected to the wiring CSEL[1]. The gate of the transistor included in the switch 42S is electrically connected to the wiring CSEL[2].

[0053] The output-side wirings of the switches 40S to 42S are electrically connected to one output line OUT for every three. With such a configuration, it is possible to output data for each pixel block 13.

[0054] Note that the readout circuit 40 can be provided in the layer 20 as an element of the circuit 35 or the circuit 36 shown in FIG. 1.

[0055] FIG. 9 is a timing chart for explaining the reading of operation data from pixel blocks 12 (pixel blocks 13[1,1] to 13[3,3]). It is assumed that all operations in each pixel block 13 are completed before time T1, and the operation data is held in the binarization circuit 24. In the following description, the potential (high potential) that makes the transistor conductive is expressed as "H", and the potential (low potential) that makes the transistor non-conductive is expressed as "L".

[0056] At time T1, when the potential of wiring RSEL[0] is set to "H", all the selection transistors 24S of the binarization circuits 24 in the pixel block 13 arranged in the 0th row are turned on, and the operation data is output to the readout circuit 40.

[0057] Also, at time T1, when the potential of wiring CSEL[0] is set to "H", the switch 40S whose gate is electrically connected to wiring CSEL[0] is turned on, and the operation data of pixel block 13[1,1] is output to output lines OUT[0] to OUT[5].

[0058] At time T2, when the potential of wiring CSEL[0] is set to "L" and the potential of wiring CSEL[1] is set to "H", the switch 40S is turned off, and the switch 41S whose gate is electrically connected to wiring CSEL[1] is turned on, and the operation data of pixel block 13[1,2] is output to output lines OUT[0] to OUT[5].

[0059] At time T3, when the potential of wiring CSEL[1] is set to "L" and the potential of wiring CSEL[2] is set to "H", the switch 41S is turned off, and the switch 42S whose gate is electrically connected to wiring CSEL[2] is turned on, and the operation data of pixel block 13[1,3] is output to output lines OUT[0] to OUT[5].

[0060] At time T4, the potential of wiring RSEL[0] is set to "L" and the potential of wiring CSEL[2] is set to "L", and the output of the operation data of the pixel block 13 (pixel blocks 13[1,1] to 13[1,3]) in the 0th row is terminated.

[0061] At times T4 to T7, the potential of wiring RSEL[1] is set to "H", and by performing the same operation as above, the arithmetic data of the pixel blocks 13 in the first row (pixel blocks 13[2,1] to pixel blocks 13[2,3]) is output.

[0062] Also, at times T7 to T10, the potential of wiring RSEL[2] is set to "H", and by performing the same operation as above, the arithmetic data of the pixel blocks 13 in the second row (pixel blocks 13[3,1] to pixel blocks 13[3,3]) is output.

[0063] Here, if the arithmetic operation is completed in one clock and the read operation of one pixel block 13 is performed in one clock, one pixel block 12 can be read in a total of 10 clocks. Note that by providing the same number of read circuits 40 as the number of columns of the pixel blocks 12, the pixel blocks 12 for one row can be read in parallel.

[0064] <Pixel Circuit> As shown in FIG. 10A, the pixel circuit 15 can include a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, and a capacitor 106.

[0065] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104. One of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 105.

[0066] The other electrode of the photoelectric conversion device 101 is electrically connected to the wiring 111. The gate of the transistor 102 is electrically connected to the wiring 114. The other of the source or drain of the transistor 103 is electrically connected to the wiring 112. The gate of the transistor 103 is electrically connected to the wiring 115. The other of the source or drain of the transistor 104 is electrically connected to the wiring 113. The other of the source or drain of the transistor 105 is electrically connected to the wiring 117. The gate of the transistor 105 is electrically connected to the wiring 116.

[0067] Here, an electrical connection point (wiring) among the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104 is defined as a node N.

[0068] The wirings 111, 112, and 113 can function as power supply lines. For example, the wiring 111 can function as a low-potential power supply line, and the wirings 112 and 113 can function as high-potential power supply lines. Note that the wirings 112 and 113 may be electrically connected. The wirings 114, 115, and 116 can function as signal lines for controlling the conduction of each transistor. The wiring 117 can function as a wiring for electrically connecting the pixel circuit 15 and the binarization circuit 22.

[0069] As the photoelectric conversion device 101, a photodiode can be used. When it is desired to enhance the light detection sensitivity in low illuminance, it is preferable to use an avalanche photodiode.

[0070] The transistor 102 can have a function of controlling the potential of the node N. The transistor 103 can have a function of initializing the potential of the node N. The transistor 104 can have a function of passing a current according to the potential of the node N. The transistor 105 can have a function of selecting a pixel.

[0071] Note that the connection direction of the pair of electrodes included in the photoelectric conversion device 101 may be reversed. In this case, the wiring 111 may be made to function as a high-potential power line, and the wiring 112 may be made to function as a low-potential power line.

[0072] For the transistors 102 and 103, it is preferable to use transistors (OS transistors) in which a metal oxide is used for the channel formation region. The OS transistor has a characteristic of extremely low off-current. By using the OS transistor for the transistors 102 and 103, the period during which charge can be held at the node N can be made extremely long. In addition, a global shutter method in which the charge accumulation operation is performed simultaneously for all pixels can be applied without complicating the circuit configuration and the operation method.

[0073] On the other hand, in some cases, it may be desired that the transistor 104 has excellent amplification characteristics. Also, in some cases, it may be preferable to use a transistor having a high mobility enabling high-speed operation for the transistor 105. Therefore, a transistor (Si transistor) using silicon for the channel formation region may be applied to the transistors 104 and 105.

[0074] Note that the present invention is not limited to the above, and the OS transistor and the Si transistor may be arbitrarily combined and applied. Also, all the transistors may be OS transistors. Alternatively, all the transistors may be Si transistors. Examples of the Si transistor include a transistor having amorphous silicon and a transistor having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single-crystalline silicon).

[0075] Further, as shown in FIG. 10B, a configuration in which a back gate (second gate) is provided for the transistor may be adopted. By electrically connecting the back gate to the front gate, the on-current of the transistor can be increased. Further, by supplying an appropriate constant potential to the back gate, the threshold voltage of the transistor can be controlled. Note that the configuration in which a back gate is provided for the transistor can also be applied to other circuits in this specification. Further, a circuit may be configured by mixing transistors with and without a back gate.

[0076] Further, as shown in FIG. 10C, a configuration in which transistors 107 and 108 are added to the configuration of FIG. 10A may be adopted. The gate of transistor 107 is electrically connected to the gate of transistor 104. One of the source or drain of transistor 107 is electrically connected to one of the source or drain of transistor 108. The other of the source or drain of transistor 107 is electrically connected to wiring 113. The gate of transistor 108 is electrically connected to wiring 118. The other of the source or drain of transistor 108 is electrically connected to wiring 119.

[0077] Here, wiring 118 can function as a signal line for controlling the conduction of transistor 108. Further, wiring 119 can be electrically connected to circuit 60. Circuit 60 is an image readout circuit, and for example, a CDS circuit (correlated double sampling circuit) or the like can be used. By using this configuration, image data can be output to wiring 117 and wiring 119. The image data output to wiring 117 is input to binarization circuit 22, and then a product-sum operation is performed. The image data output to wiring 119 is read out to the outside via circuit 60. These operations can be performed in parallel. Further, only the operation (image processing) or only the readout of the image data can be performed.

[0078] Note that circuit 60 can be provided in layer 20 as an element of circuit 35 or circuit 36 shown in FIG. 1.

[0079] <Memory circuit 1> As shown in FIG. 2, the memory circuit 16 is provided in the pixel 14. The memory circuit 16 has a plurality of memory cells, and 1-bit data corresponding to the weight coefficient is stored in the memory cells.

[0080] FIG. 11A is a diagram showing the connection relationship of the memory cell 150, the load driver 33, and the column driver 34 included in the memory circuit 16. The plurality of memory cells 150 are provided in the layer 10 as the memory circuit 16. The load driver 33 and the column driver 34 are drive circuits for the memory cell 150 and can be provided in the layer 20. Note that a sense amplifier or the like may be used for data reading.

[0081] The memory circuit 16 has a total of m×n memory cells 150, where m (m is an integer of 1 or more) memory cells are arranged in a column and n (n is an integer of 1 or more) memory cells are arranged in a row, and the memory cells 150 are arranged in a matrix.

[0082] FIGS. 11B to 11D are diagrams for explaining the memory cells 150a to 150c applicable to the memory cell 150. In the following description, the bit lines can be electrically connected to the column driver 34. The word lines can be electrically connected to the load driver 33. The bit lines are also electrically connected to the product-sum operation circuit 23, but are not shown here.

[0083] For example, a decoder or a shift register can be used for the load driver 33 and the column driver 34. Note that a plurality of load drivers 33 and column drivers 34 may be provided.

[0084] FIG. 11B shows a circuit configuration example of the DRAM type memory cell 150a. The memory cell 150a includes a transistor 271 and a capacitor 274.

[0085] One of the source or drain of the transistor 271 is connected to one electrode of the capacitor 274, the other of the source or drain of the transistor 271 is connected to the wiring BIL, the gate of the transistor 271 is connected to the wiring WL, and the back gate of the transistor 271 is connected to the wiring BGL. The other electrode of the capacitor 274 is connected to the wiring GNDL. The wiring GNDL is a wiring that provides a low-level potential (reference potential).

[0086] The wiring BIL functions as a bit line. The wiring WL functions as a word line. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor 271. By applying an appropriate potential to the wiring BGL, the threshold voltage of the transistor 271 can be increased or decreased. Alternatively, the wiring BGL may be electrically connected to the wiring WL. By applying the same potential as the wiring WL to the wiring BGL, the on-current of the transistor 271 can be increased.

[0087] Writing and reading of data are performed by applying a high-level potential to the wiring WL to turn on the transistor 271 and electrically connecting the wiring BIL and one electrode of the capacitor 274. For example, a sense amplifier is electrically connected to the wiring BIL, and the potential of the wiring BIL can be amplified and read by the sense amplifier.

[0088] It is preferable to use an OS transistor for the transistor 271. In this specification and the like, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).

[0089] An OS transistor using an oxide semiconductor containing indium, gallium, and zinc has the characteristic that its off-current is extremely small. By using the OS transistor as transistor 271, the leakage current of transistor 271 can be made very low. That is, since the written data can be held by transistor 271 for a long time, the frequency of refreshing the memory cell can be reduced. Or, the refresh operation of the memory cell can be made unnecessary.

[0090] FIG. 11C shows a circuit configuration example of a gain cell type (also referred to as "2Tr1C type") memory cell 150b having two transistors and one capacitor. Memory cell 150b includes transistor 273, transistor 272, and capacitor 275.

[0091] One of the source or drain of transistor 273 is connected to one electrode of capacitor 275, the other of the source or drain of transistor 273 is connected to wiring WBL, the gate of transistor 273 is connected to wiring WL, and the back gate of transistor 273 is connected to wiring BGL. The other electrode of capacitor 275 is connected to wiring RL. One of the source or drain of transistor 272 is connected to wiring RBL, the other of the source or drain of transistor 272 is connected to wiring SL, and the gate of transistor 272 is connected to one electrode of capacitor 275.

[0092] Wiring WBL functions as a write bit line. Wiring RBL functions as a read bit line. Wiring WL functions as a word line. Wiring RL functions as a wiring for applying a predetermined potential to the other electrode of capacitor 275. During data writing and during data holding, it is preferable to apply a reference potential to wiring RL.

[0093] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor 273. By applying an appropriate potential to the wiring BGL, the threshold voltage of the transistor 273 can be increased or decreased. Alternatively, the wiring BGL may be electrically connected to the wiring WL. By applying the same potential as the wiring WL to the wiring BGL, the current characteristics of the transistor 273 can be enhanced.

[0094] Writing of data is performed by applying a high-level potential to the wiring WL to turn on the transistor 273 and electrically connecting one electrode of the wiring WBL and the capacitor 275. Specifically, when the transistor 273 is in the conductive state, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to one electrode of the capacitor 275 and the gate of the transistor 272. Thereafter, by applying a low-level potential to the wiring WL to turn off the transistor 273, the potential of one electrode of the capacitor 275 and the potential of the gate of the transistor 272 are held.

[0095] Reading of data is performed by applying predetermined potentials to the wiring RL and the wiring SL. Since the current flowing between the source and drain of the transistor 272 and the potential of one of the source or drain of the transistor 273 are determined by the potential of the gate of the transistor 272 and the potential of the other of the source or drain of the transistor 273, by reading the potential of the wiring RBL connected to one of the source or drain of the transistor 272, the potential held by one electrode of the capacitor 275 (or the gate of the transistor 272) can be read. That is, the information written in this memory cell can be read from the potential held by one electrode of the capacitor 275 (or the gate of the transistor 272). Alternatively, it is possible to know the presence or absence of the information written in this memory cell.

[0096] Further, as shown in FIG. 11D, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. The memory cell 150c shown in FIG. 11D has a configuration in which the wiring WBL and the wiring RBL of the memory cell 150b are combined into a single wiring BIL, and the other of the source or drain of the transistor 273 and one of the source or drain of the transistor 272 are connected to the wiring BIL. That is, the memory cell 150c is configured to operate with a single wiring BIL for the write bit line and the read bit line.

[0097] In the memory cells 150b and 150c, it is preferable to use an OS transistor for the transistor 273. When an OS transistor is used for the transistor 273, a storage device using a 2Tr1C type memory cell such as the memory cells 150b and 150c is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory). Note that the configuration of the memory cell can be changed as appropriate.

[0098] <Memory Circuit 2> Further, the memory circuit 16 may have the configuration shown in FIG. 12A. The memory circuit 16 having the configuration shown in FIG. 12A can use the memory cell 150d shown in FIG. 12B.

[0099] The memory cell 150d includes a transistor 276 and a capacitor 277. One of the source or drain of the transistor 276 is connected to one electrode of the capacitor 277, the other of the source or drain of the transistor 276 is connected to the wiring BIL, and the gate of the transistor 276 is connected to the wiring WL. The other electrode of the capacitor 277 is connected to the wiring PL.

[0100] The wiring BIL functions as a bit line. The wiring WL functions as a word line. The wiring PL is a wiring that applies the plate potential required for data writing or data reading to the capacitor 277. The circuit 37 shown in FIG. 12A is a circuit that supplies the plate potential and can be provided in the layer 20 as an element of the circuit 35 or the circuit 36. Also, a sense amplifier may be electrically connected to the wiring BIL. The sense amplifier can amplify and read the potential of the wiring BIL.

[0101] For the transistor 276, an Si transistor, an OS transistor, or the like can be used. When an OS transistor is used for the transistor 276, as shown in FIG. 12C, it is preferable to provide a back gate that is electrically connected to the wiring BGL. By applying an appropriate potential to the wiring BGL, the threshold voltage of the transistor 271 can be increased or decreased. Alternatively, the wiring BGL may be electrically connected to the wiring WL. By applying the same potential as the wiring WL to the wiring BGL, the current characteristics of the transistor 271 can be improved.

[0102] Also, the OS transistor has the characteristic of high breakdown voltage. Therefore, by using the OS transistor for the transistor 276, even if the transistor 276 is miniaturized, a high voltage can be applied to the transistor 276. By miniaturizing the transistor 276, the occupied area of the memory cell 150d can be reduced.

[0103] The capacitor 277 has a material that can have ferroelectricity as a dielectric layer between two electrodes. Hereinafter, the dielectric layer included in the capacitor 277 is referred to as a ferroelectric layer. Also, a capacitor having a ferroelectric layer can be called a ferroelectric capacitor. Further, a configuration combining a switch such as a transistor and a ferroelectric capacitor can be called a ferroelectric memory.

[0104] Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X(Let X be a real number greater than 0), materials obtained by adding element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide, materials obtained by adding element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide, and the like can be mentioned. Further, as a material that can have ferroelectricity, piezoelectric ceramics having a perovskite structure such as lead titanate (PT), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. may be used. Further, as a material that can have ferroelectricity, for example, a mixture or compound containing a plurality of materials selected from the materials listed above can be used. Alternatively, the ferroelectric layer can be formed into a laminated structure composed of a plurality of materials selected from the materials listed above.

[0105] Among them, as a material that can have ferroelectricity, hafnium oxide, or a material having hafnium oxide and zirconium oxide can have ferroelectricity even when processed into a thin film of several nm. The ability to thin the ferroelectric layer can improve the compatibility with the miniaturization process of the transistor.

[0106] Also, as a material that can have ferroelectricity, HfZrO XWhen using it, it is preferable to form a film by an atomic layer deposition (ALD) method, particularly a thermal ALD method. Further, when forming a film of a material that can have ferroelectricity using the thermal ALD method, it is suitable to use a material that does not contain a hydrocarbon (also referred to as HC) as a precursor. When either one or both of hydrogen and carbon are contained in a material that can have ferroelectricity, it may inhibit the crystallization of the material that can have ferroelectricity. For this reason, as described above, by using a precursor that does not contain a hydrocarbon, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be given as a precursor that does not contain a hydrocarbon. In addition, as a material that can have ferroelectricity, a material having hafnium oxide and zirconium oxide (HfZrO x ) when using, as a precursor, HfCl4 and / or ZrCl4 may be used.

[0107] In addition, when forming a film using a material that can have ferroelectricity, by thoroughly removing impurities in the film, here at least one or more of hydrogen, hydrocarbon, and carbon, a film having high-purity true ferroelectricity can be formed. Note that the film having high-purity true ferroelectricity and the high-purity true oxide semiconductor shown in the embodiments described later have very high manufacturing process compatibility. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0108] In addition, when using HfZrO as a material that can have ferroelectricity X it is preferable to alternately form hafnium oxide and zirconium oxide in a composition of 1:1 by using the thermal ALD method.

[0109] In addition, when forming a film of a material that can have ferroelectricity using the thermal ALD method, H2O or O3 can be used as an oxidizing agent. However, the oxidizing agent for the thermal ALD method is not limited to this. For example, the oxidizing agent for the thermal ALD method may contain any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0110] Also, the crystal structure of the material that can have ferroelectricity is not particularly limited. For example, as the crystal structure of the material that can have ferroelectricity, any one or more selected from cubic system, tetragonal system, orthorhombic system, and monoclinic system may be used. In particular, as the material that can have ferroelectricity, having an orthorhombic crystal structure is preferable because ferroelectricity is exhibited. Or, as the material that can have ferroelectricity, a composite structure having an amorphous structure and a crystal structure may also be used.

[0111] FIG. 13A is a graph showing an example of the hysteresis characteristics of the ferroelectric layer. In FIG. 13A, the horizontal axis represents the voltage applied to the ferroelectric layer. The voltage can be, for example, the difference between the potential of one electrode of the capacitor 277 and the potential of the other electrode of the capacitor 277. Also, in FIG. 13A, the vertical axis represents the polarization amount of the ferroelectric layer.

[0112] As shown in FIG. 13A, the hysteresis characteristics of the ferroelectric layer can be represented by curve 71 and curve 72. Let the voltages at the intersection of curve 71 and curve 72 be VSP and -VSP. VSP and -VSP can be said to have different polarities.

[0113] After applying a voltage of -VSP or less to the ferroelectric layer and then increasing the voltage applied to the ferroelectric layer, the polarization amount of the ferroelectric layer increases according to curve 71. On the other hand, after applying a voltage of VSP or more to the ferroelectric layer and then decreasing the voltage applied to the ferroelectric layer, the polarization amount of the ferroelectric layer decreases according to curve 72. Here, VSP and -VSP can be called saturation polarization voltages. For example, VSP may be called the first saturation polarization voltage and -VSP may be called the second saturation polarization voltage. Also, in FIG. 13A, it is assumed that the absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage are equal, but they may be different.

[0114] Here, when the polarization amount of the ferroelectric layer changes according to curve 71, the voltage (antivoltage) at which the polarization amount of the ferroelectric layer becomes 0 is defined as Vc. Also, when the polarization amount of the ferroelectric layer changes according to curve 72, the voltage (antivoltage) at which the polarization amount of the ferroelectric layer becomes 0 is defined as -Vc. It can be said that the value of Vc and the value of -Vc are within the range between -VSP and VSP. For example, Vc may be referred to as the first antivoltage, and -Vc may be referred to as the second antivoltage. In addition, in FIG. 13A, an example is shown where the absolute value of the first antivoltage and the absolute value of the second antivoltage are equal, but they may be different.

[0115] As described above, the voltage applied to the ferroelectric layer included in the capacitor 277 can be represented by the difference between the potential of one electrode of the capacitor 277 and the potential of the other electrode of the capacitor 277. The other electrode of the capacitor 277 is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer included in the capacitor 277 can be controlled.

[0116] <An example of the driving method of the memory cell> Hereinafter, an example of the driving method of the memory cell 150d shown in FIG. 12B will be described. In the following description, the voltage applied to the ferroelectric layer of the capacitor 277 is defined as the difference between the potential of one electrode of the capacitor 277 and the potential of the other electrode (wiring PL) of the capacitor 277. Also, the transistor 276 is an n-channel type transistor.

[0117] FIG. 13B is a timing chart showing an example of the driving method of the memory cell 150d shown in FIG. 12B. In FIG. 13B, an example of writing and reading binary digital data to and from the memory cell 150d is shown.

[0118] Note that a sense amplifier is electrically connected to the wiring BIL, and Vref is supplied to the sense amplifier as a reference potential. For example, when the potential of the wiring BIL is higher than Vref, data "1" can be read. Also, when the potential of the wiring BIL is lower than Vref, data "0" can be read.

[0119] First, the operation of writing data "1" into the memory cell 150d at times T01 to T03 will be described.

[0120] At times T01 to T02, when the potential of the wiring WL is set to the high potential H, the transistor 276 is turned on. Also, the potential of the wiring BIL is set to Vw. Since the transistor 276 is in the on state, the potential of one electrode of the capacitor 277 becomes Vw. Further, the potential of the wiring PL is set to GND. By this operation, the voltage applied to the ferroelectric layer of the capacitor 277 becomes "Vw - GND". Therefore, data "1" can be written into the memory cell 150d.

[0121] Here, Vw is preferably VSP or higher, and for example, it can be equal to VSP. Also, GND can be, for example, the ground potential or 0V, but it can also be other potentials.

[0122] Subsequently, at time T02, when the potentials of the wiring BIL and the wiring PL are set to GND, the voltage applied to the ferroelectric layer of the capacitor 277 becomes 0V. When the voltage "Vw - GND" applied to the ferroelectric layer of the capacitor 277 is VSP or higher from time T01 to time T02, from time T02 to time T03, the polarization amount of the ferroelectric layer of the capacitor 277 changes to the position of 0V according to the curve 72 shown in FIG. 13A. Therefore, the direction of polarization in the ferroelectric layer of the capacitor 277 is maintained.

[0123] After setting the potentials of the wiring BIL and the wiring PL to GND, when the potential of the wiring WL is set to the low potential L, the transistor 276 is turned off. Thus, the writing operation is completed, and data "1" is held in the memory cell 150d.

[0124] Next, the data reading operation at times T03 to T04 will be described.

[0125] When the potential of the wiring WL is set to the high potential H from time T03 to time T04, the transistor 276 is turned on. Also, the potential of the wiring PL is set to Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitor 277 becomes "GND - Vw".

[0126] At this time, since the voltage applied to the ferroelectric layer of the capacitor 277 is inverted from "Vw - GND" to "GND - Vw", polarization inversion occurs in the ferroelectric layer of the capacitor 277. When polarization inversion occurs, a current flows through the wiring BIL, so the potential of the wiring BIL becomes higher than Vref. Therefore, the data "1" held in the memory cell 150d can be read out by the operation of the sense amplifier. Note that although the case where Vref is higher than GND and lower than Vw is exemplified, it may be higher than Vw, for example.

[0127] Next, the operation of rewriting data from time T04 to time T05 will be described.

[0128] Since the above read operation is a destructive read that reverses the direction of polarization, the data "1" held in the memory cell 150d is lost. Therefore, from time T04 to time T05, the potential of the wiring BIL is set to Vw, the potential of the wiring PL is set to GND, and the data "1" is rewritten into the memory cell 150d.

[0129] At time T05, the potentials of the wiring BIL and the wiring PL are set to GND. After that, the potential of the wiring WL is set to the low potential L. Thus, the rewrite operation is completed, and the data "1" is held in the memory cell 150d.

[0130] Next, the read operation from time T11 to time T13 and the operation of writing the data "0" into the memory cell 150d will be described.

[0131] At times T11 to T12, the potential of wiring WL is set to high potential H, and the potential of wiring PL is set to Vw. Since the memory cell 150d holds data "1", the potential of wiring BIL becomes higher than Vref, and the data "1" held in the memory cell 150d is read out.

[0132] At times T12 to T13, the potential of wiring BIL is set to GND. Since transistor 276 is in the on state, the potential of one electrode of capacitor 277 becomes GND. Also, the potential of wiring PL is set to Vw. From the above, the voltage applied to the ferroelectric layer of capacitor 277 becomes "GND - Vw". Therefore, data "0" can be written into the memory cell 150d.

[0133] Subsequently, at time T13, when the potential of wiring BIL and the potential of wiring PL are set to GND, the voltage applied to the ferroelectric layer of capacitor 277 becomes 0V. When the voltage "GND - Vw" applied to the ferroelectric layer of capacitor 277 at times T12 to T13 is -VSP or less, at times T13 to T14, the polarization amount of the ferroelectric layer of capacitor 277 changes to the position of 0V according to the curve 71 shown in FIG. 13A. Therefore, the direction of polarization in the ferroelectric layer of capacitor 277 is maintained.

[0134] After the potential of wiring BIL and the potential of wiring PL are set to GND, when the potential of wiring WL is set to low potential L, transistor 276 becomes in the off state. As described above, the write operation is completed, and data "0" is held in the memory cell 150d.

[0135] Next, the data read operation at times T14 to T15 will be described.

[0136] At times T14 to T15, when the potential of wiring WL is set to high potential H, transistor 276 becomes in the on state. Also, the potential of wiring PL is set to Vw. By setting the potential of wiring PL to Vw, the voltage applied to the ferroelectric layer of capacitor 277 becomes "GND - Vw".

[0137] At this time, since the voltage applied to the ferroelectric layer of the capacitor 277 becomes the same "GND-Vw" as when writing data, polarization reversal does not occur in the ferroelectric layer of the capacitor 277. Therefore, the amount of current flowing through the wiring BIL becomes smaller than the case where polarization reversal occurs in the ferroelectric layer of the capacitor 277. Accordingly, the rising width of the potential of the wiring BIL also becomes smaller. Specifically, the potential of the wiring BIL becomes equal to or lower than Vref, and the data "0" held in the memory cell 150d can be read out by the operation of the sense amplifier.

[0138] Next, the data rewrite operation from time T15 to time T17 will be described.

[0139] From time T15 to time T16, the potential of the wiring BIL is set to GND, and the potential of the wiring PL is set to Vw. By this operation, the data "0" is rewritten in the memory cell 150d.

[0140] From time T16 to time T17, the potentials of the wiring BIL and the wiring PL are set to GND. Then, the potential of the wiring WL is set to the low potential L. As described above, the rewrite operation is completed, and the data "0" is held in the memory cell 150d.

[0141] Next, the data read operation from time T17 to time T19 and the operation of writing the data "1" into the memory cell 150d will be described.

[0142] From time T17 to time T18, the potential of the wiring WL is set to the high potential H, and the potential of the wiring PL is set to Vw. Since the data "0" is held in the memory cell 150d, the potential of the wiring BIL becomes lower than Vref, and the data "0" held in the memory cell 150d is read out.

[0143] At time T18 to time T19, let the potential of wiring BIL be Vw. Since transistor 276 is in the on state, the potential of one electrode of capacitor 277 becomes Vw. Also, let the potential of wiring PL be GND. Thus, the voltage applied to the ferroelectric layer of capacitor 277 is "Vw - GND". Therefore, data "1" can be written into memory cell 150d.

[0144] After time T19, let the potential of wiring BIL and the potential of wiring PL be GND. Then, let the potential of wiring WL be low potential L. Thus, the writing operation is completed, and data "1" is held in memory cell 150d.

[0145] The above is an example of the operation of memory cell 150d, but operations such as writing, reading, and rewriting data may be performed by other methods.

[0146] <Layout> FIG. 14A and FIG. 14B are examples of a layout (top view) that can be used for the pixel circuit of one aspect of the present invention. FIG. 14A and FIG. 14B are the layouts of the pixel circuit shown in FIG. 10B. In FIG. 14A, back gate wiring 170, metal oxide layer 175, and source-drain wiring 180 are shown. Here, metal oxide layer 175 is a layer in which a channel formation region of an OS transistor is provided.

[0147] In order to improve the resolution of the imaging device, miniaturization of the pixel circuit is required. In the miniaturization process, since adjacent structures affect each other, arranging the structures randomly promotes variations such as wiring width. Therefore, as shown in FIG. 14A, it is preferable to arrange the structures at equal intervals in the horizontal direction (X direction) and the vertical direction (Y direction).

[0148] FIG. 14B shows a configuration in which a gate wiring 185 and a wiring 190 electrically connected to the gate wiring 185 are added to FIG. 14A. By overlapping each element in this way, the transistors 102, 103, 104, and 105 shown in FIG. 10B are formed. In addition, a plurality of transistors 109 are formed. The transistor 109 is a dummy transistor that does not participate in the circuit operation, but by adopting such a configuration, the uniformity of the wiring width and the like can be improved, and variations in transistor characteristics and the like can be suppressed.

[0149] According to one aspect of the present invention described in this embodiment, an imaging device having an image processing function and capable of high-speed operation can be provided.

[0150] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0151] (Embodiment 2) In this embodiment, an imaging device having a configuration different from that of Embodiment 1 will be described with reference to the drawings. The imaging device described in Embodiment 1 has a configuration in which a multiplication-accumulation operation is performed once on image data and the operation data is taken out, while the imaging device described in this embodiment has a configuration in which a multiplication-accumulation operation is performed a plurality of times on image data and the operation data is taken out.

[0152] Since the basic configurations of the pixel 14 and the pixel blocks (pixel block 12, pixel block 13) are common to those in Embodiment 1, detailed descriptions thereof are omitted.

[0153] The imaging device has two registers as elements for performing a multiplication-accumulation operation a plurality of times and taking out the operation data. FIG. 15 is a diagram for explaining the connection relationship between the pixel block 12 and a register 51 which is one of the two registers (register 51, register 52). Note that a selection circuit can be provided between the pixel block 13 and the register 51 to reduce the number of wirings.

[0154] The pixel block 12 shown in FIG. 15 is a simplified diagram of the pixel block 12 shown in FIG. 8, indicating that the arithmetic data output from each pixel block 13 after the first multiplication and accumulation operation is 6 bits (1 bit × 6). The 6-bit arithmetic data output from each pixel block 13 is input to and stored in the register 51. Here, since the 6-bit arithmetic data output from 9 pixel blocks 13 is input to the register 51, a total of 54 bits (6 bits × 9) of arithmetic data will be stored.

[0155] Next, as shown in FIG. 16, the 54-bit arithmetic data stored in the register 51 is redistributed to each pixel block 13. Six multiplication and accumulation circuits 23 capable of processing 9-bit data shown in FIG. 6A are provided in each pixel block 13, and 9-bit arithmetic data is distributed to each multiplication and accumulation circuit 23. Also, 9-bit weight coefficients are supplied from the 9 storage circuits 16 included in the pixel block 13 to each multiplication and accumulation circuit 23. Therefore, each multiplication and accumulation circuit 23 can perform the second multiplication and accumulation operation.

[0156] Next, as shown in FIG. 17A, the 4-bit arithmetic data output from each multiplication and accumulation circuit 23 is respectively input to circuits 25 provided in the same number as the pixel blocks 13. Here, since there are 6 multiplication and accumulation circuits 23, the arithmetic data input to the circuits 25 is 24 bits (4 bits × 6).

[0157] FIG. 17B is a diagram for explaining the circuit 25. The circuit 25 includes an addition circuit 26a and a binarization circuit 26b. Since 4-bit (corresponding to 0 to 9) arithmetic data is respectively input from 6 multiplication and accumulation circuits 23 to the addition circuit 26a, the output of the addition circuit 26a is 6-bit (corresponding to 0 to 54) arithmetic data. The 6-bit data is input to the binarization circuit 26b. The binarization circuit 26b can convert the input data into 1 bit, output 1 when the data is 28 or more, and output 0 when the data is 27 or less. Note that in FIG. 17, the circuit 25 is illustrated inside the pixel block 12, but it may be provided outside the pixel block 12.

[0158] The 1-bit arithmetic data (a total of 9-bit data) output by each circuit 25 is input to and stored in the register 52. Here, the arithmetic data for 9 bits can be read out as necessary. Note that a selection circuit can be provided between the circuit 25 and the register 52 to reduce the number of wirings.

[0159] In the present embodiment, an operation of repeating the multiplication and addition operation by changing the weight coefficient will be further described. After the above operation, the multiplication and addition circuit 23 included in the pixel block 13 holds 54-bit arithmetic data redistributed from the register 51. By changing the weight coefficient supplied from the storage circuit 16, the multiplication and addition operation is performed again, and different arithmetic data can be obtained. Then, the arithmetic data is stored in the register 52 in the same manner as the arithmetic data obtained in the previous multiplication and addition operation. Therefore, a total of 18-bit arithmetic data is stored in the register 52.

[0160] FIG. 18A is a diagram for explaining a readout circuit 41 connected to the output side of the register 52. A plurality of six output lines are provided on the output side of the register 52 so that arithmetic data can be read out every 6 bits. The readout circuit 41 is electrically connected to the six output lines. The readout circuit 41 includes switches 43S, 44S, and 45S that are electrically connected to the six output lines, respectively.

[0161] The switches 43S to 45S have a plurality of transistors. The gate of the transistor included in the switch 43S is electrically connected to the wiring CSEL[0]. The gate of the transistor included in the switch 44S is electrically connected to the wiring CSEL[1]. The gate of the transistor included in the switch 45S is electrically connected to the wiring CSEL[2].

[0162] The output-side wirings of the switches 43S to 45S are electrically connected to one output line OUT (OUT[0] to OUT[5]) every three. With such a configuration, arithmetic data can be output every 6 bits.

[0163] Note that the register 51, the register 52, and the read circuit 41 can be provided in the layer 20 as elements of the circuit 35 or the circuit 36 shown in FIG. 1.

[0164] FIG. 18B is a timing chart for explaining the reading of the arithmetic data stored in the register 52. It is assumed that all the arithmetic data (for 18 bits) are held in the register 52 before the time T1. Also, in the following description, the potential (high potential) that makes the transistor in the conductive state is expressed as "H", and the potential (low potential) that makes the transistor in the non-conductive state is expressed as "L".

[0165] When the potential of the wiring CSEL[0] is set to "H" at the time T1, the switch 43S whose gate is electrically connected to the wiring CSEL[0] conducts, and the first 6-bit portion of the arithmetic data is output to the output lines OUT[0] to OUT[5].

[0166] When the potential of the wiring CSEL[0] is set to "L" and the potential of the wiring CSEL[1] is set to "H" at the time T2, the switch 43S becomes non-conductive, and the switch 44S whose gate is electrically connected to the wiring CSEL[1] conducts, and the second 6-bit portion of the arithmetic data different from the first data is output to the output lines OUT[0] to OUT[5].

[0167] When the potential of the wiring CSEL[1] is set to "L" and the potential of the wiring CSEL[2] is set to "H" at the time T3, the switch 44S becomes non-conductive, and the switch 45S whose gate is electrically connected to the wiring CSEL[2] conducts, and the third 6-bit portion of the arithmetic data different from the first and second data is output to the output lines OUT[0] to OUT[5].

[0168] Here, it is assumed that storing 54 bits of arithmetic data in register 51 is performed in the first clock, storing the first 9 bits of arithmetic data in register 52 is performed in the second clock, and storing the second 9 bits of arithmetic data in register 52 is performed in the third clock. Then, it is assumed that reading the first 6 bits of arithmetic data from register 52 is performed in the fourth clock, reading the second 6 bits of arithmetic data is performed in the fifth clock, and reading the third 6 bits of arithmetic data is performed in the sixth clock. With this, all operations can be completed in 6 clocks.

[0169] The operations in the first to third clocks and the operations in the fourth to sixth clocks can be parallel operations. If the period from time T1 to time T2 in the timing chart shown in FIG. 18B corresponds to the fourth clock, the period from time T2 to time T3 corresponds to the fifth clock, and the period from time T3 to time T4 corresponds to the sixth clock, then from time T4 to time T7, the next 18 bits of arithmetic data can be read. Also, from time T7 to time T10, the next 18 bits of arithmetic data can be read.

[0170] Note that the operation of reading arithmetic data from pixel block 12 in Embodiment 1 and this embodiment corresponds to the operation with a stride of 3, and the pooling process is omitted. However, the pooling process may be performed to further compress the arithmetic data.

[0171] According to one aspect of the present invention described in this embodiment, an imaging device having an image processing function and capable of high-speed operation can be provided.

[0172] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0173] (Embodiment 3) In this embodiment, a structural example of an imaging device according to one aspect of the present invention will be described.

[0174] <Structural example> FIG. 19A is a diagram showing an example of the structure of a pixel of an imaging device, and can have a stacked structure of layer 561 and layer 563.

[0175] Layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can have a layer 565a and a layer 565b as shown in FIG. 20A. In some cases, the layer may be equivalently referred to as a region.

[0176] The photoelectric conversion device 101 shown in FIG. 20A is a pn junction type photodiode. For example, a p-type semiconductor can be used for layer 565a and an n-type semiconductor can be used for layer 565b. Alternatively, an n-type semiconductor can be used for layer 565a and a p-type semiconductor can be used for layer 565b.

[0177] The above pn junction type photodiode can typically be formed using single crystal silicon. A photodiode having a single crystal silicon as a photoelectric conversion layer has relatively wide spectral sensitivity characteristics from ultraviolet light to near-infrared light, and can detect light of various wavelengths by combining with an optical conversion layer described later.

[0178] In addition, a compound semiconductor may be used as the photoelectric conversion layer of the pn junction type photodiode. Examples of the compound semiconductor include gallium-arsenic-phosphorus compound (GaAsP), gallium-phosphorus compound (GaP), indium-gallium-arsenic compound (InGaAs), lead-sulfur compound (PbS), lead-selenium compound (PbSe), indium-arsenic compound (InAs), indium-antimony compound (InSb), mercury-cadmium-tellurium compound (HgCdTe), etc.

[0179] The compound semiconductor is preferably a compound semiconductor having group 13 elements (such as aluminum, gallium, indium, etc.) and group 15 elements (such as nitrogen, phosphorus, arsenic, antimony, etc.) (also referred to as 3-5 group compound semiconductors), or a compound semiconductor having group 12 elements (such as magnesium, zinc, cadmium, mercury, etc.) and group 16 elements (such as oxygen, sulfur, selenium, tellurium, etc.) (also referred to as 2-6 group compound semiconductors).

[0180] Compound semiconductors can change the bandgap according to the combination of constituent elements and their atomic ratio, so photodiodes with sensitivity in various wavelength ranges from ultraviolet light to infrared light can be formed.

[0181] Note that the wavelength of ultraviolet light can generally be defined as in the vicinity of 0.01 μm to in the vicinity of 0.38 μm, the wavelength of visible light as in the vicinity of 0.38 μm to in the vicinity of 0.75 μm, the wavelength of near-infrared light as in the vicinity of 0.75 μm to in the vicinity of 2.5 μm, the wavelength of mid-infrared light as in the vicinity of 2.5 μm to in the vicinity of 4 μm, and the wavelength of far-infrared light as in the vicinity of 4 μm to in the vicinity of 1000 μm.

[0182] For example, to form a photodiode with photosensitivity from ultraviolet light to visible light, GaP or the like can be used for the photoelectric conversion layer. Also, to form a photodiode with photosensitivity from ultraviolet light to near-infrared light, silicon or GaAsP or the like can be used for the photoelectric conversion layer. Also, to form a photodiode with photosensitivity from visible light to mid-infrared light, InGaAs or the like can be used for the photoelectric conversion layer. Also, to form a photodiode with photosensitivity from near-infrared light to mid-infrared light, PbS or InAs or the like can be used for the photoelectric conversion layer. Also, to form a photodiode with photosensitivity from mid-infrared light to far-infrared light, PbSe, InSb, or HgCdTe or the like can be used for the photoelectric conversion layer.

[0183] Note that the photodiode using the above compound semiconductor may be not only a pn junction but also a pin junction. Also, the pn junction and the pin junction are not limited to a homojunction structure and may be a heterojunction structure.

[0184] For example, in a heterojunction, a first compound semiconductor can be used for one layer of the pn junction structure, and a second compound semiconductor different from the first compound semiconductor can be used for the other layer. Also, a first compound semiconductor can be used for any one or two layers of the pin junction structure, and a second compound semiconductor different from the first compound semiconductor can be used for the other layers. Note that one of the first compound semiconductor or the second compound semiconductor may be a single semiconductor such as silicon.

[0185] Note that different materials may be used for each pixel to form the photoelectric conversion layer of the photodiode. By using such a configuration, an imaging device having any two types of pixels, such as pixels for detecting ultraviolet light, pixels for detecting visible light, and pixels for detecting infrared light, or three types of pixels can be formed.

[0186] Also, as shown in FIG. 20B, the photoelectric conversion device 101 included in layer 561 may be a stack of layer 566a, layer 566b, layer 566c, and layer 566d. The photoelectric conversion device 101 shown in FIG. 20B is an example of an avalanche photodiode. Layer 566a and layer 566d correspond to electrodes, and layer 566b and 566c correspond to the photoelectric conversion part.

[0187] Layer 566a is preferably a low-resistance metal layer or the like. For example, aluminum, titanium, tungsten, tantalum, silver, or a stack thereof can be used.

[0188] For layer 566d, it is preferable to use a conductive layer having high transmittance for visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, or graphene can be used. Note that a configuration in which layer 566d is omitted is also possible.

[0189] The layers 566b and 566c of the photoelectric conversion unit can be configured as a pn junction photodiode using, for example, a selenium-based material as the photoelectric conversion layer. As the layer 566b, it is preferable to use a selenium-based material that is a p-type semiconductor, and as the layer 566c, it is preferable to use a gallium oxide or the like that is an n-type semiconductor.

[0190] A photoelectric conversion device using a selenium-based material has the characteristic of high external quantum efficiency for visible light. In this photoelectric conversion device, by utilizing avalanche multiplication, the amplification of electrons with respect to the amount of incident light can be increased. In addition, since the selenium-based material has a high light absorption coefficient, it has production advantages such as being able to fabricate the photoelectric conversion layer as a thin film. The thin film of the selenium-based material can be formed using a vacuum evaporation method, a sputtering method, or the like.

[0191] As the selenium-based material, crystalline selenium (single crystal selenium, polycrystalline selenium), amorphous selenium can be used. These have photosensitivity from ultraviolet light to visible light. In addition, compounds of copper, indium, selenium (CIS), or compounds of copper, indium, gallium, selenium (CIGS), etc. can be used. These have photosensitivity from ultraviolet light to near-infrared light.

[0192] The n-type semiconductor is preferably formed of a material having a wide bandgap and being transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or oxides in which they are mixed can be used. In addition, these materials also have the function as a hole injection blocking layer and can also reduce the dark current.

[0193] In addition, as shown in FIG. 20C, the photoelectric conversion device 101 included in the layer 561 may be a laminate of the layer 567a, the layer 567b, the layer 567c, the layer 567d, and the layer 567e. The photoelectric conversion device 101 shown in FIG. 20C is an example of an organic photoconductive film. The layer 567a is a lower electrode, the layer 567e is a transparent upper electrode, and the layers 567b, 567c, and 567d correspond to the photoelectric conversion unit.

[0194] Either one of the layers 567b and 567d of the photoelectric conversion unit can be a hole transport layer, and the other can be an electron transport layer. Also, the layer 567c can be a photoelectric conversion layer.

[0195] As the hole transport layer, for example, molybdenum oxide or the like can be used. As the electron transport layer, for example, C 60 、C 70 fullerenes such as, or derivatives thereof can be used.

[0196] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used. There are various types of organic semiconductors, and a material having light sensitivity to the target wavelength can be selected for the photoelectric conversion layer.

[0197] As the layer 563 shown in FIG. 19A, for example, a silicon substrate can be used. The silicon substrate has Si transistors or the like. Using the Si transistors, in addition to the pixel circuit, a circuit for driving the pixel circuit, an image signal reading circuit, an image processing circuit, a neural network, a communication circuit, etc. can be formed. Also, a memory circuit such as a DRAM (Dynamic Random Access Memory), a CPU (Central Processing Unit), an MCU (Micro Controller Unit), etc. may be formed. Note that, in this embodiment, the circuits other than the pixel circuit are referred to as functional circuits.

[0198] For example, in the transistors included in the functional circuits (arithmetic unit 21, load driver 31, column driver 32, load driver 33, column driver 34, circuit 35, circuit 36, etc.) provided in the layer 20 described in Embodiment 1, some or all of them can be provided in the layer 563.

[0199] Further, as shown in FIG. 19B, the layer 563 may be a stack of a plurality of layers. In FIG. 19B, three layers, i.e., layers 563a, 563b, and 563c are illustrated, but it may be two layers. Alternatively, the layer 563 may be a stack of four or more layers. These layers can be stacked using, for example, a bonding process or the like. With such a configuration, the pixel circuit and the functional circuit can be dispersed in a plurality of layers and the pixel circuit and the functional circuit can be provided in an overlapping manner, so that a small-sized and highly functional imaging device can be manufactured.

[0200] Further, as shown in FIG. 19C, the pixel may have a stacked structure of the layer 561, the layer 562, and the layer 563.

[0201] The layer 562 corresponds to the layer 10 described in the first embodiment and can have an OS transistor. One or more of the above-described functional circuits may be formed by the OS transistor. Alternatively, one or more of the functional circuits may be formed using the Si transistor included in the layer 563 and the OS transistor included in the layer 562. Alternatively, the layer 563 may be used as a support substrate such as a glass substrate, and the pixel circuit and the functional circuit may be formed by the OS transistor included in the layer 562.

[0202] For example, a normally-off CPU (also referred to as "NoffCPU (registered trademark)") can be realized using an OS transistor and an Si transistor. Note that the NoffCPU is an integrated circuit including a normally-off type transistor that is in a non-conductive state (also referred to as an off state) even when the gate voltage is 0V.

[0203] The NoffCPU can stop the power supply to the circuits that are not required to operate within the NoffCPU and put the circuits into a standby state. In the circuits where the power supply is stopped and the standby state is entered, no power is consumed. Therefore, the NoffCPU can minimize the power consumption. Also, the NoffCPU can retain information necessary for operations such as setting conditions for a long period even when the power supply is stopped. To resume from the standby state, it is only necessary to resume the power supply to the circuits, and no rewriting such as setting conditions is required. That is, a high-speed resume from the standby state is possible. In this way, the NoffCPU can reduce the power consumption without significantly reducing the operating speed.

[0204] Also, as shown in FIG. 19D, the layer 562 may be a stack of a plurality of layers. In FIG. 19D, two layers, layer 562a and layer 562b, are illustrated, but a stack of three or more layers may also be used. These layers can be formed, for example, by stacking them on the layer 563. Alternatively, they may be formed by bonding the layer formed on the layer 563 and the layer formed on the layer 561.

[0205] As the semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, it is an oxide semiconductor containing indium, and for example, CAAC-OS or CAC-OS described later can be used. In CAAC-OS, the atoms constituting the crystal are stable, and it is suitable for transistors that emphasize reliability. Also, since CAC-OS exhibits high mobility characteristics, it is suitable for transistors that perform high-speed driving.

[0206] Since the OS transistor has a large energy gap in the semiconductor layer, it exhibits extremely low off-current characteristics of several yA / μm (current value per 1 μm channel width). Also, the OS transistor has characteristics different from those of Si transistors, such as no occurrence of impact ionization, avalanche breakdown, and short-channel effects, and can form a high-voltage and highly reliable circuit. In addition, variations in electrical characteristics due to non-uniform crystallinity, which are a problem in Si transistors, are less likely to occur in OS transistors.

[0207] The semiconductor layer of the OS transistor can be a film represented by an In-M-Zn-based oxide containing, for example, indium, zinc, and one or more selected from metals such as M (aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn-based oxide can typically be formed by a sputtering method. Alternatively, it may be formed using the ALD (Atomic layer deposition) method.

[0208] The atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn-based oxide by the sputtering method preferably satisfies In≧M and Zn≧M. As such atomic ratios of the metal elements of the sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0209] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the semiconductor layer has a carrier density of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3Hereinafter, more preferably 1×10 13 / cm 3 Hereinafter, more preferably 1×10 11 / cm 3 Hereinafter, more preferably 1×10 10 / cm 3 or less, and an oxide semiconductor of 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect levels and stable characteristics.

[0210] Note that the present invention is not limited to these, and those having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistor. Further, in order to obtain the semiconductor characteristics of the required transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate.

[0211] In the oxide semiconductor constituting the semiconductor layer, if silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and it becomes n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0212] In addition, when an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. For this reason, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0213] In addition, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, the nitrogen concentration (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5×10 18 atoms / cm 3 or less.

[0214] In addition, when hydrogen is contained in the oxide semiconductor constituting the semiconductor layer, it reacts with oxygen that binds to metal atoms to become water, so oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor may have normally-on characteristics. Furthermore, defects in which hydrogen enters oxygen vacancies may function as donors, and electrons as carriers may be generated. Also, part of the hydrogen may combine with oxygen that binds to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.

[0215] Defects in which hydrogen enters oxygen vacancies can function as donors in the oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in the oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may be paraphrased as "donor concentration" in some cases.

[0216] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 less than, preferably 1×1019 atoms / cm 3 less than, more preferably 5×10 18 atoms / cm 3 less than, even more preferably 1×10 18 atoms / cm 3 less than. By using an oxide semiconductor with sufficiently reduced impurities such as hydrogen in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0217] Also, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c-axis, polycrystalline structure, microcrystalline structure, or amorphous structure. Among non-single crystal structures, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0218] The oxide semiconductor film with an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, the oxide semiconductor film with an amorphous structure has, for example, a completely amorphous structure and no crystal part.

[0219] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-described regions.

[0220] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

[0221] CAC-OS is, for example, a composition of a material in which elements constituting an oxide semiconductor are unevenly distributed in a size range of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following description, in an oxide semiconductor, a state in which one or more metal elements are unevenly distributed and regions having the metal elements are mixed in a size range of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0222] Note that the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may also be included.

[0223] For example, in In-Ga-Zn oxide, CAC-OS (among CAC-OS, In-Ga-Zn oxide may be particularly referred to as CAC-IGZO) refers to indium oxide (hereinafter, InO X1 (where X1 is a real number greater than 0).), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (where X2, Y2, and Z2 are real numbers greater than 0).), and gallium oxide (hereinafter, GaO X3 (where X3 is a real number greater than 0).), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are real numbers greater than 0).), etc., and the material is separated to form a mosaic state, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 is a configuration uniformly distributed in the film (hereinafter, also referred to as a cloud state).

[0224] That is, CAC-OS is a composite oxide semiconductor having a structure in which a region mainly composed of GaO X3 and a region mainly composed of In X2 Zn Y2 O Z2 or InO X1 are mixed. In this specification, for example, when the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, it is considered that the first region has a higher In concentration than the second region.

[0225] Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a representative example, InGaO3(ZnO) m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number).

[0226] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.

[0227] On the other hand, CAC-OS relates to the material composition of an oxide semiconductor. CAC-OS refers to a structure in which in a material composition containing In, Ga, Zn, and O, a region observed as nanoparticle-like with Ga as a main component and a region observed as nanoparticle-like with In as a main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0228] Note that CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, a structure composed of two layers of a film mainly composed of In and a film mainly composed of Ga is not included.

[0229] Note that GaO X3The region where [substance] is the main component and In X2 Zn Y2 O Z2 or InO X1 The region where [substance] is the main component may not have a clear boundary observable.

[0230] In addition, instead of gallium, if one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are included, CAC-OS refers to a structure in which the region observed as nanoparticles with a part of the metal element as the main component and the region observed as nanoparticles with In as the main component are randomly dispersed in a mosaic pattern.

[0231] CAC-OS can be formed by a sputtering method, for example, under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by the sputtering method, any one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used as the film-forming gas. Further, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, it is preferable to set the flow rate ratio of oxygen gas to be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0232] CAC-OS has the characteristic that no distinct peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region.

[0233] In addition, in the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), in CAC-OS, a region with high brightness (ring region) in a ring shape and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0234] Also, for example, in CAC-OS in In-Ga-Zn oxide, according to the EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX), regions where GaO X3 is the main component and regions where In X2 Zn Y2 O Z2 or InO X1 is the main component are unevenly distributed and mixed.

[0235] CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed and has properties different from those of the IGZO compound. That is, CAC-OS has a structure in which regions where GaO X3 etc. are the main components and regions where In X2 Zn Y2 O Z2 or InO X1 is the main component are phase-separated from each other, and regions with each element as the main component are mosaic-like.

[0236] Here, the regions where In X2 Zn Y2 O Z2 or InO X1 is the main component are regions with higher conductivity compared to regions where GaO X3 etc. are the main components. That is, when carriers flow through the regions where In X2 Zn Y2 O Z2 or InO X1 is the main component, conductivity as an oxide semiconductor is exhibited. Therefore, InX2 Zn Y2 O Z2 、 or InO X1 By the region mainly composed of [the above] being distributed in a cloud shape in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0237] On the other hand, the region mainly composed of GaO X3 etc. is a region with high insulation compared to the region mainly composed of In X2 Zn Y2 O Z2 、 or InO X1 That is, by the region mainly composed of GaO X3 etc. being distributed in the oxide semiconductor, the leakage current can be suppressed and a good switching operation can be realized.

[0238] Therefore, when CAC-OS is used in a semiconductor device, the insulation caused by GaO X3 etc. and the conductivity caused by In X2 Zn Y2 O Z2 、 or InO X1 act complementarily to realize a high on-current (I on ) and a high field-effect mobility (μ).

[0239] Also, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0240] <Stacked Structure 1> Next, the stacked structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Or, some of the elements shown below may be omitted. Also, the stacked structure shown below can be formed using a bonding process, a polishing process, etc. as needed.

[0241] FIG. 21 is an example of a cross-sectional view of a laminate having layers 560, 561, and 563 and having a bonding surface between layers 563a and 563b that constitute layer 563.

[0242] <layer 563b> Layer 563b can have a functional circuit provided on silicon substrate 611. Here, transistors 223, 224, and 225 are shown as some of the transistors included in the functional circuit. Note that transistor 225 is illustrated as a transistor included in binarization circuit 22.

[0243] Silicon substrate 611, insulating layers 612, 613, 614, 616, 617, and 618 are provided in layer 563b. Insulating layer 612 has a function as a protective film. Insulating layers 613, 614, 616, and 617 have functions as an interlayer insulating film and a planarizing film. Insulating layer 618 and conductive layer 619 have functions as a bonding layer. Conductive layer 619 is electrically connected to the gate of transistor 225.

[0244] As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used. As the interlayer insulating film and the planarizing film, for example, an inorganic insulating film such as a silicon oxide film, an organic insulating film such as an acrylic resin or a polyimide resin can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like can be used. The bonding layer will be described later.

[0245] In addition, as the wiring, electrodes, and conductors that can be used for electrical connection between devices, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys containing the above-described metal elements as components, or alloys combining the above-described metal elements may be appropriately selected and used. The conductor is not limited to a single layer, and may be a plurality of layers composed of different materials.

[0246] <Layer 563a> Layer 563a has elements of pixel 14. It may also have elements of a functional circuit. Here, as a part of the elements of pixel 14, transistors 102 and 105 included in pixel circuit 15 are shown. In the cross-sectional view shown in FIG. 21, the electrical connection between the two is not shown.

[0247] Silicon substrate 632, insulating layers 631, 633, 634, 635, 637, 638 are provided in layer 563a. Also, conductive layers 636, 639 are provided.

[0248] Insulating layer 631 and conductive layer 639 have the function as a bonding layer. Insulating layers 634, 635, 637 have the function as an interlayer insulating film and a planarization film. Insulating layer 633 has the function as a protective film. Insulating layer 638 has the function of insulating silicon substrate 632 and conductive layer 639. Insulating layer 638 can be formed of the same material as other insulating layers. Also, insulating layer 638 may be formed of the same material as insulating layer 631.

[0249] Conductive layer 639 is electrically connected to the other of the source or drain of transistor 105 and conductive layer 619. Also, conductive layer 636 is electrically connected to wiring 111 (see FIG. 10A).

[0250] The Si transistor shown in FIG. 21 is of a fin type having a channel formation region on a silicon substrate (silicon substrates 611 and 632). A cross-section in the channel width direction (the cross-section of A1 - A2 shown in layer 563a of FIG. 21) is shown in FIG. 22A. Note that the Si transistor may be of a planar type as shown in FIG. 22B.

[0251] Alternatively, as shown in FIG. 22C, it may be a transistor having a semiconductor layer 545 of a silicon thin film. The semiconductor layer 545 can be, for example, single-crystalline silicon (SOI (Silicon on Insulator)) formed on an insulating layer 546 on the silicon substrate 632.

[0252] <layer 561> Layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can be formed on layer 563a. In FIG. 21, as the photoelectric conversion device 101, a configuration using the organic photoconductive film shown in FIG. 20C as the photoelectric conversion layer is shown. Here, layer 567a is used as the cathode and layer 567e is used as the anode.

[0253] Insulating layers 651, 652, 653, 654, and conductive layer 655 are provided in layer 561.

[0254] Insulating layers 651, 653, 654 have functions as an interlayer insulating film and a planarizing film. Further, insulating layer 654 is provided to cover the end portion of the photoelectric conversion device 101 and also has a function of preventing a short circuit between layer 567e and layer 567a. Insulating layer 652 has a function as an element isolation layer. As the element isolation layer, it is preferable to use an organic insulating film or the like.

[0255] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102 that layer 563a has. The layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 that layer 563a has via the conductive layer 655.

[0256] <layer 560> Layer 560 is formed on layer 561. Layer 560 has a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0257] The light-shielding layer 671 can suppress the inflow of light into adjacent pixels. For the light-shielding layer 671, a metal layer such as aluminum or tungsten can be used. Also, a dielectric film having a function as an antireflection film may be laminated on the metal layer.

[0258] When the photoelectric conversion device 101 has sensitivity to visible light, a color filter can be used for the optical conversion layer 672. By assigning color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel, a color image can be obtained. For example, as shown in the perspective view (including a cross section) of FIG. 31A, the color filter 672R (red), the color filter 672G (green), and the color filter 672B (blue) can be assigned to different pixels respectively.

[0259] Also, in an appropriate combination of the photoelectric conversion device 101 and the optical conversion layer 672, if a wavelength cut filter is used for the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be achieved.

[0260] For example, if an infrared filter that blocks light having a wavelength equal to or less than that of visible light is used for the optical conversion layer 672, an infrared imaging device can be achieved. Also, if a filter that blocks light having a wavelength equal to or less than that of near-infrared light is used for the optical conversion layer 672, a far-infrared imaging device can be achieved. Also, if an ultraviolet filter that blocks light having a wavelength equal to or greater than that of visible light is used for the optical conversion layer 672, an ultraviolet imaging device can be achieved.

[0261] Note that a plurality of different optical conversion layers may be arranged in one imaging device. For example, as shown in FIG. 31B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR can be assigned to different pixels respectively. In this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0262] Alternatively, as shown in FIG. 31C, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an ultraviolet filter 672UV can be assigned to different pixels respectively. In this configuration, a visible light image and an ultraviolet light image can be acquired simultaneously.

[0263] Also, if a scintillator is used for the optical conversion layer 672, an imaging device can be obtained that visualizes the intensity of radiation used in an X-ray imaging device or the like. When radiation such as X-rays transmitted through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data is acquired by detecting the light with the photoelectric conversion device 101. Further, the imaging device having such a configuration may be used for a radiation detector or the like.

[0264] The scintillator contains a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible light or ultraviolet light when irradiated. For example, those obtained by dispersing Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO, etc. in resin or ceramics can be used.

[0265] By performing imaging using infrared light or ultraviolet light, inspection functions, security functions, sensor functions, etc. can be imparted to an imaging device. For example, by performing imaging using infrared light, non-destructive inspection of products, sorting of agricultural products (such as a sugar content meter function), vein authentication, medical inspection, etc. can be performed. Also, by performing imaging using ultraviolet light, ultraviolet light emitted from a light source or a flame can be detected, and management of light sources, heat sources, production equipment, etc. can be performed.

[0266] A microlens array 673 is provided on the optical conversion layer 672. Light passing through the individual lenses of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, the condensed light can be made to enter the photoelectric conversion device 101, so that photoelectric conversion can be performed efficiently. The microlens array 673 is preferably formed of a resin or glass that is highly transparent to light of the target wavelength.

[0267] <Lamination> Next, the lamination of layer 563b and layer 563a will be described.

[0268] An insulating layer 618 and a conductive layer 619 are provided on layer 563b. The conductive layer 619 has a region embedded in the insulating layer 618. Also, the surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that their heights match respectively.

[0269] An insulating layer 631 and a conductive layer 639 are provided on layer 563a. The conductive layer 639 has a region embedded in the insulating layer 631. Also, the surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that their heights match respectively.

[0270] Here, the conductive layer 619 and the conductive layer 639 preferably have the same metal element as the main component. Also, the insulating layer 618 and the insulating layer 631 are preferably composed of the same components.

[0271] For example, for the conductive layers 619 and 639, Cu, Al, Sn, Zn, W, Ag, Pt, Au, etc. can be used. From the perspective of ease of bonding, preferably Cu, Al, W, or Au is used. Also, for the insulating layers 618 and 631, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used.

[0272] That is, it is preferable to use the same metal material shown above for each of the conductive layer 619 and the conductive layer 639. Also, it is preferable to use the same insulating material shown above for each of the insulating layer 618 and the insulating layer 631. With such a configuration, bonding can be performed with the boundary between the layer 563b and the layer 563a as the bonding position.

[0273] Note that the conductive layer 619 and the conductive layer 639 may have a multilayer structure of multiple layers. In that case, it is only necessary that the surface layer (bonding surface) is the same metal material. Also, the insulating layer 618 and the insulating layer 631 may also have a multilayer structure of multiple layers. In that case, it is only necessary that the surface layer (bonding surface) is the same insulating material.

[0274] By this bonding, electrical connection of the conductive layer 619 and the conductive layer 639 can be obtained. Also, a connection having the mechanical strength of the insulating layer 618 and the insulating layer 631 can be obtained.

[0275] For the bonding between metal layers, a surface activation bonding method can be used, in which the oxide film on the surface and the adsorbed layer of impurities are removed by sputtering treatment, etc., and the cleaned and activated surfaces are brought into contact and bonded. Or, a diffusion bonding method, etc., in which the surfaces are bonded by using both temperature and pressure, can be used. Since bonding occurs at the atomic level in both cases, excellent bonding can be obtained not only electrically but also mechanically.

[0276] In addition, for the bonding between insulating layers, after obtaining high flatness by polishing or the like, hydrophilic surfaces treated with oxygen plasma or the like are brought into contact with each other for temporary bonding, and a hydrophilic bonding method such as performing permanent bonding by dehydration through heat treatment can be used. Since the hydrophilic bonding method also causes bonding at the atomic level, a mechanically excellent bond can be obtained.

[0277] When laminating layer 563b and layer 563a, since an insulating layer and a metal layer are mixed on each bonding surface, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.

[0278] For example, a method such as cleaning the surface after polishing, performing an antioxidant treatment on the surface of the metal layer, and then performing a hydrophilic treatment for bonding can be used. Also, the surface of the metal layer may be made of a metal with low oxidation resistance such as Au, and a hydrophilic treatment may be performed. In addition, a bonding method other than the methods described above may be used.

[0279] By the above lamination, the circuit included in layer 563b and the elements of pixel 14 included in layer 563a can be electrically connected.

[0280] <Modification Example of Stacked Structure 1> FIG. 23 is a modification example of the stacked structure shown in FIG. 21, in which the configuration of the photoelectric conversion device 101 included in layer 561 and a partial configuration of layer 563a are different, and there is also a bonding surface between layer 561 and layer 563a.

[0281] Layer 561 includes a photoelectric conversion device 101, insulating layers 661, 662, 664, 665, and conductive layers 685, 686.

[0282] The photoelectric conversion device 101 is a pn junction type photodiode, and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. Here, an example in which a pn junction type photodiode is formed on a silicon substrate is shown. The photoelectric conversion device 101 is an embedded type photodiode, and the dark current can be suppressed and the noise can be reduced by a thin p-type region (a part of the layer 565b) provided on the surface side (current extraction side) of the layer 565a.

[0283] The insulating layer 661, the conductive layers 685 and 686 have a function as a bonding layer. The insulating layer 662 has a function as an interlayer insulating film and a planarization film. The insulating layer 664 has a function as an element isolation layer.

[0284] A groove for separating pixels is provided in the silicon substrate, and the insulating layer 665 is provided on the upper surface of the silicon substrate and in the groove. By providing the insulating layer 665, carriers generated in the photoelectric conversion device 101 can be suppressed from flowing out to adjacent pixels. In addition, the insulating layer 665 also has a function of suppressing the intrusion of stray light. Therefore, color mixing can be suppressed by the insulating layer 665. Note that an antireflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0285] The insulating layer 664 can be formed using the LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed using the STI (Shallow Trench Isolation) method or the like. As the insulating layer 665, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as a polyimide resin or an acrylic resin can be used. Note that the insulating layer 665 may have a multilayer structure. In addition, a space may be provided in a part of the insulating layer 665. The space may contain a gas such as air or an inert gas. In addition, the space may be in a reduced pressure state.

[0286] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions embedded in the insulating layer 661. Also, the surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that their heights match respectively.

[0287] In the layer 563a, an insulating layer 638 is formed on the insulating layer 637. Also, a conductive layer 683 electrically connected to one of the source or drain of the transistor 102 and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0288] The insulating layer 638 and the conductive layers 683 and 684 function as bonding layers. The conductive layers 683 and 684 have regions embedded in the insulating layer 638. Also, the surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that their heights match respectively.

[0289] Here, the conductive layers 683, 684, 685, and 686 are the same bonding layers as the aforementioned conductive layers 619 and 639. Also, the insulating layers 638 and 661 are the same bonding layers as the aforementioned insulating layers 618 and 631.

[0290] Therefore, by bonding the conductive layer 683 and the conductive layer 685, one of the source or drain of the transistor 102 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101. Also, by bonding the conductive layer 684 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 can be electrically connected to the wiring 111 (see FIG. 10A). Also, by bonding the insulating layer 638 and the insulating layer 661, an electrical and mechanical junction between the layer 561 and the layer 563a can be made.

[0291] Further, FIG. 24 shows a modified example different from the above, in which the transistor 102 is provided in the layer 561. In this configuration, one of the source or drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source or drain acts as the node N. In this configuration, complete transfer of the charges accumulated in the photoelectric conversion device 101 is possible, and an imaging device with less noise can be obtained.

[0292] Here, the other of the source or drain of the transistor 102 included in the layer 561 is electrically connected to the conductive layer 692. Also, the gate of the transistor 104 included in the layer 563 is electrically connected to the conductive layer 691. The conductive layers 691 and 692 are the same bonding layers as the conductive layers 619 and 639 described above.

[0293] <Stacked Structure 2> FIG. 25 is an example of a cross-sectional view of a laminate having layers 560, 561, 562, and 563 and not having a bonding surface. An Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Since the configurations of the layer 563, the layer 561, and the layer 560 are the same as those shown in FIG. 21, the description thereof is omitted here.

[0294] <Layer 562> The layer 562 is formed on the layer 563. The layer 562 has an OS transistor. Here, the transistor 102 and the transistor 105 are shown. In the cross-sectional view shown in FIG. 25, the electrical connection between the two is not shown.

[0295] The layer 562 is provided with insulating layers 621, 622, 623, 624, 625, 626, and 628. Also, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 111 (see FIG. 10A).

[0296] The insulating layer 621 has a function as a blocking layer. The insulating layers 622, 623, 625, 626, and 628 have functions as an interlayer insulating film and a planarizing film. The insulating layer 624 has a function as a protective film.

[0297] As the blocking layer, it is preferable to use a film having a function of preventing the diffusion of hydrogen. In an Si device, hydrogen is required to terminate dangling bonds, but hydrogen in the vicinity of the OS transistor becomes one of the factors generating carriers in the oxide semiconductor layer and reduces reliability. Therefore, it is preferable to provide a hydrogen blocking film between the layer on which the Si device is formed and the layer on which the OS transistor is formed.

[0298] As the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0299] The other of the source or drain of transistor 105 is electrically connected to the gate of transistor 225 via a plug. Also, the conductive layer 627 is electrically connected to the wiring 111 (see FIG. 10A).

[0300] One of the source or drain of transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in layer 561. The conductive layer 627 is electrically connected to the anode of the photoelectric conversion device 101 included in layer 561.

[0301] The details of the OS transistor are shown in FIG. 26A. The OS transistor shown in FIG. 26A has a self-aligned structure in which an insulating layer is provided on a stack of an oxide semiconductor layer and a conductive layer, and source electrode 705 and drain electrode 706 are formed by providing an opening reaching the oxide semiconductor layer.

[0302] The OS transistor can be configured to include a channel formation region 708, a source region 703, and a drain region 704 formed in an oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may be further provided in the opening.

[0303] As shown in FIG. 26B, the OS transistor may have a self-aligned structure in which the source region 703 and the drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask.

[0304] Alternatively, as shown in FIG. 26C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0305] Although the OS transistor is shown with a back gate 735, it may have a structure without a back gate. The back gate 735 may be electrically connected to the front gate of the transistor provided opposite thereto, as in the cross-sectional view in the channel width direction of the transistor shown in FIG. 26D. Note that FIG. 26D shows an example of the cross-section taken along B1 - B2 of the transistor in FIG. 26A, and the same applies to transistors with other structures. Also, a configuration may be adopted in which a fixed potential different from that of the front gate can be supplied to the back gate 735.

[0306] <Modification Example of the Stacked Structure 2> FIG. 27 shows a modification example of the stacked structure shown in FIG. 25. The configuration of the photoelectric conversion device 101 included in the layer 561 and a partial configuration of the layer 562 are different, and there is a bonding surface between the layer 561 and the layer 562.

[0307] The photoelectric conversion device 101 included in the layer 561 is a pn junction type photodiode and has the same configuration as that shown in FIG. 23.

[0308] In layer 562, an insulating layer 648 is formed on the insulating layer 628. Also, a conductive layer 688 electrically connected to one of the source or drain of the transistor 102 and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0309] The insulating layer 648, and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have regions embedded in the insulating layer 648. Also, the surfaces of the insulating layer 648 and the conductive layers 688 and 689 are planarized so that their heights are the same.

[0310] Here, the conductive layers 688 and 689 are the same bonding layers as the above-described conductive layers 619 and 639. Also, the insulating layer 648 is the same bonding layer as the above-described insulating layers 618 and 631.

[0311] Therefore, by bonding the conductive layer 688 and the conductive layer 685, one of the source or drain of the transistor 102 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101. Also, by bonding the conductive layer 689 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 can be electrically connected to the wiring 111 (see FIG. 10A). Also, by bonding the insulating layer 648 and the insulating layer 661, electrical and mechanical bonding between the layer 561 and the layer 562 can be performed.

[0312] When stacking a plurality of Si devices, polishing processes and bonding processes are required multiple times. Therefore, there are problems such as a large number of processes, the need for dedicated equipment, and low yield, and the manufacturing cost is also high. Since the OS transistor can be formed by stacking on a semiconductor substrate on which the device is formed, the bonding process can be reduced.

[0313] Note that a configuration in which the transistor 102 is provided in the layer 561 shown in FIG. 24 may be applied to the said configuration.

[0314] FIG. 28 shows a configuration in which transistors 102, 105, etc. which are elements of a pixel circuit and transistors 278 and a capacitor 279 which are elements of a memory cell 150 are provided in layer 563a. In this case, the transistors included in the memory cell 150 can be formed of Si transistors. As the transistors 278 and the capacitor 279, if the combination of the transistor 271 and the capacitor 274 of the memory cell 150a shown in FIG. 11B is used, it can operate as a DRAM. Also, as the transistors 278 and the capacitor 279, if the combination of the transistor 276 and the capacitor 277 of the memory cell 150d shown in FIG. 12B or FIG. 12C is used, it can operate as a ferroelectric memory.

[0315] Also, the memory cell 150 can be provided in layer 562 which has an OS transistor. FIG. 29 shows a configuration in which transistors 102, 105, etc. which are elements of a pixel circuit and transistors 278 and a capacitor 279 which are elements of a memory cell 150 are provided on the same plane of layer 562. As the transistors 278 and the capacitor 279, if the combination of the transistor 271 and the capacitor 274 of the memory cell 150a shown in FIG. 11B is used, it can operate as a DOSRAM. Also, as the transistors 278 and the capacitor 279, if the combination of the transistor 276 and the capacitor 277 of the memory cell 150d shown in FIG. 12B or FIG. 12C is used, it can operate as a ferroelectric memory.

[0316] Also, FIG. 30 shows a stacked configuration in layer 562 such that there is an overlapping region between transistors 102, 104, 105, etc. which are elements of a pixel circuit and transistors 272, 273, etc. which are elements of the memory cell 150b shown in FIG. 11C or the memory cell 150c shown in FIG. 11D. With such a configuration, the circuit area can be reduced, and a highly functional and compact imaging device can be formed. Also, since the wiring length of the wiring for electrically connecting between the stacked elements can be shortened, operation at high speed and with low power consumption becomes possible.

[0317] Note that the configuration in which the transistor 102 is provided in the layer 561 shown in FIG. 24 may be applied to the configurations shown in FIGS. 29 and 30. Further, the configuration of the photoelectric conversion device 101 shown in FIG. 25 may be applied.

[0318] <Package, Module> FIG. 32A is an external perspective view of a package containing an image sensor chip. The package is a CSP (Chip Size Package) and has a bare chip 450 of an image sensor, a cover glass 440, an adhesive 430 for bonding the two, and the like.

[0319] The electrode pads 425 provided outside the pixel array 455 are electrically connected to the back surface electrode 415 via the through electrodes 420. The electrode pads 425 are electrically connected to the circuit constituting the image sensor by wiring or wires. Note that the bare chip 450 may be a stacked chip stacked with circuits having various functions.

[0320] In FIG. 32, a BGA (Ball Grid Array) in which bumps 410 are formed on the back surface electrode 415 by solder balls is illustrated. Note that it is not limited to BGA, and it may be LGA (Land Grid Array), PGA (Pin Grid Array), or the like. Alternatively, a package in which the bare chip 450 is mounted on a QFN (Quad Flat No-lead package) or QFP (Quad Flat Package) may be used.

[0321] Further, FIG. 32B is an external perspective view of the upper surface side of a camera module in which an image sensor chip and a lens are combined. The camera module has a lens cover 460, a plurality of lenses 470, and the like on the configuration of FIG. 32A. Further, an optical filter 480 that absorbs light of a specific wavelength is provided between the lens 470 and the cover glass 440 as necessary. As the optical filter 480, for example, an infrared cut filter or the like can be used in the case of an image sensor mainly for visible light imaging.

[0322] By housing the image sensor chip in a package in the form described above, it becomes easier to mount it on a printed circuit board or the like, and the image sensor chip can be incorporated into various semiconductor devices and electronic equipment.

[0323] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0324] (Embodiment 4) As electronic equipment that can use the imaging device according to one aspect of the present invention, display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game machines including portable types, portable data terminals, electronic book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, etc. can be mentioned. Specific examples of these electronic equipment are shown in FIGS. 33A to 33F.

[0325] FIG. 33A shows an example of a mobile phone, which has a housing 981, a display unit 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone is provided with a touch sensor on the display unit 982. Any operation such as making a call or inputting characters can be performed by touching the display unit 982 with a finger or a stylus. The imaging device and its operation method according to one aspect of the present invention can be applied to the mobile phone.

[0326] FIG. 33B is a portable data terminal, which has a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Information can be input and output by the touch panel function of the display unit 912. Also, characters or the like can be recognized from the image acquired by the camera 919, and the characters can be output as audio by the speaker 913. The imaging device and its operation method according to one aspect of the present invention can be applied to the portable data terminal.

[0327] Figure 33C is a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, etc. The camera unit 952 is provided with a rotation mechanism, etc., and by installing it on the ceiling, imaging of the entire surrounding area can be achieved. The imaging device and its operation method according to one aspect of the present invention can be applied to the elements for image acquisition in the camera unit. Note that the surveillance camera is a common name and does not limit the use. For example, a device having the function of a surveillance camera is also called a camera or a video camera.

[0328] Figure 33D is a drive recorder, which includes a frame 941, a camera 942, operation buttons 943, mounting parts 944, etc. By installing it on the front window of an automobile via the mounting parts 944, the scenery ahead during driving can be recorded. Note that a display panel for displaying the recorded image is provided on the back surface (not shown). The imaging device and its operation method according to one aspect of the present invention can be applied to the camera 942.

[0329] Figure 33E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting part 967, a lens 965, etc. The imaging device and its operation method according to one aspect of the present invention can be applied to the digital camera.

[0330] Figure 33F is a wristwatch-type information terminal, which includes a display part 932, a housing-cum-wristband 933, a camera 939, etc. The display part 932 is provided with a touch panel for operating the information terminal. The display part 932 and the housing-cum-wristband 933 have flexibility and excellent wearability on the body. The imaging device and its operation method according to one aspect of the present invention can be applied to the information terminal.

[0331] Figure 34A is a drone, which is an example of a moving body, and includes a frame 921, arms 922, rotors 923, blades 924, a camera 925, and a battery 926, etc., and has functions such as autonomous flight and hovering in the air. The imaging device and its operation method according to one aspect of the present invention can be applied to the camera 925.

[0332] Figure 34B illustrates an external view of an automobile as an example of a moving object. The automobile 890 has a plurality of cameras 891 and the like, and can acquire information about the front, rear, left, right, and above of the automobile 890. The imaging device and its operation method according to an aspect of the present invention can be applied to the camera 891. Further, the automobile 890 is provided with various sensors (not shown) such as an infrared radar, a millimeter-wave radar, and a laser radar. The automobile 890 analyzes the images acquired by the camera 891 in a plurality of imaging directions 892, determines the surrounding traffic conditions such as the presence or absence of guardrails or pedestrians, and can perform automatic driving. Further, it can be used in a system for performing road guidance, danger prediction, and the like.

[0333] In the imaging device according to an aspect of the present invention, by performing arithmetic processing such as a neural network on the obtained image data, for example, processing such as increasing the resolution of the image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for the purpose of automatic driving, etc.), image compression, image correction (widening the dynamic range), restoring the image of a lensless image sensor, positioning, character recognition, and reducing specular reflections can be performed.

[0334] Note that in the above description, the automobile may be any of an automobile having an internal combustion engine, an electric vehicle, a hydrogen vehicle, and the like. Further, the moving object is not limited to an automobile. For example, examples of the moving object include a train, a monorail, a ship, and an aircraft (helicopter, unmanned aerial vehicle, airplane, rocket), and a computer according to an aspect of the present invention can be applied to these moving objects to provide a system using artificial intelligence.

Explanation of reference numerals

[0335] 10: Layer, 11: Pixel section, 12: Pixel block, 13: Pixel block, 14: Pixel, 15: Pixel circuit, 16: Memory circuit, 20: Layer, 21: Arithmetic unit, 22: Binarization circuit, 23: Multiplication and addition circuit, 23a: Multiplier, 23b: Adder, 24: Binarization circuit, 24S: Selection transistor, 25: Circuit, 26a: Addition circuit, 26b: Binarization circuit, 31: Load driver, 32: Column driver, 33: Load driver, 34: Column driver, 35: Circuit, 36: Circuit, 37: Circuit, 40: Circuit, 40S: Switch, 41: Circuit, 41S: Switch, 42S: Switch, 43S: Switch, 44S: Switch, 45S: Switch, 51: Register, 52: Register, 60: Circuit, 71: Curve, 72: Curve, 101: Photoelectric conversion device, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Capacitor, 107: Transistor, 108: Transistor, 109: Transistor, 111: Wiring, 112: Wiring, 113: Wiring, 114: Wiring, 115: Wiring, 116: Wiring, 117: Wiring, 118: Wiring, 119: Wiring, 150: Memory cell, 150a: Memory cell, 150b: Memory cell, 150c: Memory cell, 150d: Memory cell, 170: Back gate wiring, 175: Metal oxide layer, 180: Source-drain wiring, 185: Gate wiring, 190: Wiring, 223: Transistor, 224: Transistor, 225: Transistor, 271: Transistor, 272: Transistor, 273: Transistor, 274: Capacitor, 275: Capacitor, 276: Transistor, 277: Capacitor, 278: Transistor, 279: Capacitor, 410: Bump, 415: Back surface electrode, 420: Through electrode, 425: Electrode pad, 430: Adhesive, 440: Cover glass, 450: Bare chip, 455: Pixel array, 460: Lens cover, 470: Lens, 480: Optical filter, 545: Semiconductor layer, 546: Insulating layer, 560: Layer, 561: Layer, 562: Layer, 562a: Layer, 562b: Layer, 563: Layer, 563a: Layer, 563b: Layer, 563c: Layer, 565a: Layer, 565b: Layer, 566a: Layer, 566b: Layer, 566c: Layer, 566d: Layer, 567a: Layer, 567b: Layer, 567c: Layer, 567d: Layer, 567e: Layer, 611: Silicon substrate, 612: Insulating layer, 613: Insulating layer,614: Insulating layer, 616: Insulating layer, 617: Insulating layer, 618: Insulating layer, 619: Conductive layer, 621: Insulating layer, 622: Insulating layer, 623: Insulating layer, 624: Insulating layer, 625: Insulating layer, 626: Insulating layer, 627: Conductive layer, 628: Insulating layer, 631: Insulating layer, 632: Silicon substrate, 633: Insulating layer, 634: Insulating layer, 635: Insulating layer, 636: Conductive layer, 637: Insulating layer, 638: Insulating layer, 639: Conductive layer, 648: Insulating layer, 651: Insulating layer, 652: Insulating layer, 653: Insulating layer, 654: Insulating layer, 655: Conductive layer, 661: Insulating layer, 662: Insulating layer, 664: Insulating layer, 665: Insulating layer, 671: Light-shielding layer, 672: Optical conversion layer, 672B: Color filter, 672G: Color filter, 672IR: Infrared filter, 672R: Color filter, 672UV: Ultraviolet filter, 673: Microlens array, 683: Conductive layer, 684: Conductive layer, 685: Conductive layer, 686: Conductive layer, 688: Conductive layer, 689: Conductive layer, 691: Conductive layer, 692: Conductive layer, 701: Gate electrode, 702: Gate insulating film, 703: Source region, 704: Drain region, 705: Source electrode, 706: Drain electrode, 707: Oxide semiconductor layer, 708: Channel formation region, 735: Back gate, 890: Automobile, 891: Camera, 892: Imaging direction, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 921: Frame, 922: Arm, 923: Rotor, 924: Blade, 925: Camera, 926: Battery, 932: Display unit, 933: Housing-cum-wristband, 939: Camera, 941: Frame, 942: Camera, 943: Operation button, 944: Component, 951: Support base, 952: Camera unit, 953: Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens, 967: Light-emitting part, 981: Housing, 982: Display unit, 983: Operation button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera,

Claims

Claim 1 An imaging device having a plurality of pixel blocks, wherein the pixel block has a first layer and a second layer, the first layer has a region overlapping with the second layer, the pixel block, the first layer has a plurality of pixel circuits and a plurality of first storage circuits, the second layer has a plurality of multiplication-and-addition circuits, a plurality of first binarization circuits, a plurality of second binarization circuits, a first load driver and a first column driver for driving the plurality of pixel circuits, and a second load driver and a second column driver for driving the plurality of first storage circuits, the pixel circuit and the first storage circuit have transistors having a metal oxide in a channel formation region, the first storage circuit has a memory cell, the memory cell has a capacitor having a ferroelectric layer.

Images