Chemical solution

Abstract

To improve the yield of a semiconductor device.SOLUTION: A chemical solution according to the present invention includes a mixed acid and an organic amine, polyethyleneimine. The mixed acid includes an inorganic acid, an oxidizing agent, a carboxylic acid, and water. The concentration of polyethyleneimine in the chemical solution is in the range of 0.05 wt% to 10 wt%.SELECTED DRAWING: None

Description

Technical Field

[0001] The embodiment relates to a chemical solution.

Background Art

[0002] A NAND-type flash memory including three-dimensionally stacked memory cells is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve the yield of semiconductor devices.

Means for Solving the Problems

[0005] The chemical solution of the embodiment includes a mixed acid and polyethyleneimine which is an organic amine. The mixed acid includes an inorganic acid, an oxidizing agent, a carboxylic acid, and water. The concentration of polyethyleneimine in the chemical solution is in the range of 0.05 wt% to 10 wt%.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The embodiments illustrate devices and methods for embodying the technical idea of the invention. The drawings are schematic or conceptual, and dimensions, ratios, etc. in each drawing are not necessarily the same as the actual ones. The technical idea of the present invention is not specified by the shape, structure, arrangement, etc. of the components.

[0008] In the following description, components having substantially the same function and configuration are denoted by the same reference numerals. The numbers after the characters constituting the reference numerals are referred to by the reference numerals including the same characters, and are used to distinguish between elements having the same configuration. Similarly, the characters after the numbers constituting the reference numerals are referred to by the reference numerals including the same numbers, and are used to distinguish between elements having the same configuration.

[0009] [Embodiment] The chemical solution according to the embodiment is an etching solution used for etching a layer containing molybdenum. The chemical solution according to the embodiment is used, for example, for etching a layer containing molybdenum formed on a high aspect ratio structure in the manufacturing process of the semiconductor device 1. Hereinafter, the chemical solution according to the embodiment and the semiconductor device 1 according to the embodiment will be described in order.

[0010] [1] Composition of the chemical solution The chemical solution according to the embodiment contains a mixed acid and polyethyleneimine (PEI). The mixed acid contains an inorganic acid, an oxidizing agent, a carboxylic acid, and water.

[0011] The concentration of polyethyleneimine in the chemical solution is in the range of 0.05 wt% to 10 wt%. When the concentration of polyethyleneimine is within this range, there is a corrosion prevention effect on molybdenum, so that the effect of reducing the etching rate is achieved. The concentration of polyethyleneimine is more preferably in the range of 1 wt% to 3 wt%.

[0012] The concentration of the inorganic acid in the chemical solution is, for example, in the range of 40 wt% to 80 wt%. When the concentration of the inorganic acid is within this range, due to the complexing effect, an etching effect is achieved. The inorganic acid can be at least one selected from the group consisting of phosphoric acid and sulfuric acid.

[0013] The concentration of the oxidizing agent in the chemical solution is, for example, 5 wt% or less. When the concentration of the oxidizing agent is within this range, due to the oxidizing effect, an effect of making it possible to complex with the inorganic acid is achieved. The oxidizing agent can be at least one selected from the group consisting of nitric acid and hydrogen peroxide.

[0014] The concentration of the carboxylic acid in the chemical solution is, for example, in the range of 0.1 wt% to 45 wt%. When the concentration of the carboxylic acid is within this range, due to the interference effect, a composition stabilizing effect is achieved. The carboxylic acid can be at least one selected from the group consisting of acetic acid, lactic acid, propionic acid, butyric acid, malonic acid, and citric acid.

[0015] The concentration of water in the chemical solution is, for example, in the range of 5 wt% to 30 wt%, preferably 20 wt% or less.

[0016] The average molecular weight of PEI in the chemical solution is 100 or more and 1800 or less. Hereinafter, the weight average molecular weight of PEI is also referred to as "PEI molecular weight". In the chemical solution, it is preferable that the concentration of polyethyleneimine is in the range of 0.15 wt% to 0.5 wt% and the PEI molecular weight is 100 or more and 600 or less, or the concentration of polyethyleneimine is in the range of 0.3 wt% to 0.5 wt% and the PEI molecular weight is 100 or more and 1800 or less. Further, in the chemical solution, it is more preferable that the concentration of polyethyleneimine is in the range of 0.3 wt% to 0.5 wt% and the PEI molecular weight is 100 or more and 600 or less.

[0017] The polyethyleneimine contained in the chemical solution according to the embodiment includes, for example, monomer units having ethyleneimine as a repeating unit. The polyethyleneimine may be a polymer composed only of the above monomer units, a copolymer containing other monomers, or a mixture thereof. In the polyethyleneimine, the proportion occupied by the portion composed of monomer units having ethyleneimine as a repeating unit is preferably 95 mol% or more, and more preferably 100 mol%. That is, it is most preferable that the polyethyleneimine contained as an additive in the chemical solution is a polymer composed only of monomer units having ethyleneimine as a repeating unit.

[0018] Whether or not the chemical solution contains polyethyleneimine can be determined from analysis using infrared spectroscopy (FT-IR: Fourier Transform Infrared Spectroscopy) and nuclear magnetic resonance (NMR: Nuclear Magnetic Resonance). Further, the weight average molecular weight of the polyethyleneimine contained in the chemical solution is determined by gel permeation chromatography (GPC: Gel Permeation Chromatography).

[0019] [2] Configuration of the semiconductor device 1 [2-1] Overall configuration of the semiconductor device 1 FIG. 1 is a block diagram showing an example of the overall configuration of the semiconductor device 1 according to the embodiment. The semiconductor device 1 is a NAND type flash memory capable of storing data non-volatilely and is controlled by an external memory controller 2. As shown in FIG. 1, the semiconductor device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0020] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer of 1 or more). A block BLK is a set of a plurality of memory cells capable of storing data non-volatily, and is used, for example, as an erasure unit of data. In addition, the memory cell array 10 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0021] The command register 11 holds the command CMD received by the semiconductor device 1 from the memory controller 2. The command CMD includes, for example, an instruction for causing the sequencer 13 to execute a read operation, a write operation, an erase operation, or the like.

[0022] The address register 12 holds the address information ADD received by the semiconductor device 1 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used for selecting a block BLK, a word line, and a bit line, respectively.

[0023] The sequencer 13 controls the operation of the entire semiconductor device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD held in the command register 11 to execute a read operation, a write operation, an erase operation, or the like.

[0024] The driver module 14 generates a voltage used in a read operation, a write operation, an erase operation, or the like. Then, the driver module 14 applies the generated voltage to a signal line corresponding to the selected word line based on, for example, the page address PAd held in the address register 12.

[0025] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BAd held in the address register 12. Then, the row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0026] In the write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. Also, in the read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 2 as the read data DAT.

[0027] Note that the semiconductor device 1 and the memory controller 2 may constitute one semiconductor device by their combination. Examples of such a semiconductor device include a memory card such as an SD TM card, and an SSD (solid state drive), etc.

[0028] [2-2] Circuit configuration of the memory cell array 10 FIG. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array 10 included in the semiconductor device 1 according to the embodiment. FIG. 2 shows one block BLK among the plurality of blocks BLK included in the memory cell array 10. As shown in FIG. 2, the block BLK includes, for example, five string units SU0 to SU4.

[0029] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage layer, and holds data non-volatilely. Each of the selection transistors ST1 and ST2 is used for the selection of the string unit SU during various operations.

[0030] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the selection transistor ST1 is connected to the associated bit line BL. The source of the selection transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the selection transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the selection transistor ST2 is connected to the source line SL.

[0031] In the same block BLK, the control gates of the memory cell transistors MT0 to MT7 are respectively connected to word lines WL0 to WL7. The gates of the plurality of selection transistors ST1 in the string unit SU0 are connected to the selection gate line SGD0. The gates of the plurality of selection transistors ST1 in the string unit SU1 are connected to the selection gate line SGD1. The gates of the plurality of selection transistors ST1 in the string unit SU2 are connected to the selection gate line SGD2. The gates of the plurality of selection transistors ST1 in the string unit SU3 are connected to the selection gate line SGD3. The gates of the plurality of selection transistors ST1 in the string unit SU4 are connected to the selection gate line SGD4. The gates of the plurality of selection transistors ST2 are connected to the selection gate line SGS.

[0032] Different column addresses are assigned to bit lines BL0 to BLm, respectively. Each bit line BL is shared by NAND strings NS to which the same column address is assigned among a plurality of blocks BLK. Each of word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared among a plurality of blocks BLK, for example.

[0033] A set of a plurality of memory cell transistors MT connected to a common word line WL within one string unit SU is called a cell unit CU, for example. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing 1-bit data is defined as "1 page of data". The cell unit CU can have a storage capacity of 2 pages of data or more depending on the number of bits of data stored in the memory cell transistor MT.

[0034] Note that the circuit configuration of the memory cell array 10 included in the semiconductor device 1 according to the embodiment may be other circuit configurations. For example, the number of string units SU included in each block BLK, the number of memory cell transistors MT included in each NAND string NS, and the number of selection transistors ST1 and ST2 can be designed to be arbitrary numbers, respectively.

[0035] [2-3] Structure of Memory Cell Array 10 Hereinafter, an example of the structure of the memory cell array 10 included in the semiconductor device 1 according to the embodiment will be described. In the drawings referred to below, the X direction corresponds to the extending direction of the word line WL, the Y direction corresponds to the extending direction of the bit line BL, and the Z direction corresponds to the vertical direction with respect to the surface of the semiconductor substrate 20 used for forming the semiconductor device 1. The hatching for the plan view is added for easy viewing of the figure, and is not necessarily related to the material or characteristics of the components with the hatching added. In the cross-sectional view, for easy viewing of the figure, the illustration of the configuration is appropriately omitted. Also, the configurations shown in each drawing are appropriately simplified.

[0036] (Planar Layout of Memory Cell Array 10) FIG. 3 is a plan view showing an example of the planar layout of the memory cell array 10 included in the semiconductor device 1 according to the embodiment. FIG. 3 shows regions corresponding to four blocks BLK0 to BLK3 included in the memory cell array 10. As shown in FIG. 3, the planar layout of the memory cell array 10 is divided, for example, in the X direction into a memory region MA, and lead-out regions HA1 and HA2. The memory cell array 10 includes, for example, a plurality of slits SLT and a plurality of slits SHE.

[0037] The memory region MA includes a plurality of NAND strings NS. The memory region MA is sandwiched in the X direction by the lead-out regions HA1 and HA2. Each of the lead-out regions HA1 and HA2 is used for connection between the stacked wiring (word lines WL and selection gate lines SGD and SGS) and the row decoder module 15. For example, each of the lead-out regions HA1 and HA2 includes a portion (terrace portion) that does not overlap with the upper wiring layer (conductor layer) of each of the selection gate line SGS, word lines WL0 to WL7, and selection gate line SGD. Then, a plurality of contacts are provided on the terrace portions of each of the selection gate line SGS, word lines WL0 to WL7, and selection gate lines SGD0 to SGD4 within each block BLK. Contacts to the stacked wiring are provided, for example, in the lead-out region HA1 for even-numbered blocks BLK and in the lead-out region HA2 for odd-numbered blocks BLK.

[0038] The plurality of slits SLT each have a portion extending along the X direction and are arranged in the Y direction. Each slit SLT crosses the memory region MA and the lead-out regions HA1 and HA2 in the X direction. Also, each slit SLT has, for example, a structure in which an insulator or a plate-like contact is embedded. And each slit SLT disconnects adjacent wirings (for example, word lines WL0 to WL7 and selection gate lines SGD and SGS) via the slit SLT. The aspect ratio of the slit SLT is, for example, 30 or more.

[0039] The plurality of slits SHE each have a portion extending along the X direction and are arranged in the Y direction. In this example, four slits SHE are arranged respectively between adjacent slits SLT. Each slit SHE traverses the memory region MA in the X direction, with one end of each slit SHE included in the extraction region HA1 and the other end included in the extraction region HA2. Also, each slit SHE has a structure in which, for example, an insulator is embedded. And each slit SHE disconnects adjacent wirings (at least the selection gate line SGD) via the slit SHE.

[0040] In the planar layout of the memory cell array 10 described above, each of the regions delimited by the slit SLT corresponds to one block BLK. Also, each of the regions delimited by the slits SLT and SHE corresponds to one string unit SU. And in the memory cell array 10, for example, the layout shown in FIG. 3 is repeatedly arranged in the Y direction.

[0041] Note that the planar layout of the memory cell array 10 included in the semiconductor device 1 according to the embodiment may be other layouts. For example, the number of slits SHE arranged between adjacent slits SLT can be designed to be any number. The number of string units SU formed between adjacent slits SLT can be changed based on the number of slits SHE arranged between adjacent slits SLT.

[0042] (Planar Layout in the Memory Region MA of the Memory Cell Array 10) FIG. 4 is a plan view showing an example of a detailed planar layout in the memory region MA of the memory cell array 10 included in the semiconductor device 1 according to the embodiment. FIG. 4 shows a region including one block BLK (that is, string units SU0 to SU4). As shown in FIG. 4, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in the memory region MA. Also, each slit SLT includes a contact LI and a spacer SP.

[0043] Each of the memory pillars MP functions as, for example, one NAND string NS. A plurality of memory pillars MP are arranged in a staggered pattern of, for example, 24 columns in the region between two adjacent slits SLT. And, for example, starting from the upper side of the paper surface, one slit SHE overlaps each of the memory pillars MP in the 5th column, the 10th column, the 15th column, and the 20th column.

[0044] The plurality of bit lines BL each have a portion extending in the Y direction and are arranged side by side in the X direction. Each bit line BL is arranged to overlap at least one memory pillar MP for each string unit SU. In this example, two bit lines BL are arranged to overlap one memory pillar MP. One of the plurality of bit lines BL overlapping the memory pillar MP is electrically connected to the memory pillar MP via a contact CV.

[0045] For example, the contact CV between the memory pillar MP in contact with the slit SHE and the bit line BL is omitted. In other words, the contact CV between the memory pillar MP and the bit line BL in contact with two different select gate lines SGD is omitted. The number and arrangement of the memory pillars MP, slits SHE, etc. between adjacent slits SLT may be other configurations and can be appropriately changed. For example, the number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0046] The contact LI is a conductor having a portion extending in the X direction. The spacer SP is an insulator provided on the side surface of the contact LI. The contact LI is sandwiched by the spacer SP. The contact LI and the conductor (for example, word lines WL0 to WL7, and select gate lines SGD and SGS) adjacent to the contact LI in the Y direction are separated and insulated by the spacer SP.

[0047] (Cross-sectional structure in the memory region MA of the memory cell array 10) FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 4, and shows an example of the cross-sectional structure in the memory region MA of the memory cell array 10 included in the semiconductor device 1 according to the embodiment. As shown in FIG. 5, the memory cell array 10 further includes, for example, a semiconductor substrate 20, conductor layers 21 to 25, and insulator layers 30 to 34.

[0048] Specifically, an insulator layer 30 is provided on the semiconductor substrate 20. Although not shown, the insulator layer 30 includes, for example, circuits corresponding to the row decoder module 15, the sense amplifier module 16, and the like.

[0049] A conductor layer 21 is provided on the insulator layer 30. The conductor layer 21 is formed, for example, in a plate shape extending along the XY plane and is used as a source line SL. The conductor layer 21 includes, for example, phosphorus-doped silicon.

[0050] An insulator layer 31 is provided on the conductor layer 21. A conductor layer 22 is provided on the insulator layer 31. The conductor layer 22 is formed, for example, in a plate shape extending along the XY plane and is used as a select gate line SGS. The conductor layer 22 includes, for example, molybdenum. The conductor layer 22 includes, for example, 99 atom% or more of molybdenum alone.

[0051] The insulator layer 32 and the conductor layer 23 are alternately stacked on the conductor layer 22. The conductor layer 23 is formed, for example, in a plate shape extending along the XY plane. The plurality of stacked conductor layers 23 are used as word lines WL0 to WL7 in order from the semiconductor substrate 20 side. The conductor layer 23 includes molybdenum. The conductor layer 23 includes, for example, 99 atom% or more of molybdenum alone.

[0052] An insulator layer 33 is provided on the uppermost conductor layer 23. A conductor layer 24 is provided on the insulator layer 33. The conductor layer 24 is formed, for example, in a plate shape extending along the XY plane and is used as a select gate line SGD. The conductor layer 24 contains, for example, molybdenum. The conductor layer 24 contains, for example, 99 atom% or more of molybdenum alone.

[0053] An insulator layer 34 is provided on the conductor layer 24. A conductor layer 25 is provided on the insulator layer 34. The conductor layer 25 is formed, for example, in a line shape extending in the Y direction and is used as a bit line BL. That is, in a region not shown, a plurality of conductor layers 25 are arranged along the X direction. The conductor layer 25 contains, for example, copper.

[0054] Each of the memory pillars MP extends along the Z direction and penetrates the insulator layers 31 to 33 and the conductor layers 22 to 24. The bottom of each of the memory pillars MP is in contact with the conductor layer 21. The portion where the memory pillar MP and the conductor layer 22 intersect functions as a select transistor ST2. The portion where the memory pillar MP and one conductor layer 23 intersect functions as one memory cell transistor MT. The portion where the memory pillar MP and the conductor layer 24 intersect functions as a select transistor ST1.

[0055] Also, each of the memory pillars MP contains, for example, a core member 40, a semiconductor layer 41, and a laminated film 42. The core member 40 is provided extending along the Z direction. For example, the upper end of the core member 40 is included in a layer above the conductor layer 24, and the lower end of the core member 40 reaches the conductor layer 21. The semiconductor layer 41 covers the periphery of the core member 40. At the lower part of the memory pillar MP, a part of the semiconductor layer 41 is in contact with the conductor layer 21. The laminated film 42 covers the side surface and the bottom surface of the semiconductor layer 41 except for the portion where the semiconductor layer 41 and the conductor layer 21 are in contact. The core member 40 is made of an insulating material such as silicon oxide, for example. The semiconductor layer 41 contains, for example, silicon.

[0056] On the semiconductor layer 41 within the memory pillar MP, a columnar contact CV is provided. In the illustrated region, two contacts CV corresponding to two of the six memory pillars MP are shown respectively. In the memory region MA, the contacts CV are connected to the memory pillars MP that do not overlap with the slit SHE and are not connected to the contacts CV in a region not shown.

[0057] On the contact CV, one conductor layer 25, that is, one bit line BL, is in contact. One contact CV is connected to each of the spaces separated by the slits SLT and SHE in one conductor layer 25. That is, for each of the conductor layers 25, the memory pillar MP provided between adjacent slits SLT and SHE and the memory pillar MP provided between two adjacent slits SHE are electrically connected.

[0058] The slit SLT has a portion provided, for example, along the XZ plane and divides the conductor layers 22 - 24. The contact LI within the slit SLT is provided along the slit SLT. A part of the upper end of the contact LI is in contact with the insulator layer 34. The lower end of the contact LI is in contact with the conductor layer 21. The contact LI is used, for example, as a part of the source line SL. The spacer SP is provided at least between the contact LI and the conductor layers 22 - 24. The contact LI and the conductor layers 22 - 24 are separated and insulated by the spacer SP.

[0059] The slit SHE has a portion provided, for example, along the XZ plane and divides at least the conductor layer 24. The upper end of the slit SHE is in contact with the insulator layer 34. The lower end of the slit SHE is in contact with the insulator layer 33. The slit SHE contains an insulator such as silicon oxide, for example. The upper end of the slit SHE and the upper end of the slit SLT may or may not be aligned. Also, the upper end of the slit SHE and the upper end of the memory pillar MP may or may not be aligned.

[0060] (Detailed cross-sectional structure in the memory region MA of the memory cell array 10) FIG. 6 is an enlarged view of region VI in FIG. 5, and shows an example of a detailed cross-sectional structure in the memory region MA of the memory cell array 10 included in the semiconductor device 1 according to the embodiment. Specifically, FIG. 6 shows the structures of the memory pillar MP and the conductor layer 23 at the portion where the conductor layer 23 and the memory pillar MP intersect. As shown in FIG. 6, the stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a cover insulating film 45. The conductor layer 23 includes, for example, a conductor 50 and a barrier metal 51. The memory cell array 10 further includes a block insulating film 46.

[0061] The tunnel insulating film 43 is provided on the side surface of the semiconductor layer 41. The insulating film 44 is provided on the side surface of the tunnel insulating film 43. The cover insulating film 45 is provided on the side surface of the insulating film 44. The cover insulating film 45 is divided by the block insulating film 46 at the portion where the memory pillar MP and the conductor layer 23 intersect. The block insulating film 46 is provided between the conductor layer 23 and the insulator layer 32 and between the conductor layer 23 and the insulating film 44. The conductor 50 is embedded in a space surrounded by three sides by the block insulating film 46. The conductor 50 and the block insulating film 46 are separated by the barrier metal 51.

[0062] As the tunnel insulating film 43, an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride film is used. The cover insulating film 45 contains, for example, silicon oxide. The insulating film 44 contains, for example, silicon nitride. The block insulating film 46 contains, for example, aluminum oxide (Al2O3). The block insulating film 46 is also used as a seed layer for forming the conductor 50. The conductor 50 contains molybdenum (Mo). The conductor 50 may contain impurities. Examples of the impurities that can be contained in the conductor 50 include oxygen (O), hydrogen (H), etc. The barrier metal 51 contains, for example, titanium nitride (TiN).

[0063] Note that the barrier metal 51 may be omitted. The block insulating film 46 may be provided on the side surface portion of the memory pillar MP instead of the cover insulating film 45. The structures of the conductor layer 22 and the memory pillar MP at the intersecting portion of the conductor layer 22 and the memory pillar MP, and the structures of the conductor layer 24 and the memory pillar MP at the intersecting portion of the conductor layer 24 and the memory pillar MP are the same as the structures of the conductor layer 23 and the memory pillar MP at the intersecting portion of the conductor layer 23 and the memory pillar MP.

[0064] (Cross-sectional structure of memory pillar MP) FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 5, and shows an example of the cross-sectional structure of the memory pillar MP in the semiconductor device 1 according to the embodiment. Specifically, FIG. 7 shows the cross-sectional structure of the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductor layer 23. As shown in FIG. 7, in the cross-section including the conductor layer 23, the core member 40 is provided at the central portion of the memory pillar MP. The semiconductor layer 41 surrounds the side surface of the core member 40. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 46 surrounds the side surface of the insulating film 44. The barrier metal 51 surrounds the side surface of the block insulating film 46. The conductor layer 23 surrounds the side surface of the barrier metal 51.

[0065] The structure of the conductor layer 22 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductor layer 22, and the structure of the conductor layer 24 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductor layer 24 are each the same as the structure of the conductor layer 23 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductor layer 23. In each of the memory pillars MP described above, the semiconductor layer 41 is used as the channel (current path) of the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The insulating film 44 is used as the charge storage layer of the memory cell transistor MT. The semiconductor device 1 can cause a current to flow between the bit line BL and the contact LI through the memory pillar MP by turning on the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2.

[0066] [3] Manufacturing method of the semiconductor device 1 FIG. 8 is a flowchart showing an example of a manufacturing method of the semiconductor device 1 according to the embodiment. Each of FIGS. 9 to 16 is a cross-sectional view showing an example of a cross-sectional structure during the manufacturing of the semiconductor device 1 according to the embodiment, and shows the same region as FIG. 5. Hereinafter, with appropriate reference to FIG. 8, an example of a manufacturing process related to the formation of the multilayer wiring of the memory cell array 10 in the semiconductor device 1 according to the embodiment will be described. As shown in FIG. 8, the manufacturing method of the semiconductor device 1 according to the embodiment sequentially executes, for example, the processes of steps S10 to S17.

[0067] In the process of step S10, as shown in FIG. 9, the sacrificial members and the insulator layers are alternately laminated. Briefly stated, an insulator layer 30 including a circuit (not shown) corresponding to the row decoder module 15 or the like is formed on the semiconductor substrate 20. A conductor layer 21 is formed on the insulator layer 30. An insulator layer 31 and a sacrificial member 60 are sequentially formed on the conductor layer 21. A sacrificial member 61 and an insulator layer 32 are alternately formed on the sacrificial member 60. An insulator layer 33 and a sacrificial member 62 are sequentially formed on the uppermost sacrificial member 61. An insulator layer 35 is formed on the sacrificial member 62. Note that the sacrificial member 60 is associated with the select gate line SGS. The sacrificial member 61 is associated with the word line WL. The sacrificial member 62 is associated with the select gate line SGD. Each of the sacrificial members 60, 61, and 62 is, for example, silicon nitride.

[0068] In the process of step S11, as shown in FIG. 10, a memory hole MH is formed. Specifically, a mask having openings in regions corresponding to a plurality of memory pillars MP is formed. Then, a plurality of memory holes MH are formed by anisotropic etching using the mask. The memory hole MH penetrates each of the insulator layers 31, 32, 33, and 35, and the sacrificial members 60, 61, and 62. Further, the bottom of the memory hole MH reaches the conductor layer 21.

[0069] In the process of step S12, as shown in FIG. 11, a memory pillar MP is formed. Specifically, a cover insulating film 45, an insulating film 44, and a tunnel insulating film 43 are sequentially formed on the side surfaces and the bottom surface of a plurality of memory holes MH. Then, a part of the cover insulating film 45, the insulating film 44, and the tunnel insulating film 43 provided at the bottom of the memory hole MH is removed, and a semiconductor layer 41 and a core member 40 are formed in the memory hole MH. Then, a part of the core member 40 provided above the memory hole is removed, and a semiconductor layer 41 is formed in the part where a part of the core member 40 is removed. Thereby, the structure of a plurality of memory pillars MP is formed. Thereafter, an insulator layer 36 is formed on the insulator layer 35 and the plurality of memory pillars MP. The insulator layer 36 protects the upper part of the memory pillar MP. The insulator layers 35 and 36 are included in the insulator layer 34 shown in FIG. 5.

[0070] In the process of step S13, as shown in FIG. 12, a slit SLT is formed. Specifically, a mask with an opening in a region corresponding to the slit SLT is formed by photolithography or the like. Then, an anisotropic etching using the mask forms a slit SLT that divides each of the insulator layers 31, 32, 33, 35, and 36, and the sacrificial members 60, 61, and 62. Also, the bottom of the slit SLT reaches, for example, the conductor layer 21. Note that after the formation of the slit SLT, a process of forming a protective film for the conductor layer 21 exposed at the bottom of the slit SLT may be executed.

[0071] In the process of step S14, as shown in FIG. 13, the sacrificial members 60, 61, and 62 are removed and formed. Specifically, in the process of step S14, a wet etching process using hot phosphoric acid or the like is executed. More specifically, the sacrificial members 60, 61, and 62 are selectively removed by supplying hot phosphoric acid or the like through the slit SLT. Although not shown, the cover insulating film 45 provided at a portion in contact with any of the sacrificial members 60, 61, and 62 in each memory pillar MP is removed. The structure in which the sacrificial members 60, 61, and 62 are removed is supported by a plurality of memory pillars MP or the like.

[0072] In the process of step S15, as shown in FIG. 14, the conductor 50 is formed. Specifically, although not shown, first, the block insulating film 46 and the barrier metal 51 are formed in sequence. For the formation of the block insulating film 46, for example, a thermal CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like is used. Then, the conductor 50 (molybdenum) is embedded in the space where the sacrificial members 60 to 62 are removed. For the formation of molybdenum, for example, a thermal CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, or the like is used. Note that each of the block insulating film 46, the barrier metal 51, and the conductor 50 is also formed on the side surface portion of the slit SLT and the upper surface portion of the insulator layer 36. At this point, the conductor 50 formed in the space where the sacrificial members 60 to 62 are removed is continuously provided and electrically connected.

[0073] In the process of step S16, as shown in FIG. 15, an etching process of the conductor 50 (molybdenum) is executed. Specifically, a wet etching process using the chemical solution according to the embodiment is executed. In the process of step S16, the conductor 50 formed on the side surface of the slit SLT and the conductor 50 formed on the upper surface of the insulator layer 36 are removed. Note that in the process of step S16, the chemical solution that contacts the conductor 50 through the slit SLT etches molybdenum at a substantially constant speed regardless of the height within the slit SLT. Also, in the process of step S16, the conductors 50 formed in adjacent wiring layers only need to be at least separated. Thereby, a conductor layer 22 that functions as a select gate line SGS, a plurality of conductor layers 23 that function as word lines WL0 to WL7, and a conductor layer 24 that functions as a select gate line SGD are respectively formed. Hereinafter, the process of step S16 is referred to as "recess process of the laminated wiring". Also, hereinafter, the removal amount of the conductor 50 above the slit SLT (for example, (1) shown in FIG. 15) is referred to as "top-side recess amount", and the removal amount of the conductor 50 below the slit SLT (for example, (2) shown in FIG. 15) is referred to as "bottom-side recess amount".

[0074] In the process of step S17, as shown in FIG. 16, an embedding process of the slit SLT is executed. Specifically, first, an insulating film (spacer SP) is formed so as to cover the side surface and the bottom surface of the slit SLT. Then, a part of the spacer SP provided at the bottom of the slit SLT is removed, and a part of the conductor layer 21 is exposed at the bottom of the slit SLT. Then, a conductor (contact LI) is formed in the slit SLT, and the conductor formed outside the slit SLT is removed by, for example, CMP (Chemical Mechanical Polishing). Thereafter, a plurality of grooves parallel to the slit SLT are formed between the slits SLT adjacent in the Y direction, and an insulating film is embedded in each groove, whereby a slit SHE that divides the conductor layer 24 in the Y direction is formed.

[0075] By the manufacturing process of the semiconductor device 1 according to the embodiment described above, a laminated wiring structure within the memory cell array 10 is formed. A series of processes in steps S13 to S17 may be called "replacement process". Note that the manufacturing process described above is merely an example and is not limited thereto. For example, other processes may be inserted between each manufacturing process, or some processes may be omitted or integrated. For example, a process of forming a stepped structure of the laminated wiring may be inserted between steps S10 and S11.

[0076] [4] Effects of the Embodiment In the manufacturing method of the semiconductor device according to the embodiment, by using a chemical solution containing polyethyleneimine in the recess process of the laminated wiring, the top / bottom difference in the recess amount can be suppressed, and the yield of the semiconductor device 1 can be improved. The details of this effect will be described below.

[0077] A semiconductor device in which memory cells are three-dimensionally stacked has, for example, a laminated wiring structure in which a conductor layer and an insulator layer are alternately stacked. For forming the laminated wiring, for example, a replacement process using a sacrificial member is utilized. The replacement process is a process of replacing the sacrificial member with a conductor after alternately stacking the sacrificial member and the insulator layer. Briefly stated, a slit SLT that divides the laminated structure of the sacrificial member and the insulator layer is formed, and the sacrificial member is selectively removed through the slit SLT. Then, through the slit SLT, a conductor is embedded in the space from which the sacrificial member has been removed. Thereafter, by an etching process (recess process), the conductor provided on the side surface of the slit SLT is separated for each laminated wiring.

[0078] As a conductor used for multilayer wiring, tungsten (W) is known. However, when tungsten is used for multilayer wiring, device failures may occur due to the generation of fluorine gas during the formation of tungsten or the occurrence of wafer warpage due to the formation of tungsten. Therefore, using molybdenum as a conductor used for multilayer wiring has been considered. When molybdenum is formed, fluorine gas is not generated as in the case of forming tungsten, so the occurrence of device failures due to degassing during the formation of multilayer wiring is suppressed. Furthermore, since molybdenum has a lower wiring resistance than tungsten, the use of multilayer wiring using molybdenum can also contribute to improving the performance of semiconductor devices.

[0079] As an etching solution for molybdenum (hereinafter referred to as Mo etching solution), for example, a mixed acid containing phosphoric acid, nitric acid, acetic acid, and water is known. However, when the mixed acid is used for etching, since the etching rate of molybdenum is high, there may be variations in the etched amount of molybdenum. For example, in the recess process of the embodiment, there may be a difference between the recess amount on the top side of the slit SLT and the recess amount on the bottom side of the slit SLT. Such a top / bottom difference in the recess amount becomes more prominent when the aspect ratio of the slit SLT is high (for example, 30 or more). A large top / bottom difference in the recess amount can be a cause of device failure. Also, even when the mixed acid has the same components, the etching of molybdenum may not proceed at all depending on the different composition ratios.

[0080] Therefore, the chemical solution according to the embodiment has a configuration in which polyethyleneimine (PEI) is added to a mixed acid containing an inorganic acid, an oxidizing agent, a carboxylic acid, and water. And in the chemical solution according to the embodiment, the PEI molecular weight is, for example, 100 or more and 1800 or less, and the additive concentration is adjusted within the range of 0.05 wt% to 10 wt%. The etching using the chemical solution according to the embodiment proceeds while protecting the surface of molybdenum by the added PEI. Thereby, the etching rate of molybdenum by the chemical solution according to the embodiment is suppressed compared to the mixed acid not containing PEI.

[0081] As a result, the method for manufacturing a semiconductor device according to the embodiment can suppress the occurrence of top / bottom differences in the recess process of the multilayer wiring. In other words, the chemical solution according to the embodiment can suppress the top / bottom difference in the recess amount, and can separate molybdenum for each wiring layer without generating an over-etched portion. Therefore, by using the chemical solution according to the embodiment in the manufacturing process of the semiconductor device 1 (for example, step S16), the yield of the semiconductor device 1 can be improved.

[0082] [5] Others The semiconductor device 1 according to the embodiment described above can be variously modified.

[0083] The structure of the memory cell array 10 in the semiconductor device 1 according to the embodiment may be other structures. For example, the memory pillar MP may have a structure in which a plurality of pillars are connected in two or more in the Z direction. The memory pillar MP may have a structure in which the pillar corresponding to the selection gate line SGD and the pillar corresponding to the word line WL are connected. The memory pillar MP and the bit line BL may be connected by a plurality of contacts connected in the Z direction. A conductor layer may be inserted into the connection portion of the plurality of contacts. The semiconductor layer 41 in the memory pillar MP and the source line SL may be connected via the side surface of the memory pillar MP.

[0084] In the drawings used in the description of the embodiment, the case where the memory pillar MP has the same diameter in the Z direction is exemplified, but it is not limited thereto. For example, the memory pillar MP may have a tapered shape or an inverse tapered shape, or may have a shape in which the middle portion bulges (barreling shape). Similarly, each of the slit SLT and SHE may have a tapered shape or an inverse tapered shape, or may have a barreling shape. Further, the cross-sectional structure of the memory pillar MP is not limited to a circular shape, and may be an elliptical shape or may be designed in an arbitrary shape.

[0085] In an embodiment, the interior of each of the slits SLT and SHE may be configured by one or more types of insulators. In this case, for example, contact with the source line SL (conductor layer 21) is provided in the extraction region HA. In the present specification, the position of the slit SLT can be specified based on, for example, the position of the contact LI. When the slit SLT is configured by an insulator, the position of the slit SLT may be specified by a seam in the slit SLT or a material remaining in the slit SLT during the replacement process.

[0086] In the embodiment, the case where a circuit such as the sense amplifier module 16 is provided under the memory cell array 10 has been described, but the present invention is not limited to this. For example, the semiconductor device 1 may have a structure in which stacked wirings such as word lines WL are formed on the semiconductor substrate 20, or may have a structure in which a chip provided with the sense amplifier module 16 or the like and a chip provided with the memory cell array 10 are bonded together. When the semiconductor device 1 has a chip bonding structure, the configuration corresponding to the semiconductor substrate 20 may be omitted.

[0087] In the present specification, "connection" indicates being electrically connected, and for example, does not exclude having another element in between. "Electrically connected" may be via an insulator as long as it can operate in the same manner as an electrically connected object. "Columnar" indicates a structure provided in a hole formed in the manufacturing process of the semiconductor device 1. "Same layer structure" only requires that at least the order in which the layers are formed is the same. "Region" may be regarded as a configuration included by the semiconductor substrate 20. For example, when the semiconductor substrate 20 is defined to include the memory region MA and the extraction region HA, the memory region MA and the extraction region HA are respectively associated with different regions above the semiconductor substrate 20. "Height" corresponds to, for example, the Z-direction interval between the configuration to be measured and the semiconductor substrate 20. As a reference for "height", a configuration other than the semiconductor substrate 20 may be used. "Molybdenum" indicates metallic molybdenum and includes molybdenum alone.

[0088] In the embodiment, it has been shown that a chemical solution containing polyethyleneimine is used in the manufacture of a three-dimensional semiconductor device, but it is not limited thereto. The chemical solution according to the embodiment may be used in the manufacture of other semiconductor devices. For example, the chemical solution according to the embodiment may be used for etching a layer containing molybdenum included in a transistor such as a Thin Film Transistor (TFT).

[0089] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Examples

[0090] Examples will be described below. Note that the present invention is not limited to the examples described below. Hereinafter, the process of selectively etching molybdenum will be referred to as "Mo etching process".

[0091] [Evaluation of top / bottom difference in Mo etching process] (Preparation of chemical solution) The chemical solution according to the embodiment is prepared by mixing phosphoric acid, nitric acid, acetic acid, and an aqueous PEI solution in this order. The temperature during the preparation of the chemical solution is, for example, room temperature (about 23 to 24 °C). For each of phosphoric acid, nitric acid, acetic acid, and the aqueous PEI solution, heating or the like is not particularly required. The time required for preparing the chemical solution is about 10 to 20 minutes from the start to the completion of the preparation of the chemical solution. The aqueous PEI solution is prepared before the preparation of the chemical solution. The aqueous PEI solution is prepared by adding PEI to water at room temperature. In the examples, 10 types of chemical solutions were used. The PEI concentration of each of the 10 types of chemical solutions is 0.05 wt%, 0.15 wt%, 0.3 wt%, 0.5 wt%, 0.9 wt%, 1%, 1.5 wt%, 2 wt%, 2.78 wt%, and 3%, respectively.

[0092] (Preparation of Samples) In the shape evaluation of the Mo etching process of the examples, chips cut out from each of the three test lots LN1, LN2, and LN3 were used. Note that the designs of the test lots LN1, LN2, and LN3 are different. Specifically, the number of stacked layers of the sacrificial member and the insulator layer, etc., are different among the wafers of the test lots LN1, LN2, and LN3. However, in each of the wafers of the test lots LN1, LN2, and LN3, a plurality of slits SLT formed in the structure including the stacked structure of the sacrificial member and the insulator layer have a high aspect ratio (>30). Therefore, it is possible to similarly verify the recess amount on the top side and the recess amount on the bottom side among the chips cut out from the wafer of the test lot LN1, the chip cut out from the wafer of the test lot LN2, and the chip cut out from the wafer of the test lot LN3.

[0093] (Evaluation Results) In the shape evaluation of the Mo etching process of the embodiment, first, for each chip, a cross-sectional image of the memory cell array 10 including the slit SLT was acquired. An SEM (Scanning Electron Microscope) was used to acquire the cross-sectional image of the memory cell array 10. Then, from the acquired cross-sectional image of the memory cell array 10, the top / bottom difference of molybdenum in the side portion of the slit SLT was confirmed. Hereinafter, with reference to FIGS. 17 and 18, the evaluation results of the top / bottom difference of the Mo etching process will be described.

[0094] FIG. 17 is a schematic diagram showing an example of the cross-sectional structure of the memory cell array 10 after the Mo etching process of the embodiment. (1) of FIG. 17 shows an example of the cross-sectional structure of the memory cell array 10 when the top / bottom difference is large. (2) of FIG. 17 shows an example of the cross-sectional structure of the memory cell array 10 when the top / bottom difference is small. Hereinafter, the three-layer conductor 50 shown in FIG. 17 will be referred to as 50A, 50B, and 50C in order from the one closer to the top.

[0095] In the example shown in (1) of FIG. 17, the amount of recess due to the etching process is larger in the conductor 50B than in the conductor 50C, and larger in the conductor A than in the conductor 50B. Thus, the large difference in the amount of recess between the top (for example, the conductor 50A) and the bottom (for example, the conductor 50C) corresponds to the large top / bottom difference. In the embodiment, when a shape close to the shape shown in (1) of FIG. 17 was confirmed, the shape evaluation result of the sample was regarded as "not acceptable", that is, a top / bottom difference was considered to have occurred.

[0096] In the example shown in (2) of FIG. 17, the amount of recess due to the etching process is substantially equal for each of the conductors 50A, 50B, and 50C. Thus, the small difference in the amount of recess between the top (for example, the conductor 50A) and the bottom (for example, the conductor 50C) corresponds to the small top / bottom difference. In the embodiment, when a shape close to the shape shown in (2) of FIG. 17 was confirmed, the shape evaluation result of the sample was regarded as "acceptable", that is, a top / bottom difference was considered not to have occurred.

[0097] Figure 18 is a table showing the results of the shape evaluation of the Mo etching process of the example, and shows the results of the shape evaluation based on the combination of the lot number, the additive concentration, and the PEI molecular weight. The evaluation results shown in Figure 18 are determined based on the evaluation criteria described with reference to Figure 17. The "x / y" shown in Figure 18 corresponds to the evaluation result. "x" indicates the number of slits SLT in the cross-sectional image confirmed in the sample where the top / bottom difference occurs. "y" indicates the total number of slits SLT included in the cross-sectional image confirmed in the sample.

[0098] The result of the cross-section evaluation in the combination of sample number SN1, additive concentration 0.05 wt%, and PEI molecular weight 600 was 5 / 5. The result of the cross-section evaluation in the combination of sample number SN1, additive concentration 0.05 wt%, and PEI molecular weight 1800 was 5 / 5.

[0099] The result of the cross-section evaluation in the combination of sample number SN1, additive concentration 0.15 wt%, and PEI molecular weight 600 was 1 / 5. The result of the cross-section evaluation in the combination of sample number SN1, additive concentration 0.15 wt%, and PEI molecular weight 1800 was 5 / 5.

[0100] The result of the cross-section evaluation in the combination of sample number SN1, additive concentration 0.3 wt%, and PEI molecular weight 600 was 0 / 5. The result of the cross-section evaluation in the combination of sample number SN1, additive concentration 0.3 wt%, and PEI molecular weight 1800 was 1 / 5.

[0101] The result of the cross-section evaluation in the combination of sample number SN2, additive concentration 0.3 wt%, and PEI molecular weight 600 was 9 / 54. The result of the cross-section evaluation in the combination of sample number SN2, additive concentration 0.3 wt%, and PEI molecular weight 1800 was 4 / 18.

[0102] The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 0.5 wt%, and PEI molecular weight of 600 was 4 / 54. The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 0.5 wt%, and PEI molecular weight of 1800 was 4 / 54. The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 0.5 wt%, and PEI molecular weight of 10000 was 54 / 54.

[0103] The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 0.9 wt%, and PEI molecular weight of 1800 was 3 / 54.

[0104] The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 1 wt%, and PEI molecular weight of 600 was 0 / 54.

[0105] The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 1.5 wt%, and PEI molecular weight of 1800 was 3 / 54.

[0106] The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 2%, and PEI molecular weight of 600 was 0 / 54.

[0107] The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 2.78 wt%, and PEI molecular weight of 10000 was 6 / 54.

[0108] The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 3 wt%, and PEI molecular weight of 600 was 0 / 54. The result of the cross-section evaluation for the combination of sample number SN2, additive concentration of 3 wt%, and PEI molecular weight of 1800 was 9 / 54.

[0109] FIG. 19 is a schematic diagram showing a cross-sectional structure of a memory cell array after Mo etching treatment in a comparative example. In the comparative example, Mo etching treatment using a metal mixed acid was performed on chips cut out from wafers of test lot LN3, which was different from test lots LN1 and LN2. "Mo" shown in FIG. 19 indicates a conductor containing molybdenum. "INS" indicates an insulator layer. "SUB" indicates a semiconductor substrate. In the comparative example, an insulator layer INS and a sacrificial member are alternately stacked on the semiconductor substrate SUB. Then, after a slit SLT is formed, a replacement process is executed, and in the replacement process, Mo etching treatment is performed.

[0110] As shown in FIG. 19, in the comparative example, on the top side, there is a portion where all molybdenum has been peeled off (Mo completely peeled off), and on the bottom side, there is a portion where molybdenum (Mo) remains on the side surface of the slit SLT (Mo remaining). Thus, in the comparative example, the recess amount on the top side and the recess amount on the bottom side are significantly different. That is, in the comparative example, the top / bottom difference in the Mo etching treatment is large.

[0111] In contrast, as described with reference to FIGS. 17 and 18, in the Mo etching process with the addition of polyethyleneimine, by using a chemical solution combining a predetermined additive concentration and a predetermined PEI molecular weight, the top / bottom difference is improved. Specifically, when the additive concentration is 0.15 wt%, the top / bottom difference when the PEI molecular weight is 600 is better than that when the PEI molecular weight is 1800. When the additive concentration is 0.3 wt%, the top / bottom difference when the PEI molecular weight is 600 is better than that when the PEI molecular weight is 1800. When the additive concentration is 0.5 wt%, the top / bottom difference when the PEI molecular weight is 600 or 1800 is better than that when the PEI molecular weight is 10000. When the PEI molecular weight is 600 and the additive concentration is 1 or more, the slit SLT where the top / bottom difference occurs was not detected. Also, when the additive concentration is 0.3 wt%, 1, 2, or 3 wt% and the PEI molecular weight is 600, the slit SLT where the top / bottom difference occurs was not detected.

[0112] That is, as the Mo etching solution, it is preferable that the additive concentration (concentration of polyethyleneimine) is in the range of 0.05 wt% to 10 wt%. Also, as the Mo etching solution, it is preferable that the PEI molecular weight (weight average molecular weight of polyethyleneimine) is 100 or more and 1800 or less. Further, as the Mo etching solution, it is more preferable that the additive concentration is in the range of 1 wt% to 3 wt% and the PEI molecular weight is 100 or more and 600 or less. The top / bottom difference in the etching process of molybdenum tends to improve as the PEI used as an additive has a lower molecular weight and a higher concentration.

[0113] Other embodiments are appended below.

[0114] (Appendix 1) A chemical solution containing a mixed acid and polyethyleneimine which is an organic amine, wherein the mixed acid contains an inorganic acid, an oxidizing agent, a carboxylic acid, and water, A chemical solution in which the concentration of the polyethyleneimine in the above chemical solution is within the range of 0.05 wt% to 10 wt%.

[0115] (Appendix 2) Used for etching the molybdenum-containing layer The chemical solution described in Appendix 1

[0116] (Appendix 3) The concentration of the above inorganic acid is within the range of 40 wt% to 80 wt%, The concentration of the above oxidizing agent is 5 wt% or less, The concentration of the above carboxylic acid is within the range of 0.1 wt% to 45 wt%, The concentration of the above water is 30 wt% or less, The chemical solution described in Appendix 1 or 2

[0117] (Appendix 4) The weight average molecular weight of the above polyethyleneimine is 100 or more and 1800 or less, The chemical solution described in any one of Appendices 1 to 3

[0118] (Appendix 5) The concentration of the above polyethyleneimine is within the range of 1 wt% to 3 wt%, and the weight average molecular weight of the above polyethyleneimine is 100 or more and 600 or less, The chemical solution described in any one of Appendices 1 to 4

[0119] (Appendix 6) The above inorganic acid is at least one selected from the group consisting of phosphoric acid and sulfuric acid, The chemical solution described in any one of Appendices 1 to 4

[0120] (Appendix 7) The above oxidizing agent is at least one selected from the group consisting of nitric acid and hydrogen peroxide, The chemical solution described in any one of Appendices 1 to 5

[0121] (Appendix 8) The carboxylic acid is at least one selected from the group consisting of acetic acid, lactic acid, propionic acid, butyric acid, malonic acid, and citric acid. The chemical solution according to any one of Appendices 1 to 6.

[0122] (Appendix 9) A method for etching a layer containing molybdenum, The etching of the layer containing molybdenum includes a mixed acid containing an inorganic acid, an oxidizing agent, a carboxylic acid, and water, and polyethyleneimine which is an organic amine, and a chemical solution in which the concentration of the polyethyleneimine is in the range of 0.05 wt% to 10 wt% is used.

[0123] (Appendix 10) The concentration of the inorganic acid in the chemical solution is in the range of 40 wt% to 80 wt%, The concentration of the oxidizing agent in the chemical solution is 5 wt% or less, The concentration of the carboxylic acid in the chemical solution is in the range of 0.1 wt% to 45 wt%, The concentration of the water in the chemical solution is 30 wt% or less. The etching method according to Appendix 9.

[0124] (Appendix 11) The weight average molecular weight of the polyethyleneimine in the chemical solution is 100 or more and 1800 or less. The etching method according to any one of Appendix 9 or Appendix 10.

[0125] (Appendix 12) The concentration of the polyethyleneimine in the chemical solution is in the range of 1 wt% to 3 wt%, and the weight average molecular weight of the polyethyleneimine is 100 or more and 600 or less. The etching method according to any one of Appendices 9 to 11.

[0126] (Appendix 13) The inorganic acid is at least one selected from the group consisting of phosphoric acid and sulfuric acid. The etching method according to any one of Supplementary Notes 9 to 12.

[0127] (Supplementary Note 14) The oxidizing agent is at least one selected from the group consisting of nitric acid and hydrogen peroxide. The etching method according to any one of Supplementary Notes 9 to 13.

[0128] (Supplementary Note 15) The carboxylic acid is at least one selected from the group consisting of acetic acid, lactic acid, propionic acid, butyric acid, malonic acid, and citric acid. The etching method according to any one of Supplementary Notes 9 to 14.

[0129] (Supplementary Note 16) Forming a structure in which a sacrificial member and an insulator layer are alternately laminated. Forming a slit for dividing the structure. Removing the sacrificial member from the structure through the slit. After removing the sacrificial member, filling the space from which the sacrificial member has been removed by forming a conductor. After forming the conductor, etching the conductor provided in the slit, and comprising: The conductor contains molybdenum. A method for manufacturing a semiconductor device, wherein a chemical solution containing an inorganic acid, an oxidizing agent, a carboxylic acid, water, and a mixed acid, and a polyethyleneimine which is an organic amine and has a concentration in the range of 0.05 wt% to 10 wt% is used for the etching.

[0130] (Supplementary Note 17) The concentration of the inorganic acid in the chemical solution is in the range of 40 wt% to 80 wt%. The concentration of the oxidizing agent in the chemical solution is 5 wt% or less. The concentration of the carboxylic acid in the chemical solution is in the range of 0.1 wt% to 45 wt%. The concentration of the water in the chemical solution is 30 wt% or less. The manufacturing method of the semiconductor device described in Supplementary Note 16.

[0131] (Supplementary Note 18) The weight average molecular weight of the polyethyleneimine in the chemical solution is 100 or more and 1800 or less. The manufacturing method of the semiconductor device described in Supplementary Note 16 or Supplementary Note 17.

[0132] (Supplementary Note 19) The concentration of the polyethyleneimine in the chemical solution is in the range of 1 wt% to 3 wt%, and the weight average molecular weight of the polyethyleneimine is 100 or more and 600 or less. The manufacturing method of the semiconductor device described in any one of Supplementary Notes 16 to 18.

[0133] (Supplementary Note 20) The inorganic acid is at least one selected from the group consisting of phosphoric acid and sulfuric acid. The manufacturing method of the semiconductor device described in any one of Supplementary Notes 16 to 19.

[0134] (Supplementary Note 21) The oxidizing agent is at least one selected from the group consisting of nitric acid and hydrogen peroxide. The manufacturing method of the semiconductor device described in any one of Supplementary Notes 16 to 20.

[0135] (Supplementary Note 22) The carboxylic acid is at least one selected from the group consisting of acetic acid, lactic acid, propionic acid, butyric acid, malonic acid, and citric acid. The manufacturing method of the semiconductor device described in any one of Supplementary Notes 16 to 21.

Explanation of symbols

[0136] 1…Semiconductor device, 2…Memory controller, 10…Memory cell array, 11…Command register, 12…Address register, 13…Sequencer, 14…Driver module, 15…Row decoder module, 16…Sense amplifier module, 20…Semiconductor substrate, 21 - 25…Conductor layer, 30 - 36…Insulator layer, 40…Core member, 41…Semiconductor layer, 42…Stacked film, 43…Tunnel insulating film, 44…Insulating film, 45…Cover insulating film, 46…Block insulating film, 50…Conductor, 51…Barrier metal, 60 - 62…Sacrificial member, MA…Memory area, HA…Lead-out area, BL…Bit line, WL…Word line, SGD, SGS…Select gate line, BLK…Block, SU…String unit, NS…NAND string, MT…Memory cell transistor, ST1, ST2…Select transistor

Claims

Claim 1 A chemical solution comprising a mixed acid and polyethyleneimine which is an organic amine, wherein the mixed acid contains an inorganic acid, an oxidizing agent, a carboxylic acid, and water, and the concentration of the polyethyleneimine in the chemical solution is in the range of 0.05 wt% to 10 wt%.

Images