Semiconductor memory device

Abstract

To provide a semiconductor memory device that suppresses an increase in write voltage.SOLUTION: A semiconductor memory device according to an embodiment includes: a first memory string to which a plurality of memory cells, including first and second memory cells, are connected in series; a first word line connected to the gate of the first memory cell; a second word line connected to the gate of the second memory cell; a first bit line connected to one end of the first memory string; a source line connected to the other end of the first memory string; and a control circuit, in which the control circuit is constituted to apply a write voltage to the first word line in program operations targeted to the first memory cell, make the channel of the first memory string in a floating state for electrically insulating from the first bit line and the source line; and reduce the voltage of the second word line from a first voltage, which is less than the write voltage, to a second voltage, which is less than the first voltage, after making the channel of the first memory string in the floating state.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] Embodiments relate to a semiconductor memory device.

Background Art

[0002] As a semiconductor memory device, a NAND type flash memory is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Suppress an increase in the write voltage.

Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment includes a first memory string in which a plurality of memory cells including a first memory cell and a second memory cell are connected in series, a first word line connected to the gate of the first memory cell, a second word line connected to the gate of the second memory cell, a first bit line connected to one end of the first memory string, a source line connected to the other end of the first memory string, and a control circuit. The control circuit is configured to, in a program operation targeting the first memory cell, while applying a write voltage to the first word line, put the channel of the first memory string in a floating state electrically insulated from the first bit line and the source line, and after putting the channel of the first memory string in the floating state, reduce the voltage of the second word line from a first voltage less than the write voltage to a second voltage less than the first voltage.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are denoted by common reference numerals.

[0008] 1 First Embodiment Hereinafter, a semiconductor memory device according to the first embodiment will be described. Hereinafter, an NAND type flash memory will be described as an example of the semiconductor memory device.

[0009] 1.1 Configuration The configuration of the semiconductor memory device according to the first embodiment will be described.

[0010] 1.1.1 Memory System First, a configuration example of the memory system will be described with reference to FIG. 1. FIG. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to the first embodiment and a host device.

[0011] The memory system 3 communicates with, for example, an external host device 4. The memory system 3 stores data from the host device 4. Also, the memory system 3 reads out data to the host device 4. The memory system 3 is, for example, an SSD (Solid State Drive), an SD TM card, or the like.

[0012] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0013] The semiconductor memory device 1 includes a plurality of memory cells and stores data non-volatilely. The semiconductor memory device 1 is connected to the memory controller 2 by a NAND bus.

[0014] The NAND bus transmits and receives signals / CE, CLE, ALE, / WE, / RE, RE, / WP, / RB, DQ<7:0>, DQS, and / DQS according to the NAND interface via individual signal lines. The signal / CE is a Chip Enable signal and is used to enable the semiconductor memory device 1. The signal CLE is a Command Latch Enable signal, and when the signal CLE is at the “H (High)” level, it notifies the semiconductor memory device 1 that the signal DQ<7:0> flowing into the semiconductor memory device 1 is a command. The signal ALE is an Address Latch Enable signal, and when the signal ALE is at the “H” level, it notifies the semiconductor memory device 1 that the signal DQ<7:0> flowing into the semiconductor memory device 1 is an address. The signal / WE is a Write Enable signal and instructs the semiconductor memory device 1 to capture the signal DQ<7:0>. For example, in Single Data Rate (SDR), the signal / WE instructs the semiconductor memory device 1 to capture the signal DQ<7:0> as a command, address, or data at the rising edge of the signal / WE. Also, in Double Data Rate (DDR), the signal / WE instructs the semiconductor memory device 1 to capture the signal DQ<7:0> as a command or address at the rising edge of the signal / WE. The signal / RE is a Read Enable signal and instructs the semiconductor memory device 1 to output the signal DQ<7:0>. For example, in Single Data Rate, the signal / RE instructs the semiconductor memory device 1 to output the signal DQ<7:0> as data at the falling edge of the signal / RE. Also, in Double Data Rate, the signal / RE instructs the semiconductor memory device 1 to output the signal DQ<7:0> as data at the falling edge and rising edge of the signal / RE. The signal RE is the complementary signal of the signal / RE.The signal / WP is a Write Protect signal, which instructs the semiconductor memory device 1 to prohibit data writing and erasing. The signal / RB is a Ready Busy signal, which indicates whether the semiconductor memory device 1 is in a ready state (a state of accepting commands from the outside) or a busy state (a state of not accepting commands from the outside). The signal DQ<7:0> is, for example, an 8-bit signal. The signal DQS is a Data Strobe signal, which is used to control the operation timing of the semiconductor memory device 1 related to the signal DQ<7:0>. For example, in double data rate, the signal DQS instructs the semiconductor memory device 1 to capture the signal DQ<7:0> as data at the falling edge and rising edge of the signal DQS. Also, the signal DQS is generated based on the falling edge and rising edge of the signal / RE in double data rate and is output together with the signal DQ<7:0> as data from the semiconductor memory device 1. The signal / DQS is the complementary signal of the signal DQS.

[0015] The signal DQ<7:0> is transmitted and received between the semiconductor memory device 1 and the memory controller 2. The signal DQ<7:0> includes a command CMD, an address ADD, and data DAT. The command CMD includes, for example, a command to cause the semiconductor memory device 1 to perform an erase operation (erase command), a command to cause the semiconductor memory device 1 to perform a write operation (write command), and a command to cause the semiconductor memory device 1 to perform a read operation (read command), etc. The data DAT includes read data and write data.

[0016] The memory controller 2 receives commands from the host device 4. Also, the memory controller 2 controls the semiconductor memory device 1 based on the received commands. More specifically, the memory controller 2 writes the data for which the write operation has been commanded to the semiconductor memory device 1 based on the write command received from the host device 4. Also, the memory controller 2 reads out the data for which the read operation has been commanded from the host device 4 from the semiconductor memory device 1 based on the read command received from the host device 4. Then, the memory controller 2 transmits the read data to the host device 4.

[0017] Examples of the host device 4 that uses the memory system 3 described above include a digital camera, a personal computer, and a server in a data center.

[0018] 1.1.2 Memory Controller As shown in FIG. 1, the memory controller 2 includes a CPU (Central Processing Unit) 20, a built-in memory 21, a buffer memory 22, a NAND I / F (NAND interface circuit) 23, and a host I / F (host interface circuit) 24. The memory controller 2 is configured as, for example, a SoC (System-on-a-chip).

[0019] The CPU 20 controls the operation of the entire memory controller 2. The CPU 20 issues, for example, commands for instructing the execution of various operations such as write operations, read operations, and erase operations on the semiconductor memory device 1.

[0020] The built-in memory 21 is, for example, a semiconductor memory such as a DRAM (Dynamic Random Access Memory). The built-in memory 21 is used, for example, as a work area for the CPU 20. The built-in memory 21 stores, for example, firmware for managing the semiconductor memory device 1 and various management tables.

[0021] The buffer memory 22 temporarily stores the write data received from the host device 4, the read data received by the memory controller 2 from the semiconductor memory device 1, and the like.

[0022] The NAND interface circuit 23 is connected to the semiconductor memory device 1 via the NAND bus. The NAND interface circuit 23 controls the communication with the semiconductor memory device 1. For example, the NAND interface circuit 23 transmits a command CMD, an address ADD, and write data to the semiconductor memory device 1 according to an instruction from the CPU 20. Also, the NAND interface circuit 23 receives read data from the semiconductor memory device 1.

[0023] The host interface circuit 24 is connected to the host device 4 via the host bus. The host interface circuit 24 controls the communication between the memory controller 2 and the host device 4. The host interface circuit 24 transfers, for example, the instructions and data received from the host device 4 to the CPU 20 and the buffer memory 22, respectively.

[0024] 1.1.3 Semiconductor Memory Device Next, a configuration example of the semiconductor memory device 1 according to the first embodiment will be described with reference to FIG. 2. FIG. 2 is a block diagram showing an example of the configuration of the semiconductor memory device according to the first embodiment.

[0025] The semiconductor memory device 1 includes a memory cell array 10, an input / output circuit 11, a logic control circuit 12, an address register 13, a command register 14, a sequencer 15, a driver module 16, a row decoder module 17, and a sense amplifier module 18.

[0026] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(m - 1) (m is an integer of 1 or more). In the following description, when the plurality of blocks BLK0 to BLK(m - 1) are not distinguished from each other, each of the plurality of blocks BLK0 to BLK(m - 1) is simply referred to as block BLK. Each block BLK is a set of a plurality of memory cell transistors capable of storing data non-volatily. Each block BLK is used, for example, as an erasure unit of data. That is, the data stored in the memory cell transistors included in the same block BLK is erased collectively. The detailed configuration of the memory cell array 10 will be described later.

[0027] The input / output circuit 11 transmits and receives the signal DQ<7:0> to and from the memory controller 2. The input / output circuit 11 transfers the address ADD and the command CMD in the signal DQ<7:0> to the address register 13 and the command register 14, respectively. Further, the input / output circuit 11 transmits and receives data DAT to and from the sense amplifier module 18.

[0028] The logic control circuit 12 receives, for example, signals / CE, CLE, ALE, / WE, / RE, RE, / WP, DQS, and / DQS from the memory controller 2, and controls the input / output circuit 11 based on the received signals. Further, the logic control circuit 12 generates a signal / RB and transmits it to the memory controller 2.

[0029] The address register 13 stores the address ADD transferred from the input / output circuit 11. The address register 13 transfers the stored address ADD to the row decoder module 17 and the sense amplifier module 18.

[0030] The command register 14 stores the command CMD transferred from the input / output circuit 11. The command register 14 transfers the stored command CMD to the sequencer 15.

[0031] The sequencer 15 receives the command CMD from the command register 14. The sequencer 15 controls the entire semiconductor memory device 1 according to a sequence based on the received command CMD. For example, when the sequencer 15 receives each of an erase command, a write command, and a read command, it instructs the driver module 16 to generate a voltage used in an operation corresponding to the command.

[0032] The driver module 16 generates voltages used in an erase operation, a write operation, a read operation, etc. based on an instruction from the sequencer 15. The driver module 16 supplies the generated voltages to the row decoder module 17, the sense amplifier module 18, the memory cell array 10, etc.

[0033] The row decoder module 17 receives the block address in the address ADD from the address register 13. The row decoder module 17 selects one of the m blocks BLK based on the received block address. The row decoder module 17 applies, for example, the voltage supplied from the driver module 16 to the selected block BLK.

[0034] The sense amplifier module 18 receives the column address in the address ADD from the address register 13. The sense amplifier module 18 transfers data DAT between the memory controller 2 and the memory cell array 10 based on the received column address. More specifically, the sense amplifier module 18 receives write data from the input / output circuit 11 during a write operation. Then, the sense amplifier module 18 transfers the received write data to the memory cell array 10. Also, the sense amplifier module 18 senses the threshold voltage of the memory cell transistor targeted for the read operation in the memory cell array 10 and generates read data during a read operation. Then, the sense amplifier module 18 transfers the generated read data to the input / output circuit 11.

[0035] 1.1.4 Circuit Configuration of Memory Cell Array The circuit configuration of the memory cell array 10 of the semiconductor memory device 1 according to the first embodiment will be described with reference to FIG. 3. FIG. 3 is a circuit diagram for explaining an example of the configuration of the memory cell array of the semiconductor memory device according to the first embodiment.

[0036] Each block BLK includes, for example, five string units SU0 to SU4. Each of the string units SU0 to SU4 includes a plurality of NAND strings NS. In the following description, when the string units SU0 to SU4 are not distinguished from each other, each of the string units SU0 to SU4 is simply referred to as a string unit SU. Also, the number of string units SU provided in each block BLK is not limited to five. The number of string units SU provided in each block BLK may be 1 to 4, or 6 or more.

[0037] Each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7, and selection transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a gate and a charge storage layer. The memory cell transistors MT0 to MT7 are connected in series between the selection transistors ST1 and ST2. In the following description, when the memory cell transistors MT0 to MT7 are not distinguished from each other, each of the memory cell transistors MT0 to MT7 is simply referred to as a memory cell transistor MT. Also, when the selection transistors ST1 and ST2 are not distinguished from each other, each of the selection transistors ST1 and ST2 is simply referred to as a selection transistor ST. Also, the number of memory cell transistors MT provided in each NAND string NS is not limited to eight. The number of memory cell transistors MT provided in each NAND string NS may be 16, 32, 48, 64, 96, or 128, etc., and the number is not limited. Also, the number of selection transistors ST1 and ST2 is not limited to one each, and may be any number.

[0038] The gates of the selection transistors ST1 of the string units SU0 to SU4 within each block BLK are each connected to the selection gate lines SGD0 to SGD4. The gate of the selection transistor ST2 of the string unit SU within each block BLK is connected to the selection gate line SGS. Although not shown in the figure, each block BLK may include, for example, five selection gate lines SGS0 to SGS4. In this case, the gates of the selection transistors ST2 of the string units SU0 to SU4 may each be connected to the selection gate lines SGS0 to SGS4 in the same manner as the gates of the selection transistors ST1 of the string units SU0 to SU4. In the following description, when the selection gate lines SGD0 to SGD4 are not distinguished from each other, each of the selection gate lines SGD0 to SGD4 is simply referred to as the selection gate line SGD.

[0039] The gates of the memory cell transistors MT0 to MT7 within each block BLK are each connected to the word lines WL0 to WL7. Note that the number of word lines WL included in each block BLK is not limited to eight, similar to the number of memory cell transistors MT provided in each NAND string NS. The number of word lines WL included in each block BLK may be 16, 32, 48, 64, 96, or 128, etc., and the number is not limited. Also, in the following description, when the word lines WL0 to WL7 are not distinguished from each other, each of the word lines WL0 to WL7 is simply referred to as the word line WL.

[0040] With the above configuration, in each block BLK, the word line WL and the selection gate line SGS are connected to the string units SU0 to SU4. On the other hand, in each block BLK, each selection gate line SGD is connected to one string unit SU corresponding to the selection gate line SGD.

[0041] Among the NAND strings NS arranged in a matrix within the memory cell array 10, the other ends of the selection transistors ST1 of the NAND strings NS in the same row are connected to any one of n (n is an integer of 2 or more) bit lines BL (BL0 to BL(n - 1)). Further, the bit lines BL are connected to the NAND strings NS in the same column across a plurality of blocks BLK.

[0042] The other end of the selection transistor ST2 is connected to the source line SL. The source line SL is shared, for example, among a plurality of blocks BLK.

[0043] A set of a plurality of memory cell transistors MT connected to a common word line WL within each string unit SU is called, for example, a cell unit CU. The storage capacity of the cell unit CU including a plurality of memory cell transistors MT each storing 1-bit data is defined as, for example, "1-page data". The cell unit CU can have a storage capacity of 2-page data or more according to the number of bits of data stored in the memory cell transistor MT.

[0044] 1.1.5 Structure of Memory Cell Array The structure of the memory cell array 10 of the semiconductor memory device 1 according to the first embodiment will be described with reference to FIG. 4. FIG. 4 is a cross-sectional view for explaining an example of the structure of the memory cell array of the semiconductor memory device according to the first embodiment. In the following drawings, the X direction corresponds to the extending direction of the word line WL. Also, the Y direction orthogonal to the X direction in the horizontal plane corresponds to the extending direction of the bit line BL. The Z direction orthogonal to the horizontal plane corresponds to the vertical direction with respect to the surface of the semiconductor substrate used for forming the semiconductor memory device 1.

[0045] The memory cell array 10 further includes a semiconductor substrate 40, conductor layers 41 to 45, and insulator layers 30 to 34.

[0046] An insulator layer 30 is provided on a semiconductor substrate 40. Although not shown in FIG. 4, the insulator layer 30 and the semiconductor substrate 40 include circuits such as, for example, a row decoder module 17 and a sense amplifier module 18. In the following description, the side on which the memory cell array 10 is provided with respect to the semiconductor substrate 40 is defined as the upper side.

[0047] A conductor layer 41 is provided on the insulator layer 30. The conductor layer 41 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 41 is used as a source line SL. The conductor layer 41 includes, for example, silicon doped with phosphorus.

[0048] An insulator layer 31 is provided on the conductor layer 41. A conductor layer 42 is provided on the insulator layer 31. The conductor layer 42 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 42 is used as a select gate line SGS. The conductor layer 42 includes, for example, tungsten.

[0049] Eight insulator layers 32 and eight conductor layers 43 are stacked on the conductor layer 42. The eight insulator layers 32 and the eight conductor layers 43 are stacked in the order of insulator layer 32, conductor layer 43, insulator layer 32,..., conductor layer 43, insulator layer 32, and conductor layer 43 upward. The conductor layer 43 is formed, for example, in a plate shape extending along the XY plane. The plurality of stacked conductor layers 43 are used as word lines WL0 to WL7 in order from the semiconductor substrate 40 side. The conductor layer 43 includes, for example, tungsten.

[0050] An insulator layer 33 is provided on the uppermost conductor layer 43. A conductor layer 44 is provided on the insulator layer 33. The conductor layer 44 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 44 is used as a select gate line SGD. The conductor layer 44 includes, for example, tungsten.

[0051] In the following description, each of the conductor layers 42 to 44 is also simply referred to as a stacked wiring.

[0052] An insulator layer 34 is provided on the conductor layer 44. A plurality of conductor layers 45 are provided on the insulator layer 34. Each conductor layer 45 is formed, for example, in a line shape extending in the Y direction. In FIG. 4, only one of the plurality of conductor layers 45 is shown. Each conductor layer 45 is used as a bit line BL. The conductor layer 45 contains, for example, copper.

[0053] Each of the memory pillars MP extends along the Z direction and penetrates the insulator layers 31 to 33 and the conductor layers 42 to 44. The bottom of the memory pillar MP is in contact with the conductor layer 41. The portion where the memory pillar MP and the conductor layer 42 intersect functions as a selection transistor ST2. The portion where the memory pillar MP and one conductor layer 43 intersect functions as one memory cell transistor MT. The portion where the memory pillar MP and the conductor layer 44 intersect functions as a selection transistor ST1.

[0054] Also, each of the memory pillars MP includes, for example, a core member 50, a semiconductor layer 51, and a laminated film 52. The core member 50 extends along the Z direction. The upper end of the core member 50 is located, for example, above the conductor layer 44. The lower end of the core member 50 is located, for example, in a layer lower than the conductor layer 42. The semiconductor layer 51 covers the periphery of the core member 50. At the lower part of the memory pillar MP, a part of the semiconductor layer 51 is in contact with the conductor layer 41. The laminated film 52 covers the side surface and the bottom surface of the semiconductor layer 51 except for the portion where the semiconductor layer 51 and the conductor layer 41 are in contact. The core member 50 contains, for example, an insulator such as silicon oxide. The semiconductor layer 51 contains, for example, silicon.

[0055] A columnar contact CV is provided on the upper surface of the semiconductor layer 51 in the memory pillar MP. In the illustrated region, one contact CV corresponding to one of the three memory pillars MP is shown. In the memory region MR, for the memory pillars MP that do not overlap with the member SHE and to which the contact CV is not connected, the contact CV is connected in a region not shown.

[0056] The upper surface of the contact CV is electrically connected to one conductor layer 45. The contact CV is provided such that one contact CV is connected to one conductor layer 45 in each of the spaces separated by the members SLT and SHE. That is, one memory pillar MP included in each string unit SU is electrically connected to each of the conductor layers 45.

[0057] The member SLT has, for example, a portion provided along the XZ plane. The member SLT divides, for example, the conductor layers 42 to 44. The member SLT includes the contact LI and the spacer SP. The contact LI is, for example, a conductor having a portion extending in the X direction. The spacer SP is, for example, an insulator provided on the side surface of the contact LI. The contact LI and the laminated wiring adjacent to the contact LI in the Y direction are separated by the spacer SP. Thereby, the contact LI and the laminated wiring adjacent to the contact LI in the Y direction are electrically insulated from each other. Note that the contact LI may be an insulator. In this case, the contact LI and the spacer SP may be integrally formed.

[0058] The member SHE has, for example, a portion provided along the XZ plane. The member SHE divides, for example, the conductor layer 44. The lower surface of the member SHE is located, for example, between the uppermost conductor layer 43 and the conductor layer 44. The member SHE includes an insulator such as silicon oxide.

[0059] 1.1.6 Structure of Memory Pillar The structure of the memory pillar MP in the semiconductor memory device 1 according to the first embodiment will be described with reference to FIG. 5. FIG. 5 is a cross-sectional view taken along the line V-V of FIG. 4, showing an example of the cross-sectional structure of the memory pillar included in the memory cell array of the semiconductor memory device according to the first embodiment.

[0060] The laminated film 52 includes, for example, a tunnel insulating film 53, an insulating film 54, and a block insulating film 55.

[0061] In a cross-section including the conductor layer 43, the core member 50 is provided at the center of the memory pillar MP. The core member 50 has, for example, a circular shape in the XY plane. The semiconductor layer 51 surrounds the side surface of the core member 50. The tunnel insulating film 53 surrounds the side surface of the semiconductor layer 51. The insulating film 54 surrounds the side surface of the tunnel insulating film 53. The block insulating film 55 surrounds the side surface of the insulating film 54. The conductor layer 43 surrounds the side surface of the block insulating film 55. Each of the tunnel insulating film 53 and the block insulating film 55 contains, for example, silicon oxide. The insulating film 54 contains, for example, silicon nitride.

[0062] With the above configuration, in the XY plane, the memory pillar MP has, for example, a circular shape.

[0063] The semiconductor layer 51 functions as the channels of the memory cell transistors MT0 to MT7, the selection transistors ST1, and ST2. That is, the semiconductor layer 51 functions as the channel of the memory pillar MP and the channel of the NAND string NS. Also, the insulating film 54 is used as the charge storage layer of the memory cell transistor MT. The semiconductor memory device 1 causes a current to flow through the memory pillar MP between the bit line BL and the source line SL by turning on the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2.

[0064] 1.1.7 Threshold Voltage Distribution of Memory Cell Transistors The threshold voltage distribution of the memory cell transistor MT in the semiconductor memory device 1 according to the first embodiment will be described with reference to FIG. 6. FIG. 6 is a schematic diagram showing an example of the threshold voltage distribution of the memory cell transistors included in the memory cell array of the semiconductor memory device according to the first embodiment. In the threshold voltage distribution shown in FIG. 6, the horizontal axis corresponds to the threshold voltage of the memory cell transistor MT. The vertical axis corresponds to the number of memory cell transistors MT. In FIG. 6, the threshold voltage and the number of memory cell transistors MT are shown as voltage Vth and value NMTs, respectively.

[0065] In the semiconductor memory device 1 according to the first embodiment, in each block BLK, for example, eight states are formed according to the threshold voltages of a plurality of memory cell transistors MT. Hereinafter, the eight states are referred to as "Er" state, "A" state, "B" state, "C" state, "D" state, "E" state, "F" state, and "G" state in order from the lower threshold voltage. The number of memory cell transistors MT included in the "Er" state to "G" state is, for example, made substantially equal to each other.

[0066] The "Er" state corresponds to, for example, a data erasure state. The threshold voltage of the memory cell transistor MT included in the "Er" state is less than the voltage VRA.

[0067] The "A" state, "B" state, "C" state, "D" state, "E" state, "F" state, and "G" state correspond to states in which data is written. The threshold voltage of the memory cell transistor MT included in the "A" state is equal to or higher than the voltage VRA and less than the voltage VRB (VRB > VRA). The threshold voltage of the memory cell transistor MT included in the "B" state is equal to or higher than the voltage VRB and less than the voltage VRC (VRC > VRB). The threshold voltage of the memory cell transistor MT included in the "C" state is equal to or higher than the voltage VRC and less than the voltage VRD (VRD > VRC). The threshold voltage of the memory cell transistor MT included in the "D" state is equal to or higher than the voltage VRD and less than the voltage VRE (VRE > VRD). The threshold voltage of the memory cell transistor MT included in the "E" state is equal to or higher than the voltage VRE and less than the voltage VRF (VRF > VRE). The threshold voltage of the memory cell transistor MT included in the "F" state is equal to or higher than the voltage VRF and less than the voltage VRG (VRG > VRF). The threshold voltage of the memory cell transistor MT included in the "G" state is equal to or higher than the voltage VRG and less than the voltage VREAD (VREAD > VRG). The voltage VREAD is a voltage that turns on the memory cell transistor MT regardless of whether the memory cell transistor MT is in the "Er" state to "G" state when the voltage is supplied to the gate (word line WL) of the memory cell transistor MT.

[0068] The memory cell transistor MT turns on when the voltage supplied to the gate (word line WL) is greater than the threshold voltage of the memory cell transistor MT. Also, the memory cell transistor MT turns off when the voltage supplied to the gate (word line WL) is less than or equal to the threshold voltage of the memory cell transistor MT.

[0069] To the threshold voltage distributions of the eight types of memory cell transistors MT described above, different 3-bit data are assigned respectively. An example of the assignment of data to the threshold voltage distributions is listed below. Hereinafter, the data assigned to each state are shown in the order of "upper bit, middle bit, lower bit" corresponding to the state.

[0070] "Er" state: "1, 1, 1" data, "A" state: "1, 1, 0" data, "B" state: "1, 0, 0" data, "C" state: "0, 0, 0" data, "D" state: "0, 1, 0" data, "E" state: "0, 1, 1" data, "F" state: "0, 0, 1" data, "G" state: "1, 0, 1" data.

[0071] When such data assignment is applied, one-page data (lower page data) composed of lower bits is determined by a read operation using each of the voltages VRA and VRE. One-page data (middle page data) composed of middle bits is determined by a read operation using each of the voltages VRB, VRD, and VRF. One-page data (upper page data) composed of upper bits is determined by a read operation using each of the voltages VRC and VRG.

[0072] Also, a verify voltage used for determining the threshold voltage of the memory cell transistor MT during a write operation is set between adjacent states. More specifically, a voltage VA is set as the verify voltage between the "Er" state and the "A" state. The voltage VA is, for example, higher than the voltage VRA. A voltage VB is set as the verify voltage between the "A" state and the "B" state. The voltage VB is, for example, higher than the voltage VRB. A voltage VC is set as the verify voltage between the "B" state and the "C" state. The voltage VC is, for example, higher than the voltage VRC. A voltage VD is set as the verify voltage between the "C" state and the "D" state. The voltage VD is, for example, higher than the voltage VRD. A voltage VE is set as the verify voltage between the "D" state and the "E" state. The voltage VE is, for example, higher than the voltage VRE. A voltage VF is set as the verify voltage between the "E" state and the "F" state. The voltage VF is, for example, higher than the voltage VRF. A voltage VG is set as the verify voltage between the "F" state and the "G" state. The voltage VG is, for example, higher than the voltage VRG.

[0073] In the description of the semiconductor memory device 1 according to the first embodiment, the case where each memory cell transistor MT stores 3-bit data is shown, but it is not limited thereto. The semiconductor memory device 1 may be configured such that each memory cell transistor MT stores 2-bit data or 4-bit data or more, for example.

[0074] 1.1.8 Sense Amplifier Module Next, the configuration of the sense amplifier module 18 in the semiconductor memory device 1 according to the first embodiment will be described with reference to FIG. 7. FIG. 7 is a block diagram showing an example of the configuration of the sense amplifier module of the semiconductor memory device according to the first embodiment.

[0075] The sense amplifier module 18 includes sense amplifier units SAU0 to SAU(n-1). The sense amplifier units SAU0 to SAU(n-1) are respectively associated with bit lines BL0 to BL(n-1). Hereinafter, when not distinguishing the sense amplifier units SAU0 to SAU(n-1), each of the sense amplifier units SAU0 to SAU(n-1) is simply referred to as a sense amplifier unit SAU.

[0076] Each sense amplifier unit SAU includes, for example, a sense amplifier section SA, and latch circuits SDL, ADL, BDL, CDL, and XDL.

[0077] In each sense amplifier unit SAU, the sense amplifier section SA, and the latch circuits SDL, ADL, BDL, CDL, and XDL are connected to the bus LBUS. The latch circuits SDL, ADL, BDL, CDL, and XDL can transmit and receive data with each other.

[0078] The sense amplifier section SA directly controls the bit line BL. During a write operation, the sense amplifier section SA applies a voltage to the bit line BL according to the write data. Also, during a read operation, the sense amplifier section SA senses the threshold voltage of the memory cell transistor MT by the voltage or current of the bit line BL corresponding to the sense amplifier unit SAU, and reads the data. During a read operation, a signal STB is given to the sense amplifier section SA by, for example, the sequencer 15. The sense amplifier section SA determines the read data at the timing when the signal STB is asserted, and stores it in the latch circuit SDL.

[0079] The latch circuits SDL, ADL, BDL, CDL, and XDL each temporarily hold data. The latch circuit XDL is used for input / output of data DAT between the input / output circuit of the semiconductor memory device 1 and the sense amplifier unit SAU. Also, the latch circuit XDL can also be used as, for example, the cache memory CM of the semiconductor memory device 1.

[0080] 1.2 Operations Next, the operation using the semiconductor memory device 1 according to the first embodiment will be described.

[0081] In the following description, the word line WL selected based on the address ADD is referred to as the selected word line WL. Also, the word line WL that is not selected is referred to as the non-selected word line WL. Further, the memory cell transistor MT connected to the selected word line WL is referred to as the selected memory cell transistor MT.

[0082] 1.2.1 Outline of Write Operation The outline of the write operation of the semiconductor memory device 1 according to the first embodiment will be described with reference to FIG. 8. FIG. 8 is a timing chart showing the outline of the write operation of the semiconductor memory device according to the first embodiment.

[0083] In the write operation, the semiconductor memory device 1 repeatedly executes a program loop operation. FIG. 8 shows the change in the voltage of the selected word line WL as the number of times the program loop operation is executed in the write operation increases. In the figures described below, the selected word line WL is shown as selected WL. In the following description, the number of times the program loop operation is executed is simply referred to as the loop count.

[0084] Each program loop operation includes a program operation and a verify operation. The semiconductor memory device 1 raises the threshold voltage of the memory cell transistor MT to a target voltage (hereinafter also referred to as the target level) by repeating the program loop operation.

[0085] In each program loop operation, the sequencer 15 executes the program operation before the verify operation.

[0086] The program operation is an operation that can increase the threshold voltage of the memory cell transistor MT. In the program operation, a plurality of selected memory cell transistors MT are set to the memory cell transistor MT to be programmed or the memory cell transistor MT prohibited from being programmed based on the write data stored in the associated sense amplifier unit SAU. When the threshold voltage of the selected memory cell transistor MT has not reached the target threshold voltage, the selected memory cell transistor MT is set to the memory cell transistor MT to be programmed. On the other hand, when the threshold voltage of the selected memory cell transistor MT has reached the target threshold voltage, the selected memory cell transistor MT is set to the memory cell transistor MT prohibited from being programmed.

[0087] In the program operation, a voltage VPGM (write voltage) is supplied to the selected word line WL. The voltage VPGM is a voltage capable of increasing the threshold voltage of the selected memory cell transistor MT. The voltage VPGM increases, for example, in response to an increase in the number of loops. In the example of FIG. 8, each time the number of loops increases, the voltage VPGM increases by the voltage dVP. When the voltage VPGM is supplied to the selected word line WL, the threshold voltage of the memory cell transistor MT to be programmed increases. On the other hand, the threshold voltage of the selected memory cell transistor MT set to the memory cell transistor MT prohibited from being programmed is maintained.

[0088] Hereinafter, the operation of increasing the threshold voltage of the memory cell transistor MT is referred to as “‘0’ program operation”. Also, the operation of maintaining the threshold voltage of the memory cell transistor MT is referred to as “‘1’ program operation”.

[0089] When the program operation ends, the sequencer 15 executes a verify operation.

[0090] The verify operation is a read operation that checks whether the threshold voltage of the selected memory cell transistor MT has reached the target threshold voltage. For example, in each program loop operation, the sequencer 15 performs a read operation using a predetermined verify voltage on the memory cell transistor MT to be programmed.

[0091] Note that in the example of FIG. 8, an example in which one verify voltage is used in each verify operation is shown, but it is not limited to this. In each verify operation, a plurality of verify voltages may be used. In this case, the sequencer 15, for example, sequentially performs read operations using a plurality of verify voltages.

[0092] In the verify operation, the sense amplifier unit SAU determines, based on the voltage of the bit line BL, whether the threshold voltage of the selected memory cell transistor MT is higher than the verify voltage supplied to the selected word line WL. Each sense amplifier unit SAU determines that the selected memory cell transistor MT for which it is determined that the threshold voltage is higher than the verify voltage is a "verify pass". On the other hand, each sense amplifier unit SAU determines that the selected memory cell transistor MT for which the threshold voltage is less than or equal to the verify voltage is a "verify fail". Each sense amplifier unit SAU stores the verify result described above in one of the latch circuits inside the sense amplifier unit SAU. When the verify operation is completed, the sequencer 15 sets each selected memory cell transistor MT as a memory cell transistor to be programmed or a memory cell transistor for which programming is prohibited based on the result of the verify operation, and starts the next program loop operation.

[0093] 1.2.2 Program Operation The program operation in the write operation using the semiconductor memory device 1 according to the first embodiment will be described with reference to FIG. 9. FIG. 9 is a timing chart showing an example of the voltages of the source line, bit line, channel of the memory pillar, word line, and selection gate line during the program operation in the write operation using the semiconductor memory device according to the first embodiment. Note that in the following timing chart, the voltage of the bit line BL is the voltage applied to the bit line BL by the sense amplifier section SA.

[0094] At time t0, the row decoder module 17 selects any one block BLK (selected block BLK) out of the plurality of blocks BLK. Also, the row decoder module 17 selects any one string unit SU (selected string unit SU) out of the plurality of string units SU. Then, the row decoder module 17 applies a voltage VPC1 (>VSS) to the selection gate line SGD (selected SGD in FIG. 9) in the selected string unit SU. The voltage VSS is the ground voltage. Thereby, the selection transistor ST1 corresponding to the selected string unit SU is in the on state. A voltage VSS is applied to the selection gate line SGD (non-selected SGD in FIG. 9) of the string unit SU (non-selected string unit SU) that is not the selected string unit SU among the plurality of string units SU. Thereby, the selection transistor ST1 corresponding to the non-selected string unit SU is in the off state. Also, a voltage VSS is applied to the selection gate line SGS. Thereby, the selection transistor ST2 is in the off state. Also, the row decoder module 17 applies a voltage VPC2 (>VSS) to all the word lines WL of the selected block BLK. Thereby, all the memory cell transistors MT of the selected block BLK are in the on state.

[0095] That is, at time t0, the row decoder module 17 supplies a voltage for electrically connecting the channels of all memory pillars MP to the corresponding bit lines BL to the selection block BLK. In this case, among the word lines WL of the selection block BLK, a voltage VPC2 may be applied only to the word line WL (selected word line WL) that is the target of the programming operation and the word line WL (non-selected word line WL) located closer to the bit line BL side than that. Note that at time t0, the row decoder module 17 may supply a voltage for electrically connecting the channels of all memory pillars MP to the source line SL to the selection block BLK. In this case, a voltage VPC1 is applied to the selection gate line SGS, and a voltage VPC2 may be applied only to the word line WL (selected word line WL) that is the target of the programming operation and the word line WL (non-selected word line WL) located closer to the source line SL side than that among the word lines WL of the selection block BLK.

[0096] At time t1, the sense amplifier module 18 applies a voltage VBL to the bit line BL (hereinafter, bit line BL(“1”)) corresponding to the memory cell transistor MT that is the target of the “1” programming operation. As a result, the voltage of the channel of the memory pillar MP (hereinafter, memory pillar MP(“1”)) corresponding to the memory cell transistor MT that is the target of the “1” programming operation becomes equal to the voltage VBL. On the other hand, a voltage VSS is applied to the bit line BL (hereinafter, bit line BL(“0”)) corresponding to the memory cell transistor MT that is the target of the “0” programming operation. As a result, the voltage of the channel of the memory pillar MP (hereinafter, memory pillar MP(“0”)) corresponding to the memory cell transistor MT that is the target of the “0” programming operation is equal to the voltage VSS. Note that in FIG. 9, the voltage of the channel of the memory pillar MP(“1”) and the voltage of the channel of the memory pillar MP(“0”) are simply shown as the memory pillars MP(“1”) and MP(“0”), respectively.

[0097] At time t2, the row decoder module 17 reduces the voltage of the selection gate line SGD in the selection string unit SU from the voltage VPC1 to the voltage VSS. Also, the row decoder module 17 reduces the voltage of all word lines WL in the selection block BLK from the voltage VPC2 to the voltage VSS.

[0098] At time t3, the row decoder module 17 applies a voltage VS1 (>VSS) to the selection gate line SGD in the selection string unit SU. The voltage VS1 turns on the selection transistor ST1 to which the voltage VSS is applied to the bit line BL, but is a voltage that turns off the selection transistor ST1 to which the voltage VBL is applied to the bit line BL. The voltage VS1 is, for example, equal to or less than the voltage VPC1. Also, the driver module 16 applies a voltage VSL (>VSS) to the source line SL. As a result, the channel of the memory pillar MP (“1”) becomes a floating state electrically insulated from the bit line BL and the source line SL. In the figure showing the following timing chart, the voltage in the floating state is indicated by a dashed line.

[0099] At time t4, the row decoder module 17 selects any word line WL (selected word line WL) in the selection block BLK. The row decoder module 17 applies a voltage VPGM1 to the selected word line WL. Also, the row decoder module 17 applies a voltage VPASSH to the other word lines WL (non-selected word lines WL) of the word lines WL in the selection block BLK other than the selected word line WL. In the figure described below, the non-selected word line WL is shown as non-selected WL. In FIG. 9, an example is shown in which the row decoder module 17 raises the voltage of the selected word line WL and the non-selected word line WL to the voltage VPASSH and then raises the voltage of the selected word line WL to the voltage VPGM1.

[0100] Also, due to the capacitive coupling between the channel of the floating memory pillar MP(“1”) and the word line WL, the voltage of the channel rises to a voltage equivalent to the voltage VPASSH, similar to the non-selected word line WL.

[0101] At time t5, the row decoder module 17 reduces the voltage of the selected gate line SGD in the selection string unit SU from the voltage VS1 to the voltage VSS. As a result, the channel of the memory pillar MP(“0”) also enters a floating state, electrically insulated from the bit line BL and the source line SL.

[0102] At time t6, the row decoder module 17 reduces the voltage of the other non-selected word lines WL from the voltage VPASSH to the voltage VPASSL1. The voltage VPASSL1 is a voltage lower than the voltage VPASSH by the voltage VC1.

[0103] As a result, the channel of the floating memory pillar MP(“0”) is reduced to a voltage approximately equivalent to the voltage Vn1(<VSS) due to the capacitive coupling between the channel and the word line WL. The voltage Vn1 is a voltage lower than the voltage VSS by the voltage VC1. The voltage Vn1 is, for example, a negative voltage. Also, the channel of the floating memory pillar MP(“1”) is reduced to a voltage approximately equivalent to the voltage VPASSL1, similar to the non-selected word line WL, due to the capacitive coupling between the channel and the word line WL.

[0104] That is, in the NAND string NS corresponding to the bit line BL(“0”), the potential difference between the selected word line WL and the channel increases from “VPGM1 - VSS” to “VPGM1 - Vn1”, electrons are injected into the charge storage layer of the memory cell transistor MT, and its threshold voltage increases.

[0105] Even for the NAND string NS corresponding to the bit line BL(“1”), although the potential difference between the selected word line WL and the channel increases from “VPGM1 - VPASSH” to “VPGM1 - VPASSL1”, since “VPGM1 - VPASSL1” is sufficiently small, electrons are not injected into the charge storage layer of the memory cell transistor MT, and its threshold voltage is maintained.

[0106] At time t7, the row decoder module 17 applies the voltage VSS to the selected word line WL and the non - selected word line WL. Thereby, the injection of charge into the charge storage layer ends.

[0107] At time t8, the sense amplifier module 18 applies the voltage VSS to the bit line BL.

[0108] Also, the driver module 16 applies the voltage VSS to the source line SL.

[0109] Thus, the program operation ends.

[0110] Note that FIG. 9 is merely an example of the timing chart of the program operation according to the first embodiment, and the timing of applying each voltage to each of the source line SL, the bit line BL, the channel of the memory pillar MP, the word line WL, and the selected gate lines SGD and SGS does not necessarily coincide with the timing shown in FIG. 9. For example, in FIG. 9, an example is shown in which the voltage of the selected word line WL reaches the voltage VPGM1 before the time t6 when the voltage of the non - selected word line WL is reduced from the voltage VPASSH to the voltage VPASSL1, but it is not limited to this. The row decoder module 17 may apply a voltage so that the voltage of the selected word line WL reaches the voltage VPGM1, for example, after the time t6 when the voltage of the non - selected word line WL is reduced from the voltage VPASSH to the voltage VPASSL1.

[0111] Also, the magnitude relationship of the voltages applied to each of the source line SL, bit line BL, channel of the memory pillar MP, word line WL, and the voltages of the select gate lines SGD and SGS is not necessarily the same as the magnitude relationship of the voltages shown in FIG. 9. For example, the voltage VPC1 applied to the select gate line SGD in the select string unit SU at time t0 may be a voltage that turns on the select transistor ST1, and can be appropriately set according to the threshold voltage of the select transistor ST1. The voltages applied to the other select gate lines SGD, word line WL, and select gate line SGS can also be appropriately set according to the threshold voltages of the select transistor ST1, memory cell transistor MT, and select transistor ST2.

[0112] 1.3 Effects According to the first embodiment, an increase in the write voltage can be suppressed. The effects of the first embodiment will be described below.

[0113] In the semiconductor memory device 1 according to the first embodiment, in the program operation of the write operation, the sequencer 15 is configured to make the channel of the NAND string NS corresponding to the bit line BL(“0”) in a floating state while applying the voltage VPGM1 to the selected word line WL. That is, in the semiconductor memory device 1 according to the first embodiment, when injecting electrons into the charge storage layer of the memory cell transistor MT by applying the voltage VPGM1 to the selected word line WL (for example, during the period from time t4 to time t7 in FIG. 9), the channel of the NAND string NS corresponding to the bit line BL(“0”) is transitioned from a state of being electrically connected to at least the bit line BL(“0”) to a floating state electrically insulated from the bit line BL(“0”) and the source line SL. At this time, the row decoder module 17 reduces the voltage of the non-selected word line from the voltage VPASSH to the voltage VPASSL1. As a result, the voltage of the channel of the NAND string NS in the floating state is reduced by the capacitive coupling between the channel and the word line WL. Therefore, according to the semiconductor memory device 1 according to the first embodiment, by reducing the voltage of the channel via the non-selected word line, the potential difference between the selected word line and the channel can be increased. In other words, by making the channel of the NAND string NS corresponding to the bit line BL(“0”) in a floating state and reducing the voltage of the non-selected word line, the voltage of the selected word line can be effectively increased. While suppressing an increase in the write voltage, it is possible to secure the potential difference between the selected word line and the channel for injecting electrons into the charge storage layer in the program operation.

[0114] Also, according to the semiconductor memory device 1 according to the first embodiment, by suppressing the increase in the writing voltage as described above, it is possible to suppress an increase in the size of the semiconductor memory device 1 and an increase in the manufacturing cost. Supplementally, for example, by thinning the conductor layer and the insulator layer in the memory cell array in the Z direction, an increase in the size of the memory cell array and the semiconductor memory device can be suppressed. However, in this case, it is known that the potential difference between the selection word line and the channel required for injecting electrons into the charge storage layer increases. As a result, when the size of the memory cell array is reduced, the size of a circuit such as a driver module may increase as the writing voltage increases. According to the semiconductor memory device 1 according to the first embodiment, the increase in the writing voltage can be suppressed as described above. Thereby, even when the size of the memory cell array 10 is reduced, an increase in the size of the circuit can be suppressed. Therefore, according to the semiconductor memory device 1 according to the first embodiment, an increase in the size of the semiconductor memory device 1 and an increase in the manufacturing cost can be suppressed.

[0115] Also, according to the semiconductor memory device 1 according to the first embodiment, instead of directly applying a voltage (negative voltage) less than VSS to the bit line BL, the sense amplifier module 18 reduces the voltage of the channel by capacitive coupling between the channel and the word line WL. With such a configuration, an increase in the circuit configuration for the sense amplifier module to apply a voltage less than VSS to the bit line can be suppressed. Also by the above, an increase in the size of the semiconductor memory device 1 and an increase in the manufacturing cost can be suppressed.

[0116] 2 Variations of the First Embodiment The above-described first embodiment can be variously modified. Hereinafter, a semiconductor memory device according to a variation of the first embodiment will be described.

[0117] 2.1 First Variation of the First Embodiment In the above-described first embodiment, an example in which the "0" program operation and the "1" program operation are executed in the program operation has been shown, but the present invention is not limited thereto. For example, in the "0" program operation, depending on the difference between the target level and the threshold voltage of the memory cell transistor MT, either a first program condition in which the amount of increase in the threshold voltage is relatively large, or a second program condition in which the amount of increase in the threshold voltage is smaller than the first program condition may be applied.

[0118] The configuration of the semiconductor memory device according to the first modification of the first embodiment can be made substantially equivalent to the configuration of the semiconductor memory device according to the first embodiment. Hereinafter, the program operation in the writing operation using the semiconductor memory device according to the first modification of the first embodiment will be mainly described.

[0119] 2.1.1 Outline of Program Operation The program operation in the writing operation using the semiconductor memory device according to the first modification of the first embodiment will be described with reference to FIG. 10. FIG. 10 is a diagram for explaining the selection of the program operation in the writing operation using the semiconductor memory device according to the first modification. In the example of FIG. 10, an example of the threshold voltage distribution in the middle of writing the memory cell transistor MT having a target level of voltage VA from the "Er" state to the "A" state is shown.

[0120] For example, when it is assumed that the threshold voltage of the memory cell transistor MT is sufficiently lower than the target level and the target level cannot be reached in the next program operation, the first program condition in which the amount of increase in the threshold voltage is relatively large is applied. Further, when the threshold voltage of the memory cell transistor MT is relatively close to the target target level and it is assumed that the threshold voltage will greatly exceed the target level if the first program condition is applied in the next program operation, the second program condition is applied.

[0121] Similar to the first embodiment, when the threshold voltage of the memory cell transistor MT is equal to or higher than the voltage VH (target level), a "1" programming operation is applied to the memory cell transistor MT. Also, when the threshold voltage of the memory cell transistor MT is lower than the voltage VH, a "0" programming operation is applied to the memory cell transistor MT. In the example of FIG. 10, the voltage VH is the voltage VA.

[0122] Among the "0" programming operations, in order to determine which of the first programming condition and the second programming condition is applied, for example, a predetermined voltage VL lower than the voltage VH can be set. That is, when the threshold voltage of the memory cell transistor MT is lower than the voltage VL, the first programming condition is applied to the memory cell transistor MT. The "0" programming operation to which the first programming condition is applied corresponds to the "0" programming operation in the first embodiment. When the threshold voltage of the memory cell transistor MT is equal to or higher than the voltage VL and lower than the voltage VH, in the next programming operation, the second programming condition is applied to the memory cell transistor MT. In the example of FIG. 10, the state where the threshold voltage of the memory cell transistor MT is lower than the voltage VL and the state where the threshold voltage of the memory cell transistor MT is equal to or higher than the voltage VL and lower than the voltage VH are the "Er_1" state and the "Er_2" state, respectively.

[0123] 2.1.2 Timing Chart Next, the timing chart during the programming operation using the semiconductor memory device 1 according to the first modification of the first embodiment will be described with reference to FIG. 11. FIG. 11 is a timing chart showing an example of the voltages of the source line, bit line, channel of the memory pillar, word line, and select gate line during the programming operation in the writing operation using the semiconductor memory device according to the first modification of the first embodiment.

[0124] In the first modification of the first embodiment, the bit line BL corresponding to the memory cell transistor MT targeted by the "0" program operation to which the first program condition is applied, and the bit line BL corresponding to the memory cell transistor MT targeted by the "1" program operation are respectively referred to as bit line BL("0") and BL("1"). Further, the bit line BL corresponding to the memory cell transistor MT targeted by the "0" program operation to which the second program condition is applied is referred to as BL("QPW") to distinguish it from the bit line BL("0").

[0125] The operations of the semiconductor memory device 1 at times t10 to t13, t15, t17, and t18 can be made substantially equivalent to the operations of the semiconductor memory device at times t0 to t3, t5, t7, and t8 in the first embodiment, except that voltages equivalent to the bit line BL("0") in the first embodiment are applied to the bit lines BL("0") and BL("QPW").

[0126] At time t14, the sense amplifier module 18 applies a voltage VBLQ (> VSS) to the bit line BL("QPW"). The voltage VBLQ is lower than the voltage VBL. When a voltage VS1 is applied to the selection gate line SGD, the selection transistor ST1 to which the voltage VBLQ is applied to the bit line BL is turned on. As a result, the voltage of the channel of the memory pillar MP("QPW") corresponding to the bit line BL("QPW") becomes equal to the voltage VBLQ of the bit line BL("QPW").

[0127] At time t15, similar to time t5 in the first embodiment, the voltage of the selection gate line SGD is reduced from the voltage VS1 to the voltage VSS. As a result, the channels of the memory pillar MP("0") corresponding to the bit line BL("0") and the memory pillar MP("QPW") become in a floating state electrically insulated from the bit line BL and the source line SL, similar to the channel of the memory pillar MP("0") at time t5 in the first embodiment.

[0128] At time t16, the voltages of the channels of the memory pillars MP(“0”) and the voltages of the channels of the memory pillars MP(“1”) are each reduced by capacitive coupling between the channels and the word lines WL, similar to the channels of the memory pillars MP(“0”) and the channels of the memory pillars MP(“1”) at time t6 in the first embodiment. Also, the voltage of the channel of the memory pillar MP(“QPW”) corresponding to the bit line BL(“QPW”) is reduced to a voltage substantially equal to the voltage Vn2 by capacitive coupling between the channel and the word line WL. The voltage Vn2 is a voltage lower than the voltage VC1 by the voltage VBLQ.

[0129] As described above, in the NAND string NS corresponding to the bit line BL(“0”), electrons are injected into the charge storage layer and the threshold voltage of the memory cell transistor MT is increased, similar to the NAND string NS corresponding to the bit line BL(“0”) in the first embodiment.

[0130] Also, in the NAND string NS corresponding to the bit line BL(“QPW”), since the potential difference (VPGM1 - Vn2) between the selected word line and the channel is large, electrons are injected into the charge storage layer and the threshold voltage of the memory cell transistor MT is increased. Note that since the potential difference (VPGM1 - Vn2) is smaller than the potential difference (VPGM1 - Vn1), the amount of increase in the threshold voltage of the memory cell transistor MT is smaller than the amount of increase in the threshold voltage of the memory cell transistor MT of the NAND string NS corresponding to the bit line BL(“0”).

[0131] As described above, the program operation ends.

[0132] According to the first modification of the first embodiment, the same effects as those of the first embodiment are achieved.

[0133] 2.2 Second Modification of the First Embodiment In the above-described first embodiment, an example was shown in which the low decoder module 17 reduces the voltage of the selection gate line SGD in the selection string unit SU to the voltage VSS at the time t5 of the program operation. However, the present invention is not limited to this. The low decoder module 17 may reduce the voltage of the selection gate line SGD to a voltage lower than the voltage VSS.

[0134] The configuration of the semiconductor memory device according to the second modification of the first embodiment can be made substantially equivalent to the configurations of the semiconductor memory devices according to the first embodiment and the first modification of the first embodiment. Hereinafter, the program operation in the writing operation using the semiconductor memory device according to the second modification of the first embodiment will be mainly described.

[0135] The timing chart during the program operation using the semiconductor memory device 1 according to the second modification of the first embodiment will be described with reference to FIG. 12. FIG. 12 is a timing chart showing an example of the voltages of the source line, bit line, channel of the memory pillar, word line, and selection gate line during the program operation in the writing operation using the semiconductor memory device according to the second modification of the first embodiment.

[0136] The operations of the semiconductor memory device 1 at times t20 to t24 and t26 to t28 can be made substantially equivalent to the operations of the semiconductor memory device at times t0 to t4 and t6 to t8 in the first embodiment.

[0137] At time t25, as described above, the sense amplifier module 18 reduces the voltage of the selection gate line SGD in the selection string unit SU from the voltage VS1 to a voltage lower than the voltage VSS. Thereby, for example, the selection transistor ST1 in the selection string unit SU can be surely turned off.

[0138] Thus, the program operation ends.

[0139] Also according to the first modification of the first embodiment, the same effects as those of the first embodiment and the first modification of the first embodiment are achieved.

[0140] 2.3 Third Modification Example of the First Embodiment In the first modification example of the first embodiment described above, similar to the first embodiment, an example was shown in which the row decoder module 17 reduces the voltage of the selection gate line SGD in the selection string unit SU to the voltage VSS at the time t15 of the program operation, but it is not limited to this. The row decoder module 17 may reduce the voltage of the selection gate line SGD to a voltage less than the voltage VSS, similar to the second modification example of the first embodiment.

[0141] The configuration of the semiconductor memory device according to the third modification example of the first embodiment can be made substantially equivalent to the configurations of the semiconductor memory devices according to the first embodiment, the first modification example of the first embodiment, and the second modification example of the first embodiment. Hereinafter, the program operation in the writing operation using the semiconductor memory device according to the third modification example of the first embodiment will be mainly described.

[0142] The timing chart during the program operation using the semiconductor memory device 1 according to the third modification example of the first embodiment will be described with reference to FIG. 13. FIG. 13 is a timing chart showing an example of the voltages of the source line, bit line, channel of the memory pillar, word line, and selection gate line during the program operation in the writing operation using the semiconductor memory device according to the third modification example of the first embodiment.

[0143] The operations of the semiconductor memory device 1 at times t30 to t34 and t36 to t38 can be made substantially equivalent to the operations of the semiconductor memory device at times t10 to t14 and t16 to t18 in the first modification example of the first embodiment.

[0144] At time t35, as described above, the sense amplifier module 18 reduces the voltage of the selection gate line SGD in the selection string unit SU from the voltage VS1 to a voltage less than the voltage VSS, similar to the operation at time t25 in the second modification example of the first embodiment. Thereby, for example, the selection transistor ST1 in the selection string unit SU can be surely turned off.

[0145] Thus, the program operation ends.

[0146] Also according to the third modification example of the first embodiment, effects equivalent to those of the first embodiment, the first modification example of the first embodiment, and the second modification example of the first embodiment are achieved.

[0147] 3 Second Embodiment In the above-described first embodiment, the first modification example of the first embodiment, the second modification example of the first embodiment, and the third modification example of the first embodiment, an example is shown in which the channel of the memory pillar MP targeted for the "0" program operation is made floating by the selection transistor ST, but it is not limited thereto. For example, each NAND string includes a dummy cell transistor. Then, the channel of the memory pillar MP targeted for the "0" program operation may be made floating by the dummy cell transistor.

[0148] Hereinafter, the configuration and operation of the semiconductor memory device according to the second embodiment will be mainly described with differences from the first embodiment.

[0149] 3.1 Configuration The configuration of the memory system including the semiconductor memory device according to the second embodiment can be the same as that of the memory system including the semiconductor memory device according to the first embodiment. Also, the semiconductor memory device 1 according to the second embodiment, similar to the semiconductor memory device according to the first embodiment, includes a memory cell array 10, an input / output circuit 11, a logic control circuit 12, an address register 13, a command register 14, a sequencer 15, a driver module 16, a row decoder module 17, and a sense amplifier module 18. The configurations of the input / output circuit 11, the logic control circuit 12, the address register 13, the command register 14, the sequencer 15, the driver module 16, the row decoder module 17, and the sense amplifier module 18 of the semiconductor memory device 1 according to the second embodiment can be substantially equivalent to those of these configurations according to the first embodiment. Therefore, hereinafter, the configuration of the memory cell array 10 according to the second embodiment will be mainly described with differences from the configuration of the memory cell array according to the first embodiment.

[0150] 3.1.1 Circuit Configuration of Memory Cell Array The configuration of the memory cell array 10 in the second embodiment will be described with reference to FIG. 14. FIG. 14 is a circuit diagram for explaining an example of the configuration of the memory cell array of the semiconductor memory device according to the second embodiment.

[0151] In the second embodiment, each NAND string NS includes, for example, eight memory cell transistors MT0 to MT7, selection transistors ST1 and ST2, and dummy cell transistors DTD and DTS. In the following description, when the dummy cell transistors DTD and DTS are not distinguished, each of the dummy cell transistors DTD and DTS is simply referred to as a dummy cell transistor DT.

[0152] The drain of the dummy cell transistor DTD is connected to the source of the selection transistor ST1. The source of the dummy cell transistor DTD is connected to the drain of the memory cell transistor MT7.

[0153] The drain of the dummy cell transistor DTS is connected to the source of the memory cell transistor MT0. The source of the dummy cell transistor DTS is connected to the drain of the selection transistor ST2.

[0154] The gates of the dummy cell transistors DTD included in each block BLK are connected to the dummy word line DWLD. Also, the gates of the dummy cell transistors DTS included in each block BLK are connected to the dummy word line DWLS. In the following description, when the dummy word lines DWLD and DWLS are not distinguished, each of the dummy word lines DWLD and DWLS is simply referred to as the dummy word line DWL.

[0155] 3.1.2 Structure of Memory Cell Array The structure of the memory cell array 10 of the semiconductor memory device 1 according to the second embodiment will be described with reference to FIG. 15. FIG. 15 is a cross-sectional view for explaining an example of the structure of the memory cell array of the semiconductor memory device according to the second embodiment.

[0156] The memory cell array 10 further includes conductor layers 46 and 47, and insulator layers 35 and 36.

[0157] An insulator layer 35 is laminated on the conductor layer 42. A conductor layer 46 is laminated on the insulator layer 35. The conductor layer 46 is used as the dummy word line DWLS. The conductor layer 46 contains, for example, tungsten.

[0158] On the conductor layer 46, eight insulator layers 32 and eight conductor layers 43 are laminated in the same manner as in the first embodiment. An insulator layer 36 is laminated on the uppermost conductor layer 43. A conductor layer 47 is laminated on the insulator layer 36. The conductor layer 47 is used as the dummy word line DWLD. The conductor layer 47 contains, for example, tungsten.

[0159] On the conductor layer 47, an insulator layer 33, a conductor layer 44, an insulator layer 34, and a conductor layer 45 are laminated in this order in the same manner as in the first embodiment.

[0160] Each of the memory pillars MP penetrates through the insulator layers 31 to 33, 35, and 36, and the conductor layers 42 to 44, 46, and 47. The portion where the memory pillar MP intersects with the conductor layer 46 functions as a dummy cell transistor DTS. The portion where the memory pillar MP intersects with the conductor layer 47 functions as a dummy cell transistor DTD.

[0161] The member SLT divides, for example, the conductor layers 42 to 44, 46, and 47.

[0162] The lower surface of the member SHE is located, for example, between the conductor layer 47 and the conductor layer 44.

[0163] 3.1.3 Threshold Voltage Distribution of Memory Cell Transistors The threshold voltage distribution of the memory cell transistor MT in the semiconductor memory device 1 according to the second embodiment will be described with reference to FIG. 16. FIG. 16 is a schematic diagram showing an example of the threshold voltage distribution of the memory cell transistors included in the memory cell array of the semiconductor memory device according to the second embodiment. In the threshold voltage distribution shown in FIG. 16, the horizontal axis corresponds to the threshold voltages of the memory cell transistor MT and the dummy cell transistor DT. The vertical axis corresponds to the number of the memory cell transistor MT and the dummy cell transistor DT. In FIG. 16, the number of the memory cell transistor MT and the dummy cell transistor DT is shown as a value NMTs.

[0164] The threshold voltage distributions of the plurality of memory cell transistors MT are equivalent to those of the plurality of memory cell transistors MT in the first embodiment. The dummy cell transistor DT has a threshold voltage higher than the threshold voltage of the erased state of the memory cell transistor MT. The threshold voltage of the dummy cell transistor DT is, for example, equal to or higher than the voltage VRG and lower than the voltage VREAD. That is, the dummy cell transistor DT is included in the "G" state, for example. In FIG. 16, among the memory cell transistors MT and the dummy cell transistors DT included in the "G" state, the dummy cell transistors DT are indicated by hatching.

[0165] 3.2 Operation Next, the operation using the semiconductor memory device 1 according to the second embodiment will be described.

[0166] The outline of the writing operation using the semiconductor memory device 1 according to the second embodiment is the same as the outline of the writing operation using the semiconductor memory device 1 according to the first embodiment. Hereinafter, the program operation in the writing operation using the semiconductor memory device 1 according to the second embodiment will be described with reference to FIG. 17. FIG. 17 is a timing chart showing an example of the voltages of the source line, bit line, channel of the memory pillar, word line, dummy word line, and selection gate line during the program operation in the writing operation using the semiconductor memory device according to the second embodiment.

[0167] At time t40, the row decoder module 17 applies the voltage VPC3 to the dummy word line DWL. Also, the row decoder module 17 applies voltages to the word line WL and the selection gate line SGD in the same manner as the operation of the semiconductor memory device at time t0 in the first embodiment.

[0168] The operation of the semiconductor memory device 1 at time t41 can be made substantially equivalent to the operation of the semiconductor memory device at time t1 in the first embodiment.

[0169] At time t42, the row decoder module 17 reduces the voltage of the dummy word line DWL from the voltage VPC3 to the voltage VSS. Also, the row decoder module 17 reduces the voltages of the word line WL and the selection gate line SGD in the same manner as the operation of the semiconductor memory device at time t2 in the first embodiment.

[0170] The operation of the semiconductor memory device 1 at time t43 can be made equivalent to the operation of the semiconductor memory device at time t3 in the first embodiment. By the process at time t43, as in the first embodiment, the channel of the memory pillar MP(“1”) becomes a floating state electrically insulated from the bit line BL and the source line SL.

[0171] At time t44, the row decoder module 17 applies the voltage VPASSH to the dummy word line DWL. Also, the row decoder module 17 applies a voltage to the word line WL in the same manner as the operation of the semiconductor memory device at time t4 in the first embodiment, except that the voltage VPGM2 is applied instead of the voltage VPGM1.

[0172] Also, similar to the first embodiment, due to the capacitive coupling between the channel of the memory pillar MP(“1”) and the word line WL, the voltage of the channel rises to a voltage equivalent to the voltage VPASSH, similar to the non-selected word line WL.

[0173] At time t45, the row decoder module 17 reduces the voltage of the dummy word line DWL from the voltage VPASSH to the voltage VSS. As a result, the channel of the memory pillar MP(“0”) becomes in a floating state electrically insulated from the bit line BL and the source line SL. Also, the row decoder module 17 reduces the voltage of the selected gate line SGD to the voltage VSS, for example, in the same manner as the operation of the semiconductor memory device at time t5 in the first embodiment.

[0174] At time t46, the row decoder module 17 reduces the voltage of the non-selected word line WL from the voltage VPASSH to the voltage VPASSL2. The voltage VPASSL2 is a voltage lower than the voltage VC2 with respect to the voltage VPASSH.

[0175] Also, the channel of the memory pillar MP(“0”) reduces to a voltage equivalent to the voltage Vn3(<VSS) due to the capacitive coupling between the channel and the word line WL. The voltage Vn3 is a voltage lower than the voltage VC2 with respect to the voltage VSS. The voltage Vn3 is, for example, a negative voltage. Also, similar to the first embodiment, the channel of the memory pillar MP(“1”) reduces to a voltage equivalent to the voltage VPASSL2 due to the capacitive coupling between the channel and the word line WL.

[0176] As described above, in the NAND string NS corresponding to the bit line BL(“0”), since the potential difference (VPGM2 - Vn3) between the selected word line and the channel is large, electrons are injected into the charge storage layer, and the threshold voltage of the memory cell transistor MT increases.

[0177] Also, in the NAND string NS corresponding to the bit line BL(“1”), since the potential difference between the selected word line and the channel is small, almost no electrons are injected into the charge storage layer. As a result, the threshold voltage of the memory cell transistor MT is maintained.

[0178] The operations of the semiconductor memory device 1 at times t47 and t48 are the same as the operations of the semiconductor memory device at times t7 and t8 in the first embodiment.

[0179] As described above, the program operation ends.

[0180] Also, according to the second embodiment, the same effects as those of the first embodiment, the first modification of the first embodiment, the second modification of the first embodiment, and the third modification of the first embodiment are achieved.

[0181] In addition, since the dummy cell transistor DT has a threshold voltage higher than the erased state, the voltage of the channel of the memory pillar MP(“0”) can be reduced. To supplement, since the threshold voltage of the dummy cell transistor DT is higher than the erased state, for example, when the voltage of the channel of the memory pillar MP(“0”) is reduced at time t46, it is suppressed that the dummy cell transistor DT becomes on. That is, the channel of the memory pillar MP(“0”) can be maintained in a floating state. Also, with such a configuration, an increase in the write voltage can be suppressed.

[0182] 4 Others Note that the embodiments described above are presented as examples and are not intended to limit the scope of the invention. The above embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0183] 1…Semiconductor memory device, 2…Memory controller, 3…Memory system, 4…Host device, 10…Memory cell array, 11…Input / output circuit, 12…Logic control circuit, 13…Address register, 14…Command register, 15…Sequencer, 16…Driver module, 17…Row decoder module, 18…Sense amplifier module, 20…CPU, 21…Built-in memory, 22…Buffer memory, 23…NAND I / F, 24…Host I / F, WL…Word line, MT…Memory cell transistor, DMT…Dummy cell transistor, ST1, ST2…Selection transistor, NS…NAND string, CU…Cell unit, SU…String unit.

Claims

1. A first memory string in which a plurality of memory cells including a first memory cell and a second memory cell are connected in series; A first word line connected to the gate of the first memory cell; A second word line connected to the gate of the second memory cell; A first bit line connected to one end of the first memory string; A source line connected to the other end of the first memory string; A control circuit; Comprising; In the programming operation for the first memory cell, the control circuit While applying a write voltage to the first word line, puts the channel of the first memory string in a floating state electrically insulated from the first bit line and the source line; After putting the channel of the first memory string in a floating state, reduces the voltage of the second word line from a first voltage less than the write voltage to a second voltage less than the first voltage; Configured as; A semiconductor memory device.

2. Configured such that when the control circuit reduces the voltage of the second word line to the second voltage, the voltage of the channel of the first memory string becomes less than the ground voltage; Configured as; The semiconductor memory device according to Claim 1.

3. A first selection transistor provided between the first bit line and one end of the plurality of memory cells; A second selection transistor provided between the source line and the other end of the plurality of memory cells; Further comprising; In the programming operation for the first memory cell, the control circuit Makes the first memory string in a floating state by turning off the first selection transistor and the second selection transistor; Configured as; The semiconductor memory device according to Claim 1.

4. A second memory string in which a plurality of memory cells including a third memory cell and a fourth memory cell are connected in series; A second bit line connected to one end of the second memory string; Further comprising; The first word line is connected to the gate of the third memory cell, The second word line is connected to the gate of the fourth memory cell, The source line is connected to the other end of the second memory string, In the programming operation for the first memory cell, the control circuit While putting the channel of the second memory string in a floating state, reduces the voltage of the second word line from the first voltage to the second voltage; Configured as; The semiconductor memory device according to claim 1.

5. When the control circuit reduces the voltage of the second word line to the second voltage, the voltage of the channel of the second memory string becomes less than the first voltage. It is configured as follows. The semiconductor memory device according to claim 4.

6. The threshold voltage of the first selection transistor and the threshold voltage of the second selection transistor are higher than the threshold voltage of the erased state of the plurality of memory cells. The semiconductor memory device according to claim 3.

7. It further includes a first gate line connected to the gate of the first selection transistor. In the programming operation for the first memory cell, when the control circuit sets the first memory string to a floating state. The voltage of the first gate line is made less than the ground voltage. It is configured as follows. The semiconductor memory device according to claim 3.

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