Power supply circuit and drive circuit

The power supply circuit addresses the issue of output voltage exceeding breakdown voltage by using a transistor configuration with a protection diode and passive elements to manage gate potential, ensuring safe operation.

JP2025110693APending Publication Date: 2025-07-29MITSUMI ELECTRIC CO LTD
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Patent Information

Application Number
JP2024004670
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-01-16
Publication Date
2025-07-29

AI Technical Summary

Technical Problem

In power supply circuits using series regulators, there is a risk that the output voltage may rise and exceed the breakdown voltage of elements due to current flowing into the output terminal when the input voltage rises, particularly in systems with N-channel MOS transistors.

Method used

A power supply circuit configuration with a first transistor for output control, a protection diode connected between the output and gate terminals, a second transistor for pull-down, and a third transistor controlled by an external signal, utilizing passive elements to manage the gate potential of the pull-down transistor, preventing excessive output voltage rise.

Benefits of technology

Prevents the output terminal potential from rising above the breakdown voltage of elements by ensuring current flows through low-resistance paths, thereby maintaining safe operating conditions.

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Abstract

To provide a power supply circuit capable of preventing the potential at an output terminal from rising to exceed the withstand voltage of a load as an electric current flows to the output terminal from outside when an input voltage rises.SOLUTION: A power supply circuit comprises a voltage regulator which has a first transistor for output control connected between a voltage input terminal and a voltage output terminal, and an amplifier. A diode for protection is so provided between the voltage output terminal and the gate terminal of the first transistor as to have its cathode terminal connected to the gate terminal. A second transistor for pull-down is provided between the gate terminal of the first transistor and a reference potential point, and a third transistor in which an external control signal is input is provided between the gate terminal of the second transistor and the reference potential point. Then a voltage generated by a resistance element connected in series between the voltage input terminal and reference potential point and a reversely-connected diode is applied to the gate terminal of the second transistor.SELECTED DRAWING: Figure 1
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Description

Technical Field

[0001] The present invention relates to a technique effective for use in a power supply circuit and a drive circuit.

Background Art

[0002] A power supply circuit is used to supply an appropriate power supply voltage to loads such as an IC (integrated circuit) and circuit blocks in the IC. Various types of power supply circuits are known, such as a linear regulator and a switching regulator, and for example, an invention related to a power supply circuit composed of a linear regulator is described in Patent Document 1. In addition, in a linear power supply circuit, an invention for avoiding problems occurring in a load using the output voltage of the linear power supply circuit due to a steep rise in the input voltage is described in Patent Document 2.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] As a power supply circuit that supplies a power supply voltage to a drive circuit that drives a load such as a motor, there is one that uses a series regulator. In a system using such a power supply circuit, an overvoltage protection circuit is provided to prevent an overvoltage from being supplied to the load. Generally, the overvoltage protection circuit is intended to prevent an overvoltage from being applied to the load during normal operation after the power supply starts up. On the one hand, as shown in FIG. 4(A), the inventor has found that in a power supply circuit composed of a series regulator REG configured to be operated by an enable signal EN from a control device, there is a risk that the output voltage VRG may rise and exceed the breakdown voltage of the element when the input voltage rises.

[0005] Specifically, in the regulator REG shown in FIG. 4(A), while the enable signal EN is negated, a circuit is provided for lowering the gate terminal of the MOS transistor NM0 for output control to a low level to turn it off. This circuit includes a pull-down MOS transistor NM1 connected between the gate terminal of the transistor NM0 and the ground point, and an inverter INV as a logic circuit for generating the gate control voltage of the transistor NM1. The inverter INV takes the enable signal EN as an input and is configured to control the gate terminal of the pull-down transistor NM1 with the inverted signal. Further, the transistor NM0 is of the N-channel type, and a breakdown voltage protection diode D1 is provided between the gate terminal and the output terminal OUT so as to be in the forward direction when viewed from the output terminal OUT side.

[0006] The regulator REG shown in FIG. 4(A) starts operating when the input voltage VDD and the operating voltage DVDD of the inverter INV are supplied. Here, the voltage DVDD is a voltage generated in response to the input voltage VDD. Immediately before the voltage DVDD rises, it is desired to output a high-level signal to the gate terminal of the pull-down transistor NM1 from the inverter INV to turn on NM1 and turn off the output control transistor NM0. However, since the logic circuit (inverter INV) operates with the voltage DVDD, as shown in FIG. 5, it can only output a low level before the timing t2 when the voltage DVDD rises. Therefore, the pull-down transistor NM1 is turned off, and the gate terminal of the output control transistor NM0 becomes high impedance.

[0007] Also, since the transistor NM1 is in the off state, NM1 appears to be a high-resistance element. As a result, if current flows into the regulator REG from the output terminal OUT due to some factor, as shown in FIG. 4(B), the current flows through the protection diode D1 to the high-resistance element (NM1), and the gate potential VG0 of the output control transistor NM0 increases. Here, since the potential of the output terminal OUT is determined by VG0 - (Vth + Veff), when the gate potential VG0 of NM0 increases, the potential of the output terminal OUT also increases, and there is a problem that the output voltage VRG may exceed the breakdown voltage of the element.

[0008] Note that the above problem is a problem specific to the case where the MOS transistor NM0 for output control is of the N-channel type. Also, the phenomenon of current flowing into the regulator REG from the output terminal OUT may occur, for example, as a reverse current from the pre-driver when the regulator is used as a power supply circuit that supplies the power supply voltage of the pre-driver constituting the motor drive system. The present invention has been made based on the above background, and an object thereof is to provide a power supply circuit and a drive circuit using the same that can prevent the potential of the output terminal from rising due to current flowing into the output terminal from the outside when the input voltage rises, thereby exceeding the breakdown voltage of the element.

Means for Solving the Problem

[0009] To achieve the above object, the power supply circuit according to the present invention includes a voltage regulator having a first transistor for output control connected between a voltage input terminal and a voltage output terminal and an amplifier for controlling the first transistor, and converting a DC voltage input to the voltage input terminal into a predetermined DC voltage and outputting it, the first transistor is composed of an N-channel insulated gate field effect transistor, a protection diode is provided between the voltage output terminal and the gate terminal of the first transistor such that the cathode terminal of the diode is connected to the gate terminal, A second transistor for pull-down is provided between the gate terminal of the first transistor and the reference potential point. A third transistor, to whose gate terminal an external control signal is input, is provided between the gate terminal of the second transistor and the reference potential point. The voltage generated by a first passive element and a second passive element connected in series between the voltage input terminal and the reference potential point is applied to the gate terminal of the second transistor.

[0010] According to the power supply circuit having the above configuration, when the voltage input to the voltage input terminal rises, the second transistor for pull-down is turned on by the first passive element and the second passive element, and the resistance value decreases. Therefore, when a current flows into the output terminal from the outside, the current flows through the protection diode and then through the second transistor for pull-down in the low-resistance state. As a result, it is possible to prevent the potential of the output terminal from rising due to the current flowing into the output terminal from the outside and exceeding the breakdown voltage of the element. [Effect of the Invention]

[0011] According to the power supply circuit of the present invention, when the input voltage rises, it is possible to prevent the potential of the output terminal from rising due to the current flowing into the output terminal from the outside and exceeding the breakdown voltage of the element. [Brief Description of the Drawings]

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0013] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit configuration diagram of an embodiment of the power supply circuit according to the present invention, and FIG. 2 shows its operation timing. As shown in FIG. 1(A), the power supply circuit of the present embodiment is composed of a series regulator (hereinafter referred to as a regulator) 10.

[0014] The regulator 10 includes an output control transistor NM0 composed of an N-channel MOSFET (insulated gate field effect transistor) connected between a voltage input terminal IN to which a DC voltage VDD supplied from a battery or the like is input and a voltage output terminal OUT. The regulator 10 also includes an error amplifier 11 that generates a gate control voltage for the transistor NM0, and a voltage dividing circuit 12 composed of series resistors R1 and R2 connected between the source terminal of the transistor NM0 and the ground point GND, and the source terminal of the transistor NM0 is connected to the output terminal OUT.

[0015] The voltage divided by the voltage dividing circuit 12 is fed back to the non-inverting input terminal of the error amplifier 11. A reference voltage VBG generated by a circuit such as a BGR (bandgap reference) circuit is input to the inverting input terminal of the error amplifier 11, and a voltage corresponding to the potential difference between the reference voltage VBG and the feedback voltage VFB is applied to the gate terminal of the transistor NM0. Thereby, the error amplifier 11 controls the transistor NM0 so that the feedback voltage VFB matches the reference voltage VBG. Then, the voltage VRG generated at the source terminal of the transistor NM0 is output from the output terminal OUT.

[0016] A Zener diode D1 for withstand voltage protection is provided between the gate terminal and the output terminal OUT of the transistor NM0. Also, an N-channel MOS transistor NM1 for pull-down is connected between the gate terminal of the transistor NM0 and the ground point GND, and an N-channel MOS transistor NM2 is connected between the gate terminal of this transistor NM1 and the ground point GND.

[0017] Furthermore, a resistor R3 and a reverse diode D2 are connected in series between the voltage input terminal IN and the ground point GND, and the potential of the connection node of the resistor R3 and the diode D2 is applied to the gate terminal of the transistor NM1. Here, it is preferable to use a Zener diode for the diode D2. Also, the resistance value of the resistor R3 is preferably set so that when a reverse current flows through the diode D2, the reverse voltage of D2 becomes higher than the threshold voltage of the transistor NM1.

[0018] In the operating state where the enable signal EN is at a high level and the transistor NM2 is turned on in the regulator 10 of FIG. 1(A), unnecessary current flows through the resistor R3 and the transistor NM2. Therefore, in the operating state where NM2 is turned on, even if the resistance value of R3 is set to a relatively large value to suppress the current flowing through R3 and NM2, by using the diode D2 as a passive element in series with the resistor R3 as described above, a voltage that can turn on the pull-down transistor NM1 can be generated at the cathode terminal of D2 when the input voltage rises.

[0019] Note that the power supply voltage VBIAS of the error amplifier 11 may be the DC voltage VDD of the input terminal IN, or may be a voltage obtained by boosting the output voltage VRG by a charge pump circuit or the like. In the case of this modification, after starting up the power supply circuit by raising the DC voltage VDD, if the voltage obtained by boosting the output voltage VRG by the charge pump circuit reaches a predetermined level, it is advisable to switch the power supply voltage VBIAS. By doing so, the error amplifier 11 can be operated in the saturation region, and a decrease in the output voltage VRG can be prevented. When realizing the function of switching VBIAS as described above, for example, a circuit such as a multiplexer that switches between the DC voltage VDD and the boosted voltage of VRG, and a comparator that detects that the boosted voltage has reached a predetermined level may be provided.

[0020] Also, as shown in FIG. 1(B), when a charge pump circuit 20 is provided at the subsequent stage of the regulator 10, in a system equipped with a drive circuit such as a motor drive system, the output voltage VRG of the regulator 10 can be used as the power supply for the low-side pre-driver, and the voltage boosted by the subsequent charge pump circuit 20 can be used as the power supply for the high-side pre-driver.

[0021] And when configured to supply the output voltage of the regulator 10 as the power supply voltage of the pre-driver of the motor drive system, reverse current may occur from the pre-driver. However, in the regulator of this embodiment, even if such a current flows into the output terminal OUT, the transistor NM1 turns on, thereby avoiding a large increase in the output voltage. Also, when a power supply circuit including a regulator and a charge pump circuit is used in the above-described motor drive system, the charge pump circuit can be shared by a circuit that generates a voltage for operating the error amplifier 11 in the saturation region and a circuit that generates the power supply for the high-side driver.

[0022] Next, the operation of the regulator 10 shown in FIG. 1 when the input voltage rises will be described using the time chart shown in FIG. 2. As shown in FIG. 2, when the input DC voltage VDD starts to rise at timing t1, at this point, the pull-down transistor NM1 is off and the gate terminal of the output control transistor NM0 is at high impedance. Therefore, the gate voltage VG0 of NM0 rises following VDD through the gate capacitance of the output transistor NM0. Also, when VDD rises, the gate voltage VG1 of the pull-down transistor NM1 also rises following VDD through the resistor R3. At this time, the output voltage VRG also rises following VDD.

[0023] Then, when the potential of the connection node of the resistor R3 and the diode D2 becomes equal to or higher than the reverse voltage of the diode D2, a reverse current flows through the diode D2 and becomes a substantially constant potential, and this potential is applied to the gate terminal of the transistor NM1, turning on NM1, and the gate voltage VG0 of the output transistor NM0 drops to the ground potential (timing t2). Then, the output control transistor NM0 turns off, and the output voltage VRG drops.

[0024] And in this state, even if a current flows into the regulator REG from the output terminal OUT due to some factor and the current flows through the protection diode D1 to the pull-down transistor NM1, since NM1 is on and its resistance value has decreased, the gate potential VG0 of the output transistor NM0 does not rise significantly. Therefore, it is possible to prevent a situation where the potential of the output terminal OUT rises and the output voltage VRG exceeds the breakdown voltage of the element.

[0025] Note that thereafter, at timing t3, when the external enable signal EN changes from a low level to a high level, the transistor NM2 turns on, the gate voltage of the pull-down transistor NM1 drops to the ground potential, and NM1 turns off. As a result, the gate terminal of the output control transistor NM0 comes to be controlled by the output voltage of the error amplifier 11, and the output voltage VRG rises.

[0026] Next, with reference to FIG. 3, a case where the power supply circuit of the present invention is applied to a power supply circuit incorporated in a driving IC that constitutes a motor drive system as an example will be described. The motor drive system shown in FIG. 3 has a function of converting a DC voltage VDD supplied from a DC power supply into an AC voltage to be supplied to a motor 200 as a load, and includes a high-side transistor M1 that supplies current to the motor 200, a low-side transistor M2 that draws current from the motor 200, and a driving IC 100 that drives these transistors M1 and M2. The load 200 is not limited to a motor.

[0027] The driving IC 100 is a pre-driver that drives the transistors M1 and M2 externally attached to the IC. Although not particularly limited, N-channel field effect transistors (FETs) are used for the transistors M1 and M2 here. Further, the driving IC 100 incorporates a power supply circuit 101 that generates a voltage for operating the driving circuit, and the power supply circuit of the above-described embodiment (FIG. 1) is used as the power supply circuit 101.

[0028] The driving IC 100 in FIG. 3 drives the transistors M1 and M2 according to signals (clock CLK, high-side command signal HIN, and low-side command signal LIN) supplied from a controller (not shown), thereby switching (turning on or off) the transistors M1 and M2. The high-side command signal HIN and the low-side command signal LIN change in synchronization with the clock CLK. The driving IC 100 alternately turns on the transistors M1 and M2 with a dead time for turning off the transistors M1 and M2 according to the high-side command signal HIN and the low-side command signal LIN.

[0029] Also, the driving IC 100 includes a control circuit 130, a high-side source current source 111, a high-side sink current source 112, a low-side source current source 121, and a low-side sink current source 122. Further, the driving IC 100 includes a high-side driving terminal GH, an intermediate terminal SH, a low-side driving terminal GL, and a ground terminal PGND.

[0030] The control circuit 130 controls the source current source 111 that turns on the transistor M1 and controls the sink current source 112 that turns off the transistor M1. Also, the control circuit 130 controls the source current source 121 that turns on the transistor M2 and controls the sink current source 122 that turns off the transistor M2. To realize such functions, the control circuit 130 includes a logic circuit 131, a high-side control circuit 132, and a low-side control circuit 133.

[0031] Based on the high-side command signal HIN and the low-side command signal LIN, the logic circuit 131 generates a driving command HHIN for source control and a driving command HLIN for sink control. Also, based on the high-side command signal HIN and the low-side command signal LIN, the logic circuit 131 generates a driving command LHIN for source control and a driving command LLIN for sink control. The enable signal EN input to the regulator 10 in FIG. 1 is generated by the logic circuit 131. Note that the logic circuit 131 may be external to the control circuit 130 and further external to the driving IC 100.

[0032] The high-side control circuit 132 controls the source current generated by the high-side source current source 111 according to the driving command HHIN for source control. Also, the high-side control circuit 132 controls the sink current generated by the high-side sink current source 112 according to the driving command HLIN for sink control. Further, the high-side control circuit 132 alternately turns on the output transistors of the current sources 111, 112 with a dead time that turns off the output transistors of the current sources 111, 112 according to the driving command HHIN and the driving command HLIN.

[0033] The low-side control circuit 133 controls the source current generated by the source current source 121 on the low side in accordance with the drive command LHIN for source control. Further, the low-side control circuit 133 controls the sink current generated by the sink current source 122 on the low side in accordance with the drive command LLIN for sink control. Furthermore, the low-side control circuit 133 alternately turns on the output transistors of the current sources 121 and 122 with a dead time for turning off the output transistors of the current sources 121 and 122 in accordance with the drive command LHIN and the drive command LLIN.

[0034] The source current source 111 includes an output transistor formed of a P-channel type MOSFET, and generates a source current flowing into the gate of the transistor M1. The source current source 111 is connected between a drive terminal GH connected to the gate of the transistor M1 and a power supply node of the high-side power supply voltage VCP. The power supply voltage VCP is equal to the sum of the DC voltage VDD and the low-side power supply voltage (regulator voltage VRG). The power supply voltage VCP is generated, for example, by the charge pump circuit 20 in the power supply circuit 101 using the DC voltage VDD and the regulator voltage VRG.

[0035] The driving IC 100 charges the gate of the transistor M1 by flowing a source current from the PMOS output transistor of the source current source 111 into the drive terminal GH, and turns on the transistor M1. Further, the driving IC 100 discharges the gate of the transistor M1 by drawing a sink current from the drive terminal GH into the NMOS output transistor of the sink current source 112, and turns off the transistor M1. Similarly, the driving IC 100 charges the gate of the transistor M2 by flowing a source current from the PMOS output transistor of the source current source 121 into the drive terminal GL, and turns on the transistor M2. Further, the driving IC 100 discharges the gate of the transistor M2 by drawing a sink current from the drive terminal GL into the NMOS output transistor of the sink current source 122, and turns off the transistor M2.

[0036] Furthermore, the driving IC 100 includes a high-side source current source 111 as a first driving source 110 that uses the boosted voltage (power supply voltage VCP) generated by the charge pump in the power supply circuit 101. The driving IC 100 includes a low-side source current source 121 as a second driving source 120 that uses the regulator voltage VRG generated by the regulator in the power supply circuit 101. Also, the output signal RDY of the comparator provided in the regulator 10 or the charge pump circuit 20 of the power supply circuit of the modification example of the above-described embodiment may be supplied to the logic circuit 131, or a signal delayed by a predetermined number of seconds may be generated by a counter and supplied. The comparator functions as a voltage monitoring circuit that monitors the voltage VCP generated by the charge pump circuit 20.

[0037] When the output signal RDY of the voltage monitoring circuit (comparator) is asserted because the voltage VCPH generated by the charge pump circuit 20 becomes higher than a predetermined potential, the logic circuit 131 permits the operations of the high-side source current source 111 and the low-side source current source 121. Thereby, the logic circuit 131 starts generating a drive command HHIN for source control and a drive command HLIN for sink control based on the high-side command signal HIN and the low-side command signal LIN.

[0038] Also, the logic circuit 131 starts generating a drive command LHIN for source control and a drive command LLIN for sink control based on the high-side command signal HIN and the low-side command signal LIN. In this way, when the output signal RDY of the voltage monitoring circuit (comparator) is asserted, the first driving source 110 and the second driving source 120 can be prevented from driving the transistors M1 and M2 in a state where the power supply voltage VCP generated by the boosting operation of the charge pump has not risen sufficiently.

[0039] As described above, the present invention has been described based on embodiments, but the present invention is not limited to the above embodiments. For example, in the above embodiment, the circuit that generates the gate voltage of the transistor NM1 for pull-down is constituted by the resistor R3 and the diode D2 connected in series between the input terminal IN and the ground point. However, it is also possible to use a passive element other than the diode, such as a resistor element, instead of the diode D2. Also, in the above embodiment, as an example of the use of the regulator 10, the case of using it as a power supply circuit in the motor drive IC has been described. However, the regulator of the present invention can be widely used as a power supply circuit in an IC that drives a load other than the motor or as an independent power supply circuit.

Description of Reference Numerals

[0040] 10... Regulator, 11... Error amplifier, 12... Voltage dividing circuit, 20... Charge pump circuit, M0... Output transistor, M1... Transistor for pull-down, D1... Diode for withstand voltage protection, 100... Drive IC, 101... Power supply circuit, 110... First drive source, 120... Second drive source, 130... Control circuit, 131... Logic circuit, 200... Load (motor)

Claims

1. A power supply circuit comprising a first transistor for output control connected between a voltage input terminal and a voltage output terminal, and an amplifier for controlling the first transistor, which converts a DC voltage input to the voltage input terminal into a predetermined DC voltage and outputs it, wherein the first transistor is composed of an N-channel insulated gate field effect transistor, a protection diode is provided between the voltage output terminal and the gate terminal of the first transistor such that the cathode terminal of the diode is connected to the gate terminal, a second transistor for pull-down is provided between the gate terminal of the first transistor and a reference potential point, a third transistor is provided between the gate terminal of the second transistor and the reference potential point, and an external control signal is input to the gate terminal of the third transistor, and a voltage generated by a first passive element and a second passive element connected in series between the voltage input terminal and the reference potential point is applied to the gate terminal of the second transistor. A power supply circuit characterized by this.

2. The power supply circuit according to claim 1, wherein the first passive element is a resistive element, the second passive element is a diode connected in the reverse direction, and the potential of the connection node between the resistive element and the diode is applied to the gate terminal of the second transistor.

3. The power supply circuit according to claim 2, further comprising a charge pump circuit for boosting the output voltage of the voltage regulator.

4. A drive circuit comprising the power supply circuit according to claim 3, wherein a first drive means for supplying current to a load and a second drive means for drawing current from the load are respectively turned on and off, a first drive source that receives the supply of the first output voltage of the power supply circuit and turns on the first drive means, a second drive source that receives the supply of the second output voltage of the power supply circuit and turns on the second drive means, and the output voltage of the charge pump circuit is supplied to the first drive source as the first output voltage, and the output voltage of the voltage regulator is supplied to the second drive source as the second output voltage. A drive circuit characterized by this.

Citation Information

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