Output current detection method, electronic equipment and storage medium thereof

Abstract

The embodiment of the invention discloses an output current detection method, electronic equipment and a storage medium thereof. The method comprises the following steps: acquiring a midpoint current of a switching tube of the switched capacitor converter at a preset moment of a switching period of the switched capacitor converter; the midpoint current is the sum of the currents of the switching tubes; based on the midpoint current, obtaining an output current of the switched capacitor converter; at a preset moment, the midpoint current is equal to the output current; the preset time is set based on the duty ratio of the switch tube. According to the embodiment of the invention, for the switched capacitor converter, the output current is obtained by detecting the current of the switching tube at a specific moment according to the relation between the current of the switching tube and the output current, and a sampling resistor is prevented from being additionally arranged in an output loop, so that the system loss is reduced, the heat dissipation area is reduced, and the power density of the switched capacitor converter is improved; and the possibility that a sampling result is easily influenced by switching noise interference when a sampling resistor is additionally arranged in a high-frequency switching loop is avoided.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of switched capacitors, and in particular, to an output current detection method, an electronic device, and a storage medium thereof. Background Art

[0002] With the rapid development of artificial intelligence technology, the surge in computing power demand has driven the evolution of hardware systems towards low voltage and high current. Against this background, DrMOS (Driver-MOSFET integrated module) has become the core support technology for modern power systems due to its high integration, high efficiency, and optimized thermal management capabilities. Compared with the problems of high parasitic parameters and slow dynamic response caused by the separation of the driver and MOSFET in traditional discrete solutions, DrMOS integrates the two in a single package, significantly reducing the board area (which can be reduced to one-fourth of the traditional design), while reducing power loss by more than 15% and effectively suppressing high-frequency switching noise.

[0003] In the current sampling technology, DrMOS has achieved a revolutionary breakthrough. Traditional DCR sampling relies on the DC resistance of the inductor and an external RC circuit, and has defects such as accuracy problems caused by poor temperature coefficients, complex debugging, and inability to detect inductor saturation in real time. DrMOS uses a single-die current mirror technology to directly output a mirror current that is strictly proportional to the inductor current through the CS pin, achieving Cycle-by-Cycle precise monitoring with an error controllable within ±2%. This technology has the characteristics of temperature self-compensation and is independent of the on-resistance, duty cycle, and frequency changes, greatly improving the detection accuracy of each phase current. The current detection mechanism using DrMOS can replace the traditional output current detection network composed of sampling resistors, reducing system loss, reducing the board area, and increasing the power density.

[0004] In some specific topologies using DrMOS, such as switch-cap converters, directly using the current signal generated by DrMOS cannot directly obtain the actual required output current, causing difficulties in detecting and protecting the output current. Existing switch-cap converters generally adopt an output current detection scheme, that is, a sampling resistor R is connected in series in the inductor and output capacitor loop. CS Then, signal conversion is performed through a signal processing circuit such as an operational amplifier, and then analog-to-digital conversion is performed through the ADC of the controller to finally obtain the output current. This method requires an additional sampling resistor, additional system loss, and a larger heat dissipation area at the same time, greatly reducing the power density of the power system. In addition, because the sampling resistor is in the high-frequency switching loop, it is easily affected by switching noise interference, affecting the final sampling result. Summary of the Invention

[0005] The technical problem mainly solved by the embodiments of the present invention is to provide an output current detection method, an electronic device and a storage medium thereof, which can solve at least some defects existing in the existing switched-capacitor converters.

[0006] In a first aspect, an embodiment of the present invention provides an output current detection method applied to a switched-capacitor converter, including: at a preset moment in a switching period of the switched-capacitor converter, obtaining a midpoint current of a switching transistor of the switched-capacitor converter; the midpoint current is the sum of the currents of the switching transistors; obtaining the output current of the switched-capacitor converter based on the midpoint current; at the preset moment, the midpoint current is equal to the output current; the preset moment is set based on the duty cycle of the switching transistor.

[0007] Optionally, the switching transistors include two main switching transistors and two synchronous rectifier switching transistors. Obtaining the midpoint current of the switching transistors of the switched-capacitor converter at a preset moment in the switching period of the switched-capacitor converter includes: at the preset moment, obtaining the currents of the two main switching transistors and the two synchronous rectifier switching transistors; summing up the currents of the two main switching transistors and the two synchronous rectifier switching transistors to obtain a total switching current; converting the total switching current into a voltage signal; performing sample and hold on the voltage signal to obtain a digital quantity; performing data conversion on the digital quantity to obtain the midpoint current.

[0008] Optionally, the switching transistors include two main switching transistors and two synchronous rectifier switching transistors. Obtaining the midpoint current of the switching transistors of the switched-capacitor converter at a preset moment in the switching period of the switched-capacitor converter includes: at the preset moment, obtaining the currents of the two synchronous rectifier switching transistors; summing up the currents of the two synchronous rectifier switching transistors to obtain a total switching current; converting the total switching current into a voltage signal; performing sample and hold on the voltage signal to obtain a digital quantity; performing data conversion on the digital quantity to obtain the midpoint current.

[0009] Optionally, when the total switching current is the sum of the currents of the two main switching transistors and the two synchronous rectifier switching transistors, the preset moment is 0.5dT PRD ; where d is the duty cycle of the main switching transistor, and T PRD is the switching period.

[0010] Optionally, when the total switching current is the sum of the currents of the two synchronous rectifier switching transistors, the preset moment is (0.5 + 0.5d)T PRD ; where d is the duty cycle of the main switching transistor, and T PRD is the switching period.

[0011] Optionally, the data conversion of the digital quantity to obtain the midpoint current includes: multiplying the digital quantity by a conversion coefficient and dividing by a current sensing coefficient to obtain the midpoint current; the conversion coefficient is the reference voltage of the analog-to-digital conversion unit divided by 2 to the power of n, where n is the number of bits of the analog-to-digital conversion unit; the current sensing coefficient is the resistance value of the sampling resistor, or the product of the sampling resistor and the mirror current ratio.

[0012] Optionally, the two main switching tubes include a first main switching tube and a second main switching tube; the first main switching tube and the second main switching tube are integrated in a first switching tube driving integrated module, and the current of the first main switching tube and the current of the second main switching tube are obtained through the internal current mirror of the first switching tube driving integrated module.

[0013] Optionally, the two synchronous rectifier switching tubes include a first synchronous rectifier switching tube and a second synchronous rectifier switching tube; the first synchronous rectifier switching tube and the second synchronous rectifier switching tube are integrated in a second switching tube driving integrated module, and the current of the first synchronous rectifier switching tube and the current of the second synchronous rectifier switching tube are obtained through the internal current mirror of the second switching tube driving integrated module.

[0014] In a second aspect, an embodiment of the present invention provides an electronic device, including: at least one processor; at least one network interface, the network interface is communicatively connected to the corresponding processor; and, a memory communicatively connected to the at least one processor; wherein, the network interface is used to establish a communication connection between the processor and other external devices; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute an output current detection method as described in the first aspect.

[0015] In a third aspect, an embodiment of the present invention provides a non-volatile computer storage medium, the computer storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by one or more processors, the one or more processors can execute an output current detection method as described in the first aspect.

[0016] The beneficial effects of the embodiments of the present invention are: different from the prior art, the embodiments of the present invention are directed to a switched-capacitor converter. According to the relationship between the switching tube current and the output current, the output current is obtained by detecting the switching tube current at a specific moment, avoiding adding an additional sampling resistor in the output loop, thereby reducing system losses, reducing the heat dissipation area, improving the power density of the switched-capacitor converter, and also avoiding the possibility that adding a sampling resistor in the high-frequency switching loop is vulnerable to switching noise interference and affects the sampling result. Description of the Drawings

[0017] One or more embodiments are exemplarily illustrated by the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0018] Figure 1 is a schematic diagram of the output current detection structure of an existing switched-capacitor converter;

[0019] Figure 2 is a circuit schematic diagram of a switched-capacitor converter;

[0020] Figure 3 is a waveform diagram of the currents of each switching transistor when the duty cycle of the main switching transistor is less than or equal to 50%;

[0021] Figure 4 is a waveform diagram of the currents of each switching transistor when the duty cycle of the main switching transistor is greater than 50%;

[0022] Figure 5 is a waveform diagram of the currents of two synchronous rectifier switching transistors when the duty cycle of the main switching transistor is less than or equal to 50%;

[0023] Figure 6 is a waveform diagram of the currents of two synchronous rectifier switching transistors when the duty cycle of the main switching transistor is greater than 50%;

[0024] Figure 7 is a schematic flowchart of an output current detection method provided by an embodiment of the present invention;

[0025] Figure 8 is a schematic diagram of the output current detection structure of the first switched-capacitor converter provided by an embodiment of the present invention;

[0026] Figure 9 is a schematic diagram of the output current detection structure of the second switched-capacitor converter provided by an embodiment of the present invention;

[0027] Figure 10 is a schematic diagram of the output current detection structure of the third switched-capacitor converter provided by an embodiment of the present invention;

[0028] Figure 11 is a schematic diagram of the output current detection structure of the fourth switched-capacitor converter provided by an embodiment of the present invention;

[0029] Figure 12 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed Embodiments

[0030] To facilitate the understanding of the present application, the following provides a more detailed description of the present application in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on the other element, or there can be one or more intermediate elements therebetween. When an element is described as "connected to" another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween. The terms "upper", "lower", "inner", "outer", "bottom", etc. used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0031] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in this specification in the description of the present application are only for the purpose of describing specific embodiments and are not used to limit the present application. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0032] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0033] The following will describe the technical solutions in the present application in conjunction with the accompanying drawings.

[0034] Referring to Figure 1 , the switching capacitor converter in the prior art mainly includes: a main circuit part and a control and detection part. Among them, the main circuit part includes: a power input terminal V IN , switching transistor Q1, switching transistor Q5, switching transistor Q2, switching transistor Q6, flying capacitor C FLY , inductor L1, inductor L2, output capacitor C O , and load resistor R LOAD ; the control and detection part includes: a sampling resistor R connected in series in the output current path CS , signal processing module 10 and control module 20. The control module 20 internally includes an analog-to-digital conversion unit 210 and a data conversion unit 220.

[0035] The working principle of the switching capacitor converter in the prior art is as follows: The power supply voltage V IN passes through the high-frequency switching actions of switching transistors Q1, Q5, Q2, and Q6, and via the flying capacitor C FLYTogether with inductor L1 and inductor L2, the energy is transferred to the output terminal to form a stable output voltage V OUT Supply load R LOAD During the operation of the switched capacitor converter, the four switching transistors are switched on and off according to a specific control strategy to achieve efficient energy transmission.

[0036] For the detection of output current, the existing technology adopts the following method: O A sampling resistor R is connected in series in the loop CS , when the current I OUT Flowing through the sampling resistor R CS When the current is proportional to the voltage drop across the two ends, the voltage signal is conditioned and amplified by the signal processing module 10, and then sent to the analog-to-digital conversion unit 210 (such as ADC) inside the control module 20 for analog-to-digital conversion. The converted digital signal is processed by the data conversion unit 220, and finally the output current I is obtained. OUT The numeric value of .

[0037] The signal processing module 10 in the prior art usually includes a signal processing circuit such as an operational amplifier, which mainly performs the following functions: amplification of the voltage signal: due to the sampling resistor R CS The resistance value is usually small (milliohm level), and the voltage signal generated is weak, which needs to be amplified; signal filtering: removes high-frequency switching noise and extracts the real current signal; level conversion: adjusts the signal to the acceptable input range of the ADC of the control module 20; common-mode suppression: reduces common-mode interference through the differential structure; the analog-to-digital conversion unit 210 in the control module 20 is responsible for converting the analog voltage signal into a digital signal, while the data conversion unit 220 is responsible for processing the digital signal into the actual output current value according to the preset algorithm.

[0038] Although the above solution can realize the detection of output current, it has several technical defects: First, the sampling resistor R CS This will lead to additional power loss, especially in high current applications. Even if a very small sampling resistor (such as 1mΩ) is used, significant power loss will occur under current conditions of tens of amperes (P = I 2 R); secondly, the heat generated by the sampling resistor requires additional heat dissipation design, which increases the heat dissipation area required; thirdly, the additional sampling resistor, signal conditioning circuit and other components significantly increase the circuit board area occupied, reducing the power density of the power supply system; fourthly, the sampling resistor is located in a high-frequency switching loop and is susceptible to switching transients and electromagnetic interference (EMI), which reduces sampling accuracy; finally, parameters such as the temperature coefficient and parasitic inductance of the sampling resistor also affect measurement accuracy, especially in working environments with large temperature fluctuations.

[0039] For modern power systems, especially for the power supply requirements of high-performance computing devices such as artificial intelligence hardware, power density, efficiency, and precise current monitoring have become increasingly important. Under the trend of low voltage and high current, the disadvantages of traditional sampling resistor solutions have become more obvious. For example, in a typical power supply scenario for an AI accelerator with a 12V input and a 1V / 100A output, the sampling resistor solution may result in an additional 1-3% efficiency loss, while also increasing the difficulty of heat dissipation design by 30-50%.

[0040] Example of power loss calculation introduced by the sampling resistor: Assume a 1mΩ sampling resistor, at a current of 100A, the power loss is P = I 2 R = 100 2 ×0.001 = 10W. And the output power of the entire power system is P = V × I = 1V × 100A = 100W. Then the loss ratio introduced by the sampling resistor is 10 / 100 = 10%, significantly reducing the system efficiency. At the same time, a heat dissipation solution needs to be designed for the additional 10W of heat, increasing the system volume and cost.

[0041] The signal processing flow of existing technical solutions is also relatively complex: First, the current signal must be converted into a voltage signal, then amplified and filtered, then converted into a digital signal through an ADC, and finally the output current value is obtained through data processing. The multi-stage signal processing not only increases the design complexity but also may introduce various errors and delays, affecting the dynamic performance and protection response speed of the system.

[0042] Referring to Figure 2 , the main circuit block diagram structure of the switched-capacitor converter includes: input voltage terminal VIN, first main switch Q1, first synchronous rectifier switch Q5, second main switch Q2, second synchronous rectifier switch Q6, flying capacitor C FLY , first inductor L1, second inductor L2, output capacitor C O and load resistor R LOAD . Figure 2 also marks the key current paths, including the first inductor current I1, the second inductor current I2, and the output current I OUT .

[0043] The working mode of the switched-capacitor converter is: The first main switch Q1 and the second main switch Q2 are used as the main control switches, and their duty cycles of conduction in one switching period are equal, and the switching signals of the two are staggered by 180 degrees in phase. The first synchronous rectifier switch Q5 is complementary to the conduction state of the first main switch Q1, and the second synchronous rectifier switch Q6 is complementary to the conduction state of the second main switch Q2. Through the coordinated operation of the four switches, efficient energy transfer from the input end to the output end is achieved.

[0044] In the switched-capacitor converter, the flying capacitor CFLY Acts as a charge pump, charges and discharges through the switching of switching transistors, and cooperates with two inductors L1 and L2 to form a specific power conversion path. When the circuit operates stably, the currents I1 and I2 in the two inductors L1 and L2 will be directly related to the output current I OUT , that is, the output current I OUT is equal to the sum of the two inductor currents I1 and I2.

[0045] The working mode of the switched-capacitor converter is as follows: The first main switching transistor Q1 and the second main switching transistor Q2 serve as the main control switches. The duty cycles of conduction within one switching period are equal, and the switching signals of the two are 180 degrees out of phase. The first synchronous rectification switching transistor Q5 is complementary to the conduction state of the first main switching transistor Q1, and the second synchronous rectification switching transistor Q6 is complementary to the conduction state of the second main switching transistor Q2. Through the coordinated operation of the four switching transistors, efficient energy transfer from the input end to the output end is achieved.

[0046] In the switched-capacitor converter, the flying capacitor C FLY Acts as a charge pump, charges and discharges through the switching of switching transistors, and cooperates with two inductors L1 and L2 to form a specific power conversion path. When the circuit operates stably, the currents I1 and I2 in the two inductors L1 and L2 will be directly related to the output current I OUT , that is, the output current I OUT is equal to the sum of the two inductor currents I1 and I2.

[0047] It should be noted that the inductor L1 and the inductor L2 can be two windings of a coupled inductor or two independent inductors.

[0048] According to the different duty cycles of the main switching transistors, the operating states of the switched-capacitor converter can be divided into two cases: the duty cycle is less than or equal to 50% and the duty cycle is greater than 50%. Referring to Figure 3 and Figure 4 , the following will analyze the two cases in detail.

[0049] As Figure 3 shown, when the duty cycles d of the main switching transistor Q1 and the main switching transistor Q2 are less than or equal to 50%, within a complete switching period T PRD , the circuit goes through four different operating stages (I, II, III, IV). Figure 3 Shows the control signals (PWM1, PWM5, PWM2, PWM6) of the four switching transistors and the current waveforms of each path, including the inductor currents i1(t) and i2(t), and the current combinations i M1 (t) and i M2 (t) of the main switching transistor and the synchronous rectification switching transistor.

[0050] In the case where the duty cycle is less than or equal to 50%, a switching cycle can be divided into the following four stages:

[0051] Stage I (0 - d): The first main switching transistor Q1 is turned on, and the second synchronous rectifier switching transistor Q6 is turned on;

[0052] Stage II (d - 0.5): The first synchronous rectifier switching transistor Q5 is turned on, and the second synchronous rectifier switching transistor Q6 is turned on;

[0053] Stage III (0.5 - 0.5 + d): The first synchronous rectifier switching transistor Q5 is turned on, and the second main switching transistor Q2 is turned on;

[0054] Stage IV (0.5 + d - 1): The first synchronous rectifier switching transistor Q5 is turned on, and the second synchronous rectifier switching transistor Q6 is turned on.

[0055] The currents flowing through the switching transistors Q1, Q2, Q5, and Q6 in each switching stage are shown in the following table:

[0056] Phase I Phase II Phase III Phase IV Duration ratio d 0.5-d d 0.5-d <![CDATA[i Q1 (t)]]> <![CDATA[i1(t)]]> 0 0 0 <![CDATA[i Q2 (t)]]> 0 0 <![CDATA[i2(t)]]> 0 <![CDATA[i Q5 (t)]]> 0 <![CDATA[i1(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)]]> <![CDATA[i Q6 (t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> 0 <![CDATA[i2(t)]]> <![CDATA[i M1 (t) = i Q1 (t) + i Q5 (t)]]> <![CDATA[i1(t)]]> <![CDATA[i1(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)]]> <![CDATA[i M2 (t) = i Q2 (t) + i Q6 (t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i Q_56 (t) = i Q5 (t) + i Q6 (t)]]> <![CDATA[i2(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)+i2(t)]]>

[0057] Table 1

[0058] Analyze the currents flowing through each switching transistor in each stage:

[0059] The first main switching transistor Q1: Conducts only in Stage I, and the current is i1(t); The second main switching transistor Q2: Conducts only in Stage III, and the current is i2(t); The first synchronous rectifier switching transistor Q5: Conducts in Stages II, III, and IV, and the currents are i1(t), i1(t) + i2(t), and i1(t) respectively; The second synchronous rectifier switching transistor Q6: Conducts in Stages I, II, and IV, and the current is i2(t).

[0060] If i M1 (t) represents the sum of the currents of the first main switching transistor Q1 and the first synchronous rectifier switching transistor Q5, then i M1 (t) is i1(t) throughout the entire cycle, and only includes the part of i2(t) in Stage III. If i M2 (t) represents the sum of the currents of the second main switching transistor Q2 and the second synchronous rectifier switching transistor Q6, then i M2 (t) is i2(t) throughout the entire cycle.

[0061] As can be seen from Table 1, when the duty cycle d of the main switching transistor is less than or equal to 50%, in Stages I, II, and IV, the sum of the currents of the first main switching transistor Q1, the second main switching transistor Q2, the first synchronous rectifier switching transistor Q5, and the second synchronous rectifier switching transistor Q6, i M1 (t) + i M2(t), which is exactly equal to the inductor current i1(t)+i2(t); in phases II, III and IV, the sum of the currents of the first synchronous rectifier switch Q5 and the second synchronous rectifier switch Q6 is i Q_56 , which is exactly equal to the inductor current i1(t)+i2(t).

[0062] like Figure 4 As shown in Figure 1, when the duty cycle d of the main switches Q1 and Q2 is greater than 50%, the circuit also goes through four different working stages, but the duration of each stage is different from the previous one:

[0063] Phase I (0 to d-0.5): the first main switch Q1 and the second main switch Q2 are turned on at the same time;

[0064] Phase II (d-0.5~0.5): the first main switch Q1 and the second synchronous rectification switch Q6 are turned on;

[0065] Phase III (0.5-d): the first main switch Q1 and the second main switch Q2 are turned on;

[0066] Phase IV (d-1): the first synchronous rectification switch Q5 and the second main switch Q2 are turned on.

[0067] The currents flowing through the switch tubes Q1, Q2, Q5, and Q6 in each switching stage are shown in the following table:

[0068] Phase I Phase II Phase III Phase IV Duration ratio d-0.5 1-d d-0.5 1-d <![CDATA[i Q1 (t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)]]> <![CDATA[i1(t)+i2(t)]]> 0 <![CDATA[i Q2 (t)]]> <![CDATA[i2(t)]]> 0 <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i Q5 (t)]]> 0 0 0 <![CDATA[i1(t)+i2(t)]]> <![CDATA[i Q6 (t)]]> 0 <![CDATA[i2(t)]]> 0 0 <![CDATA[i M1 (t) = i Q1 (t) + i Q5 (t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i1(t)+i2(t)]]> <![CDATA[i M2 (t) = i Q2 (t) + i Q6 (t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i2(t)]]> <![CDATA[i Q_56 (t) = i Q5 (t) + i Q6 (t)]]> 0 <![CDATA[i2(t)]]> 0 <![CDATA[i1(t)+i2(t)]]>

[0069] Table 2

[0070] Analyze the current flowing through each switch tube in each stage:

[0071] The first main switch Q1 is turned on in phases I, II, and III, with currents i1(t)+i2(t), i1(t), and i1(t)+i2(t), respectively.

[0072] The second main switch Q2 is turned on in phases I and III, with currents i2(t) and i2(t) respectively.

[0073] The first synchronous rectifier switch Q5 is turned on in phase IV, with a current of i1(t)+i2(t).

[0074] The second synchronous rectification switch tube Q6 is turned on in phase II, and the current is i2(t).

[0075] As can be seen from Table 2, when the duty cycle d of the main switch tube is greater than 50%, in phase II, the sum of the currents i of the first main switch tube Q1, the second main switch tube Q2, the first synchronous rectifier switch tube Q5, and the second synchronous rectifier switch tube Q6 is M1(t) + i M2 (t) is exactly equal to the inductor current i1(t) + i2(t); in stage IV, the sum of the currents of the first synchronous rectification switch Q5 and the second synchronous rectification switch Q6, i Q_56 is exactly equal to the inductor current i1(t) + i2(t).

[0076] Refer to Figure 3 and Figure 4 , by selecting the moment 0.5dT of a switching period PRD to sample the sum signal of the currents of the first main switch Q1, the second main switch Q2, the first synchronous rectification switch Q5, and the second synchronous rectification switch Q6. At this time, under the condition that the duty cycle is greater than or less than 50%, there is: the stage where the sum of the total currents of the four switches is equal to the sum of the two inductor currents i1(t) and i2(t); and 0.5dT PRD is the middle moment of this stage. Then, sampling the total current of the four switches at this moment can obtain the switching period average value of the output current.

[0077] Similarly, refer to Figure 5 and Figure 6 , by selecting the moment (0.5 + 0.5d)T of a switching period PRD to sample the sum signal of the currents of the first synchronous rectification switch Q5 and the second synchronous rectification switch Q6. At this time, under the condition that the duty cycle is greater than or less than 50%, there is: the stage where the sum of the total currents of the first synchronous rectification switch Q5 and the second synchronous rectification switch Q6 is equal to the sum of the two inductor currents i1(t) and i2(t); and (0.5 + 0.5d)T PRD is the middle moment of this stage. Then, sampling the total current of the first synchronous rectification switch Q5 and the second synchronous rectification switch Q6 at this moment can obtain the switching period average value of the output current.

[0078] Through Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 's analysis, it can be seen that due to the specific topology and switching timing of the switched-capacitor converter, there is a deterministic relationship between the switch current and the output current. This embodiment uses the method of combining the switch current information and the duty cycle information, and without the traditional output current sampling resistor, it can achieve accurate measurement of the output current, providing a lossless output current detection scheme for the switched-capacitor converter.

[0079] Refer to Figure 7 , the schematic flowchart of a method for detecting output current provided by this application. This method is applied to Figure 2The shown switched-capacitor converter mainly includes the following two steps:

[0080] Step S100: At a preset moment in the switching period of the switched-capacitor converter, obtain the midpoint current of the switching transistors of the switched-capacitor converter.

[0081] In the switched-capacitor converter, the switching transistors perform switching operations according to a specific control strategy, and the current switches between different paths. Through the above theoretical analysis, it can be known that at a specific moment within the switching period, there is a deterministic relationship between the midpoint current (i.e., the sum of the switching transistor currents) and the output current of the switching transistors.

[0082] The determination of the preset moment is the key to this method. By analyzing the operating states of the switched-capacitor converter under different duty cycles, determine when the midpoint current of the switching transistors is equal to the output current. This preset moment is set based on the duty cycle of the switching transistors to ensure that the sampled current value can accurately reflect the output current.

[0083] For the case where the duty cycle d is less than or equal to 0.5, the preset moment can be 0.5dT PRD , where T PRD is the switching period; for the case where the duty cycle d is greater than 0.5, the preset moment can also be 0.5dT PRD . Under different duty cycle conditions, there may be multiple preset moment points, but this embodiment is described by taking the above moment points as examples.

[0084] It should be noted that the midpoint current is expressed as the sum of the switching transistor currents, which can be the total sum of all switching transistor currents or the sum of partial switching transistor currents, depending on the specific detection scheme.

[0085] Step S200: Based on the midpoint current, obtain the output current of the switched-capacitor converter.

[0086] Since at the preset moment, the midpoint current is equal to the output current, therefore, based on the midpoint current obtained in step S100, the output current of the switched-capacitor converter can be directly obtained without additional calculation and conversion.

[0087] In practical applications, the obtained midpoint current may need to be processed through signal processing before being used as the final output current value. Signal processing may include steps such as amplification, filtering, and analog-to-digital conversion to improve the quality and accuracy of the signal.

[0088] In some embodiments of the present application, step S100 specifically includes the following steps:

[0089] Step S110: At the preset moment, obtain the currents of two main switching transistors and two synchronous rectifier switching transistors.

[0090] In a switched-capacitor converter, the four key switching transistors include two main switching transistors (Q1, Q2) and two synchronous rectifier switching transistors (Q5, Q6). The determination of the preset time is the core of the entire current detection method, which specifically depends on the duty cycle d of the main switching transistor and the switching period TPRD.

[0091] When the duty cycle d of the main switching transistor is less than or equal to 0.5, the preset time can be 0.5dT PRD ; when the duty cycle d is greater than 0.5, the preset time is also 0.5dT PRD . The precise selection of the preset time ensures that the sum of the currents of the four switching transistors at this time is exactly equal to the output current.

[0092] There are multiple implementation ways to obtain the currents of the switching transistors. In Figure 8 , it can be seen that the four switching transistors Q1, Q5, Q2, and Q6 are respectively marked with current detection points IS1, IS5, IS2, and IS6. These detection points are used to obtain the current signals flowing through each switching transistor during conduction.

[0093] There are multiple possible specific implementation ways: for example, traces are led out from the source or drain terminals of the switching transistors, and the current is directly measured by a current sensor (such as a Hall sensor, a current transformer, etc.) in the signal processing module 10. Or a current detection circuit is integrated in the signal processing module to realize the separate detection of the currents of the high-side switching transistors (Q1 / Q2) and the low-side switching transistors (Q5 / Q6).

[0094] Step S120: Summarize the currents of the two main switching transistors and the two synchronous rectifier switching transistors to obtain the total switching current.

[0095] The current summarization operation is a process of combining the currents of the four switching transistors in a specific way to obtain the total switching current. The summarization method can be implemented at the hardware or software level, depending on the system design requirements and resource limitations. Hardware summarization is usually achieved through the connection of current nodes. According to Kirchhoff's current law, multiple current signals are connected to the same node, and current superposition is naturally formed. Another hardware implementation method is to use a current adder to construct a current summation circuit based on an operational amplifier to achieve precise current addition. In addition, multiple current signals can also share the same sampling resistor, so that the currents are naturally superimposed and converted into corresponding voltage signals.

[0096] Software summarization is to first obtain the current values of the four switching transistors separately, and then perform digital addition operations in the processor. For most implementation schemes, the total switching current can be expressed as the algebraic sum of the currents of the four switching transistors, that is, I Q_all = IQ1 + IQ2 + IQ5 + IQ6. At the carefully selected preset time, this total switching current is exactly equal to the output current of the switched-capacitor converter.

[0097] In Figure 8 In the illustrated embodiment, a hardware summing method is adopted. The current signals of the four switching transistors are introduced into the signal processing module 10 and directly summed into a total current signal through the internal circuit.

[0098] Step S130: Convert the total switching current into a voltage signal.

[0099] From Figure 8 It can be seen that the output of the signal processing module 10 is connected to the control module 20 through two ports CS+ and CS-. This indicates that the signal processing module 10 converts the summed current signal into a differential voltage signal for subsequent analog-to-digital conversion processing.

[0100] The current-to-voltage conversion is usually achieved through a precision sampling resistor R CS . Different from the traditional scheme, the sampling resistor here is not located in the power loop but inside the signal processing circuit. Therefore, the power loss on the resistor is extremely small and will not significantly affect the system efficiency.

[0101] The conversion circuit may include the following functional blocks: a current-to-voltage converter that converts the current signal into a voltage signal, with the conversion ratio determined by the sampling resistor R CS (V = I × R CS) ); a differential amplifier that converts the single-ended voltage signal into a differential signal to improve the anti-interference ability; a filter circuit that removes high-frequency noise and extracts the effective components of the current signal; and a level adjustment circuit that ensures the output signal is within the input range of the analog-to-digital conversion unit 210, maximizes the dynamic range of the analog-to-digital conversion unit 210, and improves the measurement accuracy. It should be noted that the current-to-voltage conversion process will introduce a certain gain coefficient, which needs to be compensated in the subsequent data processing to ensure the accuracy of the final calculation result.

[0102] Step S140: Sample and hold the voltage signal to obtain a digital quantity.

[0103] The analog-to-digital conversion unit 210 samples and holds the voltage signal to obtain a digital quantity. Preferably, a successive approximation analog-to-digital converter (SAR ADC) is used as the analog-to-digital conversion unit 210 because the SAR ADC can sample at an accurate moment and provide sufficient conversion accuracy. The sampling timing control is particularly important. The system needs to precisely control the sampling trigger moment to ensure that the voltage signal is captured at a preset moment (0.5dT PRD ). To achieve this, the sampling clock is usually synchronized with the PWM control signal to eliminate the error at the sampling moment.

[0104] The sample-and-hold circuit inside the SAR ADC consists of a sampling switch, a holding capacitor, and a buffer amplifier. When a sampling command arrives, the sampling switch conducts, transferring the input voltage to the holding capacitor. Subsequently, the sampling switch disconnects, and the holding capacitor stores the voltage value until the SAR ADC completes the conversion. The buffer amplifier isolates the holding capacitor from the subsequent circuit to prevent measurement errors caused by charge leakage. The SAR ADC conversion process is based on the binary search algorithm. The comparator compares the held voltage value with the internal reference voltage, and the successive approximation register controls the output of the internal DAC. After n comparisons, an n-bit digital output is obtained. When selecting an SAR ADC, factors such as its number of bits, conversion rate, and reference voltage accuracy need to be considered. In general applications, SAR ADCs with 8-12 bit resolution are commonly used to achieve a balance between speed and accuracy.

[0105] It should be noted that the sample-and-hold voltage signal ADC can not only be an SAR ADC, but can also be replaced by other ADC types that can sample the current signal at specific moments during the switching cycle, and the same purpose can be achieved.

[0106] Step S150: Perform data conversion on the digital quantity to obtain the midpoint current.

[0107] Data conversion is a calculation process that converts the digital quantity output by the analog-to-digital conversion unit 210 into an actual current value. The basic conversion formula can be expressed as: midpoint current = digital quantity × conversion coefficient ÷ current sensing coefficient. Among them, the conversion coefficient is equal to the reference voltage divided by 2 to the power of n (n is the number of bits of the analog-to-digital conversion unit 210), and the reference voltage is the full-scale reference voltage of the analog-to-digital conversion unit 210. For example, for a 10-bit ADC, its conversion coefficient is the reference voltage divided by 1024.

[0108] The determination of the current sensing coefficient depends on the current detection implementation method. When using the sampling resistor scheme, the current sensing coefficient is equal to the sampling resistor value; when using the current mirror scheme to collect the switch tube current, the current sensing coefficient is equal to the sampling resistor value multiplied by the mirror current ratio. In practical applications, various calibrations and compensations are also required, including temperature compensation, non-linear compensation, and offset calibration. Temperature compensation is used to offset the measurement deviation caused by the temperature characteristics of the components; non-linear compensation corrects the non-linear part of the ADC conversion characteristic curve; offset calibration eliminates the static error in the system and improves the measurement accuracy.

[0109] It should also be noted that in combination with the switch tube drive integration module, there is also the following implementation method for step S110. Refer to Figure 9 , this application embodiment shows a specific implementation scheme for detecting the output current of a switched-capacitor converter using two half-bridge DrMOS modules. Figure 7The overall structure of the system is presented in detail, including the DrMOS module integrating the switching transistor, the connection structure, and the control module 20. The following will be combined with Figure 9 to elaborate on the DrMOS built-in current mirror technology in detail.

[0110] As Figure 9 shown, the four switching transistors in the switched-capacitor converter are integrated in two half-bridge DrMOS modules: DrMOS1 integrates the first main switching transistor Q1 and the first synchronous rectifier switching transistor Q5; DrMOS2 integrates the second main switching transistor Q2 and the second synchronous rectifier switching transistor Q6. Each DrMOS module contains the following key pins: PWM: used to receive the pulse-width modulation control signal; IMON: the current monitoring output pin, which outputs a mirror current proportional to the current of the internal switching transistor; IREF: the current reference setting pin, used to provide a common-mode voltage for IMON to facilitate the generation of a negative current signal; other functional pins: such as GND (ground), power input, etc.

[0111] The working principle of the DrMOS built-in current mirror technology is as follows: Next to each MOSFET, a mirror MOSFET with a very small area ratio (usually 1:500 to 1:2000) is integrated inside the DrMOS chip. This mirror MOSFET shares the same gate drive signal with the main MOSFET, so it has exactly the same switching characteristics.

[0112] Since the area of the mirror MOSFET is much smaller than that of the main MOSFET, but both bear the same gate-source voltage, the current flowing through the mirror MOSFET is in a strict proportional relationship with the main MOSFET current, and this ratio is equal to the area ratio of the two. For example, if the area of the mirror MOSFET is 1 / 1000 of the main MOSFET, the mirror current is 1 / 1000 of the main current.

[0113] DrMOS integrates the main MOSFET and the mirror MOSFET on the same silicon chip, ensuring that both have exactly the same temperature coefficient and process parameters, thus achieving excellent temperature stability and accuracy.

[0114] In the half-bridge structure, the high-side MOSFET (main switching transistor) and the low-side MOSFET (synchronous rectifier switching transistor) usually conduct complementarily. The internal circuit of DrMOS can automatically track which MOSFET is currently conducting and output the corresponding mirror current to the IMON pin.

[0115] As Figure 9 shown, the IMON pins of the two DrMOS modules are connected together and passed through a shared sampling resistor R CSConverted into a voltage signal. This connection method realizes the automatic summation of the currents of the four switching transistors, forming a composite signal representing the total switching transistor current.

[0116] The specific implementation details include: the mirror currents output from the IMON pins of the two DrMOS are naturally summed up and flow through the shared sampling resistor R CS , generating a voltage signal proportional to the total mirror current. The generated voltage signal is input to the analog-to-digital conversion unit 210 of the control module 20 through differential connection (CS+ and CS-). The control module 20 sends control signals to the two DrMOS modules through the PWM1 and PWM2 pins to control the switching states of the four switching transistors. The IREF pin of each DrMOS module is connected to a reference voltage source or a resistor network to set the proportionality coefficient of the current mirror and ensure the accuracy of the measurement results.

[0117] It should also be noted that the device capable of realizing the switching transistor current detection function is not only DrMOS, but also other discrete circuits with the switching transistor current detection function, switching transistor drive chips integrated with the switching transistor current detection function, etc.

[0118] In some other embodiments of the present application, step S100 specifically includes the following steps:

[0119] Step S160: At a preset moment, obtain the currents of the two synchronous rectifier switching transistors.

[0120] In the switched-capacitor converter, the currents of the synchronous rectifier switching transistors (Q5, Q6) are significantly related to the output current at a specific moment. Different from sampling all four switching transistors, this embodiment only focuses on the currents of the two synchronous rectifier switching transistors, greatly simplifying the detection circuit. In this scheme, the selection of the preset moment is particularly crucial. When the duty cycle d of the main switching transistor is less than or equal to 0.5, the preset moment is (0.5 + 0.5d)T PRD ; when the duty cycle d is greater than 0.5, the preset moment is also (0.5 + 0.5d)T PRD . By analyzing the working principle of the switched-capacitor converter, it can be known that at the above-mentioned moment, the sum of the currents of the two synchronous rectifier switching transistors is exactly equal to the output current.

[0121] There are various implementation ways to obtain the switching transistor current. In Figure 10 , it can be seen that the four switching transistors Q5, Q6 are respectively marked with current detection points IS5, IS6. These detection points are used to obtain the current signals flowing through each switching transistor during conduction.

[0122] There are multiple possible specific implementation methods: for example, a trace is led out from the source or drain terminal of the switching transistor, and the current is directly measured through a current sensor (such as a Hall sensor, a current transformer, etc.) in the signal processing module 10. Or a current detection circuit is integrated in the signal processing module to realize the separate detection of the currents of the low-side switching transistors (Q5 / Q6).

[0123] Step S170: Summarize the currents of the two synchronous rectifier switching transistors to obtain the total switching current.

[0124] The current summarization step combines the currents of the two synchronous rectifier switching transistors Q5 and Q6 to obtain the total switching current. Compared with the four-switching-transistor scheme, the summarization circuit is simpler because only two current signals need to be processed.

[0125] The summarization method can be implemented at the hardware or software level, depending on the system design requirements and resource limitations. Hardware summarization is usually achieved through the connection of current nodes. According to Kirchhoff's current law, multiple current signals are connected to the same node, and current superposition is naturally formed. Another hardware implementation method is to use a current adder to construct a current summation circuit based on an operational amplifier to achieve precise current addition. In addition, multiple current signals can also share the same sampling resistor, enabling the natural superposition of currents and converting them into corresponding voltage signals.

[0126] Software summarization is to first obtain the current values of the two synchronous rectifier switching transistors separately, and then perform digital addition operations in the processor. For most implementation schemes, the total switching current can be expressed as the algebraic sum of the currents of the two synchronous rectifier switching transistors, that is, I Q_all = IQ5 + IQ6. At a carefully selected preset moment, this total switching current is exactly equal to the output current of the switched-capacitor converter.

[0127] In Figure 10 the shown embodiment, the hardware summarization method is adopted. The current signals of the two synchronous rectifier switching transistors are introduced into the signal processing module 10 and directly summarized into a total current signal through the internal circuit.

[0128] Step S130: Convert the total switching current into a voltage signal.

[0129] From Figure 10 it can be seen that the output of the signal processing module 10 is connected to the control module 20 through two ports CS+ and CS-. This indicates that the signal processing module 10 converts the summarized current signal into a differential voltage signal for subsequent analog-to-digital conversion processing.

[0130] The current-to-voltage conversion is usually achieved through a precision sampling resistor R CSImplementation. Different from traditional solutions, the sampling resistor here is not located in the power loop but inside the signal processing circuit. Therefore, the power loss on the resistor is extremely small and will not significantly affect the system efficiency.

[0131] The conversion circuit may include the following functional blocks: converting the current signal into a voltage signal, and the conversion ratio is determined by the sampling resistor R CS (V = I × R CS) current-voltage converter; differential amplifier that converts a single-ended voltage signal into a differential signal to improve the anti-interference ability; filter circuit that removes high-frequency noise and extracts the effective components of the current signal; and level adjustment circuit that ensures the output signal is within the input range of the analog-to-digital conversion unit 210, maximizes the utilization of the dynamic range of the analog-to-digital conversion unit 210, and improves the measurement accuracy. It should be noted that the current-voltage conversion process will introduce a certain gain coefficient, which needs to be compensated in subsequent data processing to ensure the accuracy of the final calculation result.

[0132] Step S140: Sample and hold the voltage signal to obtain a digital quantity.

[0133] The analog-to-digital conversion unit 210 samples and holds the voltage signal to obtain a digital quantity. Preferably, a successive approximation analog-to-digital converter (SAR ADC) is used as the analog-to-digital conversion unit 210 because the SAR ADC can sample at an exact moment and provide sufficient conversion accuracy. Sampling timing control is particularly important. The system needs to precisely control the sampling trigger moment to ensure that the voltage signal is captured at a preset moment (0.5dT PRD ). To achieve this, the sampling clock is usually synchronized with the PWM control signal to eliminate the error at the sampling moment.

[0134] The sample-and-hold circuit inside the SAR ADC consists of a sampling switch, a holding capacitor, and a buffer amplifier. When the sampling command arrives, the sampling switch conducts, transferring the input voltage to the holding capacitor; then the sampling switch disconnects, and the holding capacitor stores the voltage value until the SAR ADC completes the conversion; the buffer amplifier isolates the holding capacitor from the subsequent circuit to prevent measurement errors caused by charge leakage. The SAR ADC conversion process is based on a binary search algorithm. The comparator compares the held voltage value with the internal reference voltage, and the successive approximation register controls the output of the internal DAC. After n comparisons, an n-bit digital quantity output is obtained. When selecting a SAR ADC, factors such as its number of bits, conversion rate, and reference voltage accuracy need to be considered. In general applications, SAR ADCs with 8 - 12-bit resolution are commonly used to balance speed and accuracy.

[0135] Step S150: Perform data conversion on the digital quantity to obtain the midpoint current.

[0136] Data conversion is a calculation process that converts the digital quantity output by the analog-to-digital conversion unit 210 into an actual current value. The basic conversion formula can be expressed as: midpoint current = digital quantity × conversion coefficient ÷ current sensing coefficient. Among them, the conversion coefficient is equal to the reference voltage divided by 2 to the power of n (n is the number of bits of the analog-to-digital conversion unit 210), and the reference voltage is the full-scale reference voltage of the analog-to-digital conversion unit 210. For example, for a 10-bit ADC, its conversion coefficient is the reference voltage divided by 1024.

[0137] The determination of the current sensing coefficient depends on the current detection implementation method. When adopting the sampling resistor scheme, the current sensing coefficient is equal to the sampling resistor value; while when using the current mirror scheme to collect the current of the switching tube, the current sensing coefficient is equal to the sampling resistor value multiplied by the mirror current ratio.

[0138] It should also be noted that in combination with the switching tube drive integration module, step S160 also has the following implementation methods. Refer to Figure 11 , this application embodiment shows a specific implementation scheme for realizing the current detection of the synchronous rectification switching tube by using two half-bridge DrMOS modules. Different from Figure 9 the embodiment shown, Figure 11 the implementation method in

[0139] As Figure 11 shown, the switched-capacitor converter is constructed by using two half-bridge DrMOS modules: DrMOS1 integrates the first main switching tube Q1 and the first synchronous rectification switching tube Q5; DrMOS2 integrates the second main switching tube Q2 and the second synchronous rectification switching tube Q6. The key connections and components of the system include: the input voltage terminal V IN is connected to the two DrMOS modules, the flying capacitor C FLY is connected between the two half-bridges, the first inductor L1 and the second inductor L2 are respectively connected to the output capacitor C O and the load R LOAD , the control module 20 sends control signals to the DrMOS modules through the PWM1 and PWM2 pins, the IMON pin of the DrMOS outputs the mirror current, which is connected to the sampling resistor R CS , and the CS+ and CS- differential signals are connected to the analog-to-digital conversion unit 210 of the control module 20.

[0140] The key difference from Figure 9 is that, Figure 11The DrMOS in it is configured to output only the current information of the synchronous rectifier switch (low-side MOSFET), without including the current information of the main switch (high-side MOSFET). The first synchronous rectifier switch and the second synchronous rectifier switch are integrated in the second switch driver integrated module, and the current information is obtained through the internal current mirror of this module. In Figure 11 In the embodiment of, this technology is implemented through the low-side current mirror of DrMOS.

[0141] The working principle of the DrMOS low-side current mirror is as follows: DrMOS integrates a scaled-down mirror MOSFET inside the low-side MOSFET (synchronous rectifier switch) chip. This mirror MOSFET shares the same gate drive signal with the main MOSFET and has exactly the same switching characteristics.

[0142] The area of the mirror MOSFET is usually 1 / 500 to 1 / 2000 of that of the main MOSFET. Therefore, the current flowing through the mirror MOSFET has an exact proportional relationship with the main MOSFET.

[0143] Since the mirror MOSFET and the main MOSFET are integrated on the same silicon chip, they have exactly the same temperature coefficient, ensuring a stable proportional relationship when the temperature changes.

[0144] DrMOS can usually select to output the current information of the low-side MOSFET, high-side MOSFET, or both through configuration. In Figure 11 In the embodiment of, DrMOS is configured to output only the current information of the low-side MOSFET (synchronous rectifier switch).

[0145] In Figure 11 In the implementation shown, the IMON pins of two DrMOS modules are connected together, and the output mirror current flows through the shared sampling resistor R CS , and is converted into a differential voltage signal (CS+ and CS-) and input to the control module 20.

[0146] Compared with detecting the currents of all four switches, detecting only the current of the synchronous rectifier switch has the following significant advantages: The current detection technology of the low-side MOSFET is more mature, and the implementation difficulty is much lower than that of the high-side MOSFET current detection. The high-side MOSFET is at a floating potential, and the current detection is more complex. The reliability of the low-side current mirror technology is higher, and it is less affected by factors such as temperature and voltage fluctuations. Almost all DrMOS products support low-side current detection, while some early or low-cost products may not support high-side current detection. The source of the low-side MOSFET is grounded, and the common-mode noise of the current detection signal is smaller, and the signal quality is usually higher.

[0147] The total switch current must be converted into a voltage signal before it can be collected and processed by the analog-to-digital conversion unit 210. In the synchronous rectifier switch tube current detection scheme, the current-to-voltage conversion usually adopts the sampling resistor method. Since the synchronous rectifier switch tube current detection circuit is located on the low side, the sampling resistor can be directly connected between the IMON signal path and the ground to form a simple I-V conversion. When the mirror currents of two synchronous rectifier switch tubes flow through the sampling resistor R CS a voltage drop V OUT =(IQ5 + IQ6)×R CS is generated. The selection of the sampling resistor should balance the measurement sensitivity and power consumption, usually in the range of a few ohms to dozens of ohms, depending on the mirror current ratio and the input range of the analog-to-digital conversion unit 210.

[0148] Different from the prior art, the embodiment of the present invention is directed to a switched-capacitor converter. According to the relationship between the switch tube current and the output current, the output current is obtained by detecting the switch tube current at a specific moment, avoiding adding an additional sampling resistor in the output loop, thereby reducing the system loss, reducing the heat dissipation area, improving the power density of the switched-capacitor converter, and also avoiding the possibility that adding a sampling resistor in the high-frequency switching loop is vulnerable to switch noise interference and affects the sampling result.

[0149] The embodiment of the present invention also provides an electronic device based on the above output current detection method. The structural schematic diagram is as shown in Figure 12 The electronic device 700 includes:

[0150] One or more processors 701, a network interface 702, and a memory 703. Figure 12 Here, one processor 701, one network interface 702, and one memory 703 are taken as examples.

[0151] The network interface 702 is communicatively connected to the corresponding processor 701. The processor 701 and the memory 702 can be connected through a bus or other means. Figure 12 Here, the connection through the bus is taken as an example.

[0152] The network interface 702 is used to establish a communication connection between the processor 701 and other external devices, including the following types: RJ-45 interface, SC fiber optic interface, AUI interface, FDDI interface, and Console interface, etc.

[0153] The memory 703, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor 701 executes various functional applications and data processing of the electronic device by running the non-volatile software programs, instructions, and units stored in the memory 703, that is, implementing the output current detection method in the above method embodiment.

[0154] The memory 103 may include a program storage area and a data storage area. The program storage area may store an operating system and application programs required for at least one function. The data storage area may store data created according to the use of the electronic device and the like. In addition, the memory 703 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 703 may optionally include a memory remotely disposed relative to the processor 701, and these remote memories may be connected to the electronic device through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0155] The one or more units are stored in the memory 703 and, when executed by one or more processors 701, perform the output current detection method in any of the above method embodiments. For example, perform the method steps S100 to S200 described above. Figure 7 in the above.

[0156] The above electronic device can execute the output current detection method provided by the embodiments of the present invention, and has a program module and beneficial effects corresponding to the execution of the method. For technical details not described in detail in the embodiments of the electronic device, reference may be made to the output current detection method provided by the embodiments of the present invention.

[0157] The embodiments of the present invention also provide a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium may be included in the device described in the above embodiments; or may exist alone without being assembled into the device. The above non-volatile computer-readable storage medium carries one or more programs, and when the one or more programs are executed, the output current detection method of the embodiments of the present disclosure is implemented.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other changes in different aspects of the present application as above. For the sake of brevity, they are not provided in detail; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for detecting output current, applied to a switched-capacitor converter, characterized in that Including: At a preset moment in the switching period of the switched-capacitor converter, obtaining the midpoint current of the switching transistors of the switched-capacitor converter; The midpoint current is the sum of the currents of the switching transistors; Based on the midpoint current, obtaining the output current of the switched-capacitor converter; at the preset moment, the midpoint current is equal to the output current; the preset moment is set based on the duty cycle of the switching transistors.

2. The method according to claim 1, characterized in that The switching transistors include two main switching transistors and two synchronous rectifier switching transistors. The step of obtaining the midpoint current of the switching transistors of the switched-capacitor converter at a preset moment in the switching period of the switched-capacitor converter includes: At the preset moment, obtaining the currents of the two main switching transistors and the two synchronous rectifier switching transistors; Summarizing the currents of the two main switching transistors and the two synchronous rectifier switching transistors to obtain the total switching current; Converting the total switching current into a voltage signal; Sampling and holding the voltage signal to obtain a digital quantity; Performing data conversion on the digital quantity to obtain the midpoint current.

3. The method according to claim 1, wherein The switching transistors include two main switching transistors and two synchronous rectifier switching transistors. The step of obtaining the midpoint current of the switching transistors of the switched-capacitor converter at a preset moment in the switching period of the switched-capacitor converter includes: At the preset moment, obtaining the currents of the two synchronous rectifier switching transistors; Summarizing the currents of the two synchronous rectifier switching transistors to obtain the total switching current; Converting the total switching current into a voltage signal; Sampling and holding the voltage signal to obtain a digital quantity; Performing data conversion on the digital quantity to obtain the midpoint current.

4. The method according to claim 2, characterized in that, When the total switching current is the sum of the currents of the two main switching transistors and the two synchronous rectifier switching transistors, The preset time is 0.5dT PRD ; where d is the duty cycle of the main switching transistor, and T PRD is the switching period.

5. The method according to claim 3, characterized in that, When the total switching current is the sum of the currents of the two synchronous rectifier switching transistors, The preset moment is (0.5 + 0.5d)T PRD ; where d is the duty cycle of the main switch transistor, and T PRD is the switching period.

6. The method according to claim 2 or 3, characterized in that, The step of performing data conversion on the digital quantity to obtain the midpoint current includes: Multiplying the digital quantity by a conversion coefficient and dividing by a current sensing coefficient to obtain the midpoint current; The conversion coefficient is the reference voltage of the analog-to-digital conversion unit divided by 2 to the power of n, where n is the number of bits of the analog-to-digital conversion unit; The current sensing coefficient is the resistance value of the sampling resistor, or the product of the sampling resistor and the mirror current ratio.

7. The method according to claim 6, characterized in that The two main switching transistors include a first main switching transistor and a second main switching transistor; The first main switching transistor and the second main switching transistor are integrated in a first switching transistor drive integrated module, and the currents of the first main switching transistor and the second main switching transistor are obtained through the internal current mirror of the first switching transistor drive integrated module.

8. The method according to claim 6, characterized in that The two synchronous rectifier switching transistors include a first synchronous rectifier switching transistor and a second synchronous rectifier switching transistor; The first synchronous rectifier switching transistor and the second synchronous rectifier switching transistor are integrated in a second switching transistor drive integrated module, and the currents of the first synchronous rectifier switching transistor and the second synchronous rectifier switching transistor are obtained through the internal current mirror of the second switching transistor drive integrated module.

9. An electronic device, characterized in that, Including: At least one processor; At least one network interface, the network interface being communicatively connected to the corresponding processor; And, A memory communicatively connected to the at least one processor; wherein, The network interface is used to establish a communication connection between the processor and other external devices; The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute an output current detection method according to any one of claims 1-8.

10. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by one or more processors, the one or more processors can be caused to execute an output current detection method according to any one of claims 1-8.

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