Amplification method of radio frequency signal

Abstract

To provide a signal amplifier for a wireless communication device that provides impedance scaling with gain mode conversion.SOLUTION: A signal amplifier 10 having an input impedance Zin that varies over different bias currents includes a gain stage including a plurality of switchable amplifier branches and a scalable impedance block 104 having a plurality of switchable inductive elements Zs1 to Zs4, and one or more of the amplifier branches when activated provides a targeted adjustment to the input impedance.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present disclosure generally relates to amplifiers for wireless communication devices.

[0002] Cross - reference to related applications This application claims priority to U.S. Provisional Application No. 62 / 382,252, entitled "Amplifier with Improved Reflection Loss and Mismatch in Gain Mode," filed on August 31, 2016. The entire disclosure of which is hereby expressly incorporated by reference in its entirety for all purposes.

Background Art

[0003] In electronic applications such as radio frequency (RF) applications, it may be desirable to amplify a signal. For example, a signal scheduled for transmission can be amplified by a power amplifier, and a received signal can be amplified by a low - noise amplifier. In some applications, it is advantageous to reduce impedance mismatches in the amplification chain to improve signal quality.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] According to certain implementations, the present disclosure relates to a signal amplifier having an input impedance that varies over different bias currents. The signal amplifier includes a gain stage that includes a plurality of switchable amplification branches. Each of the plurality of switchable amplification branches is active can become a branch. One or more of the activated amplification branches input the target adjustment to the impedance.

[0006] In some embodiments, each of the plurality of switchable amplification branches includes a switching transistor and an RF stage transistor. In a further embodiment, a first plurality of RF stage transistors become active in a first gain mode, and a second plurality of RF stage transistors become active in a second gain mode lower than the first gain mode, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode. In the first gain mode, a first plurality of RF stage transistors become active, in a second gain mode lower than the first gain mode, a second plurality of RF stage transistors become active, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode. In the second gain mode, a second plurality of RF stage transistors become active, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode. In the second gain mode, the number of active RF stage transistors is less than that in the first gain mode. Yes.

[0007] According to certain implementations, the present disclosure relates to a signal amplifier including a variable gain stage configured to provide a plurality of gain levels resulting in different input impedance values. The different input impedance values are presented to each signal by the variable gain stage. The variable gain stage includes a plurality of switchable amplification branches each of which can become active. One or more of the active amplification branches provide a target adjustment to each input impedance value. According to certain implementations, the present disclosure relates to a signal amplifier including a variable gain stage configured to provide a plurality of gain levels resulting in different input impedance values. The different input impedance values are presented to each signal by the variable gain stage. The variable gain stage includes a plurality of switchable amplification branches each of which can become active. One or more of the active amplification branches provide a target adjustment to each input impedance value. In some embodiments, each of the plurality of switchable amplification branches includes a switching transistor and an RF stage transistor. In a further embodiment, a first plurality of RF stage transistors become active in a first gain mode, and a second plurality of RF stage transistors become active in a second gain mode lower than the first gain mode, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode. In some embodiments, each of the plurality of switchable amplification branches includes a switching transistor and an RF stage transistor. In a further embodiment, a first plurality of RF stage transistors become active in a first gain mode, and a second plurality of RF stage transistors become active in a second gain mode lower than the first gain mode, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode.

[0008] In some embodiments, each of the plurality of switchable amplification branches includes a switching transistor and an RF stage transistor. In a further embodiment, a first plurality of RF stage transistors become active in a first gain mode, and a second plurality of RF stage transistors become active in a second gain mode lower than the first gain mode, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode. In the first gain mode, a first plurality of RF stage transistors become active, in a second gain mode lower than the first gain mode, a second plurality of RF stage transistors become active, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode. In the second gain mode, a second plurality of RF stage transistors become active, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode. In the second gain mode, the number of active RF stage transistors is less than that in the first gain mode. Yes.

[0009] According to certain implementations, the present disclosure relates to a signal amplifier including a variable gain stage configured to provide a plurality of gain levels resulting in different input impedance values. The different input impedance values are presented to each signal by the variable gain stage. The variable gain stage includes a scalable impedance block having a plurality of switchable inductive elements. The plurality of switchable inductive elements are configured to be activated to provide target adjustment to each input impedance value. In some embodiments, the scalable impedance block is configured to increase inductance when the gain level decreases. In some embodiments, the scalable impedance block is coupled to the source of the RF stage transistor of the variable gain stage. According to certain implementations, the present disclosure relates to a radio frequency (RF) amplifier including an input node and an output node. The amplifier also includes a gain stage including a plurality of switchable amplification branches. Each of the plurality of switchable amplification branches can be activated. One or more of the active amplification branches provide target adjustment to the input impedance. In some embodiments, the RF amplifier is a low noise amplifier (LNA). In further embodiments, the LNA can be implemented in a cascode configuration having an input stage and a cascode stage. In some embodiments, the input impedance at each of the plurality of gain settings

[0010]

[0011]

[0012]

[0013] The target adjustment for is to approximately provide a constant impedance at the input node is selected. In some embodiments, a plurality of transistors are one transistor operates at the lowest gain setting, and one additional transistor for each increased gain setting is configured to operate.

[0014] According to certain implementations, the present disclosure relates to a method of amplifying a signal. The method includes configuring a gain stage to one of a plurality of selected gain settings. At least some of the gain settings result in different impedances presented to the signal. The method also includes adjusting the impedance presented to the signal by the gain stage for the selected gain setting. The adjusted impedance is configured to provide a target constant impedance value to the input across a plurality of gain settings ..

[0015] In some embodiments, the gain stage is part of a low noise amplifier (LNA). In some embodiments, the adjusted impedance results in approximately a constant impedance among a plurality of gain settings . In some embodiments, adjusting the impedance includes adjusting one or more inductances coupled to the source of the RF stage transistors of the gain stage .

[0016] In some embodiments, adjusting the impedance includes operating a plurality of transistors in an electrically parallel configuration. Each transistor has an associated switch to selectively activate the associated transistor . In further embodiments, operating a plurality of transistors includes, at the drain of each transistor, the transistor including performing a switching operation to control the operation of

[0017] According to some implementations, the present disclosure relates to a semiconductor die having a radio frequency (RF) circuit. The RF circuit includes a substrate and an RF amplifier mounted on the substrate. The RF amplifier includes a gain stage including a plurality of switchable amplification branches that can each be activated. One or more of the active amplification branches provide a target adjustment to the input impedance.

[0018] In some embodiments, the substrate includes a silicon-on-insulator (SOI) substrate. In some embodiments, the RF amplifier is a low noise amplifier (LNA).

[0019] According to some implementations, the present disclosure relates to a radio frequency (RF) module including a package substrate. The package substrate is configured to receive a plurality of components and an RF amplifier mounted on the package substrate. The RF amplifier includes a gain stage including a plurality of switchable amplification branches that can each be activated. One or more of the active amplification branches provide a target adjustment to the input impedance.

[0020] In some embodiments, the RF amplifier is implemented on a semiconductor die attached to the package substrate. In some embodiments, the RF amplifier is a low noise amplifier (LNA). In some embodiments, the RF module is a diversity receive (DRx) module.

[0021] According to some implementations, the present disclosure is configured to receive at least a radio frequency (RF) signal. Relates to a wireless device including an antenna configured therein. The wireless device also includes an RF amplifier that communicates with the antenna, and includes a gain stage including a plurality of switchable amplification branches that are each activated. One or more of the active amplification branches apply a target adjustment to the input impedance to provide a target phase. The wireless device also includes a transceiver configured to process an amplified RF signal having a target phase from the RF amplifier. In some embodiments, the wireless device is a mobile phone configured to have different gains in a receive operation. For the purpose of summarizing the present disclosure, certain aspects, advantages, and novel features have been described herein. It is not necessarily the case that all such advantages are achieved in any particular embodiment. Thus, embodiments of the present disclosure can be implemented or optimized in a manner that achieves or optimizes one advantage or a group of advantages taught or suggested herein without necessarily achieving other advantages taught or suggested herein.

Brief Description of the Drawings

[0022] Illustrates a typical LNA configured as a cascode amplifier but without an impedance adjustment circuit.

[0023] In some embodiments, the wireless device is a mobile phone configured to have different gains in a receive operation.

[0024]

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Best Mode for Carrying Out the Invention

[0025] The headings given here, if any, are for convenience only and do not necessarily affect the scope or meaning of the invention related to the claims. It does not necessarily affect the scope or meaning of the invention related thereto.

[0026] Summary

[0027] Described herein is, among other things, an architecture, circuit, device and method related to a radio frequency (RF) amplifier having an impedance adjustment function for various gain modes. There is. FIG. 1 depicts a signal amplifier 100 having a gain stage 102 and an impedance adjustment circuit 104. Such a signal amplifier 100 receives an input signal (IN) and amplifies such a signal to generate an output signal (OUT). In certain implementations, the gain stage 102 includes one or more amplification transistors. For purposes of illustration, various examples related to such a signal amplifier 100 are described in the context of a low noise amplifier (LNA). However, it will be understood that one or more features of the present disclosure can also be implemented for other types of signal amplifiers including power amplifiers (PAs). In many LNA applications, it is desirable to match the impedance to increase or maximize the power transfer between signal processing stages. Due to such performance characteristics, for example, in reception demodulation over different LNA gain modes, especially in high-order modulation systems, desirable signal characteristics can be maintained. In some embodiments, an LNA circuit having one or more features described herein is configured to adjust the impedance to match the input impedance at the input of the LNA circuit over different gain modes.

[0028] In many LNA applications, it is desirable to match the impedance to increase or maximize the power transfer between signal processing stages. This can maintain desirable signal characteristics. In some embodiments, an LNA circuit having one or more features described herein is configured to adjust the impedance to match the input impedance at the input of the LNA circuit over different gain modes. For example, in reception demodulation over different LNA gain modes, especially in high-order modulation systems, desirable signal characteristics can be maintained. In some embodiments, an LNA circuit having one or more features described herein is configured to adjust the impedance to match the input impedance at the input of the LNA circuit over different gain modes. To eliminate or minimize significant reflections or mismatches that can lead to performance degradation. It can be configured to adjust the impedance to match the input impedance at the input of the LNA circuit over different gain modes. To eliminate or minimize significant reflections or mismatches that can lead to performance degradation. It is also desirable to have an actual value of the input impedance close to the target value (e.g., 50 Ω). Yes.

[0029] The impedance adjustment circuit 104 can provide a scalable gain stage having a plurality of switchable amplification branches each of which can be activated. By selectively activating the amplification branches, adjustments can be provided that are targeted, designed, or desired for the input impedance. Similarly, the impedance adjustment circuit 104 can provide a scalable impedance block having a plurality of switchable inductive elements that can be activated. By selectively activating the inductive elements, adjustments can be provided that are targeted, designed, or desired for the input impedance. Advantageously, the impedance adjustment circuit 104 can be configured to reduce or eliminate power loss by fixing the LNA input impedance to transmit maximum power over the gain mode. The impedance adjustment circuit 104 can be configured to improve the receive NF performance by reducing or minimizing the impedance mismatch from the previous signal processing stage. The impedance adjustment circuit 104 can be configured to maintain the performance of the LNA front-end filter by reducing or eliminating the impedance mismatch with the LNA circuit.

[0030] Advantageously, the impedance adjustment circuit 104 can be configured to reduce or eliminate power loss by fixing the LNA input impedance to transmit maximum power over the gain mode. The impedance adjustment circuit 104 can be configured to improve the receive NF performance by reducing or minimizing the impedance mismatch from the previous signal processing stage. The impedance adjustment circuit 104 can be configured to maintain the performance of the LNA front-end filter by reducing or eliminating the impedance mismatch with the LNA circuit. Figure 2 shows that the LNA 100 having one or more features described herein is implemented in a cascode configuration with a first transistor and a second transistor (collectively shown as gain stage 102). The impedance adjustment circuit 104 can be configured to maintain the performance of the LNA front-end filter by reducing or eliminating the impedance mismatch with the LNA circuit.

[0031] Figure 2 shows that the LNA 100 having one or more features described herein is implemented in a cascode configuration with a first transistor and a second transistor (collectively shown as gain stage 102). The first transistor and the second transistor (collectively shown as gain stage 102) implemented in a cascode configuration. ​​​may include. For example, the first transistor Q1 can be configured to operate as a common source device (also referred to as an RF stage) and the second transistor Q2 can be configured to operate as a common gate device (also referred to as a cascode stage). More specifically , an input signal (IN) is shown to be applied to the gate of the first transistor Q1, and the amplified signal is shown to be output through its drain. The source of the first transistor Q1 is shown to be coupled to ground. The amplified signal from the drain of the first transistor Q1 is applied to the source of the second transistor Q2 for further amplification . Such further amplified signal is shown to be output through the drain of the second transistor Q2 . The gate of the second transistor Q2 is shown to be coupled to ground . Appropriate biasing can be applied to the first transistor and the second transistors Q1, Q2 . In the example of FIG. 2, the second transistor Q2 is shown to have a supply voltage V DD applied to its drain.

[0032] FIG. 2 further shows that in some embodiments, the LNA 100 includes or comprises an impedance adjustment circuit 104. Various examples of such impedance adjustment circuits are described in detail herein .

[0033] In the example of FIG. 2, the impedance adjustment circuit 104 is shown to be associated with the first transistor Q1 (RF stage ). However, it is understood that such a phase compensation circuit can be provided for either or both of the first transistor Q1 (RF stage) and the second transistor Q2 (cascode stage) .

[0034] Figure 3 shows a typical configuration of a cascode amplifier without an impedance adjustment circuit. A typical LNA 10 is shown. The RF stage 12 is associated with various portions of transistor Q1. For example, the input path to the gate of Q1 is drawn as having an impedance The input impedance Zin presented to the signal may be an effective inductance. Similarly, the ground path of the source of Q1 is an effective inductor that results in a source impedance Zs. For example, the gate-source impedance Zgs and the transconductance One or more other impedances, including the coulomb-related impedance gm*Zgs*Zs, This example of impedance results from Q1. The total impedance Ztot is Ztot=Zin+Zs+Zgs+gm*Zgs *Can be expressed as Zs.

[0035] FIG. 4 shows an example of how the RF stage 12 of FIG. 3 can be represented as an RLC circuit 12. The circuit may include a resistor R connected at one end to the input and at the other end to one end of an inductance L. The other end of the inductance L can be coupled to ground via a capacitance C. The resistance R is related to the transconductance term gm*Zgs*Zs, and the inductance The capacitance L is related to the sum of Zin and Zs, and the capacitance C is related to Zgs. In this representation, the resonant frequency can be expressed as:

number

[0036] In the examples of FIGS. 3 and 4, the LNA 10 can operate in different gain modes by adjusting the supply current Idd. Along with such a change in Idd, electrical parameters such as Cgs can also change. For example, FIG. 5 shows that R (gm*Ls / Cgs) of FIGS. 3 and 4 can change as a function of Idd. That is, at a first Idd setting corresponding to an example G3 of the gain mode, R can have a first value. Similarly, a second Idd setting for the gain mode G2 can result in an R having a second value greater than the first R value. If such a trend continues, the third and fourth settings for the gain modes G1 and G0 can result in an R having a third value and a fourth value that continuously increase. That is, in FIG. 5, the solid line depicts an example of the relationship between R and Idd. along with such a change in Idd, electrical parameters such as Cgs can also change. For example, FIG. 5 shows that R (gm*Ls / Cgs) of FIGS. 3 and 4 can change as a function of Idd. That is, at a first Idd setting corresponding to an example G3 of the gain mode, R can have a first value. Similarly, a second Idd setting for the gain mode G2 can result in an R having a second value greater than the first R value. If such a trend continues, the third and fourth settings for the gain modes G1 and G0 can result in an R having a third value and a fourth value that continuously increase. That is, in FIG. 5, the solid line depicts an example of the relationship between R and Idd. In the examples of FIGS. 3 and 4, the LNA 10 can operate in different gain modes by adjusting the supply current Idd. Along with such a change in Idd, electrical parameters such as Cgs can also change. For example, FIG. 5 shows that R (gm*Ls / Cgs) of FIGS. 3 and 4 can change as a function of Idd. That is, at a first Idd setting corresponding to an example G3 of the gain mode, R can have a first value. Similarly, a second Idd setting for the gain mode G2 can result in an R having a second value greater than the first R value. If such a trend continues, the third and fourth settings for the gain modes G1 and G0 can result in an R having a third value and a fourth value that continuously increase. That is, in FIG. 5, the solid line depicts an example of the relationship between R and Idd. In the examples of FIGS. 3 and 4, the LNA 10 can operate in different gain modes by adjusting the supply current Idd. Along with such a change in Idd, electrical parameters such as Cgs can also change. For example, FIG. 5 shows that R (gm*Ls / Cgs) of FIGS. 3 and 4 can change as a function of Idd. That is, at a first Idd setting corresponding to an example G3 of the gain mode, R can have a first value. Similarly, a second Idd setting for the gain mode G2 can result in an R having a second value greater than the first R value. If such a trend continues, the third and fourth settings for the gain modes G1 and G0 can result in an R having a third value and a fourth value that continuously increase. That is, in FIG. 5, the solid line depicts an example of the relationship between R and Idd. In the examples of FIGS. 3 and 4, the LNA 10 can operate in different gain modes by adjusting the supply current Idd. Along with such a change in Idd, electrical parameters such as Cgs can also change. For example, FIG. 5 shows that R (gm*Ls / Cgs) of FIGS. 3 and 4 can change as a function of Idd. That is, at a first Idd setting corresponding to an example G3 of the gain mode, R can have a first value. Similarly, a second Idd setting for the gain mode G2 can result in an R having a second value greater than the first R value. If such a trend continues, the third and fourth settings for the gain modes G1 and G0 can result in an R having a third value and a fourth value that continuously increase. That is, in FIG. 5, the solid line depicts an example of the relationship between R and Idd. In the examples of FIGS. 3 and 4, the LNA 10 can operate in different gain modes by adjusting the supply current Idd. Along with such a change in Idd, electrical parameters such as Cgs can also change. For example, FIG. 5 shows that R (gm*Ls / Cgs) of FIGS. 3 and 4 can change as a function of Idd. That is, at a first Idd setting corresponding to an example G3 of the gain mode, R can have a first value. Similarly, a second Idd setting for the gain mode G2 can result in an R having a second value greater than the first R value. If such a trend continues, the third and fourth settings for the gain modes G1 and G0 can result in an R having a third value and a fourth value that continuously increase. That is, in FIG. 5, the solid line depicts an example of the relationship between R and Idd. In the examples of FIGS. 3 and 4, the LNA 10 can operate in different gain modes by adjusting the supply current Idd. Along with such a change in Idd, electrical parameters such as Cgs can also change. For example, FIG. 5 shows that R (gm*Ls / Cgs) of FIGS. 3 and 4 can change as a function of Idd. That is, at a first Idd setting corresponding to an example G3 of the gain mode, R can have a first value. Similarly, a second Idd setting for the gain mode G2 can result in an R having a second value greater than the first R value. If such a trend continues, the third and fourth settings for the gain modes G1 and G0 can result in an R having a third value and a fourth value that continuously increase. That is, in FIG. 5, the solid line depicts an example of the relationship between R and Idd. In the examples of FIGS. 3 and 4, the LNA 10 can operate in different gain modes by adjusting the supply current Idd. Along with such a change in Idd, electrical parameters such as Cgs can also change. For example, FIG. 5 shows that R (gm*Ls / Cgs) of FIGS. 3 and 4 can change as a function of Idd. That is, at a first Idd setting corresponding to an example G3 of the gain mode, R can have a first value. Similarly, a second Idd setting for the gain mode G2 can result in an R having a second value greater than the first R value. If such a trend continues, the third and fourth settings for the gain modes G1 and G0 can result in an R having a third value and a fourth value that continuously increase. That is, in FIG. 5, the solid line depicts an example of the relationship between R and Idd. In the examples of FIGS. 3 and 4, the LNA 10 can operate in different gain modes by adjusting the supply current Idd. Along with such a change in Idd, electrical parameters such as Cgs can also change. For example, FIG. 5 shows that R (gm*Ls / Cgs) of FIGS. 3 and 4 can change as a function of Idd. That is, at a first Idd setting corresponding to an example G3 of the gain mode, R can have a first value. Similarly, a second Idd setting for the gain mode G2 can result in an R having a second value greater than the first R value. If such a trend continues, the third and fourth settings for the gain modes G1 and G0 can result in an R having a third value and a fourth value that continuously increase. That is, in FIG. 5, the solid line depicts an example of the relationship between R and Idd.

[0037] In the examples of FIGS. 3 and 4, due to the aforementioned variations in R, corresponding variations in impedance are brought about as a function of Idd. Such variations in impedance are not desirable. Therefore, it can be advantageous to adjust the R value so as to achieve a substantially constant R value over a number of gain modes and supply currents. This targeted R value is indicated by the dotted line of the value of Y in FIG. 5. The target value Y is typically 50 Ω in wireless communication applications. In the examples of FIGS. 3 and 4, due to the aforementioned variations in R, corresponding variations in impedance are brought about as a function of Idd. Such variations in impedance are not desirable. Therefore, it can be advantageous to adjust the R value so as to achieve a substantially constant R value over a number of gain modes and supply currents. This targeted R value is indicated by the dotted line of the value of Y in FIG. 5. The target value Y is typically 50 Ω in wireless communication applications. In the examples of FIGS. 3 and 4, due to the aforementioned variations in R, corresponding variations in impedance are brought about as a function of Idd. Such variations in impedance are not desirable. Therefore, it can be advantageous to adjust the R value so as to achieve a substantially constant R value over a number of gain modes and supply currents. This targeted R value is indicated by the dotted line of the value of Y in FIG. 5. The target value Y is typically 50 Ω in wireless communication applications. In the examples of FIGS. 3 and 4, due to the aforementioned variations in R, corresponding variations in impedance are brought about as a function of Idd. Such variations in impedance are not desirable. Therefore, it can be advantageous to adjust the R value so as to achieve a substantially constant R value over a number of gain modes and supply currents. This targeted R value is indicated by the dotted line of the value of Y in FIG. 5. The target value Y is typically 50 Ω in wireless communication applications. In the examples of FIGS. 3 and 4, due to the aforementioned variations in R, corresponding variations in impedance are brought about as a function of Idd. Such variations in impedance are not desirable. Therefore, it can be advantageous to adjust the R value so as to achieve a substantially constant R value over a number of gain modes and supply currents. This targeted R value is indicated by the dotted line of the value of Y in FIG. 5. The target value Y is typically 50 Ω in wireless communication applications. In the examples of FIGS. 3 and 4, due to the aforementioned variations in R, corresponding variations in impedance are brought about as a function of Idd. Such variations in impedance are not desirable. Therefore, it can be advantageous to adjust the R value so as to achieve a substantially constant R value over a number of gain modes and supply currents. This targeted R value is indicated by the dotted line of the value of Y in FIG. 5. The target value Y is typically 50 Ω in wireless communication applications.

[0038] FIG. 6 illustrates the variation of the supply current as a function of the gain mode. FIG. 7 shows different Illustrate the relationship between the device size W and the supply current Idd for the resulting gain mode. Thus for a fixed source inductance Ls, the targeted R value can be achieved by maintaining the ratio gm / Cg s relatively constant. This can be achieved by scaling the width of the device at the same rate as the supply current changes across multiple gain modes.

[0039] Since the actual impedance changes as a function of the gain mode (e.g., increases as the gain increases), an undesirable gap occurs between the actual R value at the input and the targeted R value (e.g., the value that reduces or minimizes signal degradation). Thus, described herein is an impedance adjustment circuit that includes scalable gain stages configured to provide a constant actual value R. These scalable gain stages can be configured to substantially maintain the ratio gm / Cgs constant. The impedance adjustment circuit includes a mechanism and elements configured to effectively scale the device width (W) at the same rate as the supply voltage for a given gain mode. This results in a fixed actual impedance at the targeted value. The device size ratio is approximately proportional to the supply current ratio (e.g., I dd0 / Idd1≒W0 / W1, Idd1 / Idd2≒W1 / W2, and Idd2 / Id d3≒W2 / W3). dd0 / Idd1≒W0 / W1, Idd1 / Idd2≒W1 / W2, and Idd2 / Id d3≒W2 / W3).

[0040] This can be achieved by an impedance adjustment circuit that includes scalable gain stages configured to provide a fixed actual impedance across different gain modes. FIGS. 8 and 9 show scalable gain stages that can be implemented for the signal amplifier 100 (e.g., LNA). ​​​​​- An example of a scalable gain stage 104 is illustrated. The scalable gain stage 104 includes a plurality of switches S1a to S1d and corresponding RF stage transistors Q1a to Q1d, and signals can be routed to pass through one or more of such R F stage transistors in a selective manner.

[0041] The scalable gain stage 104 includes four examples of RF stage transistors Q1a, Q1b, Q1c, Q1d implemented in parallel. Thereby, processing of an input signal passing through one or more of the RF stage transistors Q1a, Q1 b, Q1c, Q1d is allowed. More specifically, the input node IN is shown to be coupled to the gates of each of the four RF stage transistors Q1a, Q1b, Q1c, Q1d, and the drain of each RF stage transistor is connected to the switch transistor S 1a, S1b, S1c, S1d and routed to the cascode stage transistor Q2 (not shown in FIG. 9 ). For example, the drain of Q1a is routed to Q2 through the first switch transistor S1a, the drain of Q1b is routed to Q2 through the second switch transistor S1b, and so on. The signal can be processed through one or more parallel RF stage transistors by being configured in the manner of the example described above. .

[0042] As described herein, gm also decreases as the supply current decreases. By selectively adding or removing RF stage transistors, the effective de vice size of the scalable gain stage 104 can be changed. By reducing the device size along with the gain reduction, a substantially constant actual impedance can be achieved. It should be noted that However, the influence on the supply current Idd can depend on one or more dimensions of the RF stage transistors (shown as W / L in FIG. 8). That is, in the example of FIG. 9, the dimensions Wa / La, Wb / Lb, Wc / Lc, Wd / Ld corresponding to the RF stage transistors Q1a, Q1b, Q1c, Q1d can be selected to turn the switches on and off to give different effective values of the device size. For example, in the high gain mode (G0), by turning on each switch, the four RF stage transistors can be made active. In the second gain mode (G1) lower than the high gain mode (G0), by turning on each switch, three of the four RF stage transistors (e.g., RF stage transistors Q1b, Q1c, Q1d) can be made active. In the third gain mode (G2) lower than the second gain mode (G1), by turning on each switch, two of the four RF stage transistors (e.g., RF stage transistors Q1c, Q1d) can be made active. This can be continued for any suitable number of gain modes and RF stage transistors in the scalable gain stage 104. It is understood that such dimensions Wa / La, Wb / Lb, Wc / Lc, Wd / Ld can all be substantially the same, all be different, or any combination of these. By configuring in the foregoing manner, different net R values can be obtained for different gain modes. As described herein, the dimensions of the RF stage transistors Q1a, Q1b, Q1c, Q1d can be selected to give the targeted R value. Thus, FIGS. 8 and 9 show the input impedance varying over different bias currents.

[0043] ​​​​​​​​​​​​​​​​​A signal amplifier 100 having a plurality of switching amplifying branches each of which can be made active is illustrated. The signal amplifier 100 includes a gain stage 104 including a plurality of switchable amplifying branches each of which can be made active. One or more of the active amplifying branches are targeted, arranged, or desired to provide an adjustment to the input impedance. Similarly, FIGS. 8 and 9 illustrate a signal amplifier 100 including a variable gain stage 104 configured to provide a plurality of gain levels. The plurality of gain levels result in different input impedance values presented to each signal by the variable gain stage 104. The variable gain stage 104 includes a plurality of switchable amplifying branches each of which can be made active. One or more of the active amplifying branches are targeted, arranged, or desired to provide an adjustment to each input impedance value. A gain stage 104 including a plurality of switchable amplifying branches each of which can be made active is included. One or more of the active amplifying branches are targeted, arranged, or desired to provide an adjustment to the input impedance. One or more of the active amplifying branches are targeted, arranged, or desired to provide an adjustment to the input impedance. Similarly, FIGS. 8 and 9 illustrate a signal amplifier 100 including a variable gain stage 104 configured to provide a plurality of gain levels. A signal amplifier 100 including a variable gain stage 104 configured to provide a plurality of gain levels is illustrated. The plurality of gain levels result in different input impedance values presented to each signal by the variable gain stage 104. The variable gain stage 104 includes a plurality of switchable amplifying branches each of which can be made active. One or more of the active amplifying branches are targeted, arranged, or desired to provide an adjustment to each input impedance value. One or more of the active amplifying branches are targeted, arranged, or desired to provide an adjustment to each input impedance value.

[0044] FIG. 10 shows a plot of Cgs / gm as a function of different gain modes (e.g., depending on Idd). For an RF stage transistor (e.g., FET), the value of Cgs changes relatively little compared to gm with a change in supply voltage. Therefore, it is appropriate to approximate that Cgs remains substantially fixed while gm decreases with a decrease in Idd. This is represented as a solid line decreasing with an increase in supply voltage in the plot. Since R is equal to Ls*gm / Cgs, it can be advantageous to arrange the impedance value Ls such that R remains substantially fixed at the target value Y. This is shown in FIG. 11. Here, the target impedance value Ls is plotted as a function of supply voltage and gain mode. To achieve the targeted impedance value Y, the impedance value Ls For an RF stage transistor (e.g., FET), the value of Cgs changes relatively little compared to gm with a change in supply voltage. Therefore, it is appropriate to approximate that Cgs remains substantially fixed while gm decreases with a decrease in Idd. This is represented as a solid line decreasing with an increase in supply voltage in the plot. Since R is equal to Ls*gm / Cgs, it can be advantageous to arrange the impedance value Ls such that R remains substantially fixed at the target value Y. This is shown in FIG. 11. Here, the target impedance value Ls is plotted as a function of supply voltage and gain mode. To achieve the targeted impedance value Y, the impedance value Ls is plotted as a function of supply voltage and gain mode. To achieve the targeted impedance value Y, the impedance value Ls is plotted as a function of supply voltage and gain mode. To achieve the targeted impedance value Y, the impedance value Ls is equal to Y*Cgs / gm. This is illustrated by the solid line in the plot. For example, a typical target value for Y is 50 Ω.

[0045] The actual impedance changes as a function of the gain mode (e.g., increases as the gain increases), so an undesirable gap occurs between the actual R value at the input and the target R value (e.g., the value that reduces or minimizes signal degradation). Thus, described herein is an impedance adjustment circuit that includes a scalable impedance block configured to provide a constant actual value R. The scalable impedance block can be configured to scale the source impedance (Ls) to change gm such that the actual R value remains substantially fixed. The scalable impedance block includes a switch having inductive elements configured to provide scaled inductive values for different gain modes. By scaling Ls, the change in gm is compensated to achieve the target value of the actual R value. To vary the value of Ls as a function of the gain mode, a scalable impedance block coupled to the source of the RF stage transistor can be provided. FIG. 12 illustrates an example of a scalable impedance block 104 that acts as an impedance adjustment circuit. The scalable impedance block 104 includes inductive elements Zs1, Zs2, Zs3, Zs4 added to the signal amplifier 10 that can be switched using switches S1, S2, S3. For example, in the first gain mode (G0), switch S1

[0046] becomes active, and the impedance of the scalable impedance block 104 is provided by the inductive element Zs1. Similarly, in the second gain mode (G1), the switch S2 becomes active, and the impedance of the scalable impedance block 104 is provided by the inductive elements Zs1 and Zs2. Further, in the third gain mode (G2), the switch S3 becomes active, and the impedance of the scalable impedance block 10 4 is provided by the inductive elements Zs1, Zs2, and Zs3. In the fourth gain mode (G3), all of the switches S1 to S3 are deactivated, and the impedance of the scalable impedance block 104 is provided by the inductive elements Zs1, Zs2, Zs 3, and Zs4. Thus, the impedance can be scaled along with the conversion of the gain mode. For example, as the gain or supply voltage increases, the impedance can increase, so that the change in the impedance is compensated to obtain a substantially constant target impedance at the input ( IN) of the signal amplifier 10.

[0047] In the examples described herein, the impedance adjustment circuit is described to generally cancel or compensate for the described effects. It will be understood that such effects may or may not be known. By utilizing one or more features of the present disclosure, operating parameters such as the impedance in the LNA can be configured to any profile (substantially flat profile), with or without knowledge of such uncompensated effects.

[0048] Accordingly, FIG. 12 includes a variable gain stage configured to provide multiple gain levels The signal amplifier 10 is illustrated. Multiple gain levels are presented to each signal by a variable gain stage resulting in different input impedance values. The variable gain stage includes a scalable impedance block 104 having a plurality of switchable inductors . The plurality of switchable inductors are configured to become active to impart a target adjustment to each input impedance value .

[0049] Products, modules, devices, and architectures

[0050] FIG. 13 shows that in some embodiments, some or all of the LNA 100 having one or more of the features described herein can be implemented on a semiconductor die 200. Such a die may include a substrate 202. At least a portion of the impedance adjustment circuit 104 can be implemented on the substrate 202 .

[0051] FIGS. 14 and 15 show that in some embodiments, some or all of the LNA 100 having one or more of the features described herein can be implemented in a packaged module 300 . Such a module may include a package substrate 302 configured to receive a plurality of components such as one or more dies and one or more passive components .

[0052] In some implementations, an architecture, device, and / or circuit having one or more of the features described herein can be included in an RF device such as a wireless device. Such an architecture, device, and / or circuit can be implemented directly in a wireless device, in one or more modular forms, or in certain combinations thereof. In some embodiments . In this context, such a wireless device can include, for example, a mobile phone, a smartphone, a handheld wireless device without a telephone function, a wireless tablet, a wireless router, a wireless access point, a wireless base station, etc. Despite being described in the context of a wireless device, it is understood that one or more features of the present disclosure can also be implemented in other RF systems such as a base station. Figure 16 depicts a wireless device example 1300 having one or more advantageous features described herein. In some embodiments, an LNA having one or more features described herein can be implemented at each of one or more locations in such a wireless device. For example, in some embodiments, such advantageous features can be implemented in a module such as a diversity reception (DRx) module 1308 having one or more low noise amplifiers (LNAs). Figure 16 depicts a wireless device example 1300 having one or more advantageous features described herein. In the context of one or more modules having one or more features described herein, such a module is generally depicted by a dashed enclosure 1306 (which can be implemented as a front-end module) and a diversity receiver (DRx) module 1308 (which can be implemented as a front-end module). Referring to Figure 16, a plurality of power amplifiers (PAs) 1382 can each receive an RF signal from a transceiver 1304. The transceiver 1304 can be configured and operated to generate an RF signal to be amplified and transmitted, and to process the received signal. .

[0053] Figure 16 depicts a wireless device example 1300 having one or more advantageous features described herein. In some embodiments, an LNA having one or more features described herein can be implemented at each of one or more locations in such a wireless device. For example, in some embodiments, such advantageous features can be implemented in a module such as a diversity reception (DRx) module 1308 having one or more low noise amplifiers (LNAs). Figure 16 depicts a wireless device example 1300 having one or more advantageous features described herein. In the context of one or more modules having one or more features described herein, such a module is generally depicted by a dashed enclosure 1306 (which can be implemented as a front-end module) and a diversity receiver (DRx) module 1308 (which can be implemented as a front-end module). .

[0054] Figure 16 depicts a wireless device example 1300 having one or more advantageous features described herein. In the context of one or more modules having one or more features described herein, such a module is generally depicted by a dashed enclosure 1306 (which can be implemented as a front-end module) and a diversity receiver (DRx) module 1308 (which can be implemented as a front-end module). Referring to Figure 16, a plurality of power amplifiers (PAs) 1382 can each receive an RF signal from a transceiver 1304. The transceiver 1304 can be configured and operated to generate an RF signal to be amplified and transmitted, and to process the received signal. .

[0055] [[ID=??]] Referring to Figure 16, a plurality of power amplifiers (PAs) 1382 can each receive an RF signal from a transceiver 1304. The transceiver 1304 can be configured and operated to generate an RF signal to be amplified and transmitted, and to process the received signal. Figure 16 depicts a wireless device example 1300 having one or more advantageous features described herein. The transceiver 1304 transmits data and / or voice signals appropriate for the user to the transceiver 1304. a baseband subsystem 130 configured to provide conversion between an RF signal suitable for 5. The transceiver 1304 also interacts with the wireless device 1300. communicating with a power management component 1307 configured to manage power for operation purposes; Such power management may also be performed on the baseband subsystem 1305 as well as the modules. The operation of modules 1306 and 1308 may also be managed.

[0056] The baseband subsystem 1305 processes the audio and video signals provided to and received from the user. and / or a user interface 1301 to facilitate various inputs and outputs of data. The baseband subsystem 1305 is also shown connected to the wireless device. Memory 1 configured to facilitate operation and / or provide information storage for the user. 303. The memory 1303 is configured to store data and / or instructions. will be done.

[0057] In the example wireless device 1300, the output of the PA 1382 is The amplified and filtered signals are then matched and routed to each duplexer 1386. The filtered signals are routed through a switching network 1309 for transmission. The duplexer 1360 may be routed to the next antenna 1360. The antenna 1386 allows a common antenna (e.g., primary antenna 1360) to be used for transmitting. In FIG. 16, the received signal is 13. The variable gain amplifier assembly 1310a provides the features and benefits of the variable gain amplifier shown. is shown to be rotated. The DRx module 1308 also includes a similar variable gain amplifier assembly 1310b.

[0058] In the wireless device example 1300, the signal received by the primary antenna 1360 can be transmitted to the variable gain amplifier 1310a of the front end module 1306. The variable gain amplifier 1310a may include an impedance adjustment circuit 1320. The variable gain amplifier 13 10a is configured to receive a plurality of signals at the input section 1311 and output a plurality of processed signals at the output section 1319. The variable gain amplifier 1310a is configured to amplify the signal at least partially based on the gain mode and, at least partially, to provide an adjustment to the input impedance by the impedance adjustment circuit 1320 based on the gain mode so as to give. This can be done to reduce or eliminate power loss by fixing the LNA input impedance to transmit maximum power over a plurality of gain modes so as to. The impedance adjustment circuit 1320 can be configured to improve the receive NF performance by reducing or minimizing impedance mismatches from previous signal processing stages so as to. The impedance adjustment circuit 1320 can be configured to maintain the performance of the LNA front-end filter by reducing or eliminating impedance mismatch with the LNA circuit so as to. so as to. The impedance adjustment circuit 1320 can be configured to improve the receive NF performance by reducing or minimizing impedance mismatches from previous signal processing stages so as to. The impedance adjustment circuit 1320 can be configured to maintain the performance of the LNA front-end filter by reducing or eliminating impedance mismatch with the LNA circuit so as to. so as to. so as to.

[0059] The wireless device also includes a diversity antenna 1370 and a diversity receiver module 1308 that receives signals from the diversity antenna 1370. The diversity receiver module 1308 is a variable gain in the front-end module 1306 so as to. It includes a variable gain amplifier 1310b similar to the amplifier 1310a. The diversity receiver module 1308 and the variable gain amplifier 1310b process the received signal and send the processed signal to the transceiver 1304. In some embodiments, a diplexer, a triplexer, or other multiplexer or filter assembly can be included here as described between the diversity antenna 1370 and the diversity receiver module 1370 as described herein. between the diversity antenna 1370 and the diversity receiver module 1370.

[0060] A number of other wireless device configurations can also utilize one or more of the features described herein . For example, it is not necessary for the wireless device to be a multi-band device. Another example is that the wireless device can include additional antennas such as diversity antennas, as well as additional connection features such as Wi-Fi, Bluetooth®, and GPS .

[0061] One or more features of the present disclosure can be implemented with various cellular frequency bands described herein . Examples of such bands are listed in Table 1. It is understood that at least some of the bands can be divided into sub-bands. It is also understood that one or more features of the present disclosure can be implemented with frequency ranges that do not have the designations as in the example of Table 1. The terms radio frequency (RF) and radio frequency signal are understood to refer to signals including at least the frequencies listed in Table 1 . 1.

Table 1

[0062] ​​​​This disclosure describes various features, but none of them, alone, is involved in the benefits described herein. It should be understood that the various features described herein can be combined, modified, or omitted, as will be apparent to those skilled in the art. Combinations and sub-combinations other than those specifically described herein will also be apparent to those skilled in the art and are intended to form part of this disclosure. Various methods are described herein in connection with the steps and / or phases of various flowcharts. It should be understood that, in many cases, certain steps and / or phases can be combined together so as to perform a number of steps and / or phases shown in the flowchart as a single step and / or phase. Also, certain steps and / or phases can be broken down into additional sub-components that can be performed separately. In some examples, the order of steps and / or phases can be rearranged, and certain steps and / or phases can be completely omitted. Also, the methods described herein are open-ended such that additional steps and / or phases can be performed to those shown and described herein. Some aspects of the systems and methods described herein can advantageously be implemented, for example, using computer software, hardware, firmware, or any combination of computer software, hardware, and firmware. The computer software can be computer-executable code stored on a computer-readable medium (e.g., a non-transitory computer-readable medium) that performs the functions described herein at runtime.

[0063] hardware, and firmware. The computer software can be computer-executable code stored on a computer-readable medium (e.g., a non-transitory computer-readable medium) that performs the functions described herein at runtime. ​​​​​​​​​​​​​​​ may be included. In some embodiments, the computer-executable code is executed by one or more general-purpose computer processors. Those skilled in the art will recognize, in light of the present disclosure, that any feature or function that can be implemented using software executed on a general-purpose computer can also be implemented using different combinations of hardware, software, or firmware. For example, such modules can be implemented entirely in hardware using a combination of integrated circuits. Alternatively or additionally, such features or functions can be implemented entirely or partially using a dedicated computer designed to perform the specific functions described herein, rather than a general-purpose computer. Multiple distributed computing devices can be substituted for any one of the computing devices described herein. In such distributed embodiments, the functionality of one computing device is distributed (e.g., across a network). Some functions are performed at each of the distributed computing devices. Some embodiments can be described with reference to examples of equations, algorithms, and / or flowcharts. These methods can be implemented using computer program instructions executable on one or more computers. These methods can also be implemented as separate computer program products, or as a component of an apparatus or system. In this regard, each step of the flowchart

[0064]

[0065] ​​​​​​​​​​​​​​​, algorithms, blocks or steps, and combinations thereof, can be implemented by hardware, f irmware, and / or software including one or more computer program instructions embodied in computer-readable program code logic. As will be appreciated, any such computer program instructions can be loaded onto one or more computers including, without limitation, a general purpose computer or a special purpose computer, or other programmable processing apparatus. The computer program instructions executed in a computer or other programmable processing device implement the functions specified in the formulas, algorithms and / or flowcharts. Each formula, algorithm and / or block in the flowchart implements a specified function or step, or a special purpose hardware base computer system that performs a combination of special purpose hardware and computer-readable program code logic means. It will also be understood that it can be implemented. Furthermore, computer program instructions such as those embodied in computer-readable program code logic can also be stored in a computer-readable memory (e.g., a non-transitory computer-readable medium). One or more computers or other programmable processing devices are directed to function in a particular manner. The instructions stored in the computer-readable memory implement the functions specified in the blocks of the flowchart. The computer program instructions also cause a series of operational steps to be performed in one or more computers or other programmable computing devices, for a computer implementation process chart. Each formula, algorithm and / or block in the flowchart implements a specified function or step, or a special purpose hardware base computer system that performs a combination of special purpose hardware and computer-readable program code logic means. It will also be understood that it can be implemented. Furthermore, computer program instructions such as those embodied in computer-readable program code logic can also be stored in a computer-readable memory (e.g., a non-transitory computer-readable medium). One or more computers or other programmable processing devices are directed to function in a particular manner. The instructions stored in the computer-readable memory implement the functions specified in the blocks of the flowchart. The computer

[0066] program instructions also cause a series of operational steps to be performed in one or more computers or other programmable computing devices, for a computer implementation process Furthermore, computer program instructions such as those embodied in computer-readable program code logic can also be stored in a computer-readable memory (e.g., a non-transitory computer-readable [[ID=2,8]]medium). One or more computers or other programmable processing devices are directed to function in a particular manner. The instructions stored in the computer-readable memory implement the functions specified in the blocks of the flowchart. The computer program instructions also cause a series of operational steps to be performed in one or more computers or other programmable computing devices, for a computer implementation process chart. The instructions stored in the computer-readable memory implement the functions specified in the blocks of the flowchart. The computer program instructions also cause a series of operational steps to be performed in one or more computers or other programmable computing devices, for a computer implementation process chart. The instructions stored in the computer-readable memory implement the functions specified in the blocks of the flowchart. The computer One or more computers or other programmable computing devices to effect can also be loaded. In a computer or other programmable processing apparatus the instructions executed provide steps for implementing the functions specified in the flowchart form, algorithm and / or blocks.

[0067] Some or all of the methods and tasks described herein can be performed and fully automated by a computer system. The computer system may, in some cases, include a number of separate computers or computing devices (such as physical servers, workstations, storage arrays, etc.) that communicate and interoperate via a network to perform the described functions. Such computing devices typically include a processor (or multiple processors) that executes program instructions or modules stored in a memory or other non-transitory computer-readable storage medium or device. The various functions disclosed herein can be embodied in such program instructions. However, some or all of the disclosed functions can alternatively be implemented in an application-specific circuit group of the computer system (such as an ASIC or FPGA). If the computer system is a multiple computing device, these devices may be co-located but need not be. The results of the disclosed methods and tasks can be permanently stored by changing a physical storage

[0068] Throughout this specification and the claims, unless the context clearly dictates otherwise words such as "comprising", "including" and the like are to be construed in an inclusive sense opposed to an exclusive or exhaustive sense, that is to say as meaning "including but not limited to". Generally the word "coupled" as used herein refers to two or more elements which may be either directly connected or connected through one or more intervening elements. Additionally, the words "here", "above", "below" and words of similar import, when used in this application, refer to the entire application and not to any particular, distinct part of the application. Where context permits, the singular words in the above detailed description of a given embodiment using the singular or plural may each include the plural or singular respectively. The words "or" and "and / or" when referring to a list of two or more items cover all of the following interpretations of that word. Namely any item in the list, all items in the list, and any combination of items in the list. The word "exemplary" as used herein means solely "serving as an example, instance or illustration". Any implementation described herein as "exemplary" is not necessarily to be construed as

[0069] preferred or advantageous over other implementations. The present disclosure is not intended to be limited to the implementations shown herein. Various modifications to the implementations described in this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations without departing It is not limited to the method and system. The various embodiments described above can be combined to provide further embodiments. Therefore, the novel methods and systems described herein can be embodied in various other forms. Further, various omissions, substitutions, and changes in the form of the methods and systems described herein can be made without departing from the spirit of the present disclosure. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the present disclosure. ​

Claims

**Claim 1** An amplifier for signals having an input impedance that varies over different bias currents, comprising: a gain stage including a plurality of switchable amplification branches each of which can be made active, wherein one or more of the active amplification branches provide a target adjustment to the input impedance. An amplifier. **Claim 2** The amplifier according to claim 1, wherein each of the plurality of switchable amplification branches includes a switching transistor and an RF stage transistor. **Claim 3** In a first gain mode, a first plurality of the RF stage transistors are made active, in a second gain mode lower than the first gain mode, a second plurality of the RF stage transistors are made active, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode. The amplifier according to claim 2. **Claim 4** An amplifier for signals, comprising a variable gain stage configured to provide a plurality of gain levels, wherein the plurality of gain levels result in different input impedance values presented to each signal by the variable gain stage, the variable gain stage including a plurality of switchable amplification branches each of which can be made active, and one or more of the active amplification branches provide a target adjustment to each input impedance value. An amplifier. **Claim 5** The amplifier according to claim 4, wherein each of the plurality of switchable amplification branches includes a switching transistor and an RF stage transistor. **Claim 6** In a first gain mode, a first plurality of the RF stage transistors are made active, in a second gain mode lower than the first gain mode, a second plurality of the RF stage transistors are made active, and the number of active RF stage transistors in the second gain mode is less than that in the first gain mode. The amplifier according to claim 5. **Claim 7** An amplifier for signals, comprising a variable gain stage configured to provide a plurality of gain levels, wherein the plurality of gain levels result in different input impedance values presented to each signal by the variable gain stage, the variable gain stage including a scalable impedance block having a plurality of switchable inductive elements, and the plurality of switchable inductive elements are configured to be made active to provide a target adjustment to each input impedance value. An amplifier. **Claim 8** ​ ​ ​ ​ ​ ​ ​ ​ ​ The scalable impedance block is configured to increase the inductance when the gain level decreases, for the amplifier of claim 7. **Claim 9** The scalable impedance block is coupled to the source of the RF stage transistor of the variable gain stage, for the amplifier of claim 7. **Claim 10** A radio frequency (RF) amplifier, comprising: An input node, An output node, A gain stage including a plurality of switchable amplification branches each of which can be activated, and wherein one or more of the active amplification branches provide a target adjustment to the input impedance, for the RF amplifier. **Claim 11** The RF amplifier of claim 10, wherein the RF amplifier is a low noise amplifier (LNA). **Claim 12** The RF amplifier of claim 11, wherein the LNA is implemented in a cascode configuration having an input stage and a cascode stage. **Claim 13** The RF amplifier of claim 10, wherein the target adjustment to the input impedance at each of the plurality of gain settings is selected to provide an approximately constant impedance at the input node. **Claim 14** The RF amplifier of claim 10, wherein the plurality of transistors are configured such that one transistor operates at a lowest gain setting and additional transistors operate for each of the increased gain settings. **Claim 15** A method of amplifying a signal, comprising: Configuring a gain stage to be one of a plurality of selected gain settings, wherein at least some of the gain settings result in different impedances presented to the signal, and Adjusting the impedance presented to the signal by the gain stage for the selected gain setting, wherein the adjusted impedance is configured to provide a target constant value of the impedance at the input over the plurality of gain settings. **Claim 16** The method of claim 15, wherein the gain stage is part of a low noise amplifier (LNA). **Claim 17** The method of claim 15, wherein the adjusted impedance results in an approximately constant impedance between the plurality of gain settings. **Claim 18** The method of claim 15, wherein adjusting the impedance includes adjusting one or more inductances coupled to the source of the RF stage transistor of the gain stage. **Claim 19** ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ Adjusting the impedance includes operating a plurality of transistors that are electrically in parallel and each transistor has an associated switch for selectively activating an associated transistor The method of claim 15.

20. Operating the plurality of transistors includes performing a switching operation at the drain of each transistor to control the operation of the transistor. The method of claim 19.

21. A semiconductor die having a radio frequency (RF) circuit, comprising: a substrate; and an RF amplifier mounted on the substrate. The RF amplifier includes a gain stage including a plurality of switchable amplification branches that can each be activated, and one or more of the active amplification branches provide a target adjustment to the input impedance.

22. The semiconductor die of claim 21, wherein the substrate includes a silicon on insulator (SOI) substrate.

23. The semiconductor die of claim 21, wherein the RF amplifier is a low noise amplifier (LNA).

24. A radio frequency (RF) module, comprising: a package substrate configured to receive a plurality of components; and an RF amplifier mounted on the package substrate. The RF amplifier includes a gain stage including a plurality of switchable amplification branches that can each be activated, and one or more of the active amplification branches provide a target adjustment to the input impedance.

25. The RF module of claim 24, wherein the RF amplifier is mounted on a semiconductor die attached to the package substrate.

26. The RF module of claim 24, wherein the RF amplifier is a low noise amplifier (LNA).

27. The RF module of claim 24, wherein the RF module is a diversity reception (DRx) module.

28. A wireless device, comprising: an antenna configured to receive at least a radio frequency (RF) signal; an RF amplifier communicating with the antenna; and a transceiver. The RF amplifier includes a gain stage including a plurality of switchable amplification branches that can each be activated, and one or more of the active amplification branches provide a target adjustment to the input impedance to provide a target phase, and the transceiver amplifies the RF signal according to the target phase from the RF amplifier. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ A wireless device configured to perform the processing. **Claim 29** The wireless device is a mobile phone configured to include different gains in a reception operation. The wireless device of claim 28.

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