Optoelectronic semiconductor component and production method

Abstract

To provide an area-optimized optoelectronic semiconductor component.SOLUTION: An optoelectronic semiconductor component (16) includes: a laminate (9) comprising at least one side surface (9A), a first main surface (9B) and a second main surface (9C); first contact means (12) arranged at the first main surface and provided for electric contact connection of a first semiconductor region (4) of the laminate; second contact means (17) arranged at the second main surface and provided for electric contact connection of a second semiconductor region (5) of the laminate, the second contact means having beam transmission characteristics; an electrically conductive edge layer (11) arranged on the laminate and extending from the second contact means over the side surface as far as the first main surface; and a first dielectric layer (10) arranged between the edge layer and the laminate, the second main surface not being covered by the first dielectric layer.SELECTED DRAWING: Figure 11B

Description

Technical Field

[0001] Disclosed herein are optoelectronic semiconductor devices and methods for manufacturing the same. The optoelectronic semiconductor device is, for example, a flip chip.

[0002] In a flip chip, charge carriers of a first conductivity type and a second conductivity type are generally supplied and distributed below the semiconductor layer of the flip chip, i.e., not on the outer surface. For the contact connection of the semiconductor layer above the active region, wiring changes in the components are required. To enable electrical access to the semiconductor layer, flip chips using etched stop holes are known. However, this reduces the area efficiency of the flip chip.

[0003] In the present invention, the problem to be solved is to provide an optoelectronic semiconductor device optimized in terms of area. Another problem to be solved is to provide a method for manufacturing an optoelectronic semiconductor device optimized in terms of area.

[0004] These problems are solved, inter alia, by an optoelectronic semiconductor device having the characteristic configuration of the independent claims and a method for manufacturing an optoelectronic semiconductor device.

[0005] According to at least one embodiment of the optoelectronic semiconductor device, the optoelectronic semiconductor device includes a stack having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and an active region disposed between the first semiconductor region and the second semiconductor region. For example, the first semiconductor region is a p-type doped region and the second semiconductor region is an n-type doped region. Further, the active region is preferably configured to generate an electromagnetic beam.

[0006] Furthermore, the laminate includes at least one side surface that defines the laminate in the lateral direction, a first main surface, and a second main surface opposite the first main surface, and the first main surface and the second main surface are each disposed obliquely with respect to the side surface, preferably neither parallel nor perpendicular. In particular, the first main surface is the surface of the laminate disposed on the surface of the first semiconductor region, and the second main surface is the surface of the laminate disposed on the surface of the second semiconductor region. Preferably, most of the generated beam exits from the semiconductor element on the surface of the second main surface.

[0007] The laminate may be the thickest layer of the optoelectronic semiconductor element. For example, the laminate may constitute 50% of the thickness of the optoelectronic semiconductor element. This thickness substantially represents the dimension in the direction perpendicular to the main extension plane of the semiconductor element.

[0008] Furthermore, the optoelectronic semiconductor element includes first contact means disposed on the first main surface and provided for electrical contact connection of the first semiconductor region, second contact means disposed on the second main surface and provided for electrical contact connection of the second semiconductor region and being beam transmissive, and a conductive edge layer disposed in the laminate and extending from the second contact means through the side surface to the first main surface.

[0009] The edge layer may continue with the laminate in at least some regions in the lateral direction, i.e., on at least one side surface.

[0010] Furthermore, the edge layer may have an end region disposed on the second main surface and having a lateral dimension corresponding to the thickness of the conductive edge layer. The lateral dimension corresponding to the thickness is understood to be an equivalent value or the same value, and also a value up to 2 times, particularly up to 1.5 times. For example, an equivalent value or the same value is achieved when the edge layer and the second main surface are perpendicular, whereas a larger value is obtained when the angle is smaller, particularly when the angle is greater than 30° and less than 90°.

[0011] For example, the edge layer can be configured without bending or curving on the second major surface. Therefore, the edge layer can be conformally disposed on at least one side surface.

[0012] In particular, the edge layer enables electrical contact connection of the second semiconductor region on the surface of the first major surface.

[0013] Preferably, the second semiconductor region is disposed on the front surface provided for beam emission, and the first semiconductor region is disposed on the back surface of the optoelectronic semiconductor device opposite to the front surface.

[0014] Furthermore, the optoelectronic semiconductor device includes a first dielectric layer disposed between the edge layer and the laminate, and the second major surface is not covered by the first dielectric layer. In particular, the first dielectric layer electrically insulates the p-n junction of the active region. The first dielectric layer may be composed of only one layer. Alternatively, the first dielectric layer may have a plurality of layers, particularly layers with alternating refractive indices. In this case, the first dielectric layer may additionally have a mirror function.

[0015] Target materials for the first dielectric layer include oxide compounds and nitride compounds, such as AlxOy, SiOx, SixNy, NbOx, TiOx, HfOx, TaOx, AlxNy, and TixNy, etc., as well as organic polymers, such as parylene, BCB, silicone, siloxane, photoresist, spin-on glass, organic-inorganic hybrid materials, epoxides, and acryl, etc.

[0016] The first dielectric layer may continue with the laminate in at least a partial region in the lateral direction, that is, on at least one side surface.

[0017] Furthermore, the first dielectric layer may have an end region disposed on the second main surface and having a lateral dimension corresponding to the thickness of the first dielectric layer. The lateral dimension corresponding to the thickness is understood to be an equivalent value or the same value, and also a value up to twice, particularly up to 1.5 times. For example, an equivalent value or the same value is achieved when the first dielectric layer and the second main surface are perpendicular, whereas when the angle is smaller, particularly when the angle is greater than 30° and smaller than 90°, a larger value is obtained.

[0018] For example, the first dielectric layer can be configured without bending or curving on the second main surface. Therefore, the first dielectric layer can be disposed conformally on at least one side surface.

[0019] According to at least one embodiment, the second contact means is in contact with the first dielectric layer.

[0020] The active region may include a series of individual layers, and these individual layers constitute a quantum well structure, particularly a single quantum well structure (SQW) or a multiple quantum well structure (MQW).

[0021] Furthermore, the first semiconductor region and the second semiconductor region may have one or more semiconductor layers. For the semiconductor layers in the semiconductor region, materials based on nitride semiconductors, phosphide semiconductors, or arsenide semiconductors are targeted. "Based on nitride semiconductors, phosphide semiconductors, or arsenide semiconductors" in this context means that the semiconductor layer contains Al n Ga m In 1-n-m N, Al n Ga m In 1-n-m P or Al n Ga m In 1-n-mIt contains As, where 0 ≦ n ≦ 1, 0 ≦ m ≦ 1 and n + m ≦ 1 hold. This material does not necessarily have a mathematically exact composition that conforms to the above formula. Rather, this material may have one or more doping materials and Al n Ga m In 1-n-m N material, Al n Ga m In 1-n-m P material or Al n Ga m In 1-n-m As material and additional constituent components that do not substantially change the characteristic physical properties of the material. However, for the sake of clarity, even if the above formula may be partially replaced by a small amount of another material, only the important constituent components of the crystal lattice (Al, Ga, In, P or As) are included.

[0022] According to at least one embodiment, the second major surface is not substantially covered by an edge layer, that is, within the framework of normal manufacturing tolerances. The edge layer preferably does not protrude beyond the second major surface on the surface of the second major surface facing away from the laminate. In other words, the edge layer preferably does not protrude vertically beyond the second major surface. Particularly preferably, the edge layer terminates flush with the second major surface. This may be the case where, due to manufacturing, the edge layer is deposited on the laminate before the second major surface is exposed and is removed together when the second major surface is exposed.

[0023] According to at least one embodiment, the second semiconductor region includes a contact layer disposed on the second major surface and formed of a semiconductor material, and the second contact means is at least partially directly disposed on the contact layer. In particular, the contact layer is a semiconductor layer doped at a high concentration.

[0024] In an advantageous embodiment, the second contact means comprises or consists of at least one of the following materials, namely TCO, metal, semiconductor, graphene.

[0025] "TCO" is understood to refer to a transparent conductive oxide (abbreviated as "TCO"). TCO is a transparent, conductive material, typically a metal oxide, such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide, or indium tin oxide (ITO), etc. In addition to divalent metal oxygen compounds such as ZnO, SnO2, or In2O3, trivalent metal oxygen compounds such as Zn2SnO4, CdSnO3, ZnSnO3, MgIn2O4, GaInO3, Zn2In2O5, or In4Sn3O 12 , or a mixture of different transparent conductive oxides also belongs to the group of TCO. Furthermore, TCO does not necessarily have to correspond to a stoichiometric composition and may be p-doped or n-doped.

[0026] Preferably, the second contact means is a layer deposited on the second main surface. The second contact means may be a uniform layer, especially a uniform layer when it is formed from TCO, or a structured layer when it is formed from a metal, for example. For example, the second contact means may be formed as a metal grid or an inverse metal grid.

[0027] In particular, the second main surface is covered by the second contact means by at least 20%, preferably at least 50%, and particularly preferably at least 80%.

[0028] According to at least one embodiment, one or more sides of the laminate are at least mostly covered by an edge layer. Preferably, all sides of the laminate are completely covered by the edge layer.

[0029] In a preferred embodiment, a mirror surface portion of the laminate is formed by the edge layer. Thereby, advantageously, the beam generated by the active region can be deflected towards the second main surface. At this time, the edge layer can contain a metal or be composed of a metal, and particularly Rh, Al, Cr, Ti, Pt, W, Au, and Ni are targeted as the metal.

[0030] According to at least one embodiment, the edge layer comprises or consists of at least one of the following materials: a TCO, a metal, graphene.

[0031] According to at least one embodiment, the optoelectronic semiconductor element can be electrically connected from the outside on the surface of the first main surface by means of the first contact means and the edge layer. Here, the first main surface is partially covered by the edge layer, and in this case, the edge layer is used as a contact pad of the second conductivity type. In this case, the edge layer and the second contact means may be formed from different materials. In particular, the first contact means comprises or consists of a metal or a metal compound.

[0032] Furthermore, the optoelectronic semiconductor element may have third contact means arranged on the first main surface. The third contact means is preferably used as a contact pad of the second conductivity type and is conductively connected to the edge layer. The edge layer and the third contact means may be formed from different materials. In particular, the third contact means comprises or consists of a metal or a metal compound. The optoelectronic semiconductor element can be electrically connected from the outside on the surface of the first main surface by means of the first contact means and the third contact means.

[0033] The means for electrical contact connection of the first semiconductor region and the second semiconductor region are arranged outside the laminate, so that no area is "consumed" for the contact connection, and thus the area efficiency can be improved. Furthermore, the semiconductor element can be scaled by making contact connections externally. In particular, the semiconductor element has no vias.

[0034] Furthermore, it is also possible for the semiconductor element not to have a support.

[0035] In a possible variant form, the optoelectronic semiconductor device has a second dielectric layer disposed in the edge layer, the second dielectric layer insulating the edge layer outwardly on the first major surface. Further, the edge layer can be electrically insulated outwardly by the second dielectric layer on at least one side surface. In particular, for the second dielectric layer, the materials mentioned for the first dielectric layer are applicable.

[0036] According to at least one embodiment, the optoelectronic semiconductor device can be electrically connected externally on two opposite surfaces using first contact means and second contact means. Here, the second contact means is used as a contact pad of the second conductivity type.

[0037] According to a preferred embodiment, the laminate is configured in a mesa type, and the second major surface is larger than the first major surface. The beam emission is particularly performed on the side of the larger major surface.

[0038] The second major surface may be configured to be flat. Alternatively, the second semiconductor region can have structural elements on the second major surface or can be roughened, for example, to improve beam output coupling. Further, the semiconductor device may particularly have an output coupling structure disposed on the second major surface to improve beam output coupling.

[0039] Various different embodiments are applicable to the first contact means used as a contact pad of the first conductivity type and the edge layer or the third contact means used as a contact pad of the second conductivity type.

[0040] For example, the first contact means can be arranged at the center of the first main surface and can be entirely surrounded by the edge layer or the third contact means. Further, the first contact means can be arranged on the edge side, and only a part of the peripheral side surface can be surrounded by the edge layer or the third contact means. Further, the first contact means and the third contact means can be arranged side by side on the first main surface. At least the first dielectric layer is arranged between them for electrical insulation. Further, for electrical insulation, the first dielectric layer and the second dielectric layer may be arranged between them.

[0041] The method described next is suitable for the manufacture of one or more optoelectronic semiconductor devices of the type described above. Accordingly, the characteristic configurations described in relation to the semiconductor device can also be used in the method, and vice versa.

[0042] According to at least one embodiment of a method for manufacturing at least one optoelectronic semiconductor device of the type described above, the method comprises the following steps, namely, - preparing a semiconductor wafer including a support and a semiconductor layer series arranged on the support; - producing at least one laminate by forming at least one recess in the semiconductor wafer starting from the surface of the semiconductor layer series facing away from the support; - depositing a first dielectric layer on the semiconductor wafer so as to cover the laminate with the first dielectric layer; - depositing a conductive layer provided for forming the edge layer on the first dielectric layer; - exposing the second main surface of the laminate, removing the regions of the first dielectric layer and the second semiconductor region in a common step; and including.

[0043] Preferably, the above method steps are performed in the order shown. This particularly means depositing an edge layer on the first dielectric layer before exposing the second main surface. Further, the region of the edge layer is removed when the second main surface is exposed. In particular, when the second main surface is exposed, the region of the edge layer is removed so that the edge layer does not protrude beyond or terminate flush with the second main surface on the side of the second main surface facing away from the laminate.

[0044] The support is preferably a growth substrate on which a semiconductor layer sequence is epitaxially grown. In particular, a second semiconductor region is grown on the support and a first semiconductor region is grown in the second semiconductor region. When exposing the second main surface, in particular, the region of the second semiconductor region is removed.

[0045] In a preferred embodiment of the above method, the step of exposing the second main surface fragments a plurality of laminates. This is particularly done by thinning the semiconductor wafer from the support side to at least one recess.

[0046] Preferably, polishing and / or etching and / or laser lift-off methods are used to expose the second main surface.

[0047] Depending on the above method or the structure of the semiconductor device, contact connections in the second semiconductor region can be produced without using conventional photolithography process steps.

[0048] Optoelectronic semiconductor devices are particularly suitable for video walls, projectors and high-power components.

[0049] Further advantages, advantageous embodiments and developments will become apparent from the examples described below in connection with the drawings.

Brief Description of the Drawings

[0050]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11A

Figure 11B

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17A

Figure 17B

Figure 18A

Figure 18B

[0051] In the embodiments and the drawings, the same elements, elements of the same kind, or elements of the same action may each be assigned the same reference numeral. The plurality of elements shown and the ratio of their mutual sizes cannot necessarily be regarded as to scale, rather, in order to be better represented and / or better understood, individual elements may be exaggerated and shown large.

[0052] Figure 1 shows the first step of a method for manufacturing an optoelectronic semiconductor device according to a first embodiment, where a semiconductor wafer 1 is prepared having a semiconductor layer stack 2 and a support 3 on which the semiconductor layer stack 2 is deposited. The semiconductor layer stack 2 includes a first semiconductor region 4 of a first conductivity type, a second semiconductor region 5 of a second conductivity type, and an active region 6 disposed between the first semiconductor region 4 and the second semiconductor region 5. The first semiconductor region 4 follows the second semiconductor region 5 in the vertical direction V. For example, the first semiconductor region 4 is a p-type doped region and the second semiconductor region 5 is an n-type doped region. Further, the support 3 is preferably a growth substrate on which the semiconductor layer stack 2 is epitaxially grown. Further, the semiconductor wafer 1 includes a contact layer 7 for electrical contact connection of the first semiconductor region 4, the contact layer 7 being disposed on the first semiconductor region 4. The contact layer 7 can be formed from a TCO and / or a metal.

[0053] Regarding the semiconductor regions 4, 5, the active region 6, and the semiconductor layers contained therein, as already described above, materials based on nitride semiconductors, phosphide semiconductors, or arsenide semiconductors are targeted. In this context, "based on nitride semiconductors, phosphide semiconductors, or arsenide semiconductors" means that the semiconductor regions 4, 5 and the active region 6 or the semiconductor layers contained therein contain n Al m Ga 1-n-m In n N, Al m Ga 1-n-m In n P, or Al m Ga 1-n-m In

[0054] FIG. 2 shows subsequent method steps for structuring the semiconductor wafer 1 in order to produce the laminate 9. In particular, in order to produce the laminate 9, a recess F is formed in the semiconductor wafer 1 from the surface of the semiconductor layer series 2 facing away from the support 3. The recess 8 may be configured in a frame shape when the semiconductor layer series 2 is viewed in plan view. Furthermore, the recess 8 may have a cross-section that tapers in the direction of the support 3. Thereby, the laminate 9 preferably has a mesa shape. The recess 8 preferably reaches at least the contact layer 5A of the second semiconductor region 5.

[0055] FIG. 3 shows the next method step of depositing a first dielectric layer 10 on the semiconductor wafer 1 on the surface of the semiconductor layer series 2 facing away from the support 3, where the laminate 9 is covered by the first dielectric layer 10. Preferably, the first dielectric layer 10 is deposited over the entire surface that defines the semiconductor wafer 1 externally on the surface of the semiconductor wafer 1 that faces away from the support 3 and is on the surface of the semiconductor layer series 2.

[0056] In particular, the side surface 9A of the laminate 9 that laterally defines the laminate 9 is completely covered by the first dielectric layer 10. Here, "laterally" refers to the lateral direction L that is inclined with respect to the vertical direction V, particularly arranged vertically. Furthermore, the first main surface 9B of the laminate 9 that is arranged obliquely with respect to the side surface 9A is completely covered by the first dielectric layer 10.

[0057] Furthermore, a dielectric layer 10 is arranged on the bottom surface 8A of the recess 8.

[0058] FIG. 4A shows another method step of depositing a conductive layer 11A on the first dielectric layer 10. In particular, by depositing and subsequently opening the conductive layer 11A over the entire surface of the dielectric layer 10, an edge layer 11 is formed that is arranged on the side surface 9A and partially on the first main surface 9B.

[0059] As shown in FIG. 4B, the dielectric layer 10 is also opened, whereby the first main surface 9B has an uncovered region. In the uncovered region, first contact means 12 provided for electrical contact connection of the first semiconductor region 4 are arranged. In particular, the first contact means 12 are formed of a metal or a metal compound and are used as contact pads of the first conductivity type.

[0060] FIG. 5 shows method steps of a method according to a second embodiment in which the dielectric layer 10 is opened before depositing the conductive layer 11A. The conductive layer 11A is deposited over the entire surface of the semiconductor wafer 1, and the conductive layer 11A is arranged directly in the opened region on the first main surface 9B. Subsequently, the conductive layer 11A is structured, whereby an edge layer 11 arranged on the side surface 9A of the laminate 9 and first contact means 12 arranged on the first main surface 9B are produced from the conductive layer 11A.

[0061] The conductive layer 11A may be composed of one layer or multiple layers and may contain TCO and / or metal and / or graphene. Correspondingly, the edge layer 11 and the first contact means 12 may be composed of one layer or multiple layers and may contain TCO and / or metal and / or graphene.

[0062] FIG. 6 shows method steps of a method according to a third embodiment in which a filling 13 is arranged in the recess 8 to stabilize the semiconductor wafer 1 after producing the edge layer 11. For the filling 13, for example, a plastic material is targeted.

[0063] FIG. 7 shows another method step of arranging an intermediate support 14, for example a plastic support, on the side of the composite body comprising the semiconductor wafer 1 and the additionally deposited layers 10, 11, 12 opposite the support surface, and the intermediate support 14 is held on the composite body by an adhesive layer 15, for example by a sheet that can be peeled off by a UV beam or heat. After providing the intermediate support 14, the support 3 is removable.

[0064] FIG. 8 shows subsequent method steps for exposing the second major surface 9C of the laminate 9, which is opposite the first major surface 9B. In this case, in particular, the region of the second semiconductor region 5 up to the contact layer 5A is removed. In this case, the regions of the first dielectric layer 10 and the edge layer 11 arranged in the recess 8 are removed together, whereby, in particular, the first dielectric layer 10 and the edge layer 11 terminate flush with the second major surface 9C or, thereby, the edge layer 11 does not protrude beyond the second major surface 9C on the surface of the second major surface 9C facing away from the laminate 9.

[0065] In the vertical direction V, the semiconductor wafer 1 is thinned at least to the bottom surface 8A of the recess 8 (see FIG. 3 in this regard), thereby separating or singulating the laminates 9 joined by the second semiconductor region 5 from each other.

[0066] Preferably, the second major surface 9C is exposed using polishing and / or etching and / or laser lift-off methods.

[0067] FIG. 9 shows another method step of depositing second contact means 17 provided for electrical contact connection of the second semiconductor region 5 on the second major surface 9C. In this case, the second contact means 17 protrudes laterally beyond the second major surface 9C, whereby the second contact means 17 contacts the first dielectric layer 10 and the edge layer 11.

[0068] The second contact means 17 may preferably comprise or be composed of at least one of the following materials: TCO, metal, semiconductor, graphene. Preferably, the second contact means 17 is a uniform or structured layer deposited on the second major surface 9C. In particular, the second major surface is covered by the second contact means 9C by at least 20%, preferably at least 50%, particularly preferably at least 80%.

[0069] FIG. 10 shows, for example, another method step in which the intermediate support 14 is partially or completely peeled off by the action of a UV beam or heat (indicated by the arrow), whereby at least a part of the optoelectronic semiconductor element 16 is no longer firmly attached to the intermediate support 14 or is only weakly attached thereto.

[0070] FIG. 11A shows another method step in which the optoelectronic semiconductor element 16 is moved using a transfer device 18, for example, a suction nozzle or a punching machine.

[0071] FIG. 11B shows an optoelectronic semiconductor element 16 that can be manufactured using the method according to the first or third embodiment. Therefore, the characteristic configurations described in connection with the method can also be applied to the optoelectronic semiconductor element 16, and vice versa.

[0072] The optoelectronic semiconductor element 16 includes a stack 9 having a first semiconductor region 4 of a first conductivity type, a second semiconductor region 5 of a second conductivity type, and an active region 6 disposed between the first semiconductor region and the second semiconductor region. The active region 6 is configured to emit an electromagnetic beam, particularly in the visible, ultraviolet, or infrared spectral region. Further, the stack 9 includes a plurality of side surfaces 9A that laterally define the stack 9, a first main surface 9B, and a second main surface 9C opposite the first main surface 9B. The first main surface 9B and the second main surface 9C are each disposed obliquely, particularly not perpendicular, to the side surfaces 9A.

[0073] Furthermore, the optoelectronic semiconductor element 16 includes a first contact means 12 that is in contact with or disposed on the first main surface 9B and is provided for electrical contact connection of the first semiconductor region 4, and a second contact means 17 that is in contact with or disposed on the second main surface 9C and is provided for electrical contact connection of the second semiconductor region 5 and is beam transmissive.

[0074] Furthermore, the optoelectronic semiconductor element 16 includes a conductive edge layer 11 disposed on the laminate 9, the conductive edge layer 11 extending from the second contact means 17 through the side surface 9A to the first main surface 9B. The edge layer 11 has an end region 11B disposed on the second main surface 9C and having a lateral dimension b1 corresponding to the thickness d1 of the conductive edge layer 11. The lateral dimension b1 corresponding to the thickness d1 is understood to be an equivalent value or the same value, and also a value up to twice, particularly up to 1.5 times. For example, an equivalent value or the same value is achieved when the edge layer 11 and the second main surface 9C are perpendicular, while a larger value is obtained when the angle is smaller, particularly when the angle is greater than 30° and less than 90°.

[0075] For example, the edge layer 11 can be configured on the second main surface 9C without bending or curving. Accordingly, the edge layer 11 can be disposed conformally on the side surface 9A.

[0076] Preferably, the edge layer 11 forms a mirror surface portion of the laminate 9. Thereby, advantageously, the beam generated by the active region 6 can be deflected toward the second main surface 9C. In this case, the edge layer 11 can preferably contain a metal or be composed of a metal, and particularly targeted metals are Rh, Al, Cr, Ti, Pt, W, Au, and Ni.

[0077] Furthermore, the optoelectronic semiconductor element 16 has a first dielectric layer 10 disposed between the edge layer 11 and the laminate 9, where the second main surface 9C is not covered by the first dielectric layer 10.

[0078] Preferably, all side surfaces 9A of the laminate 9 are completely covered by the dielectric layer 10 and the edge layer 11.

[0079] The first dielectric layer 10 has an end region 10A disposed on the second main surface 9C, and the end region 10A has a lateral dimension b2 corresponding to the thickness d2 of the first dielectric layer 10. The lateral dimension b2 corresponding to the thickness d2 is understood to be an equivalent value or the same value, and also a value up to twice, particularly up to 1.5 times. For example, the equivalent value or the same value is achieved when the dielectric layer and the second main surface 9C are perpendicular, while in the case of a smaller angle, particularly when the angle is greater than 30° and less than 90°, a larger value is obtained.

[0080] For example, the first dielectric layer 10 can be configured on the second main surface 9C without bending or curving. Therefore, the first dielectric layer 10 can be disposed conformally on at least one side surface 9C.

[0081] Due to the edge layer 11, even though the second contact means 17 is disposed on the front surface 16B of the semiconductor element 16, an electrical contact connection can be made to the second semiconductor region 5 or the semiconductor element 16 at its back surface 16A. The first contact means 12 is also disposed on the back surface 16A, whereby the optoelectronic semiconductor element 16 can be electrically connected externally by the first contact means 12 and the edge layer 11 on the surface of the first main surface 9B or at its back surface 16A. This is because the first main surface 9B is partially covered by the edge layer 11, and at this time, the edge layer 11 is used as a contact pad of the second conductivity type.

[0082] The optoelectronic semiconductor element 16 shown in FIG. 11B is a flip chip. The means 11, 12 for electrical contact connection of the first semiconductor region 4 and the second semiconductor region 5 are disposed outside the laminate 9, whereby no area is "consumed" for the contact connection, and thus the area efficiency can be improved compared to a conventional flip chip. Furthermore, the semiconductor element 16 can be scaled by making an external contact connection.

[0083] 12 shows a method step or an optoelectronic semiconductor component 16 according to a fourth embodiment. In contrast to the embodiment shown in FIG. 11B, the second main surface 9C is not configured flat. Instead, the second semiconductor region 5 has structural elements 19, in particular to improve the radiation output coupling. To enable the production of the structural elements 19, the recesses 8 reach the regions of the second semiconductor region 5 that are arranged between the contact layer 5A and the carrier 3 (see FIG. 2 in this regard), and are configured deep enough so that the regions to be structured have a sufficient thickness for structuring.

[0084] 13 shows a method step or an optoelectronic semiconductor component 16 according to a fifth embodiment, in which the optoelectronic semiconductor component 16 has an outcoupling structure 20 arranged on the second main surface 9C, in particular for improving the radiation outcoupling.

[0085] The output coupling structure 20 can be produced by, for example, applying a beam-transmitting layer made of a dielectric material with a particularly adapted refractive index, for example Nb2O5, and having a thickness of 0.5 μm to 1.5 μm to the second main face 9C or the second contact means 17 and structuring it, whereby it has a number of structural elements 19.

[0086] For example, to stabilize the semiconductor wafer 1, a filler 13 can be placed in the recess 8, which is also removed when the semiconductor wafer 1 is thinned.

[0087] Based on Figures 14 to 16, different options for forming the first contact means 12 and the edge layer 11 on the rear surface will be explained.

[0088] For example, the first contact means 12 can be arranged at the center of the first main surface and can be entirely surrounded by the edge layer 11. Here, the dielectric layer 10 is arranged therebetween as an electrical insulating portion (see FIG. 14). The first contact means 12 can be configured, for example, in a circular shape. Here, the dielectric layer 10 can have an annular shape.

[0089] Furthermore, it is possible that the first contact means 12 is arranged on the edge side and thus shifted from the center, and only a part of the peripheral side surface is surrounded by the edge layer 11 (see FIG. 15). Here, the first contact means 12 can be configured, for example, in an elliptical shape. Here, the dielectric layer 10 can have a parabolic shape.

[0090] In particular, when manufacturing the combined body, the first contact means 12 of two adjacent elements 16 can be arranged on the lateral edge 16C facing the adjacent element 16 respectively. Thereby, advantageously, when manufacturing the first contact means 12, the conductive layers of two adjacent elements 16 can be opened in one step. By arranging the contact means 12 on the edge side, the series connection of two semiconductor elements 16 is also facilitated.

[0091] As shown in FIG. 16, the opening in the conductive layer does not need to terminate at the lateral edge 16C of the element 16 as in the case of the embodiment shown in FIG. 15, and can extend to the conductive layer of the adjacent element 16. Thereby, the edge layer 11 of the element 16 retreats from two lateral edges 16C facing each other.

[0092] While the optoelectronic semiconductor element 16 shown in FIGS. 11B, 12, and 13 is a flip chip, an optoelectronic semiconductor element 16 that can be electrically connected externally on two opposite surfaces using the first contact means 12 and the second contact means 17 is described in connection with FIG. 17. Here, the second contact means 17 is used as a contact pad of the second conductivity type.

[0093] The optoelectronic semiconductor element 16 has a second dielectric layer 22 disposed on the edge layer 11, which insulates the edge layer 11 outwardly on the first main surface 9B or the back surface 16A, thereby preventing the edge layer 11 from being exposed on the back surface 16A. Further, the edge layer 11 is electrically insulated outwardly by the second dielectric layer 22 on the side surface 9A.

[0094] In this embodiment (see FIG. 17B), the first contact means 12 covers most of the first main surface 9B and preferably forms a mirror surface portion on the back surface 16A.

[0095] FIG. 18 shows another embodiment in which the optoelectronic semiconductor element 16 similarly (see FIG. 17) has a second dielectric layer 22 disposed on the edge layer 11, which electrically insulates the edge layer 11 outwardly on the first main surface 9B or the back surface 16A. Further, the edge layer 11 is electrically insulated outwardly by the second dielectric layer 22 on the side surface 9A. In this embodiment, the optoelectronic semiconductor element 16 is a flip chip.

[0096] Unlike the embodiment shown in FIG. 17, the second dielectric layer 22 has an opening in which third contact means 21 for electrical contact connection of the edge layer 11 is disposed on the back surface 16A. The edge layer 11 and the third contact means 21 are preferably fabricated in two separate steps and can thus be formed from different materials.

[0097] The first contact means 12 and the third contact means 21 are arranged side by side on the first main surface 9B. Thereby, the optoelectronic semiconductor element 16 can be electrically connected from the outside by the first contact means 12 and the third contact means 21 on the surface of the first main surface 9B or the back surface 16A.

[0098] The invention is not limited to the description based on the examples, but rather includes each and every novel feature and each and every combination of features, including in particular each and every combination of features in the claims, even if the feature or combination itself is not explicitly set out in the claims or examples.

[0099] This patent specification claims priority from German Patent Application No. 102020124258.1, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0100] 1. Semiconductor wafer 2. Semiconductor layer sequence 3 Support 4. First semiconductor region of first conductivity type 5. Second semiconductor region of second conductivity type 5A Contact layer of second semiconductor region 6 Active area 7 Contact layer 8 recess 8A Bottom of the recess 9 Laminate 9A side 9B First main surface 9C Second main surface 10 First dielectric layer 10A end area 11 Edge Layer 11A conductive layer 11B End area 12 First contact means 13 Filling 14 Intermediate support 15 Bonding layer 16 Optoelectronic semiconductor devices 16A back 16B Front 16C Side Edge 17 Secondary contact means 18 Transfer device 19 Structural element 20 Output coupling structure 21 Third contact means 22 Second dielectric layer L Lateral direction V Vertical direction b1, b2 Lateral dimensions d1, d2 Thickness

Claims

1. An optoelectronic semiconductor device (16), wherein the optoelectronic semiconductor device (16) includes a laminate (9), and the laminate (9) includes a first semiconductor region (4) of a first conductivity type, a second semiconductor region (5) of a second conductivity type, an active region (6) disposed between the first semiconductor region (4) and the second semiconductor region (5), at least one side surface (9A) that laterally defines the laminate (9), and a first main surface (9B) and a second main surface (9C) opposite to the first main surface (9B), wherein the first main surface (9B) and the second main surface (9C) are each obliquely disposed with respect to the side surface (9A). The optoelectronic semiconductor device (16) further includes a first contact means (12) disposed on the first main surface (9B), the first contact means (12) being provided for electrical contact connection of the first semiconductor region (4), a second contact means (17) disposed on the second main surface (9C), the second contact means (17) being provided for electrical contact connection of the second semiconductor region (5) and being beam transmissive, and a conductive edge layer (11) disposed in the laminate (9), the conductive edge layer (11) extending from the second contact means (17) through the side surface (9A) to the first main surface (9B) and having an end region (11B) disposed on the second main surface (9C). The end region (11B) has a lateral dimension (b1) corresponding to the thickness (d1) of the conductive edge layer (11). The optoelectronic semiconductor device (16) further includes a first dielectric layer (10) disposed between the edge layer (11) and the laminate (9), and the second main surface (9C) is not covered by the first dielectric layer (10). Optoelectronic semiconductor device (16).

2. An optoelectronic semiconductor device (16), wherein the optoelectronic semiconductor device (16) includes a laminate (9), and the laminate (9) includes a first semiconductor region (4) of a first conductivity type, a second semiconductor region (5) of a second conductivity type, an active region (6) disposed between the first semiconductor region (4) and the second semiconductor region (5), at least one side surface (9A) that laterally defines the laminate (9), and It includes a first main surface (9B) and a second main surface (9C) on the side opposite to the first main surface (9B), and the first main surface (9B) and the second main surface (9C) are each disposed obliquely with respect to the side surface (9A). The optoelectronic semiconductor element (16) further includes a first contact means (12) disposed on the first main surface (9B), the first contact means (12) being provided for electrical contact connection of the first semiconductor region (4), a second contact means (17) disposed on the second main surface (9C), the second contact means (17) being provided for electrical contact connection of the second semiconductor region (5) and being beam transmissive, and a conductive edge layer (11) disposed in the laminate (9), the conductive edge layer (11) extending from the second contact means (17), through the side surface (9A), to the first main surface (9B), and a first dielectric layer (10) disposed between the edge layer (11) and the laminate (9). The second main surface (9C) is not covered by the first dielectric layer (10), and the first dielectric layer (10) terminates flush with the second main surface (9C). Optoelectronic semiconductor element (16).

3. The optoelectronic semiconductor element (16) according to claim 1 or 2, wherein the edge layer (11) is conformally disposed on at least one of the side surfaces (9A).

4. The optoelectronic semiconductor element (16) according to any one of claims 1 to 3, wherein the second main surface (9C) is not covered by the edge layer (11).

5. The optoelectronic semiconductor element (16) according to any one of claims 1 to 4, wherein the edge layer (11) does not protrude beyond the second main surface (9C) on the surface of the second main surface (9C) facing away from the laminate (9).

6. The optoelectronic semiconductor element (16) according to any one of claims 1 to 5, wherein the second semiconductor region (5) has a contact layer (5A) disposed on the second main surface (9C) and formed of a semiconductor material, and the second contact means (17) is at least partially directly disposed on the contact layer (5A).

7. The optoelectronic semiconductor device (16) according to any one of claims 1 to 6, wherein the second contact means (17) comprises or consists of at least one of the following materials: TCO, metal, semiconductor, graphene.

8. The optoelectronic semiconductor device (16) according to any one of claims 1 to 7, wherein the second contact means (17) is a layer deposited on the second major surface (9C).

9. The optoelectronic semiconductor device (16) according to any one of claims 1 to 8, wherein at least most of one or more of the side surfaces (9A) are covered by the edge layer (11).

10. The optoelectronic semiconductor device (16) according to any one of claims 1 to 9, wherein the edge layer (11) forms a mirror surface portion of the laminate (9).

11. The optoelectronic semiconductor device (16) according to any one of claims 1 to 10, wherein the edge layer (11) comprises or consists of at least one of the following materials: TCO, metal, graphene.

12. The optoelectronic semiconductor device (16) according to any one of claims 1 to 11, wherein the optoelectronic semiconductor device (16) is a second dielectric layer (22) disposed in the edge layer (11), and the second dielectric layer (22) electrically insulates the edge layer (11) outwardly on the first major surface (9B).

13. The optoelectronic semiconductor device (16) according to any one of claims 1 to 12, wherein the optoelectronic semiconductor device (16) can be electrically connected externally on two opposite surfaces using the first contact means (12) and the second contact means (17).

14. The optoelectronic semiconductor device (16) according to any one of claims 1 to 13, wherein the optoelectronic semiconductor device (16) can be electrically connected externally on the surface of the first major surface (9B) using the first contact means (12) and the edge layer (11), or using the first contact means (12) and the third contact means (21).

15. The laminate (9) is mesa-shaped, and the second main surface (9C) is larger than the first main surface (9B). The optoelectronic semiconductor device (16) according to any one of claims 1 to 14.

16. The second semiconductor region (5) has a structural element (19) on the second main surface (9C). The optoelectronic semiconductor device (16) according to any one of claims 1 to 15.

17. The optoelectronic semiconductor device (16) has an output coupling structure (20) disposed on the second main surface (9C). The optoelectronic semiconductor device (16) according to any one of claims 1 to 16.

18. A method of manufacturing at least one optoelectronic semiconductor device (16) according to any one of claims 1 to 17, the method comprising: Preparing a semiconductor wafer (1) including a support (3) and a semiconductor layer stack (2) disposed on the support (3); Producing at least one laminate (9) by forming at least one recess (8) in the semiconductor wafer (1) starting from the surface of the semiconductor layer stack (2) facing away from the support (3); Depositing a first dielectric layer (10) on the semiconductor wafer (1) so as to cover the laminate (9) with the first dielectric layer (10); Depositing a conductive layer (11A) provided to form an edge layer (11) on the first dielectric layer (10); Exposing the second main surface (9C) of the laminate (9), removing the regions of the first dielectric layer (10) and the second semiconductor region (5) in a common step; A method including.

19. The method according to claim 18, wherein a plurality of laminates (9) are singulated by the step of exposing the second main surface (9C).

20. The method according to claim 18 or 19, wherein the region of the edge layer (11) is removed during the step of exposing the second main surface (9C).

21. The method according to any one of claims 18 to 20, wherein the step of exposing the second main surface (9C) is performed using polishing and / or etching and / or laser lift-off method.

Images