Nitride semiconductor device and manufacturing method for nitride semiconductor device

Abstract

To relieve the local electric field concentration in a gate layer.SOLUTION: A nitride semiconductor device 10 includes an electron transit layer 24 formed of a nitride semiconductor, an electron supply layer 26 provided on the electron transit layer 24 and formed of a nitride semiconductor whose band gap is larger than that of the electron transit layer 24, a source electrode 42 and a drain electrode 44 that are provided apart from each other on the electron supply layer 26, a gate layer 30 provided between the source electrode 42 and the drain electrode 44 on the electron supply layer 26 and formed of a nitride semiconductor including acceptor type impurities, and a gate electrode 40 provided on the gate layer 30. The gate layer 30 includes a ridge part 31 where the gate electrode 40 is disposed, and an extension part 32 that is thinner than the ridge part 31. The extension part 32 includes a crystalline layer 35 provided close to the electron supply layer 26, and an amorphous layer 36 provided on the crystalline layer 35.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device.

Background Art

[0002] Currently, the commercialization of high electron mobility transistors (HEMTs) using nitride semiconductors such as gallium nitride (GaN) is progressing. Patent Document 1 discloses an example of a normally-off HEMT using a nitride semiconductor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] In an HEMT using a nitride semiconductor, for example, when a positive voltage is applied to the gate electrode, an electric field may locally concentrate in a portion near the end of the gate electrode in the gate layer. Such local electric field concentration can cause crystal defects in the gate layer and may be a factor in reducing the gate breakdown voltage. Therefore, it is required to mitigate the local electric field concentration in the gate layer.

[0005] A nitride semiconductor device according to one aspect of the present disclosure includes an electron transport layer composed of a nitride semiconductor, an electron supply layer provided on the electron transport layer and composed of a nitride semiconductor having a larger bandgap than the electron transport layer, a source electrode and a drain electrode provided separately from each other on the electron supply layer, a gate layer provided between the source electrode and the drain electrode on the electron supply layer and composed of a nitride semiconductor containing an acceptor-type impurity, and a gate electrode provided on the gate layer. The gate layer includes a ridge portion where the gate electrode is disposed and an extending portion thinner than the ridge portion. The extending portion includes a crystalline layer provided closer to the electron supply layer and an amorphous layer provided on the crystalline layer.

Brief Description of the Drawings

[0006]

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[0007] [Detailed Description] Hereinafter, embodiments of the nitride semiconductor device in the present disclosure will be described with reference to the accompanying drawings. Note that, for the sake of simplicity and clarity of the description, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, the hatching lines may be omitted in the cross-sectional views. The accompanying drawings are merely illustrative of the embodiments of the present disclosure and should not be regarded as limiting the present disclosure.

[0008] As used in this disclosure, terms such as "first," "second," "third," etc. are used to clearly distinguish components of an object and do not rank the object. Also, the expression "at least one" used in this disclosure means one or more of a plurality of desired options. As an example, if the number of options is two, the expression "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the expression "at least one" means only one option or any combination of two or more options.

[0009] The following detailed description includes apparatuses, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely for explanatory purposes and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0010] <First Embodiment> [Schematic Overall Configuration of Nitride Semiconductor Device] With reference to FIGS. 1 to 3, the schematic overall configuration of a nitride semiconductor device 10 according to the first embodiment will be described. FIG. 1 shows a schematic plan view of an exemplary nitride semiconductor device 10 according to the first embodiment. FIG. 2 shows a schematic plan view in which a part of the internal structure of the nitride semiconductor device 10 of FIG. 1 is enlarged. FIG. 3 shows a schematic cross-sectional structure obtained by cutting the nitride semiconductor device 10 along the line F3 - F3 of FIG. 2.

[0011] As shown in FIG. 1, the nitride semiconductor device 10 includes a chip body 12. The chip body 12 is formed, for example, in a rectangular flat plate shape. Note that the Z-axis direction of the XYZ axes orthogonal to each other shown in FIG. 1 and other drawings is a direction orthogonal to the main surface (the upper surface 13 in FIG. 1) of the chip body 12. The term "plan view" used in this disclosure means viewing the nitride semiconductor device 10 from above in the Z-axis direction unless otherwise explicitly stated.

[0012] The nitride semiconductor device 10 includes at least one gate pad 14, at least one source pad 16, and at least one drain pad 18. In the example shown in FIG. 1, the nitride semiconductor device 10 includes one gate pad 14, a plurality of source pads 16, and a plurality of drain pads 18. The gate pad 14, the plurality of source pads 16, and the plurality of drain pads 18 are formed on the upper surface 13 of the chip body 12. These pads 14, 16, 18 can be used as external connection terminals of the nitride semiconductor device 10.

[0013] Each of the gate pad 14, the source pad 16, and the drain pad 18 is formed, for example, in a rectangular shape in plan view. The gate pad 14 can be arranged, for example, at one corner of the upper surface 13. Each of the source pad 16 and the drain pad 18 extends in the Y-axis direction in plan view. The source pad 16 and the drain pad 18 are alternately arranged one by one in the X-axis direction orthogonal to the Y-axis direction. Thus, it can be said that each of the source pad 16 and the drain pad 18 extends in a direction (Y-axis direction) orthogonal to the direction (X-axis direction) in which these pads 16, 18 are arranged in plan view. Note that the shape of each of the gate pad 14, the source pad 16, and the drain pad 18 in plan view can be arbitrarily changed. Also, the arrangement mode of the gate pad 14, the source pad 16, and the drain pad 18 can be arbitrarily changed.

[0014] As shown in FIG. 3, the nitride semiconductor device 10 is configured as a high electron mobility transistor (HEMT) using a nitride semiconductor. The nitride semiconductor device 10 includes a semiconductor substrate 20, a buffer layer 22 formed on the semiconductor substrate 20, an electron traveling layer 24 formed on the buffer layer 22, and an electron supply layer 26 formed on the electron traveling layer 24.

[0015] The semiconductor substrate 20 can be composed of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. In one example, the semiconductor substrate 20 is a Si substrate. The thickness of the semiconductor substrate 20 can be, for example, 200 μm or more and 1500 μm or less. Note that the Z-axis direction corresponds to the thickness direction of the semiconductor substrate 20.

[0016] The buffer layer 22 can be composed of any material that can suppress the occurrence of wafer warpage and cracks due to the mismatch in the coefficient of thermal expansion between the semiconductor substrate 20 and the electron traveling layer 24. The buffer layer 22 can include one or more nitride semiconductor layers. The buffer layer 22 includes, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 22 can be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0017] The electron traveling layer 24 is composed of a nitride semiconductor. The electron traveling layer 24 can be, for example, a GaN layer. The thickness of the electron traveling layer 24 can be, for example, 0.1 μm or more and 2 μm or less. The electron traveling layer 24 can include one or more nitride semiconductor layers. Also, in order to suppress the leakage current in the electron traveling layer 24, impurities may be introduced into a part of the electron traveling layer 24 to make the region other than the surface layer region of the electron traveling layer 24 semi-insulating. In this case, the impurity is, for example, carbon (C). The impurity concentration of the carbon is, for example, 1×10 19 cm -3 or more at the peak concentration.

[0018] The electron supply layer 26 is composed of a nitride semiconductor having a larger band gap than the electron transport layer 24. The electron supply layer 26 may be, for example, an AlGaN layer. Since the band gap increases as the Al composition increases, the electron supply layer 26, which is an AlGaN layer, has a larger band gap than the electron transport layer 24, which is a GaN layer. In one example, the electron supply layer 26 is Al x Ga 1-x N. In this case, x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the electron supply layer 26 can be, for example, 5 nm or more and 20 nm or less.

[0019] The electron transport layer 24 and the electron supply layer 26 have different lattice constants in the bulk region. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transport layer 24 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 26 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 24 and the electron supply layer 26 and the piezo-polarization caused by the compressive stress received by the hetero-junction of the electron transport layer 24, the energy level of the conduction band of the electron transport layer 24 near the hetero-junction interface between the electron transport layer 24 and the electron supply layer 26 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 28 is formed in the electron transport layer 24 at a position close to the hetero-junction interface between the electron transport layer 24 and the electron supply layer 26 (e.g., at a distance of about several nm from the interface).

[0020] The nitride semiconductor device 10 includes a gate layer 30 formed on a part of the electron supply layer 26 and a gate electrode 40 formed on the gate layer 30. The gate layer 30 is composed of a nitride semiconductor. In one example, the gate layer 30 is composed of a nitride semiconductor having a smaller band gap than the electron supply layer 26 and containing acceptor-type impurities. In one example, the gate layer 30 is GaN doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurity may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurity in the gate layer 30 is, for example, 7×1018 cm -3 1×10 or more 20 cm -3 is as follows.

[0021] The gate electrode 40 includes one or more metal layers. In one example, the gate electrode 40 may be a titanium nitride (TiN) layer. In another example, the gate electrode 40 may be composed of a first metal layer made of Ti and a second metal layer provided on the first metal layer and made of TiN. The gate electrode 40 can be composed of, for example, a material that forms a Schottky junction with the gate layer 30. An example of such a material is TiN. The thickness of the gate electrode 40 can be, for example, 50 nm or more and 200 nm or less.

[0022] The nitride semiconductor device 10 includes a passivation layer 50. The passivation layer 50 covers the electron supply layer 26, the gate layer 30, and the gate electrode 40. The passivation layer 50 can be composed of, for example, one or any combination of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). The thickness of the passivation layer 50 can be, for example, 50 nm or more and 200 nm or less, preferably 80 nm or more and 150 nm or less. The passivation layer 50 includes a source opening 50A and a drain opening 50B that respectively expose a part of the upper surface 26A of the electron supply layer 26.

[0023] The nitride semiconductor device 10 includes a source electrode 42 formed in the source opening 50A and a drain electrode 44 formed in the drain opening 50B. The source electrode 42 includes a source contact portion 42A that contacts the electron supply layer 26 through the source opening 50A. The drain electrode 44 includes a drain contact portion 44A that contacts the electron supply layer 26 through the drain opening 50B.

[0024] The source electrode 42 and the drain electrode 44 include one or more metal layers. In one example, the source electrode 42 and the drain electrode 44 may be composed of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, the source electrode 42 and the drain electrode 44 are composed of a first metal layer in contact with the electron supply layer 26, a second metal layer laminated on the second metal layer, a third metal layer laminated on the second metal layer, and a fourth metal layer laminated on the third metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

[0025] The source contact portion 42A of the source electrode 42 is filled in the source opening 50A. The source contact portion 42A makes an ohmic contact with the 2DEG 28 directly under the electron supply layer 26 through the source opening 50A. The drain contact portion 44A of the drain electrode 44 is filled in the drain opening 50B. The drain contact portion 44A makes an ohmic contact with the 2DEG 28 directly under the electron supply layer 26 through the drain opening 50B. Although not shown in the figure, the semiconductor substrate 20 is electrically connected to the source electrode 42. Thereby, a voltage of the same potential as that of the source electrode 42 is applied to the semiconductor substrate 20.

[0026] In a structure in which the gate layer 30 is formed of a nitride semiconductor containing acceptor-type impurities, when a voltage is not applied to the gate electrode 40, the 2DEG 28 in the region directly under the gate layer 30 is depleted, thereby blocking the conduction path (channel). Thereby, a normally-off type HEMT in which the gate threshold voltage becomes a positive value is realized.

[0027] The nitride semiconductor device 10 includes a field plate electrode 60 provided on the passivation layer 50. The field plate electrode 60 is electrically connected to the source electrode 42. In the example shown in FIG. 3, the field plate electrode 60 is formed integrally with the source electrode 42. That is, a part of the source electrode 42 is provided as the field plate electrode 60. Therefore, a voltage having the same potential as the source electrode 42 is applied to the field plate electrode 60. The field plate electrode 60 is also called a source field plate. The field plate electrode 60 covers the entire gate layer 30 in a plan view.

[0028] The field plate electrode 60 is separated from the drain electrode 44. The field plate electrode 60 includes an end portion 61 located between the gate layer 30 and the drain electrode 44 in a plan view. When a drain voltage is applied to the drain electrode 44 in a zero bias state where no voltage is applied to the gate electrode 40, the field plate electrode 60 serves to mitigate the electric field concentration in the vicinity of the end portion of the gate electrode 40 and in the vicinity of the end portion of the gate layer 30.

[0029] [Exemplary Planar Layout of Nitride Semiconductor Device] Next, with reference to FIG. 2, an exemplary planar layout of the HEMT structure (nitride semiconductor device 10) will be described. Note that, for clarity of illustration, the illustration of the passivation layer 50 is omitted in FIG. 2. Also, the source opening 50A, the drain opening 50B, and the field plate electrode 60 are drawn with broken lines.

[0030] As shown in FIG. 2, the nitride semiconductor device 10 includes a plurality of transistor elements each having an HEMT structure in an element region. Note that FIG. 2 shows only a plurality of transistor elements arranged in the X-axis direction, but in reality, the transistor elements can be arranged side by side in both the X-axis direction and the Y-axis direction.

[0031] The drain electrode 44 is provided for each transistor element. The drain electrode 44 extends in the Y-axis direction in a plan view. The source electrode 42 is provided, for example, so as to surround each drain electrode 44 in a plan view. As described with reference to FIG. 3, the source electrode 42 includes the field plate electrode 60. The field plate electrode 60 formed integrally with the source electrode 42 extends toward the adjacent drain electrode 44 in a plan view. In the example shown in FIG. 2, the source electrode 42 is continuously formed in the X-axis direction across a plurality of transistor elements adjacent in the X-axis direction, but may be separated into a plurality of portions in the X-axis direction.

[0032] The gate layer 30 and the gate electrode 40 are provided for each transistor element. Each gate layer 30 and each gate electrode 40 are formed in an annular shape so as to surround one of the drain electrodes 44 in a plan view.

[0033] The nitride semiconductor device 10 includes a gate wiring 72, a source wiring 74, and a drain wiring 76. The gate wiring 72, the source wiring 74, and the drain wiring 76 are formed on a first interlayer insulating layer (not shown) covering the source electrode 42 and the drain electrode 44. In the example shown in FIG. 2, each of the gate wiring 72, the source wiring 74, and the drain wiring 76 extends in the X-axis direction. The gate wiring 72, the source wiring 74, and the drain wiring 76 are arranged to be spaced apart from each other in the Y-axis direction. The gate wiring 72 is arranged at a position different from the drain electrode 44, the source opening 50A, and the drain opening 50B in the Y-axis direction. The source wiring 74 and the drain wiring 76 are arranged at positions overlapping with the drain electrode 44, the source opening 50A, and the drain opening 50B in a plan view in the Y-axis direction.

[0034] For example, the gate wiring 72 is connected to the gate electrode 40 by a gate connection conductor 73 that penetrates the first interlayer insulating layer and extends to the gate electrode 40. The source wiring 74 is connected to the source electrode 42 by a source connection conductor 75 that penetrates the first interlayer insulating layer. The drain wiring 76 is connected to the drain electrode 44 by a drain connection conductor 77 that penetrates the first interlayer insulating layer. Each of the gate connection conductor 73, the source connection conductor 75, and the drain connection conductor 77 is, for example, a via that penetrates the first interlayer insulating layer. The number of each of the gate connection conductor 73, the source connection conductor 75, and the drain connection conductor 77 can be arbitrarily changed.

[0035] For example, the gate wiring 72, the source wiring 74, and the drain wiring 76 are covered by a second interlayer insulating layer (not shown). In one example, the gate pad 14, the source pad 16, and the drain pad 18 shown in FIG. 1 are formed on the second interlayer insulating layer.

[0036] For example, the gate wiring 72 is connected to the gate pad 14 by a gate connection conductor (not shown) that penetrates the second interlayer insulating layer and extends to the gate pad 14. The source wiring 74 is connected to the source pad 16 by a source connection conductor (not shown) that penetrates the second interlayer insulating layer. The drain wiring 76 is connected to the drain pad 18 by a drain connection conductor (not shown) that penetrates the second interlayer insulating layer.

[0037] [Exemplary Structure of Gate Layer] Next, with reference to FIGS. 3 and 4, an exemplary structure of the gate layer 30 will be described. FIG. 4 shows a schematic cross-sectional structure of the gate layer 30 and its surroundings in the nitride semiconductor device 10 of FIG. 3, which is enlarged. In FIG. 3, the illustration of the source electrode 42, the passivation layer 50, and the field plate electrode 60 is omitted so as not to complicate the illustration.

[0038] As shown in FIG. 3, the gate layer 30 is located between the source contact portion 42A and the drain contact portion 44A in the X-axis direction. The gate layer 30 is separated from each of the source contact portion 42A and the drain contact portion 44A. In one example, the gate layer 30 is located closer to the source contact portion 42A than to the drain contact portion 44A.

[0039] As shown in FIG. 4, the gate layer 30 includes a ridge portion 31 and an extending portion 32 that is thinner than the ridge portion 31. In the example shown in FIG. 3, the extending portion 32 extends in the X-axis direction from each of the side surfaces 31C of the ridge portion 31 in the X-axis direction.

[0040] The ridge portion 31 corresponds to a relatively thick portion of the gate layer 30. The gate electrode 40 is in contact with the ridge portion 31. The ridge portion 31 may have a rectangular shape or a trapezoidal shape in a cross section along the XZ plane. The thickness TR of the ridge portion 31 can be, for example, 100 nm or more and 200 nm or less. The thickness TR of the ridge portion 31 can be defined by the distance in the Z-axis direction between the upper surface 31A and the lower surface 31B of the ridge portion 31. The thickness TR of the ridge portion 31 is determined in consideration of various parameters such as gate breakdown voltage.

[0041] The extending portion 32 includes an upper surface 32A and a lower surface 32B opposite to the upper surface 32A. The lower surface 32B of the extending portion 32 is in contact with, for example, the electron supply layer 26. The lower surface 32B of the extending portion 32 is continuous with the lower surface 31B of the ridge portion 31. The upper surface 32A of the extending portion 32 is disposed closer to the electron supply layer 26 than the upper surface 31A of the ridge portion 31 in the Z-axis direction.

[0042] As shown in FIGS. 3 and 4, the extending portion 32 includes a source-side extending portion 33 and a drain-side extending portion 34. The source-side extending portion 33 and the drain-side extending portion 34 extend in directions opposite to each other with respect to the ridge portion 31. More specifically, the source-side extending portion 33 extends from the ridge portion 31 toward the source opening 50A of the passivation layer 50. It can also be said that the source-side extending portion 33 extends from the ridge portion 31 toward the source electrode 42. The drain-side extending portion 34 extends from the ridge portion 31 toward the drain opening 50B of the passivation layer 50. It can also be said that the drain-side extending portion 34 extends from the ridge portion 31 toward the drain electrode 44.

[0043] As shown in FIG. 4, the source-side extending portion 33 includes an upper surface 33A and a lower surface 33B opposite to the upper surface 33A. The drain-side extending portion 34 includes an upper surface 34A and a lower surface 34B opposite to the upper surface 34A. The upper surface 33A of the source-side extending portion 33 and the upper surface 34A of the drain-side extending portion 34 constitute the upper surface 32A of the extending portion 32. The lower surface 33B of the source-side extending portion 33 and the lower surface 34B of the drain-side extending portion 34 constitute the lower surface 32B of the extending portion 32.

[0044] The source-side extending portion 33 may have a width WS of, for example, 100 nm or more in the direction from the ridge portion 31 toward the source opening 50A (the width direction of the gate layer 30). The width WS of the source-side extending portion 33 can be, for example, 200 nm or more and 300 nm or less. The drain-side extending portion 34 may have a width WD of, for example, 100 nm or more in the direction from the ridge portion 31 toward the drain opening 50B (the width direction of the gate layer 30). The width WD of the drain-side extending portion 34 can be, for example, 200 nm or more and 600 nm or less. In the example shown in FIG. 4, the width WD of the drain-side extending portion 34 is larger than the width WS of the source-side extending portion 33. Note that each of the width WD of the drain-side extending portion 34 and the width WS of the source-side extending portion 33 can be arbitrarily changed. In one example, the width WD of the drain-side extending portion 34 and the width WS of the source-side extending portion 33 may be equal to each other. In one example, the width WS of the source-side extending portion 33 may be larger than the width WD of the drain-side extending portion 34.

[0045] The thickness of each of the extending portions 32 can be, for example, 60 nm or less. The thickness of each of the extending portions 32 may be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness of each of the extending portions 32 can be, for example, 10 nm or more. In one example, the thickness of each of the extending portions 32 may be greater than 30 nm and 40 nm or less. Here, the thickness of the extending portion 32 can be defined by the distance in the Z-axis direction between the upper surface 32A and the lower surface 32B of the extending portion 32.

[0046] More specifically, the thickness TS of the source-side extending portion 33 can be, for example, 60 nm or less. The thickness TS of the source-side extending portion 33 may be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness TS of the source-side extending portion 33 can be, for example, 10 nm or more. The thickness TD of the drain-side extending portion 34 can be, for example, 60 nm or less. The thickness TD of the drain-side extending portion 34 may be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness TD of the drain-side extending portion 34 can be, for example, 10 nm or more. In one example, the thickness TS of the source-side extending portion 33 and the thickness TD of the drain-side extending portion 34 are equal to each other. Here, the thickness TS of the source-side extending portion 33 can be defined by the average value of the distance in the Z-axis direction between the upper surface 33A and the lower surface 33B of the source-side extending portion 33. The thickness TD of the drain-side extending portion 34 can be defined by the average value of the distance in the Z-axis direction between the upper surface 34A and the lower surface 34B of the drain-side extending portion 34. Note that the thickness TS of the source-side extending portion 33 and the thickness TD of the drain-side extending portion 34 can also be referred to as the thickness of the extending portion 32.

[0047] As shown in FIG. 4, the extending portion 32 includes a crystalline layer 35 provided closer to the electron supply layer 26 and an amorphous layer 36 provided on the crystalline layer 35. The amorphous layer 36 may be referred to as an amorphous layer, for example.

[0048] The crystalline layer 35 is a layer including the lower surface 32B of the extending portion 32. That is, the crystalline layer 35 is in contact with the electron supply layer 26. The crystalline layer 35 is a layer including a crystal structure in which crystals having a regular spatial arrangement of atoms or molecules, for example, are aggregated. The crystalline layer 35 is provided over the entire extending portion 32 in plan view.

[0049] The amorphous layer 36 is a layer including the upper surface 32A of the extending portion 32. The amorphous layer 36 is a layer spaced apart from the electron supply layer 26 in the Z-axis direction. The amorphous layer 36 is a layer including a structure in which atoms or molecules, for example, are aggregated without forming a crystal having a regular spatial arrangement. The amorphous layer 36 is provided over the entire extending portion 32 in plan view. That is, the amorphous layer 36 is provided over the entire crystalline layer 35 in plan view. Also, it can be said that the amorphous layer 36 is provided over the entire upper surface 32A of the extending portion 32. Since the upper surface 32A of the extending portion 32 is constituted by the amorphous layer 36, the upper surface 32A is a rough surface rougher than the upper surface 31A of the ridge portion 31.

[0050] More specifically, the source-side extending portion 33 includes a source-side crystalline layer 35S provided closer to the electron supply layer 26 and a source-side amorphous layer 36S provided on the source-side crystalline layer 35S.

[0051] The source-side crystalline layer 35S is a layer including the lower surface 33B of the source-side extending portion 33. The source-side crystalline layer 35S is in contact with the electron supply layer 26. The source-side crystalline layer 35S is formed over the entire source-side extending portion 33 in plan view. The source-side crystalline layer 35S constitutes the crystalline layer 35 of the extending portion 32.

[0052] The source-side amorphous layer 36S is a layer including the upper surface 33A of the source-side extending portion 33. The source-side amorphous layer 36S is a layer spaced apart from the electron supply layer 26 in the Z-axis direction. The source-side amorphous layer 36S is provided over the entire source-side extending portion 33 in plan view. That is, the source-side amorphous layer 36S is provided over the entire source-side crystalline layer 35S in plan view. Also, it can be said that the source-side amorphous layer 36S is provided over the entire upper surface 33A of the source-side extending portion 33. For this reason, the upper surface 33A is a rough surface rougher than the upper surface 31A of the ridge portion 31. The source-side amorphous layer 36S constitutes the amorphous layer 36 of the extending portion 32.

[0053] The drain-side extending portion 34 includes a drain-side crystalline layer 35D provided closer to the electron supply layer 26 and a drain-side amorphous layer 36D provided on the drain-side crystalline layer 35D. The drain-side crystalline layer 35D is a layer including the lower surface 34B of the drain-side extending portion 34. That is, the drain-side crystalline layer 35D is in contact with the electron supply layer 26. The drain-side crystalline layer 35D is formed over the entire drain-side extending portion 34 in plan view. The drain-side crystalline layer 35D constitutes the crystalline layer 35 of the extending portion 32.

[0054] The drain-side amorphous layer 36D is a layer including the upper surface 34A of the drain-side extending portion 34. The drain-side amorphous layer 36D is a layer spaced apart from the electron supply layer 26 in the Z-axis direction. The drain-side amorphous layer 36D is provided over the entire drain-side extending portion 34 in plan view. That is, the drain-side amorphous layer 36D is provided over the entire drain-side crystalline layer 35D in plan view. Also, it can be said that the drain-side amorphous layer 36D is provided over the entire upper surface 34A of the drain-side extending portion 34. For this reason, the upper surface 34A is a rough surface rougher than the upper surface 31A of the ridge portion 31.

[0055] The thickness T1 of the crystalline layer 35 can be 20 nm or less. The thickness T1 of the crystalline layer 35 can be 15 nm or less, or 10 nm or less. Also, the thickness T1 of the crystalline layer 35 can be 5 nm or more. Here, the thickness T1 of the crystalline layer 35 can be defined by the average value of the distance in the Z-axis direction between the lower surface 32B of the extending portion 32 and the boundary between the crystalline layer 35 and the amorphous layer 36.

[0056] More specifically, the thickness TSA of the source-side crystalline layer 35S can be 20 nm or less. The thickness TSA of the source-side crystalline layer 35S can be 15 nm or less, or 10 nm or less. Also, the thickness TSA of the source-side crystalline layer 35S can be 5 nm or more. Also, the thickness TDA of the drain-side crystalline layer 35D can be 20 nm or less. The thickness TDA of the drain-side crystalline layer 35D can be 15 nm or less, or 10 nm or less. Also, the thickness TDA of the drain-side crystalline layer 35D can be 5 nm or more. Here, the thickness TSA of the source-side crystalline layer 35S can be defined by the average value of the distance in the Z-axis direction between the lower surface 33B of the source-side extending portion 33 and the boundary between the source-side crystalline layer 35S and the source-side amorphous layer 36S. The thickness TDA of the drain-side crystalline layer 35D can be defined by the average value of the distance in the Z-axis direction between the lower surface 34B of the drain-side extending portion 34 and the boundary between the drain-side crystalline layer 35D and the drain-side amorphous layer 36D.

[0057] The thickness T2 of the amorphous layer 36 can be 5 nm or more. In one example, the thickness T2 of the amorphous layer 36 can be 10 nm or more, 20 nm or more, 30 nm or more, or 40 nm or more. The thickness T2 of the amorphous layer 36 may be set such that the thickness T1 of the crystalline layer 35 is a predetermined value (for example, 20 nm) or less with respect to the thickness of the extending portion 32. Here, the thickness T2 of the amorphous layer 36 can be defined by the average value of the distance in the Z-axis direction between the upper surface 32A of the extending portion 32 and the boundary between the crystalline layer 35 and the amorphous layer 36.

[0058] More specifically, the thickness TSB of the source-side amorphous layer 36S can be 5 nm or more. In one example, the thickness TSB of the source-side amorphous layer 36S can be 10 nm or more, 20 nm or more, 30 nm or more, or 40 nm or more. The thickness TSB of the source-side amorphous layer 36S may be set such that the thickness TSA of the source-side crystalline layer 35S is equal to or less than a predetermined value (for example, 20 nm) with respect to the thickness of the source-side extending portion 33. Also, the thickness TDB of the drain-side amorphous layer 36D can be 5 nm or more. In one example, the thickness TDB of the drain-side amorphous layer 36D can be 10 nm or more, 20 nm or more, 30 nm or more, or 40 nm or more. The thickness TDB of the drain-side amorphous layer 36D may be set such that the thickness TDA of the drain-side crystalline layer 35D is equal to or less than a predetermined value (for example, 20 nm) with respect to the thickness of the drain-side extending portion 34. Here, the thickness TSB of the source-side amorphous layer 36S can be defined by the average value of the distance in the Z-axis direction between the upper surface 33A of the source-side extending portion 33 and the boundary between the source-side crystalline layer 35S and the source-side amorphous layer 36S. The thickness TDB of the drain-side amorphous layer 36D can be defined by the average value of the distance in the Z-axis direction between the upper surface 34A of the drain-side extending portion 34 and the boundary between the drain-side crystalline layer 35D and the drain-side amorphous layer 36D.

[0059] In one example, the thickness TSB of the source-side amorphous layer 36S and the thickness TDB of the drain-side amorphous layer 36D may be equal to each other. Note that the thickness TSB of the source-side amorphous layer 36S and the thickness TDB of the drain-side amorphous layer 36D may be set individually. For this reason, the thickness TSB of the source-side amorphous layer 36S may be thicker than the thickness TDB of the drain-side amorphous layer 36D. In other words, the thickness TSA of the source-side crystalline layer 35S may be thinner than the thickness TDA of the drain-side crystalline layer 35D. Also, the thickness TSB of the source-side amorphous layer 36S may be thinner than the thickness TDB of the drain-side amorphous layer 36D. In other words, the thickness TSA of the source-side crystalline layer 35S may be thicker than the thickness TDA of the drain-side crystalline layer 35D.

[0060] In one example, the thickness T1 of the crystalline layer 35 may be thinner than the thickness T2 of the amorphous layer 36. In one example, the thickness T1 of the crystalline layer 35 may be thicker than the thickness T2 of the amorphous layer 36. In one example, the thickness T2 of the amorphous layer 36 may be equal to the thickness T1 of the crystalline layer 35. More specifically, in one example, the thickness TSA of the source-side crystalline layer 35S may be thinner than the thickness TSB of the source-side amorphous layer 36S. In one example, the thickness TSA of the source-side crystalline layer 35S may be thicker than the thickness TSB of the source-side amorphous layer 36S. In one example, the thickness TSB of the source-side amorphous layer 36S may be equal to the thickness TSA of the source-side crystalline layer 35S. Also, in one example, the thickness TDA of the drain-side crystalline layer 35D may be thinner than the thickness TDB of the drain-side amorphous layer 36D. In one example, the thickness TDA of the drain-side crystalline layer 35D may be thicker than the thickness TDB of the drain-side amorphous layer 36D. In one example, the thickness TDB of the drain-side amorphous layer 36D may be equal to the thickness TDA of the drain-side crystalline layer 35D.

[0061] As a first example, when the thickness of the extending portion 32 is 10 nm, the thickness T2 of the amorphous layer 36 may be 5 nm, and the thickness T1 of the crystalline layer 35 may be 5 nm. That is, the thickness T2 of the amorphous layer 36 may be equal to the thickness T1 of the crystalline layer 35. More specifically, when the thickness TS of the source-side extending portion 33 is 10 nm, the thickness TSB of the source-side amorphous layer 36S may be 5 nm, and the thickness TSA of the source-side crystalline layer 35S may be 5 nm. That is, the thickness TSB of the source-side amorphous layer 36S may be equal to the thickness TSA of the source-side crystalline layer 35S. Also, when the thickness TD of the drain-side extending portion 34 is 10 nm, the thickness TDB of the drain-side amorphous layer 36D may be 5 nm, and the thickness TDA of the drain-side crystalline layer 35D may be 5 nm. That is, the thickness TDB of the drain-side amorphous layer 36D may be equal to the thickness TDA of the drain-side crystalline layer 35D.

[0062] As a second example, when the thickness of the extending portion 32 is 30 nm, the thickness T2 of the amorphous layer 36 may be 20 nm, and the thickness T1 of the crystalline layer 35 may be 10 nm. That is, the thickness T1 of the crystalline layer 35 may be thinner than the thickness T2 of the amorphous layer 36. Also, when the thickness of the extending portion 32 is 30 nm, the thickness T2 of the amorphous layer 36 may be 15 nm, and the thickness T1 of the crystalline layer 35 may be 15 nm. That is, the thickness T2 of the amorphous layer 36 may be equal to the thickness T1 of the crystalline layer 35. Also, when the thickness of the extending portion 32 is 30 nm, the thickness T2 of the amorphous layer 36 may be 10 nm, and the thickness T1 of the crystalline layer 35 may be 20 nm. That is, the thickness T1 of the crystalline layer 35 may be thicker than the thickness T2 of the amorphous layer 36.

[0063] More specifically, when the thickness of the source-side extending portion 33 is 30 nm, the thickness TSB of the source-side amorphous layer 36S may be 20 nm, and the thickness TSA of the source-side crystalline layer 35S may be 10 nm. That is, the thickness TSA of the source-side crystalline layer 35S may be thinner than the thickness TSB of the source-side amorphous layer 36S. Also, when the thickness of the source-side extending portion 33 is 30 nm, the thickness TSB of the source-side amorphous layer 36S may be 15 nm, and the thickness TSA of the source-side crystalline layer 35S may be 15 nm. That is, the thickness TSB of the source-side amorphous layer 36S may be equal to the thickness TSA of the source-side crystalline layer 35S. Also, when the thickness of the source-side extending portion 33 is 30 nm, the thickness TSB of the source-side amorphous layer 36S may be 10 nm, and the thickness TSA of the source-side crystalline layer 35S may be 20 nm. That is, the thickness TSA of the source-side crystalline layer 35S may be thicker than the thickness TSB of the source-side amorphous layer 36S.

[0064] Further, when the thickness of the drain-side extending portion 34 is 30 nm, the thickness TDB of the drain-side amorphous layer 36D may be 20 nm, and the thickness TDA of the drain-side crystalline layer 35D may be 10 nm. That is, the thickness TDA of the drain-side crystalline layer 35D may be thinner than the thickness TDB of the drain-side amorphous layer 36D. Further, when the thickness of the drain-side extending portion 34 is 30 nm, the thickness TDB of the drain-side amorphous layer 36D may be 15 nm, and the thickness TDA of the drain-side crystalline layer 35D may also be 15 nm. That is, the thickness TDB of the drain-side amorphous layer 36D may be equal to the thickness TDA of the drain-side crystalline layer 35D. Further, when the thickness of the drain-side extending portion 34 is 30 nm, the thickness TDB of the drain-side amorphous layer 36D may be 10 nm, and the thickness TDA of the drain-side crystalline layer 35D may also be 20 nm. That is, the thickness TDA of the drain-side crystalline layer 35D may be thicker than the thickness TDB of the drain-side amorphous layer 36D.

[0065] [Method for manufacturing a nitride semiconductor device] With reference to FIGS. 5 to 15, an example of a method for manufacturing the nitride semiconductor device 10 will be schematically described. FIGS. 5 to 15 show schematic cross-sectional structures illustrating exemplary manufacturing steps of the nitride semiconductor device 10. The cross-sectional positions of FIGS. 5 to 15 are the same as the cross-sectional position of FIG. 3, for example. For ease of understanding, in FIGS. 5 to 15, components similar to those in FIG. 3 may be assigned the same reference numerals.

[0066] As shown in FIG. 5, the method for manufacturing the nitride semiconductor device 10 includes forming an electron traveling layer 24 composed of a nitride semiconductor and forming an electron supply layer 26 composed of a nitride semiconductor. The method for manufacturing the nitride semiconductor device 10 also includes forming a nitride semiconductor layer 82 on the electron supply layer 26 and forming an electrode layer 84 on the nitride semiconductor layer 82. Further, the method for manufacturing the nitride semiconductor device 10 includes forming an insulating layer 86 on the electrode layer 84.

[0067] In one example, after a buffer layer 22 is formed on a semiconductor substrate 20 which is, for example, a Si substrate, an electron transport layer 24 may be formed on the buffer layer 22. The buffer layer 22 and the electron transport layer 24 can be epitaxially grown using a Metal Organic Chemical Vapor Deposition (MOCVD) method.

[0068] Although detailed illustration is omitted, in one example, the buffer layer 22 may be a multilayer buffer layer. The multilayer buffer layer may include an AlN layer (first buffer layer) formed on the semiconductor substrate 20 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer can be formed, for example, by stacking three AlGaN layers having Al compositions of 75%, 50%, and 25% in order from the side close to the AlN layer. The electron transport layer 24 formed on the buffer layer 22 may be a GaN layer.

[0069] Next, after an electron supply layer 26 is formed on the electron transport layer 24, a nitride semiconductor layer 82 may be formed on the electron supply layer 26. The electron supply layer 26 and the nitride semiconductor layer 82 can be epitaxially grown using, for example, the MOCVD method.

[0070] While the electron transport layer 24 is a GaN layer, the electron supply layer 26 may be an AlGaN layer. Therefore, the nitride semiconductor constituting the electron supply layer 26 has a larger bandgap than the electron transport layer 24.

[0071] The nitride semiconductor layer 82 may be composed of a nitride semiconductor containing an acceptor-type impurity. In one example, a nitride semiconductor layer 82 containing an acceptor-type impurity can be formed by doping Mg during the growth of the nitride semiconductor layer 82. The nitride semiconductor layer 82 may be composed of, for example, GaN. The nitride semiconductor layer 82 is composed of a nitride semiconductor having a smaller bandgap than the electron supply layer 26. The nitride semiconductor layer 82 is a semiconductor layer constituting a gate layer 30 (see FIG. 3).

[0072] Next, an electrode layer 84 may be formed on the nitride semiconductor layer 82. The electrode layer 84 can be formed on the nitride semiconductor layer 82 by, for example, a sputtering method. The electrode layer 84 may be formed over the entire upper surface of the nitride semiconductor layer 82. The electrode layer 84 is, for example, a TiN layer. The electrode layer 84 is a metal layer that constitutes the gate electrode 40 (see FIG. 3).

[0073] Next, an insulating layer 86 may be formed on the electrode layer 84. The insulating layer 86 is formed on the electrode layer 84 by, for example, a Low-Pressure Chemical Vapor Deposition (LPCVD) method. The insulating layer 86 may be formed over the entire upper surface of the electrode layer 84. The insulating layer 86 may be formed of at least one of, for example, SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the insulating layer 86 is formed of SiN.

[0074] As shown in FIGS. 6 to 8, the method for manufacturing the nitride semiconductor device 10 includes forming a gate electrode 40. In one example, as shown in FIG. 6, a photoresist mask 88 is formed on the insulating layer 86. The photoresist mask 88 is formed on a part of the upper surface of the insulating layer 86. More specifically, the photoresist mask 88 is formed in a region on the upper surface of the insulating layer 86 where the gate electrode 40 is to be formed. Next, as shown in FIG. 7, the insulating layer 86 and the electrode layer 84 exposed from the photoresist mask 88 are removed by exposure and development using the photoresist mask 88. Thereby, the gate electrode 40 is formed. Thereafter, as shown in FIG. 8, the photoresist mask 88 is removed.

[0075] As shown in FIGS. 9 to 11, the method for manufacturing the nitride semiconductor device 10 includes forming a gate layer 30. In one example, as shown in FIG. 9, an insulating layer 90 is formed to cover a portion of the upper surface of the nitride semiconductor layer 82 that is exposed from the gate electrode 40, the side surface of the gate electrode 40, and the side and upper surfaces of the insulating layer 86. The insulating layer 90 is formed, for example, by the LPCVD method. The insulating layer 90 may be formed of at least one of, for example, SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the insulating layer 90 is formed of SiN. Here, the insulating layer 90 is an example of a "mask".

[0076] Next, as shown in FIG. 10, the entire surface of the insulating layer 90 is etched using reactive ion etching (RIE). As a result, the insulating layer 90 formed on the upper surface of the nitride semiconductor layer 82 and the upper surface of the insulating layer 86 is removed. On the other hand, the insulating layer 90 formed on the side surface of the gate electrode 40 and the side surface of the insulating layer 86 is not removed.

[0077] Next, as shown in FIG. 11, the nitride semiconductor layer 82 is etched, for example, by plasma etching. As the plasma etching, a chlorine-based (Cl2-based) gas can be used. As a result, a ridge portion 31 directly under the gate electrode 40 and the insulating layer 86 and an extending portion 32 are formed in the nitride semiconductor layer 82. The extending portion 32 includes a source-side extending portion 33 and a drain-side extending portion 34. In this way, the gate layer 30 is formed. In one example, the thickness of the extending portion 32 (the source-side extending portion 33 and the drain-side extending portion 34) is about 30 nm.

[0078] As shown in FIG. 12, the method for manufacturing the nitride semiconductor device 10 includes forming an amorphous layer 36 on the gate layer 30. In the step of forming the amorphous layer 36, surface modification of the upper surface 32A of the extending portion 32 is performed by plasma treatment using a gas of a type different from the type of gas used for the plasma etching for forming the extending portion 32. In one example, for instance, surface modification of the upper surface 32A of the extending portion 32 is performed by plasma treatment using argon (Ar) gas. Thereby, the amorphous layer 36 is formed on the extending portion 32. This treatment is called an amorphization treatment. The thickness T2 (see FIG. 4) of the amorphous layer 36 is set according to, for example, the energy of ions colliding with the upper surface 32A of the extending portion 32. That is, the amorphous layer 36 becomes thicker as the energy of ions colliding with the upper surface 32A of the extending portion 32 increases. On the other hand, due to the surface modification of the upper surface 32A of the extending portion 32, the damage to the upper surface 32A increases. As a result, the upper surface 32A of the extending portion 32 becomes a rough surface that is rougher than the upper surface 31A of the ridge portion 31.

[0079] In one example, plasma treatment is performed on the upper surface 32A of the extending portion 32 so that the thickness T2 of the amorphous layer 36 becomes, for example, 15 nm or more. That is, the amorphous layer 36 is formed so that the thickness T2 of the amorphous layer 36 becomes equal to or greater than the thickness T1 of the crystalline layer 35. More specifically, plasma treatment is performed on the upper surface 33A of the source-side extending portion 33 so that the thickness TSB of the source-side amorphous layer 36S becomes, for example, 15 nm or more. That is, the source-side amorphous layer 36S is formed so that the thickness TSB of the source-side amorphous layer 36S becomes equal to or greater than the thickness TSA of the source-side crystalline layer 35S. Also, plasma treatment is performed on the upper surface 34A of the drain-side extending portion 34 so that the thickness TDB of the drain-side amorphous layer 36D becomes, for example, 15 nm or more. That is, the drain-side amorphous layer 36D is formed so that the thickness TDB of the drain-side amorphous layer 36D becomes equal to or greater than the thickness TDA of the drain-side crystalline layer 35D. Thereafter, as shown in FIG. 13, the insulating layer 90 is removed.

[0080] As shown in FIG. 14, the method for manufacturing the nitride semiconductor device 10 includes forming a passivation layer 50. Also, as shown in FIGS. 14 and 15, the method for manufacturing the nitride semiconductor device 10 includes forming a source electrode 42, a drain electrode 44, and a field plate electrode 60.

[0081] As shown in FIG. 14, the passivation layer 50 is formed to cover the exposed portion of the electron supply layer 26 from the gate layer 30, the exposed portions of the upper surface 32A of the extending portion 32 of the gate layer 30 and the upper surface 31A of the ridge portion 31 from the gate electrode 40, and the gate electrode 40. The passivation layer 50 is formed, for example, by the LPCVD method. The passivation layer 50 may be formed of at least one of SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the passivation layer 50 is formed of SiN.

[0082] Next, a source opening 50A and a drain opening 50B that penetrate the passivation layer 50 in the Z-axis direction to expose the electron supply layer 26 are formed. The source opening 50A and the drain opening 50B are formed, for example, by etching. The source opening 50A and the drain opening 50B are each formed such that the gate layer 30 is located closer to the source opening 50A than the drain opening 50B.

[0083] Next, an electrode layer 92 is formed on the passivation layer 50. The electrode layer 92 is a metal layer that constitutes the source electrode 42, the drain electrode 44, and the field plate electrode 60. The electrode layer 92 is formed to fill each of the source opening 50A and the drain opening 50B and to be in contact with the electron supply layer 26 through the source opening 50A and the drain opening 50B. Thereby, a source contact portion 42A and a drain contact portion 44A are formed. In one example, the electrode layer 92 may contain at least one of Ti, TiN, Al, AlSiCu, and AlCu.

[0084] Next, as shown in FIG. 15, the electrode layer 92 is selectively removed by lithography and etching. Thereby, the source electrode 42, the drain electrode 44, and the field plate electrode 60 are formed from the electrode layer 92. Through the above steps, the nitride semiconductor device 10 is manufactured.

[0085] [Operation of the First Embodiment] The operation of the nitride semiconductor device 10 of the first embodiment will be described. In a HEMT, an electric field may be locally concentrated in a portion near the end of the gate electrode 40 when a positive voltage is applied to the gate electrode 40. In this regard, the gate layer 30 of the nitride semiconductor device 10 of the first embodiment includes a ridge portion 31 where the gate electrode 40 is disposed and an extending portion 32 thinner than the ridge portion 31. The extending portion 32 can mitigate local electric field concentration (hereinafter referred to as "local electric field concentration of the gate layer 30") in a portion near the end of the gate electrode 40 in the gate layer 30.

[0086] On the other hand, by providing the extending portion 32, the 2DEG 28 directly under the extending portion 32 decreases, so there is a possibility that the on-resistance of the nitride semiconductor device 10 increases. On the other hand, if the thickness of the extending portion 32 is made as thin as possible to suppress an increase in on-resistance, there is a possibility that the desired thickness of the extending portion 32 cannot be ensured due to manufacturing variations or the like. As a result, there is a possibility that relaxation of the local electric field concentration of the gate layer 30 by the extending portion 32 cannot be achieved.

[0087] In this regard, in the first embodiment, the extending portion 32 of the gate layer 30 includes a crystalline layer 35 provided closer to the electron supply layer 26 and an amorphous layer 36 provided on the crystalline layer 35. The crystalline layer 35 can mitigate local electric field concentration of the gate layer 30. Further, since the amorphous layer 36 is provided on the crystalline layer 35, the overall thickness of the gate layer 30 can be ensured. Further, the amorphous layer 36 is a layer that is less likely to contribute to the decrease in the 2DEG 28 compared to the crystalline layer 35. Thereby, compared with the case where the entire gate layer 30 is constituted by the crystalline layer 35, the decrease in the 2DEG 28 caused by the gate layer 30 becomes smaller. Thereby, while ensuring the thickness of the extending portion 32 of the gate layer 30, a decrease in the 2DEG 28 can be suppressed. Therefore, an increase in the on-resistance of the nitride semiconductor device 10 can be suppressed.

[0088] In addition, when the thickness T1 of the crystalline layer 35 is smaller than the thickness T2 of the amorphous layer 36, the thickness T1 of the crystalline layer 35 can be reduced while ensuring the thickness of the extending portion 32, so that the effect of suppressing the decrease in the 2DEG 28 can be enhanced. On the other hand, when the thickness T1 of the crystalline layer 35 is larger than the thickness T2 of the amorphous layer 36, the thickness T1 of the crystalline layer 35 that contributes to the relaxation of the electric field concentration in the portion near the end of the gate electrode 40 in the gate layer 30 can be ensured, so that the decrease in the effect of relaxing the local electric field concentration in the gate layer 30 by the crystalline layer 35 can be suppressed. Further, when the thickness T2 of the amorphous layer 36 is equal to the thickness T1 of the crystalline layer 35, the effect of relaxing the local electric field concentration in the gate layer 30 by the crystalline layer 35 and the effect of suppressing the decrease in the 2DEG 28 can be effectively balanced while ensuring the thickness of the extending portion 32.

[0089] [Effect of the First Embodiment] According to the nitride semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The nitride semiconductor device 10 includes an electron traveling layer 24 formed of a nitride semiconductor, an electron supply layer 26 provided on the electron traveling layer 24 and formed of a nitride semiconductor having a larger bandgap than the electron traveling layer 24, a source electrode 42 and a drain electrode 44 provided separately from each other on the electron supply layer 26, a gate layer 30 provided between the source electrode 42 and the drain electrode 44 on the electron supply layer 26 and formed of a nitride semiconductor containing acceptor-type impurities, and a gate electrode 40 provided on the gate layer 30. The gate layer 30 includes a ridge portion 31 where the gate electrode 40 is disposed and an extending portion 32 thinner than the ridge portion 31. The extending portion 32 includes a crystalline layer 35 provided closer to the electron supply layer 26 and an amorphous layer 36 provided on the crystalline layer 35.

[0090] According to this configuration, while ensuring the thickness of the extending portion 32 of the gate layer 30, the decrease in the 2DEG 28 caused by the extending portion 32 can be suppressed. Therefore, while relaxing the local electric field concentration in the gate layer 30, an increase in the on-resistance can be suppressed.

[0091] (1-2) The thickness T1 of the crystalline layer 35 is smaller than the thickness T2 of the amorphous layer 36. According to this configuration, the thickness T1 of the crystalline layer 35 can be reduced while ensuring the thickness of the extension portion 32. This can enhance the effect of suppressing the reduction of the 2DEG 28.

[0092] (1-3) The thickness T2 of the amorphous layer 36 is 5 nm or more. According to this configuration, the thickness T1 of the crystalline layer 35 can be reduced while ensuring the thickness of the extension portion 32. This can enhance the effect of suppressing the reduction of the 2DEG 28.

[0093] (1-4) The thickness T1 of the crystalline layer 35 is 20 nm or less. This configuration can alleviate localized electric field concentration in the gate layer 30 while maintaining the effect of suppressing the reduction of the 2DEG 28.

[0094] (1-5) The upper surface 32A of the extension portion 32 is a rough surface that is rougher than the upper surface 31A of the ridge portion 31. This configuration improves adhesion between the passivation layer 50 covering the upper surface 32A of the extension 32 and the upper surface 32A.

[0095] (1-6) A method for manufacturing the nitride semiconductor device 10 includes forming an electron transit layer 24 made of a nitride semiconductor, forming an electron supply layer 26 made of a nitride semiconductor having a larger band gap than the electron transit layer 24 on the electron transit layer 24, forming a nitride semiconductor layer 82 containing acceptor-type impurities on the electron supply layer 26 by epitaxial growth, forming a gate electrode 40 on the nitride semiconductor layer 82, and etching the nitride semiconductor layer 82 to form a gate layer 30. Forming the gate layer 30 includes forming a ridge portion 31 and an extension portion 32 that is thinner than the ridge portion 31, and forming an amorphous layer 36 in a position of the extension portion 32 that is separated from the electron supply layer 26 in the thickness direction of the extension portion 32.

[0096] According to this configuration, while ensuring the thickness of the extending portion 32 of the gate layer 30, it is possible to suppress the decrease in the 2DEG 28 caused by the extending portion 32. Therefore, while alleviating the local electric field concentration in the gate layer 30, it is possible to suppress the increase in the on-resistance.

[0097] <Second Embodiment> Referring to FIGS. 16 and 17, the nitride semiconductor device 10 of the second embodiment will be described. In the nitride semiconductor device 10 of the second embodiment, the configuration of the gate layer 30 is mainly different from that of the nitride semiconductor device 10 of the first embodiment. Hereinafter, the differences from the nitride semiconductor device 10 of the first embodiment will be described in detail, and the same reference numerals will be given to the common components as those of the nitride semiconductor device 10 of the first embodiment, and the description thereof will be omitted.

[0098] As shown in FIGS. 16 and 17, the extending portion 32 of the gate layer 30 includes an inclined portion 37 and a flat portion 38. The inclined portion 37 is provided on the base end side of the extending portion 32 in the width direction of the gate layer 30 (the X-axis direction in FIG. 16). The flat portion 38 is provided on the tip side of the extending portion 32 rather than the inclined portion 37 in the width direction of the gate layer 30. It can be said that the flat portion 38 is disposed on the side opposite to the ridge portion 31 with respect to the inclined portion 37. In the second embodiment, the source-side extending portion 33 includes a source-side inclined portion 37S and a source-side flat portion 38S. The drain-side extending portion 34 includes a drain-side inclined portion 37D and a drain-side flat portion 38D. The source-side inclined portion 37S and the drain-side inclined portion 37D constitute the inclined portion 37 of the extending portion 32. The source-side flat portion 38S and the drain-side flat portion 38D constitute the flat portion 38 of the extending portion 32. Hereinafter, in the case of the common description of the source-side inclined portion 37S and the drain-side inclined portion 37D, it will be described as the inclined portion 37. Also, in the case of the common description of the source-side flat portion 38S and the drain-side flat portion 38D, it will be described as the flat portion 38.

[0099] The inclined portion 37 includes an inclined surface 37A that slopes toward the electron supply layer 26 from the side surface 31C of the ridge portion 31 toward the flat portion 38. The inclined portion 37 is inclined such that the thickness of the inclined portion 37 gradually decreases from the side surface 31C of the ridge portion 31 toward the flat portion 38. The inclination angle of the inclined surface 37A of the inclined portion 37 with respect to the upper surface 26A of the electron supply layer 26 can be 30° or more and 80° or less. In one example, the inclination angle of the inclined surface 37A of the inclined portion 37 with respect to the upper surface 26A of the electron supply layer 26 can be 45° or less.

[0100] In one example, the inclination angle of the inclined surface 37A of the source-side inclined portion 37S with respect to the upper surface 26A of the electron supply layer 26 is equal to the inclination angle of the drain-side inclined portion 37D with respect to the upper surface 26A of the electron supply layer 26. Note that the inclination angle of the inclined surface 37A of the source-side inclined portion 37S with respect to the upper surface 26A of the electron supply layer 26 may be different from the inclination angle of the drain-side inclined portion 37D with respect to the upper surface 26A of the electron supply layer 26. In one example, the inclination angle of the inclined surface 37A of the source-side inclined portion 37S with respect to the upper surface 26A of the electron supply layer 26 may be larger than the inclination angle of the drain-side inclined portion 37D with respect to the upper surface 26A of the electron supply layer 26.

[0101] The flat portion 38 has a generally constant thickness and extends in a direction intersecting the Z-axis direction. In the cross-sectional view shown in FIG. 16, the flat portion 38 is formed in a rectangular shape. The thickness of the flat portion 38 can be, for example, 10 μm or more and 60 μm or less. The thickness of the flat portion 38 may be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness of the flat portion 38 may be greater than 30 nm and less than 40 nm.

[0102] As shown in FIG. 17 , the extension portion 32 includes a crystalline layer 35 and an amorphous layer 36, similar to the first embodiment. More specifically, similar to the first embodiment, the source-side extension portion 33 includes a source-side crystalline layer 35S and a source-side amorphous layer 36S. The drain-side extension portion 34 includes a drain-side crystalline layer 35D and a drain-side amorphous layer 36D. Hereinafter, when the source-side crystalline layer 35S and the drain-side crystalline layer 35D are described in common, they will be referred to as the crystalline layer 35. When the source-side amorphous layer 36S and the drain-side amorphous layer 36D are described in common, they will be referred to as the amorphous layer 36.

[0103] The amorphous layer 36 is provided on both the inclined portion 37 and the flat portion 38. The amorphous layer 36 is provided over the entire upper surface 38A of the flat portion 38. The amorphous layer 36 is provided over the entire inclined surface 37A of the inclined portion 37. In this manner, the amorphous layer 36 is a layer that includes the inclined surface 37A of the inclined portion 37 and the upper surface 38A of the flat portion 38. The crystalline layer 35 is provided on both the inclined portion 37 and the flat portion 38. The crystalline layer 35 is a layer that includes the lower surface 37B of the inclined portion 37 and the lower surface 38B of the flat portion 38.

[0104] In one example, the thickness T2 of the amorphous layer 36 in the inclined portion 37 is equal to the thickness T2 of the amorphous layer 36 in the flat portion 38. Here, the thickness T2 of the amorphous layer 36 in the inclined portion 37 can be defined as the average value of the distance between the inclined surface 37A of the inclined portion 37 and the boundary between the amorphous layer 36 and the crystalline layer 35 in the direction perpendicular to the inclined surface 37A.

[0105] The thickness T2 of the amorphous layer 36 in the inclined portion 37 and the thickness T2 of the amorphous layer 36 in the flat portion 38 can each be changed as desired. In one example, the thickness T2 of the amorphous layer 36 in the inclined portion 37 may be thinner than the thickness T2 of the amorphous layer 36 in the flat portion 38. In another example, the thickness T2 of the amorphous layer 36 in the inclined portion 37 may be thicker than the thickness T2 of the amorphous layer 36 in the flat portion 38.

[0106] In one example, the thickness TSA of the source-side amorphous layer 36S in the source-side flat portion 38S is equal to the thickness TDA of the drain-side amorphous layer 36D in the drain-side flat portion 38D. In one example, the thickness TSB of the source-side amorphous layer 36S in the source-side inclined portion 37S is equal to the thickness TDB of the drain-side amorphous layer 36D in the drain-side inclined portion 37D.

[0107] Note that each of the thickness TSB of the source-side amorphous layer 36S and the thickness TDB of the drain-side amorphous layer 36D can be arbitrarily changed. In one example, the thickness TSB of the source-side amorphous layer 36S in the source-side flat portion 38S may be different from the thickness TDB of the drain-side amorphous layer 36D in the drain-side flat portion 38D. In one example, the thickness TSB of the source-side amorphous layer 36S in the source-side inclined portion 37S may be different from the thickness TDB of the drain-side amorphous layer 36D in the drain-side inclined portion 37D. Note that the thickness T1 of the crystalline layer 35 and the thickness T2 of the amorphous layer 36 in the second embodiment may be set in the same manner as in the first embodiment.

[0108] [Effect of the Second Embodiment] According to the nitride semiconductor device 10 of the second embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0109] (2-1) The extending portion 32 includes an inclined portion 37 connected to the ridge portion 31 and a flat portion 38 disposed on the side opposite to the ridge portion 31 with respect to the inclined portion 37. The inclined portion 37 includes an inclined surface 37A that inclines toward the electron supply layer 26 as it goes from the ridge portion 31 toward the flat portion 38. The amorphous layer 36 is provided on both the inclined portion 37 and the flat portion 38.

[0110] According to this configuration, the crystalline layer 35 is provided in a portion closer to the electron supply layer 26 than the amorphous layer 36 in the inclined portion 37 and the flat portion 38. Therefore, while ensuring the thicknesses of both the inclined portion 37 and the flat portion 38, a decrease in the 2DEG 28 caused by the inclined portion 37 and the flat portion 38 can be suppressed. Accordingly, an increase in the on-resistance can be suppressed while alleviating local electric field concentration in the gate layer 30.

[0111] <Third embodiment> A nitride semiconductor device 10 of the third embodiment will be described with reference to Figures 18 and 19. The nitride semiconductor device 10 of the third embodiment differs from the nitride semiconductor device 10 of the first embodiment mainly in the configuration of the gate layer 30. Below, differences from the nitride semiconductor device 10 of the first embodiment will be described in detail, and components common to the nitride semiconductor device 10 of the first embodiment will be denoted by the same reference numerals and will not be described again.

[0112] 18 and 19, the extension portion 32 of the gate layer 30 includes a first extension portion 32P and a second extension portion 32Q that is thinner than the first extension portion 32P. The first extension portion 32P is provided on the base end side of the extension portion 32 in the width direction of the gate layer 30 (the X-axis direction in FIGS. 18 and 19). The second extension portion 32Q is provided on the tip side of the extension portion 32 relative to the first extension portion 32P in the width direction of the gate layer 30. In the third embodiment, the source side extension portion 33 includes a first source side extension portion 33P and a second source side extension portion 33Q. The drain side extension portion 34 includes a first drain side extension portion 34P and a second drain side extension portion 34Q. The first source side extension portion 33P and the first drain side extension portion 34P constitute the first extension portion 32P of the extension portion 32. The second source side extension portion 33Q and the second drain side extension portion 34Q constitute the second extension portion 32Q of the extension portion 32. Hereinafter, when the first source side extension portion 33P and the first drain side extension portion 34P are commonly described, they will be referred to as the first extension portion 32P. When the second source side extension portion 33Q and the second drain side extension portion 34Q are commonly described, they will be referred to as the second extension portion 32Q.

[0113] The first extension portion 32P is connected to the ridge portion 31. The first extension portion 32P is formed in a flat shape with a substantially constant thickness. Therefore, in the cross-sectional view shown in FIG. 18, the first extension portion 32P is formed in a rectangular shape.

[0114] As shown in FIG. 19, the thickness TP of the first extending portion 32P can be, for example, 20 μm or more and 100 μm or less. In one example, the thickness TP of the first extending portion 32P may be 1 / 2 of the thickness TR of the ridge portion 31. In one example, the thickness TP of the first extending portion 32P may be less than 1 / 2 of the thickness TR of the ridge portion 31. Here, the thickness TP of the first extending portion 32P is an example of the "first thickness". Also, the thickness TP of the first extending portion 32P can be defined by the distance in the Z-axis direction between the lower surface 32PB and the upper surface 32PA of the first extending portion 32P.

[0115] The second extending portion 32Q is formed in a flat shape with its thickness being substantially constant. Therefore, in the cross-sectional view shown in FIG. 19, the second extending portion 32Q is formed in a rectangular shape. In one example, in the width direction of the gate layer 30, the width WQ of the second extending portion 32Q is shorter than the width WP of the first extending portion 32P.

[0116] The thickness TQ of the second extending portion 32Q can be, for example, 10 μm or more and 60 μm or less. The thickness TQ of the second extending portion 32Q may be, for example, 30 nm or less, 25 nm or less, 20 nm or less, or 15 nm or less. The thickness TQ of the second extending portion 32Q may be thicker than 30 nm and 40 nm or less. Here, the thickness TQ of the second extending portion 32Q is an example of the "second thickness". Also, the thickness TQ of the second extending portion 32Q can be defined by the distance in the Z-axis direction between the lower surface 32QB and the upper surface 32QA of the second extending portion 32Q.

[0117] As shown in FIG. 19, similar to the first embodiment, the extending portion 32 includes a crystalline layer 35 and an amorphous layer 36. More specifically, similar to the first embodiment, the source-side extending portion 33 includes a source-side crystalline layer 35S and a source-side amorphous layer 36S. The drain-side extending portion 34 includes a drain-side crystalline layer 35D and a drain-side amorphous layer 36D. Hereinafter, in the case of a common description of the source-side crystalline layer 35S and the drain-side crystalline layer 35D, it will be described as the crystalline layer 35. In the case of a common description of the source-side amorphous layer 36S and the drain-side amorphous layer 36D, it will be described as the amorphous layer 36.

[0118] The amorphous layer 36 is provided on both the first extension portion 32P and the second extension portion 32Q. The amorphous layer 36 is provided over the entire upper surface 32PA of the first extension portion 32P. The amorphous layer 36 is provided over the entire upper surface 32QA of the second extension portion 32Q. In this way, the amorphous layer 36 is a layer that includes the upper surface 32PA of the first extension portion 32P and the upper surface 32QA of the second extension portion 32Q. The crystalline layer 35 is provided on both the first extension portion 32P and the second extension portion 32Q. The crystalline layer 35 is a layer that includes the lower surface 32PB of the first extension portion 32P and the lower surface 32QB of the second extension portion 32Q.

[0119] In one example, the thickness T2 of the amorphous layer 36 in the first extension portion 32P is equal to the thickness T2 of the amorphous layer 36 in the second extension portion 32Q. Here, the thickness T2 of the amorphous layer 36 in the first extension portion 32P can be defined by the average value of the distance in the Z-axis direction between the upper surface 32PA of the first extension portion 32P and the boundary between the amorphous layer 36 and the crystalline layer 35 in the first extension portion 32P. The thickness T2 of the amorphous layer 36 in the second extension portion 32Q can be defined by the average value of the distance in the Z-axis direction between the upper surface 32QA of the second extension portion 32Q and the boundary between the amorphous layer 36 and the crystalline layer 35 in the second extension portion 32Q.

[0120] The thickness T2 of the amorphous layer 36 in the first extension portion 32P and the thickness T2 of the amorphous layer 36 in the second extension portion 32Q can each be changed as desired. For example, the thickness T2 of the amorphous layer 36 in the first extension portion 32P may be thinner than the thickness T2 of the amorphous layer 36 in the second extension portion 32Q. For example, the thickness T2 of the amorphous layer 36 in the first extension portion 32P may be thicker than the thickness T2 of the amorphous layer 36 in the second extension portion 32Q.

[0121] In one example, the thickness of the source side amorphous layer 36S in the first source side extension portion 33P is equal to the thickness of the drain side amorphous layer 36D in the first drain side extension portion 34P. In one example, the thickness TSB of the source side amorphous layer 36S in the second source side extension portion 33Q is equal to the thickness TDB of the drain side amorphous layer 36D in the second drain side extension portion 34Q.

[0122] The thicknesses of the source-side amorphous layer 36S and the drain-side amorphous layer 36D can be changed as desired. For example, the thickness TSB of the source-side amorphous layer 36S in the second source-side extension portion 33Q may be different from the thickness TDB of the drain-side amorphous layer 36D in the second drain-side extension portion 34Q. For example, the thickness of the source-side amorphous layer 36S in the first source-side extension portion 33P may be different from the thickness of the drain-side amorphous layer 36D in the first drain-side extension portion 34P.

[0123] [Effects of the third embodiment] According to the nitride semiconductor device 10 of the third embodiment, the following effects can be obtained in addition to the effects of the first embodiment.

[0124] (3-1) The extension portion 32 includes a first extension portion 32P connected to the ridge portion 31 and having a first thickness, and a second extension portion 32Q provided on the opposite side of the first extension portion 32P from the ridge portion 31 and having a second thickness thinner than the first thickness. The amorphous layer 36 is provided in both the first extension portion 32P and the second extension portion 32Q.

[0125] According to this configuration, the crystalline layer 35 is provided in the first extension portion 32P and the second extension portion 32Q in a portion closer to the electron supply layer 26 than the amorphous layer 36. This makes it possible to suppress a decrease in the 2DEG 28 caused by the first extension portion 32P and the second extension portion 32Q while ensuring the thickness of both the first extension portion 32P and the second extension portion 32Q. This makes it possible to suppress an increase in on-resistance while mitigating local electric field concentration in the gate layer 30.

[0126] <Fourth embodiment> Referring to FIGS. 20 and 21, the nitride semiconductor device 10 of the fourth embodiment will be described. In the nitride semiconductor device 10 of the fourth embodiment, it is mainly different from the nitride semiconductor device 10 of the first embodiment in that it includes a gate layer 100 instead of the gate layer 30. Hereinafter, the differences from the nitride semiconductor device 10 of the first embodiment will be described in detail, and the same reference numerals will be given to the components common to the nitride semiconductor device 10 of the first embodiment, and the description thereof will be omitted.

[0127] As shown in FIGS. 20 and 21, the nitride semiconductor device 10 of the fifth embodiment includes a gate layer 100. The gate layer 100 is partially provided on the electron supply layer 26. The gate layer 100 is made of a nitride semiconductor, similar to the gate layer 30 (see FIG. 3) of the first embodiment. In one example, the gate layer 100 has a smaller bandgap than the electron supply layer 26 and is made of a nitride semiconductor containing acceptor-type impurities. In one example, the gate layer 100 is GaN (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities may be at least one of Mg, Zn, and C. The maximum concentration of the acceptor-type impurities in the gate layer 100 is, for example, 7×10 18 cm -3 or more and 1×10 20 cm -3 or less.

[0128] The gate layer 100 is formed in a flat shape with a constant thickness. Therefore, in the cross-sectional view shown in FIG. 20, the gate layer 100 is formed in a rectangular shape. The gate layer 100 includes an upper surface 100A on which the gate electrode 40 is disposed and a lower surface 100B in contact with the electron supply layer 26.

[0129] As shown in FIG. 21, the width WG of the gate layer 100 is larger than the width WE of the gate electrode 40. In the width direction of the gate layer 100 (the X-axis direction in FIG. 21), the gate electrode 40 is disposed closer to the center than both ends of the gate layer 100. For this reason, in a plan view, the gate layer 100 has a portion that protrudes from the gate electrode 40. Here, in the width direction of the gate layer 100, the portion of the gate layer 100 that protrudes from the gate electrode 40 is defined as an “extending portion 102”. That is, the gate layer 100 includes an electrode arrangement portion 101 where the gate electrode 40 is disposed, and an extending portion 102 that extends in the width direction of the gate layer 100 from the electrode arrangement portion 101. It can be said that the extending portion 102 extends from the electrode arrangement portion 101 toward at least one of the source electrode 42 and the drain electrode 44. In the fourth embodiment, the extending portion 102 extends from the electrode arrangement portion 101 toward both the source electrode 42 and the drain electrode 44 (both are shown in FIG. 20).

[0130] As shown in FIGS. 20 and 21, the extending portion 102 includes a source-side extending portion 103 and a drain-side extending portion 104. The source-side extending portion 103 is a portion of the gate layer 100 that protrudes from the gate electrode 40 toward the source opening 50A. The drain-side extending portion 104 is a portion of the gate layer 100 that protrudes from the gate electrode 40 toward the drain opening 50B.

[0131] The gate electrode 40 is disposed offset with respect to the gate layer 100 in the width direction of the gate layer 100. In one example, the gate electrode 40 is disposed closer to the source opening 50A with respect to the gate layer 100. For this reason, as shown in FIG. 21, the width WD of the drain-side extending portion 104 is larger than the width WS of the source-side extending portion 103.

[0132] The thickness TG of the gate layer 100 can be, for example, 100 nm or more and 200 nm or less. The thickness TG of the gate layer 100 can be defined by the distance in the Z-axis direction between the upper surface 100A and the lower surface 100B of the gate layer 100. The thickness TG of the gate layer 100 is determined in consideration of various parameters such as the gate breakdown voltage.

[0133] The electrode arrangement part 101 is composed of the crystalline layer 105. The extending part 102 includes the crystalline layer 105 and the amorphous layer 106 provided on the crystalline layer 105.

[0134] The crystalline layer 105 is a layer including the lower surface 102B of the extending part 102. That is, the crystalline layer 105 is in contact with the electron supply layer 26. The crystalline layer 105 is provided over the entire extending part 102 in plan view.

[0135] The amorphous layer 106 is a layer including the upper surface 102A of the extending part 102. The amorphous layer 106 is a layer spaced apart from the electron supply layer 26 in the Z-axis direction. The amorphous layer 106 is provided over the entire extending part 102 in plan view. That is, the amorphous layer 106 is provided over the entire crystalline layer 105 in plan view. Also, it can be said that the amorphous layer 106 is provided over the entire upper surface 102A of the extending part 102. Since the upper surface 102A of the extending part 102 is composed of the amorphous layer 106, the upper surface 102A of the extending part 102 is a rough surface rougher than the region where the gate electrode 40 is arranged on the upper surface 100A of the gate layer 100.

[0136] More specifically, the source-side extending part 103 includes the source-side crystalline layer 105S provided closer to the electron supply layer 26 and the source-side amorphous layer 106S provided on the source-side crystalline layer 105S.

[0137] The source-side crystalline layer 105S is a layer including the lower surface 103B of the source-side extending part 103. The source-side crystalline layer 105S is in contact with the electron supply layer 26. The source-side crystalline layer 105S is formed over the entire source-side extending part 103 in plan view. The source-side crystalline layer 105S constitutes the crystalline layer 105 of the extending part 102.

[0138] The source-side amorphous layer 106S is a layer including the upper surface 103A of the source-side extending portion 103. The source-side amorphous layer 106S is a layer spaced apart from the electron supply layer 26 in the Z-axis direction. The source-side amorphous layer 106S is provided over the entire source-side extending portion 103 in plan view. That is, the source-side amorphous layer 106S is provided over the entire source-side crystalline layer 105S in plan view. Also, it can be said that the source-side amorphous layer 106S is provided over the entire upper surface 103A of the source-side extending portion 103. For this reason, the upper surface 103A of the source-side extending portion 103 is a rough surface that is rougher than the upper surface 101A of the electrode arrangement portion 101 among the upper surfaces 100A of the gate layer 100. The source-side amorphous layer 106S constitutes the amorphous layer 106 of the extending portion 102.

[0139] The drain-side extending portion 104 includes a drain-side crystalline layer 105D provided closer to the electron supply layer 26 and a drain-side amorphous layer 106D provided on the drain-side crystalline layer 105D.

[0140] The drain-side crystalline layer 105D is a layer including the lower surface 104B of the drain-side extending portion 104. That is, the drain-side crystalline layer 105D is in contact with the electron supply layer 26. The drain-side crystalline layer 105D is formed over the entire drain-side extending portion 104 in plan view. The drain-side crystalline layer 105D constitutes the crystalline layer 105 of the extending portion 102.

[0141] The drain-side amorphous layer 106D is a layer including the upper surface 104A of the drain-side extending portion 104. The drain-side amorphous layer 106D is a layer spaced apart from the electron supply layer 26 in the Z-axis direction. The drain-side amorphous layer 106D is provided over the entire drain-side extending portion 104 in plan view. That is, the drain-side amorphous layer 106D is provided over the entire drain-side crystalline layer 105D in plan view. Also, it can be said that the drain-side amorphous layer 106D is provided over the entire upper surface 104A of the drain-side extending portion 104. For this reason, the upper surface 104A of the drain-side extending portion 104 is a rough surface that is rougher than the upper surface 101A of the electrode arrangement portion 101 among the upper surfaces 100A of the gate layer 100.

[0142] Hereinafter, for the common description of the source-side crystalline layer 105S and the drain-side crystalline layer 105D, "crystalline layer 105" is used, and for the common description of the source-side amorphous layer 106S and the drain-side amorphous layer 106D, "amorphous layer 106" is used.

[0143] The thickness T1 of the crystalline layer 105 can be 20 nm or less. The thickness T1 of the crystalline layer 105 can be 15 nm or less, or 10 nm or less. Also, the thickness T1 of the crystalline layer 105 can be 5 nm or more. Here, the thickness T1 of the crystalline layer 105 can be defined by the average value of the distance in the Z-axis direction between the lower surface 102B of the extending portion 102 and the boundary between the crystalline layer 105 and the amorphous layer 106.

[0144] In the fourth embodiment, the thickness T1 of the crystalline layer 105 is thinner than the thickness T2 of the amorphous layer 106. In one example, the thickness T1 of the crystalline layer 105 is 1 / 2 or less of the thickness T2 of the amorphous layer 106. In one example, the thickness T1 of the crystalline layer 105 is 1 / 3 or less of the thickness T2 of the amorphous layer 106. In one example, the thickness T1 of the crystalline layer 105 is 1 / 4 or less of the thickness T2 of the amorphous layer 106. In one example, the thickness T1 of the crystalline layer 105 is 1 / 5 or less of the thickness T2 of the amorphous layer 106. In one example, the thickness T1 of the crystalline layer 105 is 1 / 10 or less of the thickness T2 of the amorphous layer 106. In one example, the thickness T1 of the crystalline layer 105 is 1 / 15 or less of the thickness T2 of the amorphous layer 106. In one example, the thickness T1 of the crystalline layer 105 is 1 / 20 or more of the thickness T2 of the amorphous layer 106.

[0145] The thickness T2 of the amorphous layer 106 can be 80 nm or more. In one example, the thickness T2 of the amorphous layer 106 can be 100 nm or more, 120 nm or more, 140 nm or more, 160 nm or more, or 180 nm or more. The thickness T2 of the amorphous layer 106 may be set such that the thickness T1 of the crystalline layer 105 is equal to or less than a predetermined value (for example, 20 nm) with respect to the thickness of the extending portion 102 (the thickness TG of the gate layer 100). Here, the thickness T2 of the amorphous layer 106 can be defined by the average value of the distance in the Z-axis direction between the upper surface 102A of the extending portion 102 and the boundary between the crystalline layer 105 and the amorphous layer 106.

[0146] In one example, the thickness TDB of the source-side amorphous layer 106S and the thickness TDB of the drain-side amorphous layer 106D may be equal to each other. Note that the thickness TSB of the source-side amorphous layer 106S and the thickness TDB of the drain-side amorphous layer 106D may be set individually. Therefore, the thickness TSB of the source-side amorphous layer 106S may be greater than the thickness TDB of the drain-side amorphous layer 106D. In other words, the thickness TSA of the source-side crystalline layer 105S may be less than the thickness TDA of the drain-side crystalline layer 105D. Also, the thickness TSB of the source-side amorphous layer 106S may be less than the thickness TDB of the drain-side amorphous layer 106D. In other words, the thickness TSA of the source-side crystalline layer 105S may be greater than the thickness TDB of the drain-side crystalline layer 105D.

[0147] [Effects of the Fourth Embodiment] According to the nitride semiconductor device 10 of the fourth embodiment, the following effects can be obtained. (4-1) The nitride semiconductor device 10 includes an electron transit layer 24 made of a nitride semiconductor, an electron supply layer 26 provided on the electron transit layer 24 and made of a nitride semiconductor having a larger band gap than the electron transit layer 24, a source electrode 42 and a drain electrode 44 provided spaced apart on the electron supply layer 26, a gate layer 100 provided on the electron supply layer 26 between the source electrode 42 and the drain electrode 44 and made of a nitride semiconductor containing acceptor-type impurities, and a gate electrode 40 provided on the gate layer 100. The gate layer 100 includes an electrode arrangement portion 101 in which the gate electrode 40 is arranged, and an extension portion 102 extending from the electrode arrangement portion 101 toward both the source electrode 42 and the drain electrode 44. The extension portion 102 includes a crystalline layer 105 provided closer to the electron supply layer 26 and an amorphous layer 106 provided on the crystalline layer 105.

[0148] According to this configuration, even if the thickness of the extension portion 102 of the gate layer 100 is not reduced, the amorphous layer 106 is formed in the extension portion 102, thereby suppressing a reduction in the 2DEG 28 caused by the extension portion 102. Therefore, it is possible to suppress an increase in the on-resistance while alleviating local electric field concentration in the gate layer 30.

[0149] (4-2) The thickness T1 of the crystalline layer 105 is smaller than the thickness T2 of the amorphous layer . According to this configuration, the thickness TG of the gate layer 100 can be increased in accordance with the gate breakdown voltage, and the thickness T1 of the crystalline layer 105 can be decreased, thereby suppressing a reduction in the 2DEG 28 due to the extension portion 102.

[0150] <Example of change> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0151] In each embodiment, the nitride semiconductor device 10 is not limited to a HEMT using GaN, and may be a semiconductor device using other nitride semiconductors. · The nitride semiconductor device 10 of each embodiment is not limited to being configured with the numerical values or numerical ranges described in each embodiment.

[0152] · In the first to third embodiments, the gate layer 30 is not limited to a configuration including the source-side extending portion 33 and the drain-side extending portion 34. Either one of the source-side extending portion 33 and the drain-side extending portion 34 may be omitted from the gate layer 30.

[0153] · In the first embodiment, the amorphous layer 36 may not be partially formed in the extending portion 32 of the gate layer 30. In other words, the amorphous layer 36 of the extending portion 32 may be partially formed in the extending portion 32 in plan view. In this modified example, it may be applied to the source-side extending portion 33, may be applied to the drain-side extending portion 34, or may be applied to both the source-side extending portion 33 and the drain-side extending portion 34.

[0154] · In the second embodiment, the amorphous layer 36 may not be formed in at least a part of the inclined portion 37 in the extending portion 32 of the gate layer 30. In one example, the amorphous layer 36 may not be formed in the portion of the inclined portion 37 closer to the ridge portion 31 in the width direction of the gate layer 30. In other words, the amorphous layer 36 may be formed in the portion of the inclined portion 37 closer to the flat portion 38 in the width direction of the gate layer 30. In this case, the amorphous layer 36 of the inclined portion 37 may be continuous with the amorphous layer 36 of the flat portion 38.

[0155] Furthermore, the amorphous layer 36 does not necessarily have to be formed in the inclined portion 37. That is, the inclined portion 37 may be composed of the crystalline layer 35. This modification may be applied to the source-side inclined portion 37S, the drain-side inclined portion 37D, or both the source-side inclined portion 37S and the drain-side inclined portion 37D. In this manner, the amorphous layer 36 may be provided in at least the flat portion 38 of the extension portion 32. More specifically, the amorphous layer 36 may be provided in at least the source-side flat portion 38S of the source-side extension portion 33. The amorphous layer 36 may be provided in at least the drain-side flat portion 38D of the drain-side extension portion 34.

[0156] In the second embodiment, the amorphous layer 36 may not be formed in at least a part of the flat portion 38 in the extension portion 32 of the gate layer 30. For example, the amorphous layer 36 may not be formed in a portion of the flat portion 38 on the tip side of the extension portion 32 in the width direction of the gate layer 30. This modification may be applied to the source-side flat portion 38S, the drain-side flat portion 38D, or both the source-side flat portion 38S and the drain-side flat portion 38D.

[0157] In the third embodiment, the amorphous layer 36 may not be formed in at least a part of the first extension portion 32P in the extension portion 32 of the gate layer 30. FIG. 22 shows a modified example of the gate layer 30 in the nitride semiconductor device 10. The cross-sectional position in FIG. 22 is the same as that in FIG. 19 . As shown in FIG. 22 , the amorphous layer 36 may not be formed over the entire first extension portion 32P. In this case, the first extension portion 32P is composed of a crystalline layer 35. More specifically, the source-side amorphous layer 36S is not provided in the first source-side extension portion 33P of the source-side extension portion 33, but is provided in the second source-side extension portion 33Q. The drain-side amorphous layer 36D is not provided in the first drain-side extension portion 34P of the drain-side extension portion 34, but is provided in the second drain-side extension portion 34Q.

[0158] Note that, in FIG. 22, this modification example is applied to both the first source-side extending portion 33P and the first drain-side extending portion 34P, but it is not limited thereto. It may be applied to the first source-side extending portion 33P or may be applied to the first drain-side extending portion 34P. Thus, the amorphous layer 36 only needs to be provided in at least the second extending portion 32Q among the extending portions 32. More specifically, the amorphous layer 36 only needs to be provided in at least the second source-side extending portion 33Q among the source-side extending portions 33. Also, the amorphous layer 36 only needs to be provided in at least the second drain-side extending portion 34Q among the drain-side extending portions 34.

[0159] · In the third embodiment, the amorphous layer 36 may not be formed in at least a part of the second extending portion 32Q in the extending portion 32 of the gate layer 30. In one example, the amorphous layer 36 may not be formed in the portion on the tip side of the second extending portion 32Q in the width direction of the gate layer 30. This modification example may be applied to the second source-side extending portion 33Q, may be applied to the second drain-side extending portion 34Q, or may be applied to both the second source-side extending portion 33Q and the second drain-side extending portion 34Q.

[0160] · In the first to third embodiments, the amorphous layer 36 may be formed in the portion of the side surface 31C of the ridge portion 31 closer to the upper surface 31A than the upper surface 32A of the extending portion 32. In this case, the thickness of the amorphous layer 36 of the ridge portion 31 is thinner than the thickness T2 of the amorphous layer 36 of the extending portion 32.

[0161] · In the fourth embodiment, either the source-side amorphous layer 106S or the drain-side amorphous layer 106D may be omitted from the gate layer 100. · In the fourth embodiment, either the source-side extending portion 103 or the drain-side extending portion 104 may be omitted from the gate layer 100.

[0162] One or more of the various examples described in this specification can be combined within a technically non-contradictory range. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0163] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z-axis direction described in this specification being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0164] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0165] [Appendix 1] an electron transit layer (24) made of a nitride semiconductor; an electron supply layer (26) provided on the electron transit layer (24) and made of a nitride semiconductor having a band gap larger than that of the electron transit layer (24); a source electrode (42) and a drain electrode (44) spaced apart from each other on the electron supply layer (26); a gate layer (30) formed on the electron supply layer (26) between the source electrode (42) and the drain electrode (44) and made of a nitride semiconductor containing acceptor-type impurities; a gate electrode (40) provided on the gate layer (30); Equipped with The gate layer (30) a ridge portion (31) in which the gate electrode (40) is disposed; an extension portion (32) that is thinner than the ridge portion (31); Including, The extension portion (32) is a crystalline layer (35) provided near the electron supply layer (26); an amorphous layer (36) provided on the crystalline layer (35); Contains Nitride semiconductor device (10).

[0166] [Appendix 2] The thickness (TSA / TDA) of the crystalline layer (35) is greater than the thickness (TSB / TDB) of the amorphous layer (36). 2. The nitride semiconductor device according to claim 1.

[0167] [Appendix 3] The thickness (TSA / TDA) of the crystalline layer (35) is smaller than the thickness (TSB / TDB) of the amorphous layer (36). 2. The nitride semiconductor device according to claim 1.

[0168] [Appendix 4] The thickness (TSB / TDB) of the amorphous layer (36) is equal to the thickness (TSA / TDA) of the crystalline layer (35). 2. The nitride semiconductor device according to claim 1.

[0169] [Appendix 5] The thickness (TS / TD) of the extension (32) is 10 nm or more and 60 nm or less. 5. The nitride semiconductor device according to any one of claims 1 to 4.

[0170] [Appendix 6] The thickness (TSB / TDB) of the amorphous layer (36) is 5 nm or more. 6. The nitride semiconductor device according to any one of appendices 1 to 5.

[0171] [Appendix 7] The thickness (TSA / TDA) of the crystalline layer (35) is 20 nm or less. The nitride semiconductor device according to any one of Appendices 1 to 6.

[0172] [Appendix 8] The amorphous layer (36) is provided over the entire upper surface (32A) of the extending portion (32). The nitride semiconductor device according to any one of Appendices 1 to 7.

[0173] [Appendix 9] The upper surface (32A) of the extending portion (32) is a rough surface that is rougher than the upper surface (31A) of the ridge portion (31). The nitride semiconductor device according to any one of Appendices 1 to 8.

[0174] [Appendix 10] The extending portion (32) includes a source-side extending portion (33) extending from the ridge portion (31) toward the source electrode (42), and a drain-side extending portion (34) extending from the ridge portion (31) toward the drain electrode (44). and The nitride semiconductor device according to any one of Appendices 1 to 9.

[0175] [Appendix 11] The source-side extending portion (33) includes a source-side crystalline layer (35S) provided closer to the electron supply layer (26), and a source-side amorphous layer (36S) provided on the source-side crystalline layer (35S). and The drain-side extending portion (34) includes a drain-side crystalline layer (35D) provided closer to the electron supply layer (26), and a drain-side amorphous layer (36D) provided on the drain-side crystalline layer (35D). and The nitride semiconductor device according to Appendix 10.

[0176] [Appendix 12] The extension portion (32) is an inclined portion (37) connected to the ridge portion (31); a flat portion (38) disposed on the opposite side of the ridge portion (31) with respect to the inclined portion (37); Including, The inclined portion (37) includes an inclined surface (37A) that inclines toward the electron supply layer (26) from the ridge portion (31) toward the flat portion (38). 10. The nitride semiconductor device according to any one of appendices 1 to 9.

[0177] [Appendix 13] The inclination angle of the inclined surface (37A) with respect to the upper surface (26A) of the electron supply layer (26) is 30° or more and 80° or less. 13. The nitride semiconductor device according to claim 12.

[0178] [Appendix 14] The inclination angle of the inclined surface with respect to the upper surface (26A) of the electron supply layer (26) is 45° or less. 13. The nitride semiconductor device according to claim 12.

[0179] [Appendix 15] The amorphous layer (36) is provided on both the inclined portion (37) and the flat portion (38). 15. The nitride semiconductor device according to any one of claims 12 to 14.

[0180] [Appendix 16] The extension portion (32) is a source-side extension portion (33) extending from the ridge portion (31) toward the source electrode (42); a drain-side extension portion (34) extending from the ridge portion (31) toward the drain electrode (44); Including, the source-side extending portion (33) includes a source-side inclined portion (37S) as the inclined portion (37) and a source-side flat portion (38S) as the flat portion (38), The drain-side extending portion (34) includes a drain-side inclined portion (37D) as the inclined portion (37) and a drain-side flat portion (38D) as the flat portion (38). The nitride semiconductor device according to any one of Appendices 12 to 14.

[0181] [Appendix 17] The amorphous layer (36) is a source-side amorphous layer (36S) provided on both the source-side inclined portion (37S) and the source-side flat portion (38S), a drain-side amorphous layer (36D) provided on both the drain-side inclined portion (37D) and the drain-side flat portion (38D), and includes The nitride semiconductor device according to Appendix 16.

[0182] [Appendix 18] The extending portion (32) is a first extending portion (32P) connected to the ridge portion (31) and having a first thickness (TP), a second extending portion (32Q) provided on the side opposite to the ridge portion (31) with respect to the first extending portion (32P) and having a second thickness (TQ) thinner than the first thickness (TP), and includes The nitride semiconductor device according to any one of Appendices 1 to 9.

[0183] [Appendix 19] The amorphous layer (36) is provided on both the first extending portion (32P) and the second extending portion (32Q). The nitride semiconductor device according to Appendix 18.

[0184] [Appendix 20] The amorphous layer (36) is not provided on the first extending portion (32P) and is provided on the second extending portion (32Q). The nitride semiconductor device according to Appendix 18.

[0185] [Appendix 21] The extending portion (32) is A source-side extending portion (33) extending from the ridge portion (31) toward the source electrode (42), A drain-side extending portion (34) extending from the ridge portion (31) toward the drain electrode (44), and the source-side extending portion (33) includes a first source-side extending portion (33P) as the first extending portion (32P) and a second source-side extending portion (33Q) as the second extending portion (32Q), the drain-side extending portion (34) includes a first drain-side extending portion (34P) as the first extending portion (32P) and a second drain-side extending portion (34Q) as the second extending portion (32Q). The nitride semiconductor device according to Supplementary Note 18.

[0186] [Supplementary Note 22] The amorphous layer (36) is a source-side amorphous layer (36S) provided on both the first source-side extending portion (33P) and the second source-side extending portion (33Q), a drain-side amorphous layer (36D) provided on both the first drain-side extending portion (34P) and the second drain-side extending portion (34Q), and The nitride semiconductor device according to Supplementary Note 21.

[0187] [Supplementary Note 23] The amorphous layer (36) is not provided on the first source-side extending portion (33P), and is a source-side amorphous layer (36S) provided on the second source-side extending portion (33Q), not provided on the first drain-side extending portion (34P), and is a drain-side amorphous layer (36D) provided on the second drain-side extending portion (34Q), and The nitride semiconductor device according to Supplementary Note 21.

[0188] [Supplementary Note 24] An electron traveling layer (24) composed of a nitride semiconductor, an electron supply layer (26) provided on the electron transit layer (24) and made of a nitride semiconductor having a band gap larger than that of the electron transit layer (24); a source electrode (42) and a drain electrode (44) spaced apart from each other on the electron supply layer (26); a gate layer (100) formed on the electron supply layer (26) between the source electrode (42) and the drain electrode (44) and made of a nitride semiconductor containing acceptor-type impurities; a gate electrode (40) provided on the gate layer (100); Equipped with The gate layer (100) an electrode placement portion (101) in which the gate electrode (40) is placed; an extension portion (102) extending from the electrode placement portion (101) toward at least one of the source electrode (42) and the drain electrode (44); Including, The extension portion (102) is a crystalline layer (105) provided near the electron supply layer (26); an amorphous layer (106) provided on the crystalline layer (105); Contains Nitride semiconductor device (10).

[0189] [Appendix 25] The thickness (T1) of the crystalline layer (105) is smaller than the thickness (T2) of the amorphous layer (106). 25. The nitride semiconductor device according to claim 24.

[0190] [Appendix 26] The thickness (T1) of the crystalline layer (105) is equal to or less than half the thickness (T2) of the amorphous layer (106). 25. The nitride semiconductor device according to claim 24.

[0191] [Appendix 27] The thickness (T1) of the crystalline layer (105) is 1 / 5 or less of the thickness (T2) of the amorphous layer (106). 25. The nitride semiconductor device according to claim 24.

[0192] [Appendix 28] The thickness (T1) of the crystalline layer (105) is 1 / 10 or less of the thickness (T2) of the amorphous layer (106). 25. The nitride semiconductor device according to claim 24.

[0193] [Appendix 29] The thickness (T1) of the crystalline layer (105) is 1 / 20 or more of the thickness (T2) of the amorphous layer (106). 25. The nitride semiconductor device according to claim 24.

[0194] [Appendix 30] The extension portion (102) is a source-side extension portion (103) extending from the electrode placement portion (101) toward the source electrode (42); a drain-side extension portion (104) extending from the electrode placement portion (101) toward the drain electrode (44); Contains 30. The nitride semiconductor device according to any one of claims 24 to 29.

[0195] [Appendix 31] The source side extension portion (103) is a source-side crystalline layer (105S) as the crystalline layer (105) provided near the electron supply layer (26); a source-side amorphous layer (106S) as the amorphous layer (106) provided on the source-side crystalline layer (105S); Including, The drain side extension portion (104) a drain-side crystalline layer (105D) as the crystalline layer (105) provided near the electron supply layer (26); a drain-side amorphous layer (106D) as the amorphous layer (106) provided on the drain-side crystalline layer (105D); Contains 31. The nitride semiconductor device according to claim 30.

[0196] [Appendix 32] Forming an electron transport layer (24) composed of a nitride semiconductor; Forming an electron supply layer (26) composed of a nitride semiconductor having a larger bandgap than the electron transport layer (24) on the electron transport layer (24); Forming a nitride semiconductor layer (82) containing acceptor-type impurities on the electron supply layer (26) by epitaxial growth; Forming a gate electrode (40) on the nitride semiconductor layer (82); Forming a gate layer (30) by etching the nitride semiconductor layer (82); including Forming the gate layer (30) includes forming a ridge portion (31) and an extending portion (32) thinner than the ridge portion (31); forming an amorphous layer (36) at a position of the extending portion (32) separated from the electron supply layer (26) in the thickness direction (Z) of the extending portion (32); including A method for manufacturing a nitride semiconductor device (10).

[0197] [Appendix 33] Forming the extending portion (32) by plasma etching The method for manufacturing a nitride semiconductor device according to Appendix 32.

[0198] [Appendix 34] Forming the amorphous layer (36) includes performing plasma treatment on the upper surface (32A) of the extending portion (32) after forming the extending portion (32). The method for manufacturing a nitride semiconductor device according to Appendix 33.

[0199] [Appendix 35] The type of gas used for the plasma treatment to form the amorphous layer (36) is different from the type of gas used for the plasma etching to form the extending portion (32). 35. A method for manufacturing a nitride semiconductor device according to claim 34.

[0200] [Appendix 36] Forming the gate layer (30) forming a mask (90) on the nitride semiconductor layer (82) to cover the gate electrode (40); Etching the nitride semiconductor layer (82) exposed from the mask (90); Contains 36. A method for manufacturing a nitride semiconductor device according to any one of appendices 32 to 35.

[0201] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0202] 10...Nitride semiconductor device 12...Chip body 13…Top surface 14...Gate pad 16...Sauce pad 18...Drain pad 20...Semiconductor substrate 22...Buffer layer 24...Electron transit layer 26…electron supply layer 26A…Top surface 28...2DEG 30...Gate layer 31...Ridge 31A…Top surface 31B…Bottom surface 31C…Side 32...Extension part 32A…Top surface 32B…Bottom surface 32P…1st extension part 32PA…Top surface 32PB…Bottom side 32Q…Second extension part 32QA…Upper surface 32QB…Lower surface 33…Source - side extension part 33A…Upper surface 33B…Lower surface 33P…First source - side extension part 33Q…Second source - side extension part 34…Drain - side extension part 34A…Upper surface 34B…Lower surface 34P…First drain - side extension part 34Q…Second drain - side extension part 35…Crystalline layer 35S…Source - side crystalline layer 35D…Drain - side crystalline layer 36…Amorphous layer 36S…Source - side amorphous layer 36D…Drain - side amorphous layer 37…Inclined part 37A…Inclined surface 37B…Lower surface 37S…Source - side inclined part 37D…Drain - side inclined part 38…Flat part 38A…Upper surface 38B…Lower surface 38S…Source - side flat part 38D…Drain - side flat part 40…Gate electrode 42…Source electrode 42A…Source contact part 44…Drain electrode 44A…Drain contact part 50…Passivation layer 50A…Source opening 50B…Drain opening 60…Field - plate electrode 61…End part 72…Gate wiring 73…Gate connection conductor 74…Source wiring 75…Source connection conductor 76…Drain wiring 77…Drain connection conductor 82...Nitride semiconductor layer 84...electrode layer 86...insulating layer 88...Photoresist mask 90...insulating layer 92...electrode layer 100...Gate layer 100A…Top surface 100B…Bottom surface 101...Electrode placement part 101A…Top surface 102...Extension part 102A…Top surface 102B…Bottom surface 103…Source side extension part 103A…Top surface 103B…Bottom surface 104...Drain side extension portion 104A…Top surface 104B…Bottom surface 105...Crystalline layer 105S: Source side crystalline layer 105D...Drain side crystalline layer 106...Amorphous layer 106S...source side amorphous layer 106D...Drain side amorphous layer T1: Thickness of the crystalline layer T2: Amorphous layer thickness TP: Thickness of the first extension TQ: Thickness of the second extension TR: Ridge thickness TS: Thickness of the source side extension TSA: Thickness of the source-side crystalline layer TSB: Thickness of the source-side amorphous layer TD: Thickness of the drain side extension TDA: Thickness of the drain-side crystalline layer TDB: Thickness of the amorphous layer on the drain side TG: Gate layer thickness WG: Gate layer width WE: gate electrode width WS: Width of source side extension WD: Width of drain side extension WP: Width of the first extension WQ: Width of the second extension

Claims

1. An electron transport layer composed of a nitride semiconductor, an electron supply layer provided on the electron transport layer and composed of a nitride semiconductor having a larger bandgap than the electron transport layer, a source electrode and a drain electrode provided separately from each other on the electron supply layer, a gate layer provided between the source electrode and the drain electrode on the electron supply layer and composed of a nitride semiconductor containing an acceptor-type impurity, a gate electrode provided on the gate layer, comprising the gate layer a ridge portion where the gate electrode is disposed, an extending portion thinner than the ridge portion, including the extending portion a crystalline layer provided closer to the electron supply layer, an amorphous layer provided on the crystalline layer, including a nitride semiconductor device.

2. The thickness of the crystalline layer is thicker than the thickness of the amorphous layer The nitride semiconductor device according to Claim 1.

3. The thickness of the crystalline layer is thinner than the thickness of the amorphous layer The nitride semiconductor device according to Claim 1.

4. The thickness of the amorphous layer is equal to the thickness of the crystalline layer The nitride semiconductor device according to Claim 1.

5. The thickness of the extending portion is 10 nm or more and 60 nm or less The nitride semiconductor device according to Claim 1.

6. The thickness of the amorphous layer is 5 nm or more The nitride semiconductor device according to Claim 1.

7. The thickness of the crystalline layer is 20 nm or less The nitride semiconductor device according to Claim 1.

8. The amorphous layer is provided over the entire upper surface of the extending portion The nitride semiconductor device according to Claim 1.

9. The upper surface of the extending portion is a rough surface rougher than the upper surface of the ridge portion The nitride semiconductor device according to Claim 1.

10. The extending portion a source-side extending portion extending from the ridge portion toward the source electrode, a drain-side extending portion extending from the ridge portion toward the drain electrode, including The nitride semiconductor device according to any one of Claims 1 to 9.

11. The source-side extending portion a source-side crystalline layer provided closer to the electron supply layer, a source-side amorphous layer provided on the source-side crystalline layer, including The drain-side extending portion a drain-side crystalline layer provided closer to the electron supply layer, a drain-side amorphous layer provided on the drain-side crystalline layer, including The nitride semiconductor device according to Claim 10.

12. The extending portion The inclined portion connected to the ridge portion, The flat portion disposed on the side opposite to the ridge portion with respect to the inclined portion, Including, The inclined portion includes an inclined surface that inclines toward the electron supply layer as it goes from the ridge portion toward the flat portion The nitride semiconductor device according to any one of claims 1 to 9.

13. The amorphous layer is provided on both the inclined portion and the flat portion The nitride semiconductor device according to claim 12.

14. The extending portion is, A first extending portion connected to the ridge portion and having a first thickness; A second extending portion provided on the side opposite to the ridge portion with respect to the first extending portion and having a second thickness smaller than the first thickness; Including The nitride semiconductor device according to any one of claims 1 to 9.

15. The amorphous layer is provided on both the first extending portion and the second extending portion The nitride semiconductor device according to claim 14.

16. Forming an electron traveling layer composed of a nitride semiconductor; Forming an electron supply layer composed of a nitride semiconductor having a larger band gap than the electron traveling layer on the electron traveling layer; Forming a nitride semiconductor layer containing acceptor-type impurities on the electron supply layer by epitaxial growth; Forming a gate electrode on the nitride semiconductor layer; Forming a gate layer by etching the nitride semiconductor layer; Including, Forming the gate layer includes, Forming a ridge portion and an extending portion thinner than the ridge portion; Forming an amorphous layer at a position separated from the electron supply layer in the extending portion in the thickness direction of the extending portion; [[ID= ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ etching the nitride semiconductor layer exposed from the mask; including The method of manufacturing a nitride semiconductor device according to claim 16.

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