Circuit board, semiconductor device, and mounting structure

Abstract

To provide a circuit board, a semiconductor device, and a mounting structure with which a defect hardly occurs in a connection terminal formed on a circuit board.SOLUTION: A circuit board according to the present disclosure has an insulating substrate and a conductor. The insulating substrate has a plurality of insulating layers including a surface layer insulating layer located on a surface layer of the insulating substrate. The surface layer insulating layer has a central area and a peripheral area. The central area is located in a central part of a principal surface of the surface layer insulating layer. The peripheral area includes an outer edge part of the surface layer insulating layer, and is located around the central area. The conductor includes a plurality of via conductors arranged circumferentially in the peripheral area and penetrating the surface layer insulating layer in a thickness direction. The plurality of via conductors include an inclined via conductor extending in a direction inclined relative to a direction perpendicular to the principal surface of the surface layer insulating layer.SELECTED DRAWING: Figure 3B

Description

Technical Field

[0001] The present disclosure relates to a circuit board, a semiconductor device, and a mounting structure.

Background Art

[0002] Conventionally, a wiring board in which wirings are arranged between layers of a plurality of ceramic substrates has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, with the increasing functionality and size of semiconductor elements to be mounted, a circuit board is forced to arrange connection terminals for mounting semiconductor devices in a region from the central part to the peripheral part thereof.

[0005] For example, when a semiconductor device having a smaller coefficient of thermal expansion than the circuit board is mounted, stress is likely to occur in the circuit board and the semiconductor device due to heating in a mounting process such as a reflow process, heat generation when the semiconductor device is driven, and the like.

[0006] In particular, when stress concentrates on a connection terminal for connecting a semiconductor device on a circuit board, defects are likely to occur in the connection terminal.

[0007] An object of the present disclosure is to provide a circuit board, a semiconductor device, and a mounting structure in which defects are less likely to occur in connection terminals formed on the circuit board.

Means for Solving the Problems

[0008] A circuit board according to one aspect of the present disclosure includes an insulating substrate and a conductor. The insulating substrate has a plurality of insulating layers including a surface insulating layer located on the surface layer of the insulating substrate. The surface insulating layer has a central region and a peripheral region. The central region is located at the center of the main surface of the surface insulating layer. The peripheral region includes the outer edge of the surface insulating layer and is located around the central region. The conductor is arranged in a circular shape in the peripheral region and includes a plurality of via conductors that penetrate the surface insulating layer in the thickness direction. The plurality of via conductors includes inclined via conductors that extend in a direction inclined with respect to the direction perpendicular to the main surface of the surface insulating layer.

Advantages of the Invention

[0009] According to the present disclosure, it is possible to provide a circuit board, a semiconductor device, and a mounting structure in which defects are less likely to occur in connection terminals formed on the circuit board.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2A

Figure 2B

Figure 3A

Figure 3B

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

[0011] Hereinafter, the circuit board, semiconductor device, and mounting structure of the embodiment will be described with reference to FIGS. 1 to 9. Note that one aspect of the present disclosure is not limited to the specific embodiments described below. One aspect of the present disclosure includes various aspects as long as they are in line with the spirit or scope of the general inventive concept defined by the appended claims.

[0012] In the embodiments described below, expressions such as "orthogonal" or "perpendicular" may be used, but these expressions do not necessarily require strict "orthogonality" or "perpendicularity". That is, each of the above expressions allows for deviations such as manufacturing accuracy and installation accuracy.

[0013] In each of the drawings referred to below, for the sake of easy understanding of the description, an orthogonal coordinate system may be shown that defines the X-axis direction, Y-axis direction, and Z-axis direction that are orthogonal to each other, with the Z-axis direction being the thickness direction of the wiring board.

[0014] FIG. 1 is a perspective view of a circuit board shown as an example of the embodiment. FIG. 2A is a schematic plan view of portion A shown in FIG. 1. FIG. 2B is a schematic cross-sectional view of portion A shown in FIG. 1. Specifically, FIG. 2B is a schematic cross-sectional view taken along the arrow II-II shown in FIG. 2A.

[0015] (Circuit Board) As shown in FIG. 1, the circuit board 1 has an insulating substrate 2 and a conductor 3.

[0016] (Insulating Substrate) The insulating substrate 2 is a substrate made of, for example, ceramic. As an example, the insulating substrate 2 may be formed using a ceramic composite material containing a glass component, so-called glass ceramic. Glass ceramic is any of a composite of a glass phase and ceramic particles, a composite of a glass phase and a crystal phase formed by crystallization of a part of the glass phase, a form in which the ceramic particles are present in the glass phase, and a form in which the glass phase is present at the grain boundaries between the ceramic particles. Specifically, the insulating substrate 2 may be LTCC (Low Temperature Co-fired Ceramics).

[0017] The insulating substrate 2 has a structure in which a plurality of insulating layers 20 are laminated. Among the plurality of insulating layers 20, the insulating layer 20 located on the surface layer of the insulating substrate 2 is defined as the surface layer insulating layer 21. The surface layer insulating layer 21 is located on one main surface 201 (see FIG. 2A) and the other main surface of the insulating substrate 2, respectively. The plurality of insulating layers 20 may have at least one inner layer insulating layer 23 between the two surface layer insulating layers 21.

[0018] The surface layer insulating layer 21 has a central region 212 and a peripheral region 211. The central region 212 is located at the center of the main surface of the surface layer insulating layer 21. The peripheral region 211 includes the outer edge of the surface layer insulating layer 21 and is located around the central region 212. As an example, when the circuit board 1 is divided into 9 equal parts vertically and 9 equal parts horizontally, the peripheral region 211 corresponds to the portion of three squares from the outer side, and the remaining central portion corresponds to the central region 212.

[0019] The conductor 3 is made of metal. For example, the conductor 3 may be a metal conductor made of copper. The conductor 3 includes a plurality of via conductors 31, 35 and a plurality of pad conductors 33, 37. The plurality of via conductors 31 are arranged on the main surface 201 of the surface layer insulating layer 21 so as to penetrate the surface layer insulating layer 21 in the thickness direction (here, the Z-axis direction). The via conductor 35 is arranged so as to penetrate the inner layer insulating layer 23. The pad conductor 33 is arranged on the main surface 201 of the surface layer insulating layer 21 and the main surface located opposite to the main surface 201. The pad conductor 37 is arranged between two adjacent inner layer insulating layers 23.

[0020] Among a plurality of via conductors 31 disposed in the surface insulating layer 21, a part of them are arranged in a circumferential shape, in other words, arranged to go around, in the peripheral region 211 of the main surface 201 of the surface insulating layer 21. Among the plurality of via conductors 31 arranged to go around the peripheral region 211, some of the via conductors 31 extend in a direction inclined with respect to the direction perpendicular to the main surface 201 of the surface insulating layer 21. Hereinafter, this via conductor 31 is referred to as an inclined via conductor 311.

[0021] Thereby, in the circuit board 1 according to the embodiment, defects are less likely to occur in the connection terminals formed on this circuit board 1. The reason therefor will be described with reference to FIGS. 3A and 3B. FIG. 3A is a schematic cross-sectional view of a circuit board having a via conductor extending in a direction perpendicular to the main surface of an insulating layer. FIG. 3B is a schematic cross-sectional view of a semiconductor device according to the embodiment. FIG. 3B shows a state in which the via conductor 31 extends in a direction inclined by an angle θ from the direction perpendicular to the main surface 201 of the insulating layer 20.

[0022] The semiconductor device 100X according to the comparative example shown in FIG. 3A includes a circuit board 1X and an electric element 101X. The electric element 101X is mounted on the circuit board 1X via a first connection terminal 102X. Specifically, the electric element 101X is electrically connected to the circuit board 1X via a via conductor 31X, a pad conductor 33X, a first connection terminal 102X, and a C4 (Controlled Collapsed Chip Connection) pad 103X. The surface insulating layer 21X and the via conductor 31X constituting the circuit board 1X are fixed by sintering. Note that the circuit board 1X has a plurality of insulating layers including the surface insulating layer 21X.

[0023] Suppose that the coefficient of thermal expansion of the circuit board 1X is larger than that of the electric element 101X. Also, there is a difference in the coefficient of thermal expansion between the surface insulating layer 21X constituting the circuit board 1X, for example, an insulating layer made of glass ceramics, and the via conductor 31X, for example, a metal conductor such as copper. For example, assume that the coefficient of thermal expansion of the via conductor 31X is larger than that of the surface insulating layer 21X.

[0024] When the coefficient of thermal expansion of the circuit board 1X is greater than that of the electrical element 101X, when the semiconductor device 100X is heated, the circuit board 1X tends to expand more than the electrical element 101X. At this time, since the circuit board 1X is restricted by the electrical element 101X from expanding greatly, a compressive stress acts on the circuit board 1X. On the other hand, since the electrical element 101X tends to be pulled by the expansion of the circuit board 1X, a tensile stress acts on the electrical element 101X. Thus, when the semiconductor device 100X is placed in a heated state, the circuit board 1X deforms such that its end bends toward the electrical element side.

[0025] As shown in FIG. 3B, the semiconductor device 100 according to the embodiment includes the above-described circuit board 1 and the electrical element 101. The electrical element 101 is mounted on the circuit board 1 via the first connection terminal 102. Specifically, the electrical element 101 is electrically connected to the circuit board 1 via the via conductor 31, the pad conductor 33, the first connection terminal 102, and the C4 pad 103. The surface insulating layer 21 and the via conductor 31 constituting the circuit board 1 are fixed by sintering.

[0026] Here, looking at the via conductors 31X, 31 provided on the circuit boards 1X, 1 in FIGS. 3A and 3B, the via conductors 31X, 31 are connected to the electrical elements 101X, 101 via the first connection terminals 102X, 102. The first connection terminals 102X, 102 are, for example, solder balls.

[0027] Regarding the circuit boards 1X, 1, looking at the connection (bonding) state with the electrical elements 101X, 101, since the C4 pads 103X, 103 of the electrical elements 101X, 101 and the pad conductors 33X, 33 of the circuit boards 1X, 1 are connected by the first connection terminals 102X, 102, the via conductors 31X, 31 have a stronger bonding force with the electrical elements 101X, 101 than the surface insulating layers 21X, 21.

[0028] That is, although the electrical elements 101X and 101 are connected to the circuit boards 1X and 1 in which the via conductors 31X and 31 and the surface insulating layers 21X and 21 are integrated, when viewed from the side of the electrical elements 101X and 101, the influence of the thermal expansion of the electrical elements 101X and 101 differs between the bonding force with the via conductors 31X and 31 and the bonding force with the surface insulating layers 21X and 21.

[0029] Next, when comparing the surface insulating layer 21X and the via conductor 31X in the circuit board 1X with respect to the coefficient of thermal expansion, there is a difference in the coefficient of thermal expansion between the ceramic surface insulating layer 21X and the metal via conductor 31X. As a result, stress due to the difference in the coefficient of thermal expansion also occurs between the surface insulating layer 21X and the via conductor 31X in the circuit board 1X.

[0030] Next, looking at the difference in the structure of the via conductors 31X in FIGS. 3A and 3B, in the semiconductor device 100X according to the comparative example shown in FIG. 3A, the via conductor 31X is in a state (vertical via conductor) facing in a direction substantially perpendicular to the main surface 201X of the circuit board 1X in the thickness direction. In such a case, the adhesion force between the surface insulating layer 21X and the via conductor 31X is mainly the adhesion force due to sintering between the two members. When a bending deformation occurs at the end of the circuit board 1X, shear deformation may occur at the interface between the via conductor 31X and the surface insulating layer 21X formed in the vicinity of the end according to the deformation of the circuit board 1X.

[0031] On the other hand, in the semiconductor device 100 according to the embodiment shown in FIG. 3B, the via conductor 31, specifically the inclined via conductor 311, is arranged to face in a direction inclined by an angle θ from the direction perpendicular to the main surface 201 of the circuit board 1. In this case, as can be seen from FIG. 3B, the inclined via conductor 311 has a longer length than the vertical via conductor within the thickness range of the surface insulating layer 21. Specifically, when the length of the via conductor 31X is L1 and the length of the via conductor 31 is L2, the allowable range of shear deformation increases by an amount of L2 - L1 = ΔL.

[0032] As a result, in the semiconductor device 100 according to the embodiment shown in FIG. 3B, the allowable range of shear deformation generated between the surface insulating layer 21 and the inclined via conductor 311 is larger than the allowable range of shear deformation generated between the surface insulating layer 21X and the via conductor 31X (inclined via conductor) in the semiconductor device 100X according to the comparative example shown in FIG. 3A.

[0033] Further, the length L2 of the inclined via conductor 311 shown in FIG. 3B is longer than the length L1 of the via conductor 31X (vertical via conductor) shown in FIG. 3A. For this reason, the area where the surface insulating layer 21 and the inclined via conductor 311 are adhered in the circuit board 1 according to the embodiment shown in FIG. 3B is also larger than the area where the surface insulating layer 21X and the via conductor 31X are adhered in the circuit board 1X according to the comparative example shown in FIG. 3A.

[0034] That is, when comparing the contact lengths between the inclined via conductor 311 and the via conductor 31X which is a vertical via conductor with the surface insulating layers 21X and 21, there are differences in the adhesion force and the range of shear deformation due to the difference in length. The inclined via conductor 311 has a greater shear deformation ability compared to the via conductor 31X which is a vertical via conductor.

[0035] Also, when the circuit boards 1 and 1X are bent and deformed upward (for example, when distorted), the structure of the inclined via conductor 3 [b]11[ / b] shown in FIG. 3B is more likely to cause displacement at the interface between the surface insulating layer 21 and the inclined via conductor 311 by the amount of inclination of the inclined via conductor 311 compared to the via conductor 31X which is a vertical via conductor shown in FIG. 3A. When the circuit board 1X shown in FIG. 3A is bent and deformed upward (for example, distorted), the interface between the surface insulating layer 21X and the via conductor 31X which is a vertical via conductor is likely to separate, in other words, is likely to crack. That is, the circuit board 1 according to the embodiment shown in FIG. 3B is less likely to have problems such as cracks compared to the circuit board 1X according to the comparative example shown in FIG. 3A.

[0036] When the circuit board 1 is subjected to a mechanical load, the inclined via conductor 311 is less likely to crack because the surface insulation layer 21 and the via conductor 31 are more likely to shift compared to the via conductor 31X which is a vertical via conductor.

[0037] It is also conceivable that the shear stress of the inclined via conductor 311 increases as its length increases. As a result, the circuit board 1 having the inclined via conductor 311 has enhanced durability.

[0038] From these, the circuit board 1 according to the embodiment having the inclined via conductor 311 has higher deformability and higher mechanical strength in the surface insulation layer 21 compared to the circuit board 1X having a vertical via conductor. In other words, when the end of the circuit board 1 bends upward (or downward) with the via conductor 31 being inclined, shear is likely to occur between the via conductor 31 and the insulation layer 20, so even if the end of the circuit board 1 bends, the interface between the insulation layer 20 and the via conductor 31 is difficult to separate. For this reason, the circuit board 1 is less likely to crack.

[0039] Since shear is likely to occur between the via conductor 31 and the insulation layer 20 in the circuit board 1 according to the embodiment having the inclined via conductor 311, it is easy to bend while maintaining mechanical strength. As a result, the circuit board 1 according to the embodiment has less stress concentration on the first connection terminal 102 compared to the circuit board 1X according to the comparative example. Therefore, since it is less likely that a problem occurs in the first connection terminal 102 in the circuit board 1 according to the embodiment, the mounting reliability of the semiconductor device 100 is high. The same can be said for the mounting structure 500 (see FIG. 7) in which the circuit board 1 is mounted on a mother board 501 having a higher coefficient of thermal expansion than the circuit board 1.

[0040] The above described the scenario of heating the semiconductor device 100 and the mounting structure 500, but this is the same even when the semiconductor device 100 and the mounting structure 500 are cooled from a high temperature state. In this case, the compressive stress and tensile stress generated in each member are opposite to the above, but it is similarly possible to obtain high mounting reliability.

[0041] (Method for determining the inclination of an inclined via conductor) Whether the inclined via conductors 311 are vertical or inclined can be determined, for example, as follows. First, the state of the via conductors 31 of the circuit board 1 is analyzed using an X-ray CT scanner. Analysis using the X-ray CT scanner is performed on both sides of the circuit board 1. Alternatively, the shape and structure may be determined by local observation, rather than by polishing the cross section of the circuit board 1 to prepare a sample with the via conductors 31 exposed. In this case, the sample with the polished cross section and the exposed via conductors 31 is observed under a microscope, and photographs are taken as necessary. Specifically, photographs of the portion including the surface insulating layer 21 and the via conductors 31 are taken. The microscope may be one that can magnify the length of the via conductors 31 to 50% or more of the screen or photograph size. For example, a scanning electron microscope, a digital microscope, or the like may be used.

[0042] Fig. 4 is a schematic cross-sectional view showing how to determine the angle of via conductor 31. Fig. 4 shows a schematic cross-sectional photograph of surface insulating layer 21 and via conductor 31 taken using a microscope.

[0043] As shown in Figure 4, a first straight line L11 is drawn on the photograph along the main surface 201 of the surface insulating layer 21, and then a second straight line L12 is drawn on the photograph in a direction perpendicular to the first straight line L11. The second straight line L12 is oriented in a direction perpendicular to the main surface 201 of the surface insulating layer 21. The second straight line L12 is used as a reference line.

[0044] Furthermore, a third straight line L13 is drawn along the side surface of the via conductor 31 visible in the photograph. The third straight line L13 is drawn along the side surface of the via conductor 31 that is closer to the second straight line L12. The third straight line L13 may be drawn by connecting the points where the side surface of the via conductor 31 intersects with the main surface 201 of the surface insulating layer 21 between both sides of the surface insulating layer 21. This method is effective, for example, when the side surface of the via conductor 31 is undulating.

[0045] Next, the angle (θ) between the second line L12 and the third line L13 is calculated. If this angle θ is 2° or less, the via conductor is considered to be vertical. If this angle θ is 5° or more, the via conductor is considered to be inclined. The inclination angle θ of an inclined via conductor is preferably 45° or less. This is because if the inclination angle is greater than 45°, the exposed positions of the via conductors 31 on both sides of the surface insulating layer 21 will differ significantly. Furthermore, if the inclination angle is greater than 45°, the via conductors 31 will be in a positional relationship such that, for example, the positions of the via conductors 31 on the upper main surface 201 of the surface insulating layer 21 (or the openings of the through holes formed in the surface insulating layer 21) on the lower main surface (or the openings of the through holes formed in the surface insulating layer 21) do not match when orthogonally projected onto a plane perpendicular to the thickness direction. If they are spaced apart by this much, the pitch of the via conductors 31 becomes too large, making it impossible to increase the integration density of the via conductors 31 per unit area.

[0046] (insulating substrate) As specifically described below, the insulating base 2 and the insulating layer 20 are preferably made of a glass ceramic material. Whether the insulating base 2 in the circuit board 1 is a laminate of a plurality of insulating layers 20 can be determined by observing the cross section of the circuit board 1 and checking the positions of the conductors 3 (for example, pad conductors 33) arranged in a direction along the main surface 201 of the insulating base 2. When the conductors 3 are arranged at a predetermined interval in the stacking direction, the area corresponding to the thickness between two conductors 3 adjacent in the stacking direction (the distance between one pad conductor 33 and the other pad conductor 33) may be determined to be the insulating layer 20.

[0047] (Other components that make up the circuit board) The insulating base 2 and the conductor 3 may be integrally formed by firing. In this case, the insulating base 2 and the conductor 3 may be formed by simultaneous firing. In this case, the insulating base 2 and the conductor 3 that constitute the circuit board 1 may be an integral sintered body. In other words, the insulating base 2 and the conductor 3 that constitute the circuit board 1 may be integrally sintered.

[0048] The conductor 3 may include multiple wirings. For example, the conductor 3 may include via conductors 35 and pad conductors 37 located on the inner insulating layer 23 in addition to the pad conductors 33 located on the surface insulating layer 21 (see FIG. 2B). The conductor 3 may also include a solid conductor. The solid conductor may be used as a conductor for power supply or ground in an electric circuit.

[0049] The pad conductors 33 and 37 are disposed on the via conductors 31 and 35 and joined so as to be electrically connected to the via conductors 31 and 35. Specifically, the pad conductors 33 and 37 and the via conductors 31 and 35 are sintered integrally so as to be electrically connected to each other.

[0050] The circuit board 1 may have a first connection terminal 102. The first connection terminal 102 is preferably either a solder ball or a conductive adhesive containing a metal component. The first connection terminal 102 is a structure that is thicker than the pad conductor 33. The first connection terminal 102 is formed so as to cover the entire surface of the pad conductor 33 formed on the surface of the circuit board 1. The first connection terminal 102 is formed so as to wet the entire surface of the pad conductor 33 formed on the surface of the circuit board 1. The first connection terminal 102 is formed so as to cover the entire surface of the C4 pad 103 formed on the electric element 101. The first connection terminal 102 is formed so as to wet the entire surface of the C4 pad 103 formed on the electric element 101.

[0051] Here, C4 is a type of flip-chip bonding technique. This method involves flipping an individual chip, which has numerous solders arranged as electrodes for electric element 101, and then mounting it on circuit board 1, and heating and bonding the entire circuit board 1 in a reflow furnace. Circuit board 1 is electrically connected to electric element 101 through pad conductors 33 and 37 and first connection terminal 102 on via conductors 31 and 35. Circuit board 1 is electrically connected to motherboard 501 through pad conductors 33 and 37 and second connection terminal 505 on via conductors 31 and 35.

[0052] (Aspect of the inclined via conductor group) FIG. 5 is a schematic plan perspective view when the surface insulating layer 21 is viewed from a direction perpendicular to the main surface 201 of the surface insulating layer 21 according to the embodiment.

[0053] Regarding the circuit board 1 according to the embodiment, a plurality of inclined via conductors 311 provided in the surface insulating layer 21 are defined as an inclined via conductor group. In the circuit board 1 according to the embodiment n, the inclined via conductor group preferably includes inclined via conductors 311 that are radially inclined in a direction from the central region 212 to the peripheral region 211 of the surface insulating layer 21 as shown in FIG. 5. In this case, the inclined via conductors 311 included in the inclined via conductor group are preferably radially inclined in a direction from the central region 212 to the peripheral region 211 of the surface insulating layer 21. All of the inclined via conductors 311 included in the inclined via conductor group are preferably radially inclined in a direction from the central region 212 to the peripheral region 211 of the surface insulating layer 21. Note that it is not necessary for all of the inclined via conductors 311 belonging to the inclined via conductor group to be radially inclined in a direction from the central region 212 to the peripheral region 211 of the surface insulating layer 21. Some of the inclined via conductors 311 may not be radially inclined in a direction from the central region 212 to the peripheral region 211 of the surface insulating layer 21.

[0054] Thus, the plurality of via conductors 31 may include a plurality of inclined via conductors 311 that extend radially in a direction from the central region 212 to the peripheral region 211 of the surface insulating layer 21 when the surface insulating layer 21 is viewed in a plan perspective from a direction perpendicular to the main surface 201 of the surface insulating layer 21.

[0055] Let the inclination angle θ be the angle at which the inclined via conductor 311 is inclined from the direction perpendicular to the main surface 201 of the surface insulating layer 21. Among the plurality of inclined via conductors 311 belonging to the inclined via conductor group, the inclined via conductor 311 located at the outermost periphery in the peripheral region 211 is referred to as the "outermost via conductor", and the inclined via conductor 311 located closer to the central region 212, that is, inside the outermost via conductor, is referred to as the "inner via conductor". The outermost via conductor is located in the peripheral region 211. The inner via conductor may be located in the peripheral region 211 or may be located in the central region 212. Note that FIG. 5 shows only the outermost via conductor among the outermost via conductor and the inner via conductor.

[0056] The inclined via conductor group may include a plurality of outermost via conductors and a plurality of inner via conductors. In this case, the inclined via conductor group preferably includes an outermost via conductor having an inclination angle larger than the inclination angle of the inner via conductor. For example, the inclination angle of at least one outermost via conductor among the plurality of outermost via conductors is preferably larger than the inclination angle of at least one inner via conductor among the plurality of inner via conductors. Also, the inclination angles of all the outermost via conductors included in the inclined via conductor group may be larger than the inclination angles of all the inner via conductors included in the inclined via conductor group.

[0057] Thus, when the angle at which the inclined via conductor 311 is inclined from the direction perpendicular to the main surface 201 of the surface insulating layer 21 is defined as the inclination angle, the inclination angle of the outermost via conductor located at the outermost periphery of the peripheral region 211 among the plurality of inclined via conductors 311 may be larger than the inclination angle of the inner via conductor located closer to the central region than the outermost via conductor.

[0058] In the circuit board according to the embodiment, the inclined via conductor group preferably includes an inclined via conductor 311 whose inclination angle increases in the direction from the central region 212 to the peripheral region 211. In other words, the inclined via conductor 311 included in the inclined via conductor group preferably has an inclination angle that increases in the direction from the central region 212 to the peripheral region. Specifically, when, of both ends in the longitudinal direction of the inclined via conductor 311, the end located on the main surface 201 is defined as the first end and the end located opposite to the first end is defined as the second end, the inclined via conductor 311 is preferably inclined such that the first end is located closer to the outer edge of the surface insulating layer 21 than the second end.

[0059] The plurality of inclined via conductors 311 only needs to include at least one inclined via conductor 311 as described above. Further, all the inclined via conductors 311 included in the inclined via conductor group preferably have an inclination angle that increases in the direction from the central region 212 to the peripheral region 211.

[0060] In the circuit board 1 according to the embodiment, the shape of the main surface 201 of the surface insulating layer 21 may be a quadrilateral. Further, when the angle at which the inclined via conductor 311 is inclined from the direction perpendicular to the main surface 201 of the surface insulating layer 21 is defined as the inclination angle, the inclined via conductor group preferably includes, near the corner of the main surface 201 of the surface insulating layer 21, an inclined via conductor 311 having an inclination angle larger than the inclination angle of the inclined via conductor 311 located near the center of the side forming the shape of the main surface 201 of the surface insulating layer 21.

[0061] In other words, among the plurality of inclined via conductors 311, the inclination angle of the inclined via conductor 311 located at the corner of the main surface 201 of the surface insulating layer 21 is preferably larger than the inclination angle of the inclined via conductor 311 located at the center of the side forming the shape of the main surface 201. The inclination angle in this case is the inclination angle when the surface insulating layer 21 is viewed from the side in the direction facing the side. Further, the corner is the corner located at the end of the surface insulating layer 21 when the surface insulating layer 21 is viewed from the side in the direction facing the side. In other words, the corner is the corner formed by the side and another side continuous with the side.

[0062] The plurality of inclined via conductors 311 only needs to include at least one inclined via conductor 311 as described above. Also, for all the inclined via conductors 311 included in the inclined via conductor group, the inclination angle of the inclined via conductor 311 located near the corner of the main surface 201 of the surface insulating layer 21 should be larger than the inclination angle of the inclined via conductor 311 located near the center of the side forming the shape of the main surface 201.

[0063] In the circuit board 1 according to the embodiment, the inclined via conductor group preferably includes an inclined via conductor 311 whose inclination angle increases in the direction from near the center of the side to near the corner.

[0064] Specifically, when the surface insulating layer 21 is viewed in a side perspective from the direction facing the side, the inclination angle of the inclined via conductor 311 included in the inclined via conductor group should increase in the direction from near the center of the side to near the corner. The plurality of inclined via conductors 311 only needs to include at least one inclined via conductor 311 as described above. Also, the inclination angles of all the inclined via conductors 311 included in the inclined via conductor group should increase in the direction from near the center of the side to near the corner. In other words, when the surface insulating layer 21 is viewed in a side perspective from the direction facing the side, the inclined via conductor 311 should be inclined such that one end (the first end) located on the main surface 201 is closer to the outer edge of the surface insulating layer 21 than the other end (the second end).

[0065] As shown in FIG. 5, in the circuit board 1 according to the embodiment, the direction of the inclined via conductor 311 formed in the surface insulating layer 21 of the circuit board 1 faces in a direction that uniformly spreads when viewed from the center of the central region 212 of the surface insulating layer 21. From this, it is possible to suppress deformation, cracks, or disconnection of the first connection terminal 102 that occur due to the stress between the inclined via conductor 311 arranged in the peripheral region 211 of the circuit board 1 and a part of the surface insulating layer 21 existing around the inclined via conductor 311 over the entire circumference of the peripheral region.

[0066] In FIG. 5, via conductors 31 exposed on the upper surface side of the surface insulating layer 21 are connected by a two-dot chain line looping around them. Here, when comparing the area formed by a one-dot chain line connecting the via conductors 31 exposed on the lower surface side of the surface insulating layer 21 and the area formed by a two-dot chain line connecting the via conductors 31 exposed on the upper surface side of the surface insulating layer 21, the area formed by the two-dot chain line connecting the via conductors 31 exposed on the upper surface side of the surface insulating layer 21 is larger.

[0067] Here, the change rate of the distance between two via conductors 31 when the circuit board 1 is heated and thermally expanded is compared between two via conductors 31 with a relatively short distance and two via conductors 31 with a relatively long distance. For example, the change rate of the distance between two via conductors 31 respectively arranged near two corners closer to the central region 212 in the diagonal direction of the surface insulating layer 21 is compared with the change rate of the distance between two via conductors 31 arranged between the corners with the maximum distance within the surface insulating layer 21.

[0068] Here, the corners between which the distance is maximum within the surface insulating layer 21 refer to the two corners with the maximum distance on one diagonal line L21 (see FIG. 5) that crosses the central region 212 in the surface insulating layer 21. In this case, both of the two corners located on one diagonal line L21 are within the peripheral region 211. One diagonal line connecting the two via conductors 31 closer to the central region 212 and one diagonal line connecting the corners with the maximum distance within the surface insulating layer 21 are made to overlap on the same line. Although FIG. 5 shows two via conductors 31 arranged between the corners with the maximum distance within the surface insulating layer 21, two via conductors 31 respectively arranged near the two corners closer to the central region 212 in the diagonal direction of the surface insulating layer 21 are not shown.

[0069] Taking the thermal behavior observed in the circuit board 1 as an example, when the center of gravity of the surface insulating layer 21 is set as the origin O (reference point), when the circuit board 1 is heated and thermally expanded, the change amount of the distance between the via conductors 31 close to the origin O is smaller compared to the change amount of the distance between the via conductors 31 far from the origin O and with a large distance separation. In other words, when the center of gravity of the circuit board 1 is set as the origin O (reference point), the change amount of the distance between the via conductors 31 far from the origin O and with a large distance separation is larger compared to the change amount of the distance between the via conductors P close to the origin O. As a result, the stress generated in the via conductor 31 varies depending on the arrangement of the via conductors 31 provided on the circuit board 1.

[0070] Due to such a difference in stress generated in the via conductor depending on the arrangement of the via conductor, conventionally, in a semiconductor device having an electrical element mounted on a circuit board, among the connection terminals connecting the electrical element and the circuit board, problems are likely to occur in the connection terminals located in the peripheral region of the circuit board, particularly at the corners.

[0071] Therefore, the present disclosure can solve the problems that usually occur in the circuit board for the reasons described above by having the circuit board have the following configuration. That is, in the surface insulating layer 21, the inclined via conductors 311 provided in the surface insulating layer 21 are radially inclined in the direction from the central region 212 to the peripheral region 211 of the surface insulating layer 21, the inclination angle of the inclined via conductor 311 located at the outermost periphery in the peripheral region 211 is larger than the inclination angle of the inclined via conductor 311 at a position closer to the central region 212 inside the outermost periphery, the inclination angle of the inclined via conductor 311 increases in the direction from the central region 212 to the peripheral region 211, the inclination angle of the inclined via conductor 311 located near the corner of the main surface 201 of the surface insulating layer 21 is larger than the inclination angle of the inclined via conductor 311 located near the center of the side forming the shape of the main surface 201, and the inclination angle of the inclined via conductor 311 increases in the direction from near the center of the side to near the corner.

[0072] FIG. 6 is a schematic cross-sectional view showing a circuit board 1 including inclined via conductors 311 in surface insulating layers 21 on both the upper surface side and the lower surface side. Specifically, FIG. 6 is a schematic cross-sectional view taken along the line II-II shown in FIG. 2A.

[0073] As shown in FIG. 6, the surface insulating layers 21 having inclined via conductor groups are preferably disposed on both surfaces of the insulating substrate 2. In other words, the surface insulating layer 21 includes a first surface insulating layer 21 located on one main surface 201 of the insulating substrate 2 and a second surface insulating layer located on the other main surface 202 of the insulating substrate 2, and the inclined via conductors 311 are preferably located in both the first surface insulating layer 21 and the second surface insulating layer 21.

[0074] Also, as shown in FIG. 6, the inclined via conductor group preferably includes inclined via conductors 311 that are inclined in the same direction on both surfaces of the insulating substrate 2. In other words, the inclined via conductors 311 included in the inclined via conductor group are preferably inclined in the same direction on both surfaces of the insulating substrate 2.

[0075] For example, among both longitudinal ends of the inclined via conductor 311 located in the surface insulating layer 21 on the main surface 201 side, the end located on the main surface 201 is defined as the first end, and the end located opposite to the first end is defined as the second end. Also, among both longitudinal ends of the inclined via conductor 311 located in the surface insulating layer 21 on the main surface 202 side, the end located on the main surface 202 is defined as the third end, and the end located opposite to the third end is defined as the fourth end. In the example shown in FIG. 6, the inclined via conductor 311 located in the surface insulating layer 21 on the main surface 201 side is inclined such that the first end is located closer to the outer edge of the surface insulating layer 21 than the second end. Also, the inclined via conductor 311 located in the surface insulating layer 21 on the main surface 202 side is inclined such that the third end is located closer to the outer edge of the surface insulating layer 21 than the fourth end.

[0076] Thus, at least one of the plurality of inclined via conductors 311 located inside the first surface insulating layer (the surface insulating layer 21 on the main surface 201 side) is preferably inclined in the same direction as at least one of the plurality of inclined via conductors located inside the second surface insulating layer (the surface insulating layer 21 on the main surface 202 side).

[0077] All the inclined via conductors 311 included in the inclined via conductor group should be inclined in the same direction on both sides of the insulating substrate 2.

[0078] When the inclined via conductor group with the above-described configuration is arranged on both sides of the circuit board 1, if an electrical element 101 is mounted on one surface of the circuit board 1 and the other surface of the circuit board 1 is connected to the mother board, the connection reliability of both sides of the circuit board 1 can be improved.

[0079] FIG. 7 is a schematic cross-sectional view of a mounting structure 500 according to an embodiment. As shown in FIG. 7, the mounting structure 500 according to the embodiment has a semiconductor device 100 and a mother board 501. The semiconductor device 100 is mounted on the mother board 501 via a second connection terminal 505.

[0080] The semiconductor device 100 has a circuit board 1 and an electrical element 101. The electrical element 101 is mounted on a plurality of via conductors 31 (via conductors 31) arranged in the surface insulating layer 21 of the circuit board 1 via a first connection terminal 102.

[0081] From the above, it is suitable for the semiconductor device 100 in which an electrical element 101 (an example of a semiconductor element) is mounted on a plurality of via conductors 31 arranged in the surface insulating layer 21 of the circuit board 1 via a connection terminal (first connection terminal 102).

[0082] Also, it is suitable for a mounting structure in which the disclosed electrical element 101 is mounted on the mother board 501 via a connection terminal (second connection terminal 505).

[0083] The area of the circuit board 1 is, for example, 50 mm × 50 mm or more. The upper limit of the area of the circuit board 1 is, for example, 200 mm × 200 mm. The thickness of the circuit board 1 is, for example, 1 mm or more. Preferably, the thickness of the circuit board 1 is 1.5 mm or more. The upper limit of the thickness of the circuit board 1 is, for example, 3 mm.

[0084] In the circuit board 1, the number of stacked insulating layers 20 is, for example, 10 or more. Preferably, the number of stacked insulating layers 20 is 20 or more. More preferably, the number of stacked insulating layers 20 is 25 or more. The upper limit of the number of stacked insulating layers 20 is, for example, 50 layers. The number of via conductors 31 located inside the surface insulating layer 21 is, for example, 10,000 or more. The upper limit of the number of via conductors 31 located inside the surface insulating layer 21 is, for example, 500,000.

Example

[0085] (Preparation of Samples) First, a green sheet (200 mm × 200 mm × thickness 200 μm) containing raw material powder of glass ceramics was prepared. The raw material powder of glass ceramics was a mixed powder of an alkaline earth metal borosilicate glass and silica particles. Specifically, a mixed powder in which 50 parts by mass of silica particles were added to 100 parts by mass of the alkaline earth metal borosilicate glass was used. Also, a butyral-based organic resin was used as the organic vehicle for the green sheet.

[0086] For the conductor paste to form the conductor layer, a mixture of copper powder and alkaline earth metal borosilicate glass powder was used. A cellulose-based organic resin was used as the organic vehicle. As the solid content, a composition in which 30 parts by mass of alkaline earth metal borosilicate glass powder was added to 100 parts by mass of copper powder was adopted.

[0087] Next, the prepared green sheet was placed in a stainless steel frame for framing. Next, through holes for forming via conductors were formed in the framed green sheet using a laser processing machine. In the green sheet, the region where the through holes were formed had an effective area of 100 mm × 100 mm with the interval between the center positions of the through holes. The area that becomes the circuit board after firing is 106 mm × 106 mm.

[0088] As described below, since the circuit board of the present disclosure is manufactured using the constrained firing method, after the formation of the laminate, it is cut into an area of 106 mm × 106 mm. The shape of the opening of the through-hole is circular, and its diameter is 100 μm. Also, the arrangement of the through-holes is in a grid pattern (530 × 530 = 280,900), and the interval between the through-holes is 100 μm (the pitch between the through-holes is 200 μm).

[0089] Next, the through-holes of the green sheet formed were filled with a conductor paste to produce a pattern sheet having raw via conductors (the first pattern sheet). The screen printing method was used to fill the through-holes with the conductor paste.

[0090] Next, a conductor paste was printed on the through-holes of the above-described first pattern sheet to form raw pad conductors (the second pattern sheet). The raw pad conductors are circular in shape and have a diameter of 150 μm. For the outermost peripheral pad conductors, the pad conductors are connected by a thin conductor pattern so that a daisy chain can be formed in which all the pad conductors are electrically connected in series. Twenty second pattern sheets were produced.

[0091] A temporary mother laminate was produced using the second pattern sheet and a solid green sheet. The second pattern sheet was laminated in two layers from the outermost layers on both sides of the temporary mother laminate. A solid green sheet was used for the inner layer. The number of solid green sheets used for the temporary mother laminate was 16. The sheets were stacked so that the temporary mother laminate had two layers of the second pattern sheet, 16 solid green sheets, and another two layers of the second pattern sheet from one layer. Raw pad conductors were arranged on both surfaces of the outermost layer of the temporary mother laminate.

[0092] Next, a pressure heat treatment was performed on the temporary mother laminate to produce a mother laminate. The conditions for the pressure heat treatment were a pressure of 30 MPa, a temperature of 100 °C, and a time of 10 minutes.

[0093] Next, the mother laminate was cut to produce a first laminate that would become a circuit board after firing. Next, a second laminate was produced by sandwiching the first laminate with restraint sheets. That is, in the second laminate, restraint sheets are disposed on both main surfaces of the first laminate. As the restraint sheets, green sheets containing alumina as the main component and containing borosilicate glass powder were used. The content of borosilicate glass was 1% by mass.

[0094] Next, the second laminate was fired. This fired body is one in which a restraint sheet fired body is attached to a circuit board. The firing using the restraint sheet may hereinafter be referred to as restraint firing or a restraint firing method. The firing was performed under the conditions of degreasing in a moist nitrogen atmosphere and then holding at a maximum temperature of 900°C for 2 hours in a dry nitrogen atmosphere.

[0095] Next, the restraint sheet fired body was removed from the fired body to obtain a circuit board. The obtained circuit board had a planar area of 106 mm × 106 mm, the same as that of the second laminate. The thickness was 2.4 mm (120 μm × 20 layers).

[0096] FIG. 8 is a schematic side view of a circuit board manufactured using a restraint sheet. As shown in FIG. 8, in the circuit board manufactured by performing restraint firing, the side surface is a concave curved surface. For this reason, in the circuit board, via conductors located in the peripheral region of the surface insulation layer, which is the outermost layer in the stacking direction, are inclined. The fact that the thickness of the first laminate that becomes the circuit board after firing is 1 mm or more is also one of the factors causing the inclination of the via conductors.

[0097] The thickness of the surface insulation layer was determined by measuring the thickness between the bad conductors formed on both sides. A plating film was formed on the manufactured circuit board. The plating film was formed using an electroless plating method. The metal components of the plating film were nickel and gold formed in this order. The outermost surface of the plating film is gold. A total of 10 similar circuit boards were manufactured.

[0098] On the other hand, a circuit board was fabricated by normal firing as a comparative example without using a restraining sheet. The firing method without using a restraining sheet is hereinafter sometimes referred to as normal firing. Since the circuit board using normal firing does not use a restraining sheet, there is shrinkage in the planar direction. Also, the shrinkage rate in the thickness direction of the laminate before firing is different from that in the case of using restrained firing. In normal firing, the shrinkage rates in the planar direction and the thickness direction of the green laminate are approximately 20%. Therefore, via holes were formed, unfired via conductors were formed, and the unfired pad conductors and the number of laminations were adjusted to sizes considering the shrinkage rate in the normal firing of the green sheet. The unfired laminate used for normal firing was made by taking 5 solid green sheets and making them into 11 sheets. Conditions such as the maximum temperature during firing were made the same as those for restrained firing.

[0099] Next, separately, a silicon element having no functional circuit was prepared as an electrical element. The silicon element has an area of 103 mm × 103 mm and a thickness of 0.5 mm. The number of C4 pads was made the same as that of the circuit board. The C4 pads were formed as underlying electrodes of the C4 pads by depositing Al (aluminum) on the surface of the silicon element and performing an etching process. After this, an Au (gold) plating film was formed on the surface of the underlying Al electrode.

[0100] A high-temperature solder paste was used for the connection terminals between the silicon element and the circuit board. As the high-temperature solder paste, one with a molar ratio of Pb 80 (%) - Sn 20 (%) was used. The high-temperature solder paste was printed on the surface of the Au-plated pad conductor formed on the circuit board, and the silicon element was placed thereon and heat-treated in a reflow furnace. Note that eutectic solder (molar ratio of Pb 37 (%) - Sn 63 (%)), which is used as the solder paste when connecting the circuit board of the semiconductor device to the mother board, may be used for the connection terminals between the silicon element and the circuit board.

[0101] Two semiconductor devices were fabricated by mounting a silicon element on a circuit board. One of the two fabricated semiconductor devices was mounted on a motherboard to fabricate a mounted structure. Of the two fabricated semiconductor devices, the sample that was not used in the mounted structure was designated Sample 1, and the sample that was mounted on the motherboard was designated Sample 2.

[0102] A similar plating film was also formed on a normally fired circuit board that was separately fabricated without using a restraint sheet. Two semiconductor devices were fabricated by mounting a silicon element on a normally fired circuit board. One of the two fabricated semiconductor devices was mounted on a motherboard to fabricate a mounting structure similar to the semiconductor device using the constrained fired circuit board. Of the two fabricated semiconductor devices, the sample that was not used in the mounting structure was designated Sample 3, and the sample that was mounted on a motherboard was designated Sample 4.

[0103] An FR-4 board was used for the motherboard. The FR-4 board had an area of 150mm x 150mm and a thickness of 2mm. FR-4 is a standard classification established by the NEM (National Electrical Manufacturers Association). An FR-4 board is a board that meets the requirements of the FR-4 grade. To determine the pad positions on the motherboard to fit each circuit board, an FR-4 board with solid copper foil was first prepared, and then the copper foil was etched to form pad conductors on the surface of the FR-4 board.

[0104] The physical properties of the materials used in the fabricated semiconductor device are as follows: Electrical element (silicon) thermal expansion coefficient: 4.15 x 10 -6 / ℃, Young's modulus: 193 Gpa Insulation layer (glass ceramic) thermal expansion coefficient: 11.7 x 10 -6 / ℃, Young's modulus: 95 Gpa Via conductor (copper) thermal expansion coefficient: 17.7 x 10 -6 / ℃, Young's modulus: 130 Gpa

[0105] Next, temperature cycle tests were conducted on the fabricated semiconductor device and mounting structure. For the temperature cycle test, the state after performing 1,000 temperature cycle tests, each of which involved maintaining the temperature at -55°C for 10 seconds, 125°C for 10 seconds, and changing the temperature from -55°C to 125°C in 3 minutes, was observed and evaluated. The number of samples was as follows: 1 semiconductor device using a circuit board fabricated by the constrained firing method as the present sample, 1 mounting structure fabricated using the same semiconductor device as this semiconductor device, 1 semiconductor device using a circuit board of normal firing as a comparative example, and 1 mounting structure fabricated using the same semiconductor device as this semiconductor device.

[0106] The fabricated samples are as follows. Sample 1 is a semiconductor device using a circuit board obtained by constrained firing. Sample 2 is a mounting structure with the semiconductor device of Sample 1. Sample 3 is a semiconductor device using a circuit board obtained by normal firing. Sample 4 is a mounting structure with the semiconductor device of Sample 3.

[0107] Next, the circuit board was evaluated. The fabricated semiconductor device was analyzed for the state of via conductors using an X-ray CT device. The analysis using the X-ray CT device was performed on both sides of the circuit board. From the analysis using the X-ray CT device, it was confirmed that in the circuit board fabricated by the constrained firing method, the via conductors were inclined on both sides.

[0108] Moreover, the following characteristics were observed in the circuit board fabricated by the constrained firing method. When a plurality of inclined via conductors provided in the surface insulating layer were regarded as an inclined via conductor group, the inclined via conductor group was radially inclined in the direction from the central region to the peripheral region of the surface insulating layer.

[0109] In the circuit board fabricated by the constrained firing method, when the angle of inclination of the inclined via conductor from the direction perpendicular to the main surface of the surface insulating layer was defined as the inclination angle, among the inclined via conductor group, the inclination angle of the inclined via conductor located at the outermost periphery in the peripheral region was larger than the inclination angle of the inclined via conductor at a position closer to the central region inside the outermost periphery.

[0110] In the circuit board manufactured using the constrained firing method, in the inclined via conductor group, the inclination angle of the inclined via conductors increased in the direction from the central region toward the peripheral region.

[0111] In the circuit board manufactured using the constrained firing method, when the inclination angle of the inclined via conductors is defined as the angle inclined from the direction perpendicular to the main surface of the surface insulating layer, in the inclined via conductor group, the inclination angle of the inclined via conductors located near the corner of the main surface of the surface insulating layer was larger than the inclination angle of the inclined via conductors located near the center of the side forming the shape of the main surface.

[0112] In the circuit board manufactured using the constrained firing method, in the inclined via conductor group, the inclination angle of the inclined via conductors increased in the direction from near the center of the side toward the corner.

[0113] On the other hand, it was confirmed that the via conductors of the circuit board with normal firing were perpendicular to the main surface of the circuit board.

[0114] Further, for the manufactured circuit board, in order to examine the cross-section of the via conductors in detail, a sample was prepared by polishing the cross-section of the circuit board to expose the cross-section of the via conductors. FIG. 9 is a schematic perspective view showing the position of the polished surface of the circuit board.

[0115] As shown in FIG. 9, polishing was performed in a direction perpendicular to one side of the circuit board. The cross-section was polished until the outermost peripheral via conductors of the circuit board were seen in a horizontal row. The polished sample was observed with a digital microscope, and photographs of each of the locations P1 to P3 shown in FIG. 9 were taken. The observed locations were the side surfaces of the polished circuit board where the via conductors were exposed.

[0116] P1 is a region including the via conductors located at the outermost peripheral corner. P3 is a region at the center in one side along the polished side surface. P2 is a region located between P1 and P3.

[0117] In P1, one located at the outermost corner was evaluated. In P2 and P3, the angles θ of 3 to 5 via conductors were evaluated to obtain the average value.

[0118] The angle θ of the via conductor was obtained from the photographed photo as follows. On the photo, a straight line (first straight line) was drawn along the main surface of the surface insulating layer, and then a straight line (second straight line) oriented in a direction perpendicular to this first straight line was drawn. This second straight line was oriented at a right angle to the main surface of the surface insulating layer. This was used as the reference line. Also, a straight line (third straight line) was drawn along the side surface of the via conductor visible in the photo. The third straight line was drawn along the side surface of the via conductor that was closer to the second straight line as the side surface of the via conductor. The third straight line connected the points where the side surface of the via conductor and the main surface of the insulating layer intersected between both surfaces of the insulating layer. After that, the angle (θ) between the second straight line and the third straight line was obtained.

[0119] In Sample 1, the inclination angle θ of the via conductor located at the outermost corner of P1 was larger than the inclination angle θ of the via conductor formed in the region of P2. The inclination angle θ of the via conductor located at the outermost corner of P1 was 5 to 6°. The via conductors located at P3 of Sample 1 could all be regarded as vertical via conductors regardless of their positions. For the via conductors located at P2 of Sample 1, the inclination angle θ closer to the region of P1 was smaller than the inclination angle θ of the via conductor located at the outermost corner of P1 and larger than the angle θ closer to the region of P3. The via conductors of Sample 3 could all be regarded as vertical via conductors regardless of their positions. In Sample 3 and Sample 4, cracks as visible from the observation with a digital microscope were seen in the connection terminals connected to the via conductors located at the outermost corners of the circuit board.

[0120] Regarding the fabricated semiconductor device, the resistance of the daisy chain formed on the circuit board was evaluated. The results were that when the resistance value of Sample 1 was normalized to 1, Sample 2 was 1.2. Both Sample 3 and Sample 4 had values one digit higher than Sample 1.

[0121] Although the present disclosure has been described in detail above, the present disclosure is not limited to the above-described embodiments, and various changes, improvements, etc. are possible without departing from the gist of the present disclosure.

[0122] The embodiments disclosed this time should be considered as illustrative in all respects and not restrictive. Indeed, the above-described embodiments can be embodied in various forms. Also, the above embodiments may be omitted, substituted, or changed in various forms without departing from the scope and gist of the appended claims.

[0123] Note that the present technology can have the following configuration. (1) having an insulating substrate and a conductor, the insulating substrate having a plurality of insulating layers including a surface insulating layer located on the surface layer of the insulating substrate, the surface insulating layer having a central region and a peripheral region, the central region being located at the center of the main surface of the surface insulating layer, the peripheral region including the outer edge portion of the surface insulating layer and being located around the central region, the conductor being arranged in a ring shape in the peripheral region and including a plurality of via conductors penetrating the surface insulating layer in the thickness direction, the plurality of via conductors including inclined via conductors extending in a direction inclined with respect to the direction perpendicular to the main surface of the surface insulating layer, a circuit board. (2) The plurality of via conductors include a plurality of the inclined via conductors extending radially from the central region toward the peripheral region when the surface insulating layer is viewed in a plan view from a direction perpendicular to the main surface of the surface insulating layer, the circuit board according to (1). (3) The plurality of via conductors include a plurality of the inclined via conductors, When the angle at which the inclined via conductor is inclined from the direction perpendicular to the main surface of the surface insulating layer is defined as the inclination angle, among the plurality of inclined via conductors, the inclination angle of the inclined via conductor located at the outermost periphery of the peripheral region is larger than the inclination angle of the inclined via conductor located closer to the central region than the inclined via conductor, The circuit board according to (1) or (2). (4) The plurality of inclined via conductors include an inclined via conductor in which the inclination angle increases in a direction from the central region toward the peripheral region, The circuit board according to (3). (5) The shape of the main surface of the surface insulating layer is a quadrilateral, When the angle at which the inclined via conductor is inclined from the direction perpendicular to the main surface of the surface insulating layer is defined as the inclination angle, among the plurality of inclined via conductors, the inclination angle of the inclined via conductor located at the corner of the main surface of the surface insulating layer is larger than the inclination angle of the inclined via conductor located at the center of the side forming the shape of the main surface, The circuit board according to any one of (1) to (4). (6) The plurality of inclined via conductors include an inclined via conductor in which the inclination angle increases in a direction from the center of the side toward the corner of the main surface, The circuit board according to (5). (7) The surface insulating layer includes a first surface insulating layer located on one main surface of the insulating substrate and a second surface insulating layer located on the other main surface of the insulating substrate, The inclined via conductors are located on both the first surface insulating layer and the second surface insulating layer, The circuit board according to any one of (1) to (6). (8) At least one of the plurality of inclined via conductors located inside the first surface insulating layer is inclined in the same direction as at least one of the plurality of inclined via conductors located inside the second surface insulating layer, The circuit board according to (7). (9) (1) to (8) The circuit board according to any one of the above, A semiconductor element mounted via a first connection terminal on the plurality of via conductors arranged on the surface insulating layer of the circuit board A semiconductor device having (10) the semiconductor device according to (9), a motherboard, and having a mounting structure in which the semiconductor device is mounted on the motherboard via a second connection terminal.

Description of Reference Numerals

[0124] 1 Circuit board 2 Insulating substrate 3 Conductor 20 Insulating layer 21 Surface insulating layer 23 Inner insulating layer 31, 35 Via conductor 33, 37 Pad conductor 100 Semiconductor device 101 Electric element 102 First connection terminal 211 Peripheral region 212 Central region 311 Tilted via conductor 500 Mounting structure 501 Motherboard 505 Second connection terminal

Claims

1. having an insulating substrate and a conductor, wherein the insulating substrate has a plurality of insulating layers including a surface insulating layer located on the surface layer of the insulating substrate, the surface insulating layer has a central region and a peripheral region, the central region is located at the center of the main surface of the surface insulating layer, the peripheral region includes the outer edge of the surface insulating layer and is located around the central region, the conductor is arranged in a ring shape in the peripheral region and includes a plurality of via conductors that penetrate the surface insulating layer in the thickness direction, the plurality of via conductors include inclined via conductors that extend in a direction inclined with respect to the direction perpendicular to the main surface of the surface insulating layer, a circuit board.

2. The circuit board according to claim 1, wherein the plurality of via conductors include a plurality of the inclined via conductors that extend radially from the central region toward the peripheral region when the surface insulating layer is viewed in a plan view from a direction perpendicular to the main surface of the surface insulating layer.

3. The plurality of via conductors include a plurality of the inclined via conductors, when the angle of inclination of the inclined via conductor with respect to the direction perpendicular to the main surface of the surface insulating layer is defined as the inclination angle, among the plurality of the inclined via conductors, the inclination angle of the inclined via conductor located at the outermost periphery of the peripheral region is larger than the inclination angle of the inclined via conductor located closer to the central region than the inclined via conductor, the circuit board according to claim 1.

4. The circuit board according to claim 3, wherein the plurality of the inclined via conductors include the inclined via conductors in which the inclination angle increases in the direction from the central region toward the peripheral region.

5. the shape of the main surface of the surface insulating layer is a quadrilateral, when the angle of inclination of the inclined via conductor with respect to the direction perpendicular to the main surface of the surface insulating layer is defined as the inclination angle, among the plurality of the inclined via conductors, the inclination angle of the inclined via conductor located at the corner of the main surface of the surface insulating layer is larger than the inclination angle of the inclined via conductor located at the center of the side forming the main surface shape, the circuit board according to claim 1.

6. The circuit board according to claim 5, wherein the plurality of the inclined via conductors include the inclined via conductors in which the inclination angle increases in the direction from the center of the side toward the corner of the main surface.

7. the surface insulating layer includes a first surface insulating layer located on one main surface of the insulating substrate and a second surface insulating layer located on the other main surface of the insulating substrate, The circuit board according to claim 1, wherein the inclined via conductor is located in both the first surface insulating layer and the second surface insulating layer.

8. The circuit board according to claim 7, wherein at least one of the plurality of inclined via conductors located inside the first surface insulating layer is inclined in the same direction as at least one of the plurality of inclined via conductors located inside the second surface insulating layer.

9. A circuit board according to any one of claims 1 to 8, a semiconductor element mounted via a first connection terminal on the plurality of via conductors disposed on the surface insulating layer of the circuit board, and a semiconductor device having the same.

10. A semiconductor device according to claim 9, a mother board, and a mounting structure in which the semiconductor device is mounted on the mother board via a second connection terminal. ​

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