A / d converter circuit

Abstract

To provide an ADC circuit capable of converting an analog signal to digital data more accurately.SOLUTION: An A / D converter circuit 1 includes: a trigger signal generation circuit 20 for generating a plurality of first trigger signals having a predetermined phase difference based on a clock signal; a plurality of adjustment circuits 26_1 to 26_m each of which generates a second trigger signal which is a delayed first trigger signal; a plurality of A / D converters 10_1 to 10_m, to which the same analog signal is inputted to each of them and respectively convert the analog signal to a digital signal according to the second trigger signal; and a selection part 22 for selecting one first trigger signal from the plurality of first trigger signals. The adjustment circuit corresponding to the first trigger signal selected by the selection part generates the second trigger signal so that a delay amount of the second trigger signal generated for the inputted first trigger signal approaches to a predetermined time based on a reference signal which is the selected first trigger signal delayed for the predetermined time.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to an A / D converter circuit.

Background Art

[0002] Conventionally, an interleaved ADC circuit has been proposed that converts an analog signal into a digital signal by driving a plurality of A / D converters (hereinafter also referred to as "ADCs") with a predetermined phase difference (see Non-Patent Document 1).

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

[0004] [Summary] However, if the interval between the timings for processing the analog signal in a plurality of ADCs is not appropriate, distortion occurs in the output digital signal.

[0005] The present disclosure has been made in view of such circumstances, and one of its exemplary purposes is to provide an ADC circuit that can convert an analog signal into digital data with higher accuracy.

[0006] The A / D converter circuit according to an aspect of the present disclosure includes a trigger signal generation circuit that generates a plurality of first trigger signals having a predetermined phase difference based on a clock signal, a plurality of adjustment circuits that respectively generate second trigger signals obtained by delaying corresponding first trigger signals among the plurality of first trigger signals, a plurality of A / D converters that respectively input the same analog signal and convert the analog signal into a digital signal according to the corresponding second trigger signal among the plurality of second trigger signals, and a selection unit that selects one first trigger signal from the plurality of first trigger signals. The adjustment circuit corresponding to the first trigger signal selected by the selection unit generates the second trigger signal such that the delay amount of the generated second trigger signal with respect to the input first trigger signal approaches a predetermined time based on a reference signal obtained by delaying the selected first trigger signal by a predetermined time.

[0007] In addition, any combination of the above components, as well as those obtained by converting the expressions of the present disclosure among methods, apparatuses, systems, etc., are also effective as aspects of the present disclosure.

Brief Description of Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

[0009] [Detailed Description] [Overview] The overview of some exemplary embodiments of the present disclosure will be described. This overview is for the purpose of providing a basic understanding of the embodiments as a prelude to the detailed description to follow, and simplifies and describes some concepts of one or more embodiments. It is not intended to limit the scope of the invention or disclosure. This overview is not an all-inclusive overview of all possible embodiments, nor is it intended to identify the important elements of all embodiments or to delineate the scope of some or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or modification) or a plurality of embodiments (examples or modifications) disclosed in this specification.

[0010] The A / D converter circuit according to an embodiment includes a trigger signal generation circuit that generates a plurality of first trigger signals having a predetermined phase difference based on a clock signal, a plurality of adjustment circuits that respectively generate second trigger signals obtained by delaying corresponding first trigger signals among the plurality of first trigger signals, a plurality of A / D converters into which the same analog signal is respectively input and which respectively convert the analog signal into a digital signal according to the corresponding second trigger signal among the plurality of second trigger signals, and a selection unit that selects one first trigger signal from the plurality of first trigger signals. The adjustment circuit corresponding to the first trigger signal selected by the selection unit generates the second trigger signal such that the delay amount of the generated second trigger signal with respect to the input first trigger signal approaches a predetermined time based on a reference signal obtained by delaying the selected first trigger signal by a predetermined time.

[0011] According to this configuration, an analog signal can be converted into digital data with higher accuracy.

[0012] In one embodiment, the A / D converter circuit may further include a delay control circuit that controls the delay amount of the second trigger signal in the adjustment circuit. The delay control circuit may control the delay amount of the second trigger signal in the adjustment circuit corresponding to the selected first trigger based on the read value of the second trigger signal generated by the adjustment circuit corresponding to the selected first trigger at the rising or falling edge of the reference signal.

[0013] In one embodiment, when the number of the plurality of A / D converters is m where m is an integer of 2 or more, it may be m. The phases of the m first trigger signals may be different for each cycle of the clock signal. The delay control circuit may control the delay amount of the second trigger signal in the A / D converter corresponding to the selected first trigger based on the read value every m cycles of the clock signal.

[0014] In one embodiment, when the read value has not changed from the previous read value, the control circuit increases the delay amount of the second trigger signal in the A / D converter corresponding to the selected first trigger, and when the read value of the second trigger signal has changed from the previous read value, the control circuit may maintain the delay amount of the second trigger signal in the A / D converter corresponding to the selected first trigger.

[0015] In one embodiment, the adjustment circuit may include an input node to which the first trigger signal is input, an output node from which the second trigger signal is output, a plurality of delay circuits connected in series, and a plurality of switches. The input terminal of the delay circuit at the front end among the plurality of delay circuits may be connected to the input node. The plurality of switches may be provided between each adjacent two of the plurality of delay circuits and between the output node. The delay amount of the second trigger signal in the delay circuit may be determined by turning on any one of the plurality of switches and turning off the remaining switches.

[0016] (Background) As the performance of electronic devices in increasing communication speed, the speeding up of electronic devices is required. In particular, the speeding up and high-precision of the ADC circuit, which is the interface between the analog part and the digital part, are required. The time interleaving method is one of the methods to realize the requirement.

[0017] FIG. 1 is a diagram showing an interleaved ADC circuit 9 according to the prior art. The ADC circuit 9 according to the prior art is an interleaved method having two channels. As shown in FIG. 1, the ADC circuit 9 includes a divider circuit 90, two delay circuits 92a and 92b, two ADCs 94a and 94b, and an integration circuit 96.

[0018] The divider circuit 90 receives the clock signal CLOCK and inputs the clock signal CKdiv9 to each of the delay circuits 92a and 92b. The delay circuits 92a and 92b correct the phase of the input clock signal CKdiv9 and input the corrected clock signals CK91 and CK92 to the ADCs 94a and 94b. The clock signals CK91 and CK92 have a predetermined phase difference.

[0019] The analog signal AIN is input to each of the ADCs 94a and 94b. Based on the input clock signals CK91 and CK92, the ADCs 94a and 94b sample the analog signal AIN, perform A / D conversion, and output the digital signals DOUT91 and DOUT92 to the integration circuit 96. The integration circuit 96 integrates the digital signals DOUT91 and DOUT92 and outputs the digital data ADOUT9.

[0020] FIG. 2 is a diagram for explaining the operation of the ADC circuit 9 according to the related art. FIG. 2 shows the analog signal AIN, the clock signal CK91 input to the ADC 94a of the first channel, and the clock signal CK92 input to the ADC 94b of the second channel. Here, the phase difference between the clock signal CK91 and the clock signal CK92 is half a cycle.

[0021] At the rising timing of the clock signals CK91 and CK92, the analog signal AIN is sampled in each channel. In the analog signal AIN of FIG. 2, "1" is attached to the signal sampled by the ADC 94a of the first channel, and "2" is attached to the signal sampled by the ADC 94b of the second channel. By using the two-channel ADCs 94a and 94b, the analog signal AIN can be sampled at a sampling rate twice that of using a single ADC. For example, when the sampling rate of each of the ADCs 94b and 94b is 100 MSPS (Mega sample(s) per second), a sampling rate of 200 MSPS can be achieved.

[0022] However, spurious signals appear in the output digital data, causing distortion in the waveform. The reasons for the appearance of spurious signals include the following four mismatches. · Offset mismatch (offset mismatch existing between each ADC) · Timing mismatch (clock skew and mismatch of each delay group of each ADC) · Gain mismatch (gain mismatch of each ADC) · Bandwidth mismatch (mismatch due to the mutual relationship of two parameters (gain component and phase / frequency component) of each ADC) In the correction of the ADC timing (phase equalization), in the conventional circuit configuration, the correction algorithm and the adjustment circuit itself become complex, and the adjustment itself also becomes difficult.

[0023] Figure 3 is a diagram showing an example of digital data in which spurious signals appear. Figure 3 shows digital data output by a 4-channel interleaved ADC circuit. In Figure 3, the horizontal axis is the time axis, and the analog signal 900 input to the ADC circuit is shown by a solid line. In Figure 3, the digital signals obtained by A / D conversion by each of the four ADCs are shown by circles associated with the numbers of the corresponding ADC channels. When spurious signals appear, the waveform of the digital signal obtained by the ADC becomes a distorted waveform shifted from the analog signal 900.

[0024] In order to eliminate the distortion of the digital signal waveform, it is necessary to eliminate the mismatch between each ADC. As a means of eliminating the mismatch, there is a calibration method (circuit) that measures each ADC value and performs arithmetic processing and correction using a special circuit and a CPU (Central Processing Unit), etc. In order to perform high-precision calibration, high-precision measurement must be possible, the correction accuracy must be increased, and the comparison results of each ADC must match (eliminating the mismatch).

[0025] In order to perform accurate measurements, first, it is necessary that the timing for acquiring the data of each ADC to be compared is consistent (highly accurate). In the mechanism of a conventional interleaved ADC circuit, in the first place, since the phases of each ADC are different, a method and mechanism for making the data acquisitions coincide or for obtaining them by an algorithm are required, and the mechanism and its layout become complicated. For this reason, the mechanism (circuit) itself for detecting and adjusting the timing also becomes complicated, and adjustment is difficult.

[0026] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Also, the embodiments are illustrative rather than limiting the disclosure and the invention, and not all of the features and their combinations described in the embodiments are necessarily essential to the disclosure and the invention.

[0027] In this specification, the phrase "member A is in a state of being connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0028] Similarly, the phrase "member C is in a state of being connected (provided) between member A and member B" includes not only the case where member A and member C or member B and member C are directly connected, but also the case where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0029] FIG. 4 is a block diagram of an ADC circuit 1 according to an embodiment of the present disclosure. The ADC circuit 1 converts an analog signal AIN into digital data ADOUT. The ADC circuit 1 is of an interleaved type having m (m is an integer of 2 or more) channels. The ADC circuit 1 includes m ADCs 10_1 to 10_m, a reference ADC 10_r, a trigger signal generation circuit 20, a selector 22 (multiplexer), buffer circuits 24_1 to 24_m, 24_r, adjustment circuits 26_1 to 26_m, 26_r, a controller 30, a delay control block 40, and an integration circuit 50.

[0030] The trigger signal generation circuit 20 generates m trigger signals CK1_1 to CKm_1 (first trigger signals) having a predetermined phase difference based on the clock signal CLOCK. The generated trigger signals CK1_1 to CKm_1 are respectively input to the corresponding adjustment circuits among the adjustment circuits 26_1 to 26_m via the corresponding buffer circuits among the buffer circuits 24_1 to 24_m. Also, the trigger signals CK1_1 to CKm_1 are input to the selector 22.

[0031] FIG. 5 is a diagram showing the trigger signals CK1_1 to CKm_1 generated by the trigger signal generation circuit 20 according to the present embodiment. The trigger signals CK1_1 to CKm_1 are each a rectangular pulse wave, and the pulse width thereof is one period of the clock signal CLOCK. Also, the period of the trigger signals CK1_1 to CKm_1 is m periods of the clock signal CLOCK. Further, the trigger signals CK1_1 to CKm_1 have different phases by one period of the clock signal CLOCK.

[0032] Returning to FIG. 4, the configuration of the ADC circuit 1 will be described. The adjustment circuits 26_1 to 26_m respectively adjust the phases of the input trigger signals among the trigger signals CK1_1 to CKm_1. As a result, trigger signals CK1_2 to CKm_2 (second trigger signals) are generated. In the present embodiment, the adjustment circuits 26_1 to 26_m respectively delay the input trigger signals according to the input control signals among the control signals DLYSKEW1 to DLYSKEWm. The delay amounts of the trigger signals CK1_2 to CKm_2 in the adjustment circuits 26_1 to 26_m have magnitudes corresponding to the control signals DLYSKEW1 to DLYSKEWm. The trigger signals CK1_2 to CKm_2 are respectively input to the corresponding ADCs among the ADCs 10_1 to 10_m.

[0033] In the present embodiment, although details will be described later, the adjustment circuits 26_1 to 26_m corresponding to the first trigger signals CK1_1 to CKm_1 selected by the selector 22 generate the second trigger signals CK1_2 to CKm_2 such that the delay amounts of the generated second trigger signals CK1_2 to CKm_2 with respect to the input first trigger signals CK1_1 to CKm_1 approach a predetermined time based on a reference signal CKdref obtained by delaying the selected first trigger signal CK_ref1 by a predetermined time.

[0034] The ADCs 10_1 to 10_m respectively receive the same analog signal AIN, and convert the analog signal AIN into digital signals DOUT_1 to DOUT_m according to the corresponding second trigger signals among the plurality of second trigger signals CK1_2 to CKm_2.

[0035] The selector 22 selects one of the trigger signals CK1_1 to CKm_1 generated by the trigger signal generation circuit 20 and outputs the selected trigger signal CKref_1. The trigger signal CKref_1 is input to the adjustment circuit 26_r and the delay control block 40 via the buffer circuit 24_r.

[0036] The circuit block BLK including the selector 22 and the path for inputting the trigger signals CK1_1 to CKm_1 to the selector 22 is a simple and small circuit, and it is easy to arrange them in proximity and with equal-length wiring. Therefore, it is possible to highly accurately match the delay times from the trigger signals CK1_1 to CKm_1 of each channel to the reference signal CKdref.

[0037] The adjustment circuit 26_r adjusts (delays) the phase of the trigger signal CKref_1 according to the control signal DLYSKEWm+1 and generates the trigger signal CKref_2. The trigger signal CKre_2 is input to the reference ADC10_r.

[0038] The delay control block 40 controls the delay amounts of the trigger signals CK1_2 to CKm_2 and CKref_2 in the adjustment circuits 26_1 to 26_m and 26_r based on the trigger signal CKref_1 selected by the selector 22. The delay control block 40 includes a delay circuit 42 and (m + 1) delay control circuits 44_1 to 44_m+1.

[0039] The delay circuit 42 delays the input trigger signal CKref_1 by a predetermined time and generates the reference signal CKdref. The delay time in the delay circuit 42 is a fixed time independent of the trigger signal selected by the selector 22. The reference signal CKdref is input to the delay control circuits 44_1 to 44_m+1.

[0040] The delay control circuits 44_1 to 44_m+1 control the operations of the corresponding adjustment circuits among the adjustment circuits 26_1 to 26_m and 26_r based on the corresponding trigger signals among the trigger signals CK1_2 to CKm_2 and CKref_2 and the reference signal CKdref. In this embodiment, among the delay control circuits 44_1 to 44_m+1, the delay control circuit corresponding to the trigger signal CKref_1 selected by the selector 22 controls the operation of the adjustment circuit.

[0041] The delay control circuits 44_1 to 44_m control the delay amounts of the trigger signals CK1_2 to CKm_2 in the adjustment circuits 26_1 to 26_m corresponding to the selected first trigger CKdref based on the read values of the trigger signals CK1_2 to CKm_2 generated by the selected adjustment circuits 26_1 to 26_m at the rising or falling edge of the reference signal CKdref.

[0042] For example, the delay control circuit 44_1 generates a control signal DLYSKWE1 for controlling the operation of the adjustment circuit 26_1 based on the trigger signal CK1_2 generated by the adjustment circuit 26_1 and the reference signal CKdref generated by the delay circuit 42.

[0043] The function of the delay control circuit 44_1 is realized by the detection unit 440 and the counter 442. The delay control circuits 44_2 to 44_m+1 may be configured in the same manner as the delay control circuit 44_1.

[0044] The detection unit 440 detects the trigger signal CK1_2 at the timing when the reference signal CKdref rises (or falls), and outputs a signal indicating the result (low or high) to the counter 442. The counter 442 generates a control signal DLYSKEW1 according to the signal output by the detection unit 440.

[0045] Specifically, the counter 442 counts the number of times the detection unit 440 detects a high trigger signal CK1_2 from the start of the control of the adjustment circuit 26_1, and generates a control signal DLYSKEW1 according to the number of times. In this embodiment, the counter 442 generates the control signal DLYSKEW1 so that the delay amount of the trigger signal CK1_2 in the adjustment circuit 26_1 increases as the count number increases. Also, the counter 442 maintains the control signal DLYSKEW1 when the signal FLG1 goes low.

[0046] The controller 30 controls the operations of the selector 22 and the delay control block 40. Specifically, the controller 30 generates a signal SEL that designates the trigger signals CK1_1 to CKm_1 selected by the selector 22. The signal SEL is transmitted to the selector 22 and the delay control block 40. Also, the controller 30 generates a signal SKEWON for controlling the on and off states of the delay control block 40.

[0047] The integrated circuit 50 integrates the digital signals DOUT_1 to DOUT_m and DOUT_r generated by the ADCs 10_1 to 10_m and 10_r of each channel to generate digital data ADOUT.

[0048] Before explaining the details of the adjustment circuits 26_1 to 26_m of the ADC circuit 1 according to this embodiment, with reference to FIGS. 6 to 9, the transmission of the trigger signal when the adjustment circuits 26_1 to 26_m are not present will be described.

[0049] FIG. 6 is a diagram for explaining the transmission paths 28_1 and 28_2 when two trigger signals CK1_1 and CK2_1 are transmitted with the same delay amount. FIG. 7 is a timing chart when two trigger signals CK1_1 and CK2_1 are transmitted with the same delay amount. FIG. 8 is a diagram for explaining the transmission paths 28_3 and 28_4 when two trigger signals CK1_1 and CK2_1 are transmitted with different delay amounts. FIG. 9 is a timing chart when two trigger signals CK1_1 and CK2_1 are transmitted with different delay amounts.

[0050] As shown in FIG. 6, when the adjustment circuits 26_1 and 26_2 are not present, the trigger signals CK1_1 and CK2_1 are transmitted to the circuit blocks 12_1 and 12_2 including the ADCs 10_1 and 10_2 via the transmission paths 28_1 and 28_2. The transmission paths 28_1 and 28_2 include a delay element 280 that delays the trigger signals CK1_1 and CK2_2. The delay element 280 includes a resistor and parasitic capacitance, etc.

[0051] The trigger signals CK1_1 and CK2_1 are delayed by the delay element 280, and the affected trigger signals CK1_3 and CK2_3 are input to the circuit blocks 12_1 and 12_2. At this time, it is assumed that the delay amounts caused by the delay element 280 in the transmission paths 28_1 and 28_2 are the same, and the same delay amount occurs in the trigger signals CK1_3 and CK2_3.

[0052] In this case, as shown in FIG. 7, the delay amount td1_1 of the trigger signal CK1_3 with respect to the trigger signal CK1_1 is the same as the delay amount td2_1 of the trigger signal CK2_3 with respect to the trigger signal CK2_1. As a result, it becomes possible to perform A / D conversion with an appropriate phase difference in the ADC of the circuit block 12_1 and the ADC of the circuit block 12_2.

[0053] However, as shown in FIG. 8, the delay amounts caused by the delay element 280 in the transmission paths 28_3 and 28_4 may be different. In this case, as shown in FIG. 9, the delay amount td1_2 of the trigger signal CK1_4 input to the circuit block 12_1 is different from the delay amount td2_2 of the trigger signal CK2_4 input to the circuit block 12_2. As a result, A / D conversion is performed with a shifted phase difference between the ADC of the circuit block 12_1 and the ADC of the circuit block 12_2.

[0054] FIG. 10 is a block diagram of the adjustment circuit 26 according to the present embodiment. The adjustment circuit 26 includes 2t (t is an integer of 1 or more) delay circuits 260_1 to 260_2t, 2t switches SW_ _1 to SW_2t, an input node 262, and an output node 264. The signal IN input to the input node 262 is the trigger signals CK1_1 to CKm_1 and CKref_1 generated by the trigger signal generation circuit 20. The signal OUT output from the output node 264 is the trigger signals CK1_2 to CKm_2 and CKref_2.

[0055] The delay circuits 260_1 to 260_2t each delay the input signal by a predetermined time Δt. The delay circuits 260_1 to 260_2t are connected in series in this order. The input terminal of the front-end delay circuit 260_1 is connected to the input node 262 of the adjustment circuit 26. The output terminal of the rear-end delay circuit 260_2t is connected to the output node 264 via the switch SW_2t.

[0056] The switches SW_k (k: 1 to 2t) are provided between the output terminals of the delay circuits 260_k and the output node 264. The on / off states of the switches SW_1 to SW_2t are controlled by the control signal DLYSKEW. Depending on the control signal DLYSKEW, one of the switches SW_1 to SW_2t is turned on and the remaining switches are turned off, thereby generating a delay amount corresponding to the turned-on switch. Specifically, by turning on the switch SW_k and turning off the remaining switches, an output signal OUT is generated in which the signal IN input to the adjustment circuit 26 is delayed by Δt × k.

[0057] FIG. 11 is a block diagram showing a delay control circuit 44 for generating the control signals DLYSKEW[1] to DLYSKEW[2t] of the adjustment circuit 26. FIG. 12 is a timing chart showing the operation of the delay control circuit 44. The delay control circuits 44_1 to 44_m+1 are configured in the same manner as the delay control circuit 44.

[0058] As shown in FIG. 11, the detection unit 440 of the delay control circuit 44 includes D flip-flop circuits 602, 604, a NAND circuit 606, and an AND circuit 608. The D flip-flop circuits 602, 610_1 to 610_2t are positive-edge type, and the D flip-flop circuit 604 is negative-edge type.

[0059] The D flip-flop circuit 602 is provided such that a reference signal CKdref is input to the clock input terminal and a trigger signal CKx_2 (x: 1 to m) is input to the data input terminal. The D flip-flop circuit 604 is provided such that a signal obtained by inverting the reference signal CKdref is input to the clock input terminal and the output signal FLGx_1 (x: 1 to m) of the D flip-flop circuit 602 is input to the data input terminal. The NAND circuit 606 is provided such that the output signal FLGx_2 (x: 1 to m) of the D flip-flop circuit 604 is input to the first input terminal and the reference signal CKdref is input to the second input terminal. The AND circuit 608 is provided such that the output signal FLGx_1 of the D flip-flop circuit 602 is input to the first input terminal and the output signal A of the NAND circuit 606 is input to the second input terminal.

[0060] The counter 442 of the delay control circuit 44 includes D flip-flop circuits 610_1 to 610_2t. The D flip-flop circuits 610_1 to 610_2t generate a plurality of control signals DLYSKEW[1] to DLYSKEW[2t] having a predetermined phase difference. When DLYSKEW[k] is high, the switch SW_k of the adjustment circuit 26 is turned on, and when DLYSKEW[k] is low, the switch SW_k of the adjustment circuit 26 is turned off.

[0061] The output signal B of the AND circuit 608 is commonly input to the respective clock input terminals of the D flip-flop circuits 610_1 to 610_2t. Further, set signals S[1] to S[2t] are input to the respective set terminals of the D flip-flop circuits 610_1 to 610_2t, and a reset signal RST is input to each of the reset terminals of the D flip-flop circuits 610_1 to 610_2t.

[0062] The output terminals of the D flip-flop circuits 610_1 to 610_2t are connected to the data input terminals of another one of the D flip-flop circuits 610_1 to 610_2t. Specifically, the output terminal of the D flip-flop circuit 610_f (f = 1 to 2t - 1) is connected to the data input terminal of the D flip-flop circuit 610_f + 1. For example, the output terminal of the D flip-flop circuit 610_1 is connected to the data input terminal of the D flip-flop circuit 610_2. Also, the output terminal of the D flip-flop circuit 610_2t is connected to the data input terminal of the D flip-flop circuit 610_1.

[0063] FIG. 12 is a timing chart for explaining the operation of the delay control circuit 44 according to the present embodiment. The set signals S[2t:1] shown in FIG. 12 represent the set signals S[1] to S[2t].

[0064] At timing t0, all of the set signals S[1] to S[2t] are 0, and the reset signal RST goes from low to high. At this time, all of the control signals DLYSKEW[1] to DLYSKEW[2t] output from the D flip-flop circuits 610_1 to 610_2t are low. Thereafter, at timing t1, the reset signal RST goes from high to low.

[0065] At timing t2, the set signal S[1] goes high. At timing t3, the reset signal RST goes from low to high. In response to this, the control signal DLYSKEW[1] of the D flip-flop circuit 610_1 goes high. The control signals DLYSKEW[2] to DLYSKEW[2t] of the other D flip-flop circuits 610_2 to 610_2t are low. By these control signals DLYSKEW[1] to [2t], the switch SW_1 of the adjustment circuit 26 is turned on, and the remaining switches SW_2 to SW_2t are turned off.

[0066] Next, at the timing when the output signal B falls at timing t4, the control signal DLYSKEW[1] turns off and the control signal DLYSKEW[2] turns on. Thereafter, each time the output signal B falls, the control signal DLYSKEW[k] that is on turns off and the next control signal DLYSKEW[k + 1] turns on. At timing t5, the control signal DLYSKEW[n] turns on.

[0067] At timing t6, at the timing when the reference signal CKdref rises, the trigger signal CKx_2 with the delay amount adjusted changes from high to low. In response to this, the output signal FLGx_1 changes from high to low. As a result, the output signal B is maintained at low and the control signal DLYSKEW[n] is maintained at high after timing t7 when the reference signal CKdref next falls.

[0068] FIG. 13 is a timing chart showing an example of the operation of the delay control circuit 44_2. Here, an example will be described in which the selector 22 selects the trigger signal CK2 among the trigger signals CK1 to CKm and a reference signal CKdref obtained by delaying that signal is generated.

[0069] During the period from timing t10 to t11 when the signal SKEWON is off, the trigger signal CK2_2 generated by the adjustment circuit 26_2 lags behind the trigger signal CK2_1 generated by the trigger signal generation circuit 20 by a delay time tdly(0). This delay time tdly(0) is the delay amount that occurs in the circuit block BLK including the selector 22 and is also the delay amount that occurs in the trigger signal CKref. Here, the delay time tdly(s) (s is an integer from 0 to 2t - 1) is a time corresponding to the control signal DLYSKEW2. Also, the reference signal CKdref lags behind the trigger signal CK2_1 by a fixed delay amount T.

[0070] At timing t11, SKEWON switches on. As a result, the operation of adjustment circuit 26_2 is controlled by delay control circuit 44_2. Delay control circuit 44_2 controls the delay amount of trigger signal CK2_2 based on the read value of trigger signal CK2_2 at the rising edge of reference signal CKdref every m cycles of clock signal CLOCK.

[0071] When the read value has not changed from the previous read value (specifically, remains high), delay control circuit 44_2 increases the delay amount of trigger signal CK2_2. When the read value has changed from the previous read value (specifically, changes from high to low), delay control circuit 44_2 maintains the delay amount of trigger signal CK2_2.

[0072] In response to the control of delay control circuit 44_2, adjustment circuit 26_2 delays trigger signal CK2_1. Accordingly, adjustment circuit 26_2 generates trigger signal CK2_2 which is obtained by delaying trigger signal CK2_1 by delay time tdly(1). The delay time tdly(1) may be Δt. At this time, at the rising edge (timing t12) of reference signal CKdref, trigger signal CK2_2 remains high. Accordingly, at the falling edge timing of reference signal CKdref, the code of control signal DLYSKEW2 is increased from 0 to 1. Accordingly, adjustment circuit 26_2 further delays trigger signal CK2_1 (for example, by delay time tdly(2)).

[0073] In this way, the reading of trigger signal CK2_2 at the rising edge of trigger signal CKdref, the change of the value of DLYSKEW2, and the delay of trigger signal CK2_1 according to the value are repeated.

[0074] At timing t13, after SKEWON turns on, the rising edge of the n-th (where n is an integer of 2 or more) reference signal CKdref occurs. At this time, the trigger signal CK2_2 is delayed by tdly(n) and is low at timing t13. In response to this low level, the output signal FLGx_1 changes from high to low, and the count value is maintained at n when the reference signal CKdref next falls. As a result, the delay amount tdly(n) of the trigger signal CK2_2 is maintained.

[0075] At timing t4, SKEWON turns off. As a result, the trigger signal CK2_2 becomes a signal delayed by tdly(n) with respect to the trigger signal CK2_1. Thereby, the delay time of the trigger signal CK2_2 can be made closer to the fixed delay time T. Note that the difference between tdly(n) and the delay time T is smaller than the difference between tdly(n) and tdly(n - 1).

[0076] By performing the same processing as the trigger signal CK2_1 for the other trigger signals CK1_1, CK3_1 to CKm_1, the delay times of the trigger signals CK1_2, CK3_2 to CKm_2 can be made closer to the delay time T. Thus, in this embodiment, it is possible to equalize the delay amounts of the trigger signals CK1_2 to CKm_2 from the trigger signals CK1 to CKm with respect to the reference signal CKdref.

[0077] FIG. 14 is a diagram for explaining the change of the code of the control signal DLYSKEW according to the present embodiment. The horizontal axis represents the code of DLYSKEW, and the vertical axis represents the delay amount (Delay) of the trigger signal CK2_2. In the present embodiment, Delay is adjusted by the adjustment circuit in the range of 0 to n with respect to the value of DLYSKEW so that DLYSKEW increases with the passage of time. As DLYSKEW increases, the delay amount increases. When the trigger signal CKx_2 goes low at the rising timing of the reference signal CKref as described above, the control signal DLYSKEW is maintained at a certain value (n). As a result, the adjustment circuit is controlled so that Delay is maintained at the delay amount corresponding to the control signal DLYSKEW (n).

[0078] Note that the control of the control signal DLYSKEW according to the present embodiment converges quickly with respect to the shift amount of the trigger signal. Also, by using a shifter circuit method such as the delay control circuit 44, it is possible to achieve simple and high-speed control.

[0079] According to the A / D converter circuit 1 according to the present embodiment, the adjustment circuits 26_1 to 26_m corresponding to the first trigger signal CKref_1 selected by the selector 22 (selection unit) generate the second trigger signals CK1_2 to CKm_2 for the input first trigger signals CK1_1 to CKm_1 based on the reference signal CKdref obtained by delaying the selected first trigger signal CKref_1 by a predetermined time, so that the delay amounts of the generated second trigger signals CK1_2 to CKm_2 approach the predetermined time. Thereby, the delay amounts of the second trigger signals CK1_2 to CKm_2 can be made uniform, and it becomes possible to convert the analog signal AIN into digital data ADOUT with higher accuracy.

[0080] Also, the configuration of the A / D converter circuit 1 according to the embodiment (specifically, the circuit block BLK and the delay control block 40, etc.) is simple for the circuit itself, and thus miniaturization and low power consumption can be realized.

[0081] (First Modification) In the above-described embodiment, mainly, an example in which the adjustment circuit 26 changes the delay amount so as to increase the delay amount has been described. However, the present invention is not limited to this, and the adjustment circuit 26 may change the delay amount so as to decrease the delay amount.

[0082] FIG. 15 is a diagram showing the relationship between the value of DLYSKEW and the delay amount (Delay) according to the first modification. In the first modification, starting from a value of 2t for DLYSKEW, the value may be gradually decreased to search for an n such that the delay amount by the adjustment circuit 26 becomes the fixed delay amount by the delay circuit 42. Note that according to this method, it may take time until convergence to the optimum value depending on the deviation amount of the delay amount and the cover range of the delay amount.

[0083] (Modification 2) FIG. 16 is a diagram showing the relationship between the value of DLYSKEW and the delay amount (Delay) according to the second modification. In the second modification, the value of DLYSKEW is changed so as to search for the optimum value of the delay amount by the binary search method. According to this method, although the convergence to the optimum value is fast, there is a possibility that the control circuit becomes complicated.

[0084] (Supplementary Note) Regarding the embodiments according to the present disclosure, specific terms have been used for the description, but this description is merely an exemplification for helping understanding, and does not limit the present disclosure or the scope of the claims. The scope of the present invention is defined by the scope of the claims. Also, not only the embodiments but also the embodiments, examples, and modifications not described here are included in the scope of the present invention.

[0085] (Supplementary Note) The technology disclosed in this specification can be grasped as follows in one aspect.

[0086] (Item 1) A trigger signal generation circuit that generates a plurality of first trigger signals having a predetermined phase difference based on a clock signal; A plurality of adjustment circuits that respectively generate second trigger signals obtained by delaying corresponding first trigger signals among the plurality of first trigger signals; A plurality of A / D converters, each of which receives the same analog signal and converts the analog signal into a digital signal according to a corresponding second trigger signal among the plurality of second trigger signals. A selection unit that selects one first trigger signal from the plurality of first trigger signals. The adjustment circuit corresponding to the first trigger signal selected by the selection unit generates the second trigger signal such that the delay amount of the generated second trigger signal with respect to the input first trigger signal approaches the predetermined time based on a reference signal obtained by delaying the selected first trigger signal by a predetermined time. A / D converter circuit.

[0087] (Item 2) The A / D converter circuit further includes a delay control circuit that controls the delay amount of the second trigger signal in the adjustment circuit. The delay control circuit controls the delay amount of the second trigger signal in the adjustment circuit corresponding to the selected first trigger based on the read value of the second trigger signal generated by the adjustment circuit corresponding to the selected first trigger signal at the rising or falling edge of the reference signal. The A / D converter circuit according to Item 1.

[0088] (Item 3) When m is an integer of 2 or more, the number of the plurality of A / D converters is m. The m first trigger signals have different phases for each period of the clock signal. The delay control circuit controls the delay amount of the second trigger signal in the A / D converter corresponding to the selected first trigger based on the read value every m cycles of the clock signal. The A / D converter circuit according to Item 2.

[0089] (Item 4) When the read value has not changed from the previous read value, the control circuit increases the delay amount of the second trigger signal in the A / D converter corresponding to the selected first trigger, and when the read value of the second trigger signal has changed from the previous read value, the control circuit maintains the delay amount of the second trigger signal in the A / D converter corresponding to the selected first trigger. The A / D converter circuit according to item 3.

[0090] (Item 5) The adjustment circuit includes an input node to which the first trigger signal is input, an output node from which the second trigger signal is output, a plurality of delay circuits connected in series, and a plurality of switches. The input terminal of the delay circuit at the front end among the plurality of delay circuits is connected to the input node. The plurality of switches are respectively provided between two adjacent delay circuits among the plurality of delay circuits and between the output node. When any one of the plurality of switches is turned on and the remaining switches are turned off, the delay amount of the second trigger signal in the delay circuit is determined. The A / D converter circuit according to any one of items 1 to 4.

Explanation of symbols

[0091] 1 A / D converter circuit, 10_1~10_m ADC, 10_r reference ADC, 20 trigger signal generation circuit, 26_1~26_m,26_r adjustment circuit, 30 controller, 40 delay control block, 42 delay circuit, 44_1~44_m+1 delay control circuit, 50 integrated circuit, 262 input node, 264 output node, 260_1~260_2t delay circuit, SW_1~SW_2t switch, 440 detection unit, 442 counter, 602,604,610_1~610_2t D flip-flop circuit, 606 NAND circuit, 608 AND circuit.

Claims

1. A trigger signal generation circuit that generates a plurality of first trigger signals having a predetermined phase difference based on a clock signal; A plurality of adjustment circuits that respectively generate second trigger signals obtained by delaying corresponding first trigger signals among the plurality of first trigger signals; A plurality of A / D converters into which the same analog signal is respectively input and which respectively convert the analog signal into a digital signal according to corresponding second trigger signals among the plurality of second trigger signals; A selection unit that selects one first trigger signal from the plurality of first trigger signals, and The adjustment circuit corresponding to the first trigger signal selected by the selection unit generates the second trigger signal such that the delay amount of the generated second trigger signal with respect to the input first trigger signal approaches the predetermined time based on a reference signal obtained by delaying the selected first trigger signal by a predetermined time. An A / D converter circuit.

2. Further comprising a delay control circuit that controls the delay amount of the second trigger signal in the adjustment circuit, and The delay control circuit controls the delay amount of the second trigger signal in the adjustment circuit corresponding to the selected first trigger based on a read value of the second trigger signal generated by the adjustment circuit corresponding to the selected first trigger signal at the rising or falling edge of the reference signal. The A / D converter circuit according to claim 1.

3. The number of the plurality of A / D converters is m, where m is an integer of 2 or more, The m first trigger signals have different phases for each period of the clock signal, and The delay control circuit controls the delay amount of the second trigger signal in the A / D converter corresponding to the selected first trigger based on the read value every m cycles of the clock signal. The A / D converter circuit according to claim 2.

4. When the read value has not changed from the previous read value, the control circuit increases the delay amount of the second trigger signal in the A / D converter corresponding to the selected first trigger, and when the read value of the second trigger signal has changed from the previous read value, the control circuit maintains the delay amount of the second trigger signal in the A / D converter corresponding to the selected first trigger. The A / D converter circuit according to claim 3.

5. The adjustment circuit has an input node to which the first trigger signal is input, an output node from which the second trigger signal is output, a plurality of delay circuits connected in series, and a plurality of switches. An input terminal of a delay circuit at the front end among the plurality of delay circuits is connected to the input node. The plurality of switches are respectively provided between two adjacent delay circuits among the plurality of delay circuits and between the output node. When any one of the plurality of switches is turned on and the remaining switches are turned off, a delay amount of the second trigger signal in the delay circuit is determined. The A / D converter circuit according to any one of claims 1 to 4.

Images