Image processing circuit

Abstract

To provide an image processing circuit capable of restricting generation of a horizontal synchronization signal with incomplete cycles at an output.SOLUTION: An image processing circuit includes: a memory capable of writing data based on an input clock and reading the data based on an output clock; a phase synchronization part for generating the output clock from a reference clock; an output synchronization signal generation part for generating an output vertical synchronization signal and an output horizontal synchronization signal which are output synchronization signals for output of the memory by using the output clock; a pseudo synchronization signal generation part for generating a pseudo horizontal synchronization signal which simulates the output horizontal synchronization signal by using the input clock; a feedback part for feeding back an adjustment signal for adjusting the cycle of the output horizontal synchronization signal within the cycle of the output vertical synchronization signal to the phase synchronization part based on a difference between the output horizontal synchronization signal and the pseudo horizontal synchronization signal; and a video processing part for performing video processing by using the data output from the memory.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The disclosed technology relates to an image processing circuit.

Background Art

[0002] Patent Document 1 describes "When processing an input signal with an inserted frame synchronization pattern formed by a clock of a first frequency by sampling it with a clock of a second frequency different from the first frequency, the clock of the second frequency is supplied to a PLL to form the clock of the first frequency, and the frame synchronization pattern is detected from the input signal using the formed clock of the first frequency, and the clock of the second frequency is synchronized with the input signal using the detected frame synchronization pattern."

[0003] Patent Document 2 describes "By providing a programmable arithmetic circuit, an input synchronization signal reproduction circuit, and a programmable arithmetic circuit and an output synchronization pulse generation circuit, different system clock signals are supplied to the input and output, and the processing of the video signal can be flexibly supported only by changing the signal processing program of the programmable arithmetic circuit."

[0004] Patent Document 3 describes "Synchronization signal generation means for generating a second synchronization signal based on a display system reference clock signal, phase comparison means for comparing the phases of a first synchronization signal and the second synchronization signal included in an input video signal, and synchronization means for synchronizing the second synchronization signal with the first synchronization signal when the phase difference is out of the reference based on the comparison result in the phase comparison means."

[0005] Patent Document 4 describes that "it has a clock generator that generates a clock signal, a horizontal reference generation circuit having a first frequency divider that divides the clock signal, a vertical reference generation circuit having a second frequency divider that divides the output of the first frequency divider, a switch circuit that receives as inputs an external vertical synchronization signal and the output of the second frequency divider and outputs one of the inputs, and a CPU that changes the oscillation frequency of the clock generator or the frequency division ratio of the first frequency divider when switching the input of the switch circuit."

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0007] In an image processing circuit that processes input video data and outputs it to a display, it may be necessary to switch the clock. However, when switching the clock, there is a possibility that a horizontal synchronization signal with an intermediate period (width) is generated in the output. When such a horizontal synchronization signal with an intermediate period is generated, there is a problem that the video is damaged and the video cannot be correctly displayed on some displays. Although Patent Documents 1 to 4 disclose techniques for switching the clock, the above problems still remain unsolved.

[0008] Therefore, an object of the present disclosure is to provide an image processing circuit capable of suppressing the generation of a horizontal synchronization signal with an intermediate period in the output.

Means for Solving the Problems

[0009] The image processing circuit according to the present disclosure includes: a memory capable of writing data based on an input clock and reading data based on an output clock; a phase synchronization unit that generates the output clock from a reference clock; an output synchronization signal generation unit that generates an output vertical synchronization signal and an output horizontal synchronization signal, which are synchronization signals for output of the memory, using the output clock; a pseudo synchronization signal generation unit that generates a pseudo horizontal synchronization signal by simulating the output horizontal synchronization signal using the input clock; a feedback unit that feeds back an adjustment signal for adjusting the period of the output horizontal synchronization signal within the period of the output vertical synchronization signal to the phase synchronization unit based on a difference between the output horizontal synchronization signal and the pseudo horizontal synchronization signal; and a video processing unit that performs video processing using the data output from the memory.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, an example of an embodiment of the technology of the present disclosure will be described with reference to the drawings. In each of the drawings, the same or equivalent components and parts are given the same reference numerals. Also, the dimensional ratios in the drawings may be exaggerated for convenience of explanation and may be different from the actual ratios.

[0012] In addition, when the term "connection" is used hereinafter, the term may be interpreted in a broad sense to mean an electrical connection, including not only a direct connection but also an indirect connection (for example, a connection via a passive component).

[0013] Also, when the term "provided between" is used hereinafter, the term may be interpreted to mean an electrical connection position and not a physical arrangement position.

[0014] FIG. 1 is a diagram showing an example of a configuration example of a system 1 that may include an image processing circuit 100. The system 1 may be, for example, a video system for car navigation. Such a system 1 may include an SoC 10, a video display device 20, and an image processing circuit 100.

[0015] The SoC 10 is a system-on-a-chip (SoC) on which a processor, a microcontroller, and other circuits and elements for realizing various functions are mounted. The SoC 10 is an example of a device that generates video data and generates video data to be displayed on the video display device 20.

[0016] The video display device 20 is a device that displays video and displays video using the video data generated by the SoC 10 and processed by the image processing circuit 100. As an example, the video display device 20 may be an LCD.

[0017] The image processing circuit 100 is provided between the SoC 10 and the video display device 20, processes the video data generated by the SoC 10, and outputs it to the video display device 20. The image processing circuit 100 may be provided as an integrated circuit (IC: Integrated Circuit).

[0018] In such a system configuration, in order to adjust the size, frequency, etc. of the video according to the video display device 20, scaling, frequency conversion, etc. may be performed in the image processing circuit 100. In such a case, it is necessary to change the clock in the image processing circuit 100. At this time, however, a horizontal synchronization signal with an unintended intermediate period (hereinafter also referred to as "incomplete H") may be generated at the output. First, this will be described.

[0019] FIG. 2 is a diagram showing an example of the functional configuration of the image processing circuit 100_1 according to the conventional example. Input data data_i, an input vertical synchronization signal vs_i, an input horizontal synchronization signal hs_i, and an input clock clk_i are input to the image processing circuit 100_1 from the SoC 10. Also, a reference clock clk_ref is input to the image processing circuit 100_1 from the outside. Then, output data data_o, an output vertical synchronization signal vs_o, an output horizontal synchronization signal hs_o, and an output clock clk_o are output from the image processing circuit 100_1 to the video display device 20.

[0020] The image processing circuit 100_1 includes a phase synchronization unit 110, an output synchronization signal generation unit 120, a memory 130, and a video processing unit 140. Note that these blocks are functional blocks separated functionally, and do not necessarily match the actual device configuration. That is, in this figure, just because it is shown as one block, it does not necessarily have to be constituted by one device. Also, in this figure, just because they are shown as separate blocks, they do not necessarily have to be constituted by separate devices. The same applies to other figures.

[0021] The phase synchronization unit 110 generates an output clock clk_o from a reference clock clk_ref. The phase synchronization unit 110 may be, for example, a PLL (Phase Locked Loop) that synchronizes the phases of an input signal and an output signal using a feedback loop. The generated output clock clk_o is supplied to the output synchronization signal generation unit 120, the memory 130, and the video processing unit 140. Also, the output clock clk_o is externally output to the video display device 20.

[0022] The output synchronization signal generation unit 120 generates an output vertical synchronization signal vs_o and an output horizontal synchronization signal hs_o, which are synchronization signals for output of the memory 130, using the output clock clk_o. More specifically, the output synchronization signal generation unit 120 may synchronize the input vertical synchronization signal vs_i with the output clock clk_o to generate the output vertical synchronization signal vs_o, and generate the output horizontal synchronization signal hs_o based on the output vertical synchronization signal vs_o. The generated output vertical synchronization signal vs_o and output horizontal synchronization signal hs_o are supplied to the memory 130.

[0023] The memory 130 can write input data data_i based on an input clock clk_i and read output data data_o based on the output clock clk_o. Note that the memory 130 may be any storage device that can access each of the write-side clock and the read-side clock, and may be any storage device such as a memory like a FIFO (First In First Out) or SRAM (Static Random Access Memory), a flip-flop, or a latch.

[0024] The video processing unit 140 performs video processing for causing the video display device 20 to display a video, such as image quality improvement processing, warping processing, and scaling processing, using the output data data_o output from the memory 130. After being video-processed by the video processing unit 140, the output data data_o, the output vertical synchronization signal vs_o, and the output horizontal synchronization signal hs_o are externally output to the video display device 20.

[0025] FIG. 3 is a diagram showing an example of a time chart for explaining the generation of the incomplete H. In this figure, from top to bottom, an input vertical synchronization signal vs_i, an input horizontal synchronization signal hs_i, an input data data_i, an output vertical synchronization signal vs_o, an output horizontal synchronization signal hs_o, and an output data data_o are shown respectively.

[0026] Here, the input clock clk_i and the output clock clk_o are asynchronous. Therefore, even if the frame periods are the same, when counting one frame by the input clock clk_i and the output clock clk_o respectively, there will be a difference in the number of cycles of the input clock clk_i and the number of cycles of the output clock clk_o.

[0027] Therefore, as shown by the dotted line portion in this figure, for example, at the end of a frame, the generation timing of the output horizontal synchronization signal hs_o may shift, and there is a possibility that an incomplete-cycle output horizontal synchronization signal hs_o is generated. The image processing circuit 100 according to this embodiment attempts to suppress the generation of the incomplete H, which is such an incomplete-cycle output horizontal synchronization signal hs_o.

[0028] FIG. 4 is a diagram showing an example of the functional configuration of the image processing circuit 100 according to this embodiment. In this figure, the same or equivalent components and parts as those in FIG. 2 are denoted by the same reference numerals, and the description is omitted except for the following differences.

[0029] In addition to the phase synchronization unit 110, the output synchronization signal generation unit 120, the memory 130, and the video processing unit 140, the image processing circuit 100 includes a pseudo synchronization signal generation unit 150 and a feedback unit 170. The image processing circuit 100 may further include a control unit 160 and an output terminal 180.

[0030] As described above, the phase synchronization unit 110 generates the output clock clk_o from the reference clock clk_ref. In this embodiment, the generated output clock clk_o is further supplied to the pseudo synchronization signal generation unit 150 and the feedback unit 170.

[0031] As described above, the output synchronization signal generation unit 120 generates an output vertical synchronization signal vs_o and an output horizontal synchronization signal hs_o, which are synchronization signals for output of the memory 130, using the output clock clk_o. In the present embodiment, the generated output horizontal synchronization signal hs_o is further supplied to the feedback unit 170.

[0032] As described above, the memory 130 can write the input data data_i based on the input clock clk_i and read the output data data_o based on the output clock clk_o.

[0033] As described above, the video processing unit 140 executes video processing using the output data data_o output from the memory 130. For example, the video processing unit 140 may execute at least any one of image quality improvement processing, warping processing, and scaling processing.

[0034] The pseudo synchronization signal generation unit 150 generates a pseudo horizontal synchronization signal hs_i_o that simulates the output horizontal synchronization signal hs_o using the input clock clk_i. Details of the pseudo synchronization signal generation unit 150 will be described later. The generated pseudo horizontal synchronization signal hs_i_o is supplied to the feedback unit 170. Further, the generated pseudo horizontal synchronization signal hs_i_o may be further supplied to the output terminal 180.

[0035] The control unit 160 controls a register value reg_set for setting the period of the pseudo horizontal synchronization signal hs_i_o. The register value reg_set is supplied to the pseudo synchronization signal generation unit 150.

[0036] The feedback unit 170 feeds back an adjustment signal rslt_pls for adjusting the period of the output horizontal synchronization signal hs_o within the period of the output vertical synchronization signal vs_o to the phase synchronization unit 110 based on the difference between the output horizontal synchronization signal hs_o and the pseudo horizontal synchronization signal hs_i_o. Details of the feedback unit 170 will be described later. Thereby, in the phase synchronization unit 110, the frequency of the output clock clk_o is adjusted according to the adjustment signal rslt_pls, and accordingly, the period of the output horizontal synchronization signal hs_o is adjusted within the period of the output vertical synchronization signal vs_o.

[0037] The output terminal 180 is a terminal for outputting the pseudo horizontal synchronization signal hs_i_o to the outside of the image processing circuit 100. By enabling the external output of the pseudo horizontal synchronization signal hs_i_o from the output terminal 180, the pseudo horizontal synchronization signal hs_i_o can be monitored externally or diverted for other controls other than the suppression of the partial H. Next, the details of the pseudo synchronization signal generation unit 150 will be further described.

[0038] FIG. 5 is a diagram showing an example of a time chart in the pseudo synchronization signal generation unit 150. In this figure, from top to bottom, the input clock clk_i, the register value reg_set, the input vertical synchronization signal vs_i, the pseudo signal hs_i_o´, the output clock clk_o, and the pseudo horizontal synchronization signal hs_i_o are shown respectively.

[0039] As shown in this figure, the pseudo-synchronous signal generation unit 150 may pseudo-generate a pseudo-signal hs_i_о´ using the input clock clk_i and the input vertical synchronous signal vs_i which is a synchronous signal for input to the memory 130. At this time, the pseudo-synchronous signal generation unit 150 may pseudo-generate the pseudo-signal hs_i_о´ at intervals based on the register value reg_set. As an example, the control unit 160 may control the register value reg_set so that the period is 1123.2 (H cycle @ FHD) × 6.7204 ns (clock period @ FHD) ≒ 7548.3 ns if it is FHD (Full High Definition), and 748.8 (H cycle @ HD) × 15.1208 ns (clock period @ HD) ≒ 11322.5 ns if it is HD (High Definition). Then, the pseudo-synchronous signal generation unit 150 can generate a pseudo-signal hs_i_о´ with a period corresponding to FHD or HD by pseudo-generating it at intervals based on the register value reg_set.

[0040] Here, the pseudo-signal hs_i_о´ is generated using the input clock clk_i and is an asynchronous signal for the feedback unit 170. Therefore, the pseudo-synchronous signal generation unit 150 may generate a pseudo-horizontal synchronous signal hs_i_о which is a synchronous signal for the feedback unit 170 by re-triggering the pseudo-signal hs_i_о´ with the output clock clk_о.

[0041] For example, in this way, the pseudo-synchronous signal generation unit 150 may generate a pseudo-horizontal synchronous signal hs_i_о by re-triggering the pseudo-signal hs_i_о´ which is pseudo-generated using the input clock clk_i and the input vertical synchronous signal vs_i which is a synchronous signal for input to the memory 130, with the output clock clk_о. At this time, the pseudo-synchronous signal generation unit 150 may set the period of the pseudo-signal hs_i_о´ based on the register value reg_set.

[0042] Note that depending on the frequency ratio between the input clock clk_i and the output clock clk_o, a fractional part may occur in the number of cycles, resulting in a fraction. As an example, when scaling from FHD to HD, if an attempt is made to reproduce the HD size with the FHD clock, the number of cycles becomes 3310.7. In such a case, the pseudo-synchronization signal generation unit 150 can also reproduce the fraction by combining 3310 and 3311 within one frame (for example, three times out of ten as 3310 and seven times out of ten as 3311). Next, the details of the feedback unit 170 will be further described.

[0043] Figure 6 is a diagram showing an example of a time chart in the feedback unit 170. In this figure, from top to bottom, the input vertical synchronization signal vs_i, the pseudo horizontal synchronization signal hs_i_o, the input data data_i, the output clock clk_o, the output vertical synchronization signal vs_o, the output horizontal synchronization signal hs_o, the output data data_o, and the adjustment signal rslt_pls are respectively shown.

[0044] As shown in this figure, the feedback unit 170 may calculate the number of cycles freq_cnt_i by counting the period of the pseudo horizontal synchronization signal hs_i_o with the output clock clk_o. Also, the feedback unit 170 may calculate the number of cycles freq_cnt_o by counting the period of the output horizontal synchronization signal hs_o with the output clock clk_o. Then, the feedback unit 170 may calculate the adjustment signal rslt_pls for each period of the output horizontal synchronization signal hs_o based on the number of cycles freq_cnt_i and the number of cycles freq_cnt_o.

[0045] Figure 7 is a diagram showing a specific example of the feedback unit 170. The feedback unit 170 may include an input counter 172, an output counter 174, and a subtraction unit 176.

[0046] The input counter 172 may receive the pseudo horizontal synchronization signal hs_i_о and the output clock clk_о. Then, the input counter 172 may calculate the cycle count freq_cnt_i by counting the cycle of the pseudo horizontal synchronization signal hs_i_о with the output clock clk_о.

[0047] The output counter 174 may receive the output horizontal synchronization signal hs_о and the output clock clk_о. Then, the output counter 174 may calculate the cycle count freq_cnt_о by counting the cycle of the output horizontal synchronization signal hs_о with the output clock clk_о.

[0048] The subtraction unit 176 may receive the cycle count freq_cnt_i and the cycle count freq_cnt_о. Then, the subtraction unit 176 may calculate the adjustment signal rslt_pls by subtracting the cycle count freq_cnt_о from the cycle count freq_cnt_i. The feedback unit 170 may feedback the adjustment signal rslt_pls calculated in this way to the phase synchronization unit 110, for example. Then, the phase synchronization unit 110 adjusts the phase of the reference clock clk_ref input from the difference result of the cycle count from the feedback unit 170 and generates the output clock clk_о. Thereby, the frequency of the output clock clk_о is adjusted in the phase synchronization unit 110, and accordingly, the cycle of the output horizontal synchronization signal hs_о is adjusted within the cycle of the output vertical synchronization signal vs_о.

[0049] At this time, since both the output horizontal synchronization signal hs_о output by the output synchronization signal generation unit 120 and the pseudo horizontal synchronization signal hs_i_о output by the pseudo synchronization signal generation unit 150 are generated by the output clock clk_о, even if the frequency of the output clock clk_о is adjusted in the phase synchronization unit 110, no timing deviation occurs in the feedback unit 170.

[0050] In the above description, an example was shown where the output clock clk_o is used to count the periods of the pseudo horizontal synchronization signal hs_i_o and the output horizontal synchronization signal hs_o. However, the present invention is not limited to this. As long as the same clock is used for the clock that counts the period of the pseudo horizontal synchronization signal hs_i_o and the clock that counts the period of the output horizontal synchronization signal hs_o, it is sufficient. Therefore, the input clock clk_i may be used to count the periods of the pseudo horizontal synchronization signal hs_i_o and the output horizontal synchronization signal hs_o, the reference clock clk_ref may be used, or any other arbitrary clock may be used. That is, the feedback unit 170 may feedback to the phase synchronization unit 110 the difference in the number of cycles counted by the same clock for the periods of the pseudo horizontal synchronization signal hs_i_o and the output horizontal synchronization signal hs_o as the adjustment signal rslt_pls.

[0051] However, since it is not necessary to add and supply a dedicated clock to the feedback unit 170 only for counting the period, the same clock is preferably the output clock clk_o.

[0052] As described above, the image processing circuit 100 according to the present embodiment monitors the frequency of the phase synchronization unit 110 for each line and adjusts the period of the output horizontal synchronization signal hs_o each time based on the difference from the pseudo horizontal synchronization signal hs_i_o. Thus, according to the image processing circuit 100 according to the present embodiment, while the number of cycles within one frame is kept constant, the period of the output horizontal synchronization signal hs_o is adjusted, so that the generation of partial H can be suppressed.

[0053] At this time, as described above, the output horizontal synchronization signal hs_o is generated using the output clock clk_o, and the frequency of the output clock clk_o changes each time according to the adjustment signal rslt_pls. Therefore, the period of the output horizontal synchronization signal hs_o fluctuates. When the period of the output horizontal synchronization signal hs_o fluctuates in this way, there is a possibility that the output horizontal synchronization signal hs_o may come before the input horizontal synchronization signal hs_i. Therefore, in the memory 130, the output timing of the output vertical synchronization signal vs_o may be delayed to absorb the frequency difference.

[0054] FIG. 8 is a time chart for explaining the absorption of the frequency difference in the memory 130. In this figure, from top to bottom, the input clock clk_i, the input vertical synchronization signal vs_i, the input horizontal synchronization signal hs_i, the input data data_i, the output clock clk_o, the output vertical synchronization signal vs_o, the output horizontal synchronization signal hs_o, and the output data data_o are shown respectively.

[0055] As shown in this figure, when the period of the output horizontal synchronization signal hs_o fluctuates, there is a possibility that the output horizontal synchronization signal hs_o may come before the input horizontal synchronization signal hs_i. Therefore, as indicated by the arrow in this figure, in the memory 130, the frequency difference may be absorbed by delaying the output timing of the output vertical synchronization signal vs_o.

[0056] Thereby, even when the period of the output horizontal synchronization signal hs_o fluctuates, the number of cycles of the output horizontal synchronization signal hs_o and the input horizontal synchronization signal hs_o can be made to match, and missing of the output horizontal synchronization signal hs_o can be prevented.

[0057] The present disclosure also includes the following content.

[0058] (Appendix 1) A memory capable of writing data based on an input clock and reading data based on an output clock, A phase synchronization unit that generates the output clock from a reference clock, An output synchronization signal generation unit that generates an output vertical synchronization signal and an output horizontal synchronization signal, which are synchronization signals for output of the memory, using the output clock; A pseudo-synchronization signal generation unit that generates a pseudo horizontal synchronization signal by simulating the output horizontal synchronization signal using the input clock; A feedback unit that feeds back an adjustment signal for adjusting the period of the output horizontal synchronization signal within the period of the output vertical synchronization signal to the phase synchronization unit based on the difference between the output horizontal synchronization signal and the pseudo horizontal synchronization signal; A video processing unit that performs video processing using the data output from the memory; An image processing circuit comprising: (Appendix 2) The pseudo-synchronization signal generation unit generates the pseudo horizontal synchronization signal by re-beating a pseudo signal pseudo-generated using the input clock and an input vertical synchronization signal, which is a synchronization signal for input of the memory, with the output clock. The image processing circuit according to Appendix 1. (Appendix 3) Further comprising a control unit that controls a register value, The pseudo-synchronization signal generation unit sets the period of the pseudo signal based on the register value. The image processing circuit according to Appendix 2. (Appendix 4) The feedback unit feeds back, as the adjustment signal, the difference in the number of cycles counted for the periods of the pseudo horizontal synchronization signal and the output horizontal synchronization signal using the same clock to the phase synchronization unit. The image processing circuit according to any one of Appendices 1 to 3. (Appendix 5) The same clock is the output clock. The image processing circuit according to Appendix 4. (Appendix 6) The memory delays the output timing of the output vertical synchronization signal. The image processing circuit according to any one of Appendices 1 to 5. (Appendix 7) The video processing unit executes at least one of image quality improvement processing, warping processing, and scaling processing. The image processing circuit according to any one of Appendices 1 to 6. (Appendix 8) It further includes an output terminal for outputting the pseudo horizontal synchronization signal to the outside. The image processing circuit according to any one of Appendices 1 to 7. (Appendix 9) The phase synchronization unit adjusts the phase of the reference clock input from the difference result of the number of cycles from the feedback unit and generates an output clock. The image processing circuit according to any one of Appendices 1 to 8.

Explanation of Signs

[0059] 1 System 10 SoC 20 Video display device 100 Image processing circuit 110 Phase synchronization unit 120 Output synchronization signal generation unit 130 Memory 140 Video processing unit 150 Pseudo synchronization signal generation unit 160 Control unit 170 Feedback unit 172 Input counter 174 Output counter 176 Subtraction unit 180 Output terminal

Claims

1. A memory capable of writing data based on an input clock and reading data based on an output clock, A phase synchronization unit that generates the output clock from a reference clock, An output synchronization signal generation unit that generates an output vertical synchronization signal and an output horizontal synchronization signal, which are synchronization signals for output of the memory, using the output clock, A pseudo synchronization signal generation unit that generates a pseudo horizontal synchronization signal by simulating the output horizontal synchronization signal using the input clock, A feedback unit that feeds back an adjustment signal for adjusting the period of the output horizontal synchronization signal within the period of the output vertical synchronization signal to the phase synchronization unit based on the difference between the output horizontal synchronization signal and the pseudo horizontal synchronization signal, A video processing unit that executes video processing using the data output from the memory, An image processing circuit comprising the above.

2. The pseudo synchronization signal generation unit generates the pseudo horizontal synchronization signal by re-beating a pseudo signal pseudo-generated using the input clock and an input vertical synchronization signal, which is a synchronization signal for input of the memory, with the output clock. The image processing circuit according to Claim 1.

3. Further comprising a control unit for controlling a register value, The pseudo synchronization signal generation unit sets the period of the pseudo signal based on the register value. The image processing circuit according to Claim 2.

4. The feedback unit feeds back, as the adjustment signal, the difference in the number of cycles counted for the periods of the pseudo horizontal synchronization signal and the output horizontal synchronization signal respectively with the same clock to the phase synchronization unit. The image processing circuit according to Claim 1.

5. The same clock is the output clock. The image processing circuit according to Claim 4.

6. The memory delays the output timing of the output vertical synchronization signal. The image processing circuit according to any one of Claims 1 to 5.

7. The video processing unit executes at least any one of image quality improvement processing, warping processing, and scaling processing. The image processing circuit according to any one of Claims 1 to 5.

8. Further comprising an output terminal for outputting the pseudo horizontal synchronization signal to the outside. The image processing circuit according to any one of Claims 1 to 5.

9. The phase synchronization unit adjusts the phase of the reference clock input from the difference result of the number of cycles from the feedback unit and generates an output clock. The image processing circuit according to any one of Claims 1 to 5.

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