Semiconductor device

Abstract

To provide a semiconductor device capable of reducing the generation of noise even when a plurality of semiconductor devices are connected in parallel and used at the same time, with a simple structure.SOLUTION: A semiconductor device includes: a plurality of transistor cells 18 formed in a SiC epitaxial layer 28; a gate pad 4 for electrical connection for controlling the plurality of transistor cells; a pad peripheral part 12 formed around the gate pad so as to continuously surround the gate pad; a built-in resistor 21 partially disposed below the gate pad, made of polysilicon, and electrically connecting the gate pad and the pad peripheral portion; and a plurality of source pads 6 for electrical connection. The gate pad is physically separated from the pad peripheral pad in the same layer so that a space is formed between the gate pad part and the pad periphery, and is formed around an edge of the epitaxial layer. The connection part to which the connection member is connected is selectively formed on the surface of the gate pad.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a module including a plurality of the same.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a gate pad, a gate connection wiring made of polysilicon, and a gate metal wiring formed on the gate connection wiring and integrally connected to the gate pad. When a voltage is applied to the gate pad, power is supplied to a MOSFET formed in an active region via the gate metal wiring and the gate connection wiring.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In practical use, a module having a plurality of semiconductor devices (chips) connected in parallel to each other may be used. The module is provided with a gate terminal electrically connected to the gates of the respective chips collectively. By applying a control voltage to the gate terminal, a voltage is simultaneously applied to the gates of the respective built-in chips to perform a switching operation.

[0005] However, in such a module, there is a problem that noise is likely to occur during turn-on. This is because there is variation in gate resistance among a plurality of chips, and at the initial stage of on-control, current concentrates on a chip having a relatively low gate resistance. Further, since the variation in gate resistance is caused by variation in processing accuracy (etching dimension, etc.) during chip manufacturing, it is difficult to eliminate this.

[0006] On the other hand, an external gate resistor having a resistance value larger than the gate resistors in each chip may be provided for each chip, but another problem occurs in that the structure of the module becomes complicated and assembly is difficult.

[0007] Therefore, an object of the present invention is to provide a semiconductor device with a simple structure that can reduce the generation of noise even when a plurality of semiconductor devices are connected in parallel and used simultaneously, and a module including a plurality of such semiconductor devices.

Means for Solving the Problem

[0008] One embodiment of this invention includes a semiconductor layer, a plurality of cells formed in the semiconductor layer, control pads for electrical connection for controlling the plurality of cells, a pad peripheral portion formed around the control pads so as to continuously surround the control pads, and a built-in resistor made of polysilicon partially disposed below the control pads, the built-in resistor electrically connecting the control pads and the pad peripheral portion, and a plurality of source pads for electrical connection. The control pads are physically separated from the pad peripheral portion in the same layer so that a space is formed between the control pads and the pad peripheral portion. The control pads are formed around the edge of the semiconductor layer, and a connection portion to which a connection member is connected is selectively formed on the surface of the control pads. The built-in resistor is selectively disposed in a region avoiding the connection portion in a plan view, providing a semiconductor device.

[0009] In one embodiment of this invention, the connection portion occupies more than half of the surface area of the control pads in a plan view.

[0010] In one embodiment of this invention, it further includes gate fingers extending from the pad peripheral portion.

[0011] In one embodiment of this invention, the gate fingers extend in three directions from the pad peripheral portion.

[0012] In one embodiment of the present invention, the gate finger has a portion extending to the four corners of the semiconductor device.

[0013] In one embodiment of the present invention, the width of the gate finger is narrower than the width of the built-in resistor.

[0014] In one embodiment of the present invention, the built-in resistor has a rectangular shape in a plan view.

[0015] In one embodiment of the present invention, the control pad is composed of a material containing aluminum.

[0016] In one embodiment of the present invention, the peripheral portion of the pad is composed of a material containing aluminum.

[0017] In one embodiment of the present invention, each of the source pads is composed of a material containing aluminum.

[0018] In one embodiment of the present invention, the semiconductor device has a rectangular shape in a plan view, and the control pad is provided near the center of one side of the semiconductor device in the plan view.

[0019] In one embodiment of the present invention, the peripheral portion of the pad has the same thickness as the control pad.

[0020] In one embodiment of the present invention, the built-in resistor is partially disposed in a region below the control pad, and an interlayer film is selectively disposed between the built-in resistor and the control pad.

[0021] In one embodiment of the present invention, the connection portion is formed in the central portion of the control pad.

[0022] The above-mentioned, or further other objects, features and effects of the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

[0023]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present invention. In Figure 1, for clarity, a part of the elements that are not exposed on the outermost surface of the semiconductor device 1 in the actual plan view is shown by a solid line.

[0026] The semiconductor device 1 is a semiconductor device using SiC. For example, in a plan view (hereinafter simply referred to as "plan view") when looking at its outermost surface from the normal direction, it is formed in a rectangular chip shape.

[0027] An active region 2 and a termination region 3 surrounding the active region 2 are set in the semiconductor device 1. In this embodiment, the active region 2 is formed in a substantially rectangular shape in a plan view in the inner region of the semiconductor device 1, but its shape is not particularly limited. A guard ring (not shown) may be formed between the active region 2 and the termination region 3 to improve the breakdown voltage of the semiconductor device 1.

[0028] In the active region 2, a gate metal 44, a source metal 43 as an example of the control pad of the present invention, and a gate finger 5 as an example of the finger of the present invention are formed. And, so as to cover these, a passivation film 40 is formed on the outermost surface of the semiconductor device 1. In the passivation film 40, openings 41 and 42 are formed to expose a part of the gate metal 44 and a part of the source metal 43 as a gate pad 4 and a source pad 6, respectively. On the other hand, the entire gate finger 5 is covered with the passivation film 40.

[0029] The gate metal 44, the gate finger 5, and the source metal 43 are made of metal wirings such as Al (aluminum), AlCu (aluminum - copper alloy), Cu (copper), etc.

[0030] By forming the gate finger 5 with a metal wiring having a lower resistance than polysilicon, it is possible to supply a gate current to the transistor cell 18 (see FIG. 2) at a position relatively far from the gate metal 44 in a short time. Also, in the case of Al, since its workability is good (easy to process), the formation process of these wirings can be simplified. On the other hand, compared with the case where Al is used, AlCu can improve the power cycle resistance of the semiconductor device 1 and can also improve the bonding strength of the bonding wire with respect to the gate pad 4. When Cu is used, there is an advantage that the resistivity can be reduced compared to the cases of Al and AlCu.

[0031] The gate metal 44 is selectively formed on a part of the peripheral edge of the active region 2 (near the boundary with the termination region 3). The gate finger 5 extends branched in the direction along the peripheral edge of the active region 2 and in the direction toward the inside of the active region 2 from the formation position of the gate pad 4. As a result, in the active region 2, cell regions 7 and 45 are formed in a portion partitioned by a plurality of gate fingers 5 extending in different directions sandwiching the gate metal 44 and in the outer region of the gate finger 5.

[0032] More specifically, in this embodiment, the gate metal 44 is formed in a quadrangular shape in plan view and is selectively disposed at the center of one side 8 of the active region 2. Note that the sides other than one side 8 (the side where the gate metal 44 is disposed) of the active region 2 are the opposite side 9 of the side 8 and the sides 10 and 11 that are continuous with both ends of these sides 8 and 9, respectively.

[0033] The gate finger 5 includes a pad peripheral portion 12 that surrounds the periphery of the gate metal 44 with a space therebetween, and a first finger 13 and a second finger 14 that extend from the pad peripheral portion 12 in the direction along the one side 8 of the active region 2 and in the direction orthogonal to the one side 8, respectively.

[0034] The pad peripheral portion 12 is formed in a quadrangular annular shape in plan view along the periphery of the gate metal 44.

[0035] The first fingers 13 are formed in a pair along the side 8 in the direction toward the side 10 and the opposite side 11 with respect to the pad peripheral portion 12.

[0036] The second finger 14 includes a linear main portion 15 that crosses the active region 2 to the side 9 in the direction orthogonal to the first finger 13, and a plurality of branch portions 16 that are integrally connected to the main portion 15 and extend along the first finger 13 from the connection portion. In this embodiment, the branch portions 16 are connected to two locations, i.e., the tip portion and the middle portion of the main portion 15, to form a total of two pairs, but the number is not particularly limited.

[0037] In this way, in the active region 2, the cell regions 7 and 45 are partitioned by the first finger 13 and the second finger 14 (the main portion 15 and the branch portions 16). In this embodiment, a total of four inner cell regions 7 are formed, one at each corner of the intersection formed by the main portion 15 of the second finger 14 and the central branch portion 16. In addition, an annular outer cell region 45 is formed along the periphery of the active region 2 between the periphery of the active region 2 and the gate finger 5.

[0038] The source metal 43 is formed so as to cover substantially the entire inner and outer cell regions 7 and 45. A total of four openings 42 are formed in the passivation film 40 such that the source pads 6 are disposed one by one in each of the inner cell regions 7.

[0039] Further, a recess 17 corresponding to the shape of the gate metal 44 is formed in the source metal 43. The recess 17 is a depression formed to avoid the gate metal 44, and the gate metal 44 is disposed with a setback inside the active region 2 with respect to the first finger 13.

[0040] FIG. 2 is an enlarged view of the region surrounded by the dashed-dotted line II in FIG. 1. That is, it is a view showing an enlarged view of the gate pad 4 of the semiconductor device 1 and its vicinity. In FIG. 2, for clarity, a part of the elements not exposed on the outermost surface of the semiconductor device 1 in the actual plan view is shown by a solid line.

[0041] As shown in FIG. 2, a plurality of transistor cells 18 are arranged in the inner and outer cell regions 7 and 45 partitioned by the gate fingers 5 (the pad peripheral portion 12, the first finger 13, and the second finger 14).

[0042] In this embodiment, the plurality of transistor cells 18 are arranged in a matrix in a plan view in each of the inner and outer cell regions 7 and 45. In the vicinity of the gate fingers 5, the plurality of transistor cells 18 are aligned according to the shape of the gate fingers 5. For example, the plurality of transistor cells 18 are bent and aligned according to the shape of the corner portion of the pad peripheral portion 12, and are linearly aligned according to the shape of the main portion 15 of the linear second finger 14. The source metal 43 is formed so as to cover these plurality of transistor cells 18.

[0043] Note that in FIG. 2, for clarity, only a part of the plurality of transistor cells 18 covered by the source metal 43 is shown. Further, the arrangement form of the plurality of transistor cells 18 is not limited to a matrix form, and may be, for example, a stripe form, a staggered form, or the like. Further, the planar shape of each transistor cell 18 is not limited to a rectangular shape, and may be, for example, a circular shape, a triangular shape, a hexagonal shape, or the like.

[0044] Between the adjacent transistor cells 18, a gate electrode 19, which is an example of the control electrode of the present invention, is formed. The gate electrode 19 is disposed between each of the matrix-shaped transistor cells 18 in the inner and outer cell regions 7 and 45, and is formed in a lattice shape in plan view as a whole. On the other hand, this gate electrode 19 is formed not only in the inner and outer cell regions 7 and 45 but also in the region where the gate fingers 5 are disposed, and the lower portion below the gate fingers 5 is in contact with the gate fingers 5.

[0045] In this embodiment, a part of the gate electrode 19 is formed in the lower regions of the first finger 13 and the second finger 14 and faces the first finger 13 and the second finger 14 as contact portions. In FIG. 2, for clarity, the portion formed in the lower region of the gate electrode 19 is represented by a hatched region. Thereby, the gate electrodes 19 of the adjacent inner cell regions 7 are continuous via the gate electrode 19 that crosses the second finger 14 below. The continuous form of this gate electrode 19 is the same also with respect to the inner cell region 7 adjacent to the gate metal 44 and the outer cell region 45. That is, the gate electrodes 19 in these regions are continuous via the gate electrode 19 that crosses the first finger 13 below.

[0046] The first finger 13 and the second finger 14 are each connected to the gate electrode 19 disposed in the lower region thereof by a gate contact 20. The gate contact 20 is linearly formed along the longitudinal direction thereof at the center of the finger, spaced apart from the side edges of the first finger 13 and the second finger 14.

[0047] In this embodiment, a plurality of built-in resistors 21 are arranged below the gate metal 44. By arranging the plurality of built-in resistors 21 at positions that are approximately equidistant from the centroid position of the planar shape of the gate metal 44, it is preferable to have symmetry in the arrangement of the plurality of built-in resistors 21. In this embodiment, the plurality of built-in resistors 21 are arranged one by one at each corner of the gate metal 44 that is equidistant from the centroid G of the gate metal 44 having a rectangular shape in plan view. Thereby, symmetry is given to the four built-in resistors 21.

[0048] Such symmetric patterns can be variously considered. For example, two built-in resistors 21 may be arranged one by one at two corners of the gate metal 44 in a diagonal relationship, or may be arranged facing each other one by one on two sides of the gate metal 44 in an opposite-side relationship. Also, for example, when the gate metal 44 is circular in plan view, two built-in resistors 21 may be arranged one by one at both ends of the diameter of the gate metal 44, and when the gate metal 44 is triangular in plan view, three built-in resistors 21 may be arranged one by one at the three corners of the gate metal 44.

[0049] Each built-in resistor 21 is formed so as to straddle and cross the annular gap region 26 between the gate metal 44 and the gate finger 5 (pad peripheral portion 12). Thereby, the built-in resistor 21 faces each of the gate metal 44 and the gate finger 5. The gate metal 44 and the gate finger 5 (pad peripheral portion 12) are each connected to the built-in resistor 21 arranged in its lower region by a pad-side contact 22 and a cell-side contact 23 as an example of the contact via of the present invention.

[0050] In this embodiment, the four built-in resistors 21 extend in an outer direction orthogonal to the sides from below the peripheral portions 24 of the two sides of the gate metal 44 that are in an opposite side relationship, and reach below the pad peripheral portion 12. Each built-in resistor 21 is formed in a rectangular shape in plan view, and has a size of, for example, 200 μm□ or less (200 μm × 200 μm or less). Practically, if the size of each built-in resistor 21 is 200 μm□ or less, the area of the region sacrificed for the built-in resistor 21 among the regions on the SiC epitaxial layer 28 (see FIG. 3b) can be reduced, and space saving can be achieved.

[0051] Also, the pad-side contact 22 and the cell-side contact 23 are each formed in a linear shape parallel to each other along the sides of the gate metal 44 and the pad peripheral portion 12.

[0052] By arranging the built-in resistor 21 below the peripheral portion 24 that avoids the central portion of the gate metal 44, and further covering the upper region of the region where the built-in resistor 21 is arranged with the passivation film 40, a gate pad 4 as the wire region of the present invention surrounded by the built-in resistor 21 is secured at the central portion of the gate metal 44. The gate pad 4 is a region to which a bonding wire is connected.

[0053] That is, in this embodiment, each corner of the gate metal 44 where the built-in resistor 21 is arranged is selectively covered with the passivation film 40, and the other portions of the gate metal 44 are exposed from the opening 41. As a result, on the outermost surface of the semiconductor device 1, a gate pad 4 having a rectangular shape in plan view with each corner recessed inward is exposed. In this way, by covering the upper region of the region where the built-in resistor 21 is arranged with the passivation film 40, it is possible to prevent the bonding wire from being erroneously bonded to the portion of the gate metal 44 that overlaps the built-in resistor 21 during the bonding of the bonding wire. As a result, it is possible to suppress the built-in resistor 21 from being damaged or destroyed by an impact such as ultrasonic waves during the bonding of the bonding wire.

[0054] Figs. 3A and 3B are enlarged views of the region surrounded by the two-dot chain line III in Fig. 2. Fig. 3A shows a plan view, and Fig. 3B shows a cross-sectional view when the semiconductor device 1 is cut along the cutting line IIIb-IIIb in Fig. 3A. Note that in Figs. 3A and 3B, for clarity, the scales of the respective components may be different from those in Figs. 1 and 2, and the scales of the respective components may also be different between Fig. 3A and Fig. 3B. Further, in Figs. 3A and 3B, for clarity, a part of the elements not exposed on the outermost surface of the semiconductor device 1 in the actual plan view is shown by a solid line.

[0055] Next, a more detailed configuration of the built-in resistor 21 and the vicinity thereof will be described together with the cross-sectional structure of the semiconductor device 1.

[0056] The semiconductor device 1 includes a SiC substrate 27 and a SiC epitaxial layer 28. The SiC epitaxial layer 28 is laminated on the SiC substrate 27, and this laminated structure is shown as an example of the SiC semiconductor layer of the present invention.

[0057] The SiC substrate 27 and the SiC epitaxial layer 28 are each of n + -type and n - -type SiC. The impurity concentration of the n + -type SiC substrate 27 is, for example, 1×10 17 cm -3 ~ 1×10 21 cm -3 . On the other hand, the impurity concentration of the n - -type SiC epitaxial layer 28 is, for example, 1×10 14 cm -3 ~ 1×10 17 cm -3 . Further, as the n-type impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be used (the same applies hereinafter).

[0058] In the inner cell region 7, a plurality of transistor cells 18 are formed on the surface portion of the SiC epitaxial layer 28. The plurality of transistor cells 18 include a p - -type body region 29 and a p -An n-type source region 30 selectively formed in an inner region spaced apart from the periphery of the p-type body region 29, and a p-type body contact region 31 selectively formed in an inner region spaced apart from the periphery of the n-type source region 30 are included. Further, the n-type portion of the SiC epitaxial layer 28 serves as a common drain region for a plurality of transistor cells 18. + type source region 30 and an n + As shown in FIG. 3a, in a plan view, except for the transistor cells 18 along the pad peripheral portion 12 (gate fingers 5), an n-type source region 30 is formed so as to surround the p-type body contact region 31, and further, a p-type body region 29 is formed so as to surround the n-type source region 30. In the p-type body region 29, an annular region surrounding the n-type source region 30 is a channel region 32 where a channel is formed when the semiconductor device 1 is turned on. Although not shown in FIGS. 3a and 3b, the plurality of transistor cells 18 in the outer cell region 45 also have a similar configuration. + type body contact region 31 and are included. Also, the n - type portion of the SiC epitaxial layer 28 is a common drain region of the plurality of transistor cells 18.

[0059] As shown in FIG. 3a, in a plan view, except for the transistor cells 18 along the pad peripheral portion 12 (gate fingers 5), an n + type source region 30 is formed so as to surround the p + type body contact region 31, and further, a p + type body region 29 is formed so as to surround the n - type source region 30. In the p - type body region 29, the n + type source region 30, the annular region surrounding the n-type source region 30 is a channel region 32 where a channel is formed when the semiconductor device 1 is turned on. Although FIGS. 3a and 3b are not shown, the plurality of transistor cells 18 in the outer cell region 45 also have a similar configuration.

[0060] On the other hand, in the transistor cells 18 along the pad peripheral portion 12 (gate fingers 5), the p - type body region 29 and the p + type body contact region 31 are electrically connected to a p - type region 34 and a p + type region 33 to be described later, respectively.

[0061] p - The impurity concentration of the type body region 29 is, for example, 1×10 14 cm -3 ~1×10 19 cm -3 and the impurity concentration of the n + type source region 30 is, for example, 1×10 17 cm -3 ~1×10 21 cm-3 and p + The impurity concentration of the body contact region 31 is, for example, 1×10 19 cm -3 ~1×10 21 cm -3 is.

[0062] To form these regions 29 to 31, for example, p - The p body region 29 is then formed. - By sequentially implanting n-type impurities and p-type impurities into the surface of the body region 29, n + type source region 30 and p + A p-type body contact region 31 is formed. This forms a transistor cell 18 made up of regions 29 to 31. As the p-type impurity, for example, B (boron), Al (aluminum), etc. can be used (the same applies hereinafter).

[0063] In the active region 2, in the region other than the inner and outer cell regions 7 and 45, specifically, in the region below the gate metal 44, the gate finger 5 and the gap region 26, p is formed on the surface of the SiC epitaxial layer 28. - A mold region 34 is formed. - The surface of the mold region 34 is + A mold region 33 is formed.

[0064] p + The SiC epitaxial layer 28 has a p-type region 33 in a region facing the built-in resistor 21. - p in type region 34 - The mold part is selectively exposed on the SiC surface, and in other areas, the p + The mold portion is formed over almost the entire area below the gate metal 44, etc., so that the mold portion is selectively exposed on the SiC surface. That is, the gate metal 44 and the gate finger 5 are p - In most other areas, p +is opposite to the p-type portion. Also, p + type region 33 and p - type region 34 are each formed to extend below the source metal 43, and below the source metal 43 (the outer portion than the source pad 6 in this embodiment), p + type body contact region 31 and p - type body region 29 are integrally connected. In FIG. 3a, the p + type body contact region 31 and p + type region 33 of the transistor cell 18 along the pad peripheral portion 12 (gate finger 5) are represented by the hatched regions. In practical use, the p + type body contact region 31 is fixed to the ground potential together with the source metal 43, whereby the p + type region 33 is stabilized at 0V. Therefore, as in this embodiment, most of the gate metal 44 and the gate finger 5 are preferably opposed to the p + type region 33.

[0065] p + type region 33 and p - type region 34 are each formed in the same process as the p + type body contact region 31 and p - type body region 29, and have the same impurity concentration and depth.

[0066] On the surface of the SiC epitaxial layer 28, a gate insulating film 35 as an example of the insulating film of the present invention is formed. The gate insulating film 35 is made of an insulating material such as silicon oxide and has a thickness of, for example, 0.001 μm to 1 μm. The gate insulating film 35 is a common insulating film for insulating the gate electrode 19 and the built-in resistor 21 from the SiC epitaxial layer 28.

[0067] On the gate insulating film 35, the gate electrode 19 and the built-in resistor 21 are formed. The gate electrode 19 is formed to face the channel region 32 of each transistor cell 18 with the gate insulating film 35 interposed therebetween. On the other hand, the built-in resistor 21 is p -Exposed p in the p-type region 34 - It is formed so as to face the p-type portion with the gate insulating film 35 interposed therebetween.

[0068] Both the gate electrode 19 and the built-in resistor 21 are made of p-type polysilicon and may be formed in the same process. In this embodiment, the gate electrode 19 and the built-in resistor 21 contain B (boron) as a p-type impurity. Boron (B)-containing polysilicon has a higher specific resistance value than phosphorus (P)-containing polysilicon generally used in Si semiconductor devices. Therefore, the boron-containing polysilicon (built-in resistor 21) requires a smaller area than the phosphorus-containing polysilicon even when realizing the same resistance value. Therefore, the occupied area of the built-in resistor 21 on the SiC epitaxial layer 28 can be reduced, and effective use of space can be achieved.

[0069] The concentration of the p-type impurity contained in the polysilicon can be appropriately changed according to the designed resistance value of each of the gate electrode 19 and the built-in resistor 21. In this embodiment, the concentration is set so that the sheet resistance of the built-in resistor 21 is 10 Ω / □ or more. In practical use, if the sheet resistance of the built-in resistor 21 is 10 Ω / □ or more, the resistance value of the entire built-in resistor 21 can be easily increased more than the variation in the resistance values between a plurality of semiconductor devices 1 without increasing the area of the built-in resistor 21. For example, when the variation in the resistance value is 0.1 Ω to 20 Ω, the resistance value of the built-in resistor 21 can be set to 2 Ω to 40 Ω with a small area. As a result, among the regions on the SiC epitaxial layer 28, the area of the region sacrificed for the built-in resistor 21 can be reduced, and the influence on the layout of other elements can be minimized. Also, in this case, the total resistance value of the resistance value of the gate electrode 19 and the resistance value of the built-in resistor 21 is preferably 4 Ω to 50 Ω.

[0070] Also, the thicknesses of the gate electrode 19 and the built-in resistor 21 are preferably 2 μm or less. By setting the thickness of the built-in resistor 21 to 2 μm or less, the resistance value of the entire built-in resistor 21 can be made larger more easily than the variation in the resistance values among the plurality of semiconductor devices 1. Conversely, if the built-in resistor 21 is too thick, its resistance value becomes too low, which is not preferable.

[0071] On the gate insulating film 35, an interlayer film 36 is formed so as to cover the gate electrode 19 and the built-in resistor 21. The interlayer film 36 is made of an insulating material such as silicon oxide and has a thickness of, for example, 0.1 μm to 5 μm.

[0072] Also, the interlayer film 36 is formed so as to enter a region (first region) on the gate insulating film 35 where the gate electrode 19 and the built-in resistor 21 are not arranged. Thereby, in the region where the built-in resistor 21 is not arranged, the distance (thickness T of the insulating film) between the SiC epitaxial layer 28 and the gate metal 44 can be increased, so that the capacitance between them can be reduced.

[0073] The pad-side contact 22 and the cell-side contact 23 are formed so as to penetrate the interlayer film 36. The pad-side contact 22 and the cell-side contact 23 each consist of a metal via formed integrally with the gate metal 44 and the gate finger 5 (pad peripheral portion 12).

[0074] Also, in the interlayer film 36, a source contact 46 for making contact with the source metal 43 with respect to the n + -type source region 31 and the p + -type body contact region 31 is formed to penetrate. The source contact 46 consists of a metal via formed integrally with the source metal 43.

[0075] On the interlayer film 36, the gate metal 44, the gate finger 5, and the source metal 43 are formed at intervals from each other.

[0076] Then, a passivation film 40 is formed on the interlayer film 36 so as to cover the gate metal 44, the gate finger 5, and the source metal 43. Openings 41 and 42 are formed in the passivation film 40 to expose a part of the gate metal 44 and the source metal 43.

[0077] As described above, according to the semiconductor device 1, as shown in FIGS. 3A and 3B, a polysilicon resistor (built-in resistor 21) is interposed between the gate metal 44 and the gate finger 5 (pad peripheral portion 12). That is, the built-in resistor 21 is interposed in the middle of the current path leading from the outside to the plurality of transistor cells 18.

[0078] By adjusting the resistance value of the built-in resistor 21, the resistance value of the built-in resistor 21 can be made dominant in the total resistance value (gate resistance) obtained by adding the resistance value of the gate electrode 19 and the resistance value of the built-in resistor 21. Therefore, even when a plurality of semiconductor devices 1 having variations in the resistance value of the gate electrode 19 are connected in parallel and used, by making the resistance value of the built-in resistor 21 larger than the variations, the flow of current into the semiconductor device 1 having a relatively low resistance value of the gate electrode 19 can be restricted. As a result, the generation of noise during such use can be reduced.

[0079] Moreover, the polysilicon constituting the built-in resistor 21 is a material whose resistance value can be easily controlled by impurity implantation or the like, and its processing is also established by conventional semiconductor manufacturing techniques. Therefore, when introducing the built-in resistor 21, it is also possible to avoid complicating the structure of the semiconductor device 1 itself and the module including the same.

[0080] Regarding the built-in resistor 21 as well, similar to the gate electrode 19, variations in size and thickness may occur due to variations in processing accuracy (etching dimensions, etc.) during the manufacture of the semiconductor device 1, but the processing dimensions are smaller than those of the gate electrode 19. Therefore, it is almost impossible for variations in the built-in resistor 21 to cause noise generation.

[0081] Also, since the built-in resistor 21 is connected to the gate metal 44 below the gate metal 44, the inflow of the gate current can be restricted at the entrance of the current path leading from the outside to the plurality of transistor cells 18. Thereby, it is possible to prevent the inrush current from flowing only into a specific transistor cell 18.

[0082] For example, in FIG. 2, consider a case where the built-in resistor 21 is formed in the middle of the first finger 13 or the second finger 14 of the gate finger 5 as a detour of these fingers 13, 14. In this case, on the side closer to the gate metal 44 than the built-in resistor 21, the inrush current may flow from the fingers 13, 14 to the gate electrode 19 through the gate contact 20 before reaching the built-in resistor 21. On the other hand, if the gate current can be restricted at the entrance of the current path as in this embodiment, the variation in the switching speed among the plurality of transistor cells 18 can be reduced.

[0083] Furthermore, as shown in FIG. 2, the built-in resistors 21 are arranged symmetrically. This feature can also reduce the variation in the switching speed among the plurality of transistor cells 18.

[0084] Also, as shown in FIGS. 3a and 3b, in the SiC epitaxial layer 28, the region facing the built-in resistor 21 is a p 19 cm -3 -type region 34 having an impurity concentration of 1×10 - or less. Therefore, the breakdown of the gate insulating film 35 can be favorably suppressed. Furthermore, since it is difficult for the p - -type region to accumulate carriers compared to the n-type region, the capacitance between the built-in resistor 21 and the p - -type region 34 facing each other across the gate insulating film 35 can also be reduced.

[0085] Also, as shown in FIGS. 3A and 3B, the gate metal 44 and the built-in resistor 21 are connected by a pad-side contact 22 made of a metal via. Therefore, by processing such as changing the position of the pad-side contact 22 along the surface of the SiC epitaxial layer 28 or changing the diameter of the via, the resistance value contributed by the built-in resistor 21 can be easily adjusted in the current path leading from the outside to the plurality of transistor cells 18.

[0086] For example, as in the case of the pad-side contact 37 shown by the dashed line in FIG. 3B, by simply approaching the pad-side contact 22 closer to the pad peripheral portion 12, the distance from the contact position to the pad peripheral portion 12 with respect to the built-in resistor 21 can be easily shortened from D1 to D2. Thereby, the resistance value of the built-in resistor 21 can be reduced. Conversely, if it is moved away from the pad peripheral portion 12, the resistance value of the built-in resistor 21 can be increased. Also, as in the case of the pad-side contact 38 shown by the dashed line in FIG. 3A, by simply reducing the via diameter compared to the pad-side contact 22, the resistance value of the current path leading to the built-in resistor 21 can be increased. Conversely, if the via diameter is increased, the resistance value of the path can be reduced.

[0087] Moreover, for these processes, when forming the pad-side contact 22 (via), it is only necessary to use a mask adapted to the distance design and via diameter design, so it is also possible to prevent the manufacturing process from becoming complicated.

[0088] As described above, the embodiments of the present invention have been described, but the present invention can also be implemented in other forms.

[0089] For example, in the above-described embodiment, the case where the transistor cell 18 is a MOSFET cell having a planar gate structure has been taken up, but the transistor cell 18 may be a MOSFET cell having a trench gate structure as shown in FIG. 4. In this case, the gate electrode 19 is embedded in a gate trench 39 formed between each of the plurality of transistor cells 18 via a gate insulating film 35.

[0090] Further, the transistor cell 18 may be an IGBT cell having a planar gate structure or a trench gate structure. In this case, instead of the n + -type SiC substrate 27, a p + -type SiC substrate 27 may be used.

[0091] Further, the built-in resistor 21 does not have to be embedded in the interlayer film 36 below the gate metal 44. For example, a polysilicon wiring connecting the gate metal 44 and the gate finger 5 may be formed on the surface of the interlayer film 36 as the built-in resistor of the present invention.

[0092] Further, as the material of the built-in resistor 21, instead of polysilicon, a material having a resistance value equal to or larger than that of the gate metal 44 and the gate finger 5 (for example, metal wirings such as Al (aluminum), AlCu (aluminum-copper alloy), Cu (copper), etc.) may be used. Even if the built-in resistor 21 is a metal, the distance between the gate metal 44 and the gate finger 5 can be increased, so that the total resistance value of the resistance value of the gate electrode 19 and the resistance value of the built-in resistor 21 can be increased.

[0093] Further, the built-in resistor 21 does not have to be formed below the gate metal 44. For example, it may be formed below the gate finger 5.

[0094] Further, the built-in resistor 21 may be linear along a part of the peripheral edge 24 of the gate metal 44, or may be annular along the entire circumference of the peripheral edge 24 of the gate metal 44.

[0095] Further, a configuration in which the conductivity types of the semiconductor portions of the semiconductor device 1 described above are inverted may be adopted. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.

[0096] FIG. 5 is an electric circuit diagram showing an electric circuit of a module to which the semiconductor device according to an embodiment of the present invention is applied.

[0097] Module 100 includes a plurality of semiconductor devices (chips) 101 to 104, a drain terminal 105, a source terminal 106, and a gate terminal 107. Each of the semiconductor devices 101 to 104 is composed of the semiconductor device 1 shown in FIGS. 1 to 3. Each of the semiconductor devices 101 to 104 may be composed of the semiconductor device shown in FIG. 4. The plurality of semiconductor devices 101 to 104 are connected in parallel.

[0098] Each of the semiconductor devices 101 to 104 includes a plurality of transistor cells 18 (see FIGS. 2, 3a, and 3b) connected in parallel and four built-in resistors 41 (see FIGS. 2, 3a, and 3b) connected in parallel. In FIG. 5, the plurality of transistor cells 18 connected in parallel are represented by one transistor cell Tr, and the four built-in resistors 41 connected in parallel are represented by one resistor R.

[0099] The gate electrodes of each of the semiconductor devices 101 to 104 are connected to the gate terminal 107 of the module 100 via the built-in resistor R incorporated therein. The drain electrodes of each of the semiconductor devices 101 to 104 are connected to the drain terminal 105 of the module 100. The source electrodes of each of the semiconductor devices 101 to 104 are connected to the source terminal 106 of the module 100.

[0100] In this module 100, a built-in resistor R having a resistance value larger than the gate resistance in each of the semiconductor devices 101 to 104 is incorporated in each of the semiconductor devices 101 to 104. Therefore, in this module 100, compared with the case where an external gate resistor having a resistance value larger than the gate resistance in each of the semiconductor devices 101 to 104 is provided for each of the semiconductor devices 101 to 104, the structure of the module becomes simple.

[0101] Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited only by the appended claims.

[0102] This application corresponds to Japanese Patent Application No. 2013-246474 filed with the Japan Patent Office on November 28, 2013, and the entire disclosure of that application is incorporated herein by reference.

[0103] The following further features can be extracted from this specification.

[0104] "A1" SiC semiconductor layer, A plurality of transistor cells formed on the surface side of the SiC semiconductor layer and controlled to be turned on / off by receiving a control voltage input to a control pad at its control electrode, Disposed on the SiC semiconductor layer side rather than the control pad, including a built-in resistor for electrically connecting the control pad and the control electrode and reducing the variation in on-resistance values of the plurality of transistor cells, On the surface of the control pad, a first wire region where a bonding wire is connected, exposed from a surface insulating film formed on the outermost surface, is selectively formed, The built-in resistor is selectively disposed in a region avoiding the first wire region in a plan view seen from the normal direction of the SiC semiconductor layer, Above the plurality of transistor cells, a main electrode pad to which one main electrode of the plurality of transistor cells is connected and which is different from the control pad is disposed, A semiconductor device in which a second wire region where a bonding wire is connected, exposed from the surface insulating film, is selectively formed on the surface of the main electrode pad.

[0105] In this configuration, it is disposed on the SiC semiconductor layer side rather than the control pad, electrically connects the control pad and the control electrode, and includes a built-in resistor for reducing the variation in the on-resistance values of a plurality of transistor cells. By adjusting the resistance value of this built-in resistor, the resistance value of the built-in resistor can be made dominant in the total resistance value (control resistance) obtained by adding the resistance value of the control electrode and the resistance value of the built-in resistor. Therefore, even when a plurality of semiconductor devices with variations in the resistance value of the control electrode are connected in parallel and used, by making the resistance value of the built-in resistor larger than the variation, the flow of current into a semiconductor device with a relatively low resistance value of the control electrode can be restricted. As a result, the generation of noise during such use can be reduced.

[0106] "A2" The control pad is independently formed surrounded by the surface insulating film. The semiconductor device according to "A1", wherein the built-in resistor is disposed in a region outside the first wire region in the lower region of the control pad via an interlayer film.

[0107] According to this configuration, the flow of the control current can be restricted below the control pad, that is, at the entrance of the current path leading from the outside to a plurality of cells. Thereby, it is possible to prevent an inrush current from flowing only into a specific transistor cell. As a result, the variation in the switching speed among a plurality of transistor cells can be reduced.

[0108] "A3" A part of the built-in resistor is disposed in the lower region of the control pad. In the semiconductor device according to "A2", the interlayer film is embedded in a first region in the lower region of the control pad where the built-in resistor is not disposed.

[0109] "A4" Further includes an insulating film disposed between the built-in resistor and the SiC semiconductor layer. In the semiconductor device according to "A3", a film formed of an extension of the insulating film is disposed between the interlayer film and the SiC semiconductor layer in the first region.

[0110] According to this configuration, in the first region where the built-in resistor is not arranged, the distance (thickness of the insulating film) between the SiC semiconductor layer and the control pad can be increased, so that the capacitance between them can be reduced.

[0111] "A5" In the SiC semiconductor layer, in the region facing the built-in resistor with the insulating film interposed therebetween, 1×10 19 cm -3 The semiconductor device according to "A4", in which an impurity region having the following concentration is selectively formed.

[0112] According to this configuration, since the concentration of the impurity region facing the built-in resistor is 1×10 19 cm -3 or less, dielectric breakdown of the insulating film can be favorably suppressed. In that case, the SiC semiconductor layer is an n-type SiC semiconductor layer, and the semiconductor layer has 1×10 19 cm -3 or less of a p - -type region in the region facing the built-in resistor with the insulating film interposed therebetween. It is preferable that the p - -type region has difficulty accumulating carriers compared to the n-type region, so that the capacitance between the built-in resistor and the p - -type region facing each other with the insulating film interposed therebetween can also be reduced.

[0113] "A6" A part of the built-in resistor is disposed below a peripheral portion of the control pad, The semiconductor device according to any one of "A1" to "A5", wherein the first wire region is formed in a central portion of the control pad surrounded by the peripheral portion.

[0114] "A7" The semiconductor device according to any one of "A2" to "A5", including a contact via that penetrates the interlayer film and electrically connects the control pad and the built-in resistor.

[0115] According to this configuration, in the current path leading from the outside to a plurality of transistor cells, the resistance value contributed by the built-in resistance can be easily adjusted by processing such as changing the position of the contact via along the surface of the SiC semiconductor layer or changing the diameter of the via. Moreover, for these processes, when forming the contact via, it is only necessary to use a mask that matches the distance design and via diameter design, so it is also possible to prevent the manufacturing process from becoming complicated.

[0116] "A8" The semiconductor device according to any one of "A1" to "A7", wherein the built-in resistances are arranged in a plurality with symmetry with respect to each other in a plan view seen from the normal direction of the SiC semiconductor layer.

[0117] According to this configuration, it is possible to prevent an inrush current from flowing only through a specific transistor cell, so that the variation in switching speed among a plurality of transistor cells can be reduced.

[0118] "A9" The semiconductor device according to any one of "A1" to "A8", wherein the control electrode is made of p-type polysilicon.

[0119] "A10" The semiconductor device according to "A9", wherein the control electrode contains B (boron) as a p-type impurity.

[0120] B (boron)-containing polysilicon has a higher specific resistance value than P (phosphorus)-containing polysilicon generally used in Si semiconductor devices. Therefore, the boron-containing polysilicon (built-in resistance) requires a smaller area than phosphorus-containing polysilicon even when realizing the same resistance value. Therefore, the occupied area of the built-in resistance on the SiC semiconductor layer can be reduced, and effective use of space can be achieved.

[0121] "A11" The semiconductor device according to any one of "A1" to "A10", wherein the resistance value of the built-in resistance is 2 Ω to 40 Ω.

[0122] "A12" The semiconductor device according to any one of "A1" to "A11", wherein the total resistance value of the resistance value of the control electrode and the resistance value of the built-in resistor is 4 Ω to 50 Ω.

[0123] "A13" The semiconductor device according to any one of "A1" to "A12", wherein the sheet resistance of the built-in resistor is 10 Ω / sq or more.

[0124] In practical use, if the sheet resistance of the built-in resistor is 10 Ω / sq or more, the resistance value of the entire built-in resistor can be easily increased more than the variation in resistance values between a plurality of semiconductor devices without increasing the area of the built-in resistor. As a result, the area of the region sacrificed for the built-in resistor among the regions on the SiC semiconductor layer can be reduced, and thus the influence on the layout of other elements can be minimized.

[0125] "A14" The semiconductor device according to any one of "A1" to "A13", wherein the size of the built-in resistor in a plan view seen from the normal direction of the SiC semiconductor layer is 200 μm□ or less per one.

[0126] In practical use, if the size of the built-in resistor is 200 μm□ or less per one, the area of the region sacrificed for the built-in resistor among the regions on the SiC semiconductor layer can be reduced, and space saving can be achieved.

[0127] "A15" The semiconductor device according to any one of claims 1 to 14, wherein the thickness of the built-in resistor is 2 μm or less.

[0128] By setting the thickness of the built-in resistor to 2 μm or less, the resistance value of the entire built-in resistor can be easily increased more than the variation in resistance values between a plurality of semiconductor devices. Conversely, if the built-in resistor is too thick, its resistance value becomes too low, which is not preferable.

[0129] "A16" Further including fingers extending from the control pad so as to be disposed on the surface side of the semiconductor device in the same manner as the control pad and partitioning the plurality of transistor cell regions into a plurality of regions. The built-in resistor is the semiconductor device according to any one of "A1" to "A15", which electrically connects the control pad and the finger.

[0130] Thus, the features of the present invention can be favorably applied even to a device in a form in which fingers extend from a control pad.

[0131] "A17" The semiconductor device according to "A16", wherein the finger has a portion arranged to surround the periphery of the control pad.

[0132] "A18" The semiconductor device according to "A16", wherein the finger is made of a metal wiring. By forming the finger with a metal wiring having a lower resistance than polysilicon, a control current can be supplied to cells at positions relatively distant from the control pad in a short time.

[0133] "A19" The semiconductor device according to "A17", wherein the metal wiring is made of any one of Al or AlCu or Cu.

[0134] When the metal wiring is made of Al, since Al is easy to process, the finger formation process can be simplified. When the metal wiring is made of AlCu, the power cycle tolerance can be improved compared to the case of an Al wiring. When the metal wiring is made of Cu, the resistivity can be reduced compared to the cases of an Al wiring and an AlCu wiring.

[0135] "A20" The transistor cell constitutes a MOSFET cell, the control pad is connected to the control electrode of the MOSFET cell, the main electrode pad is connected to the source electrode of the MOSFET cell, The semiconductor device according to any one of "A1" to "A19", including a drain electrode formed on the back side of the SiC semiconductor layer.

[0136] "A21" The MOSFET cell is the semiconductor device according to "A20", including a planar gate structure.

[0137] "A22" The MOSFET cell is the semiconductor device according to "A20", including a trench gate structure.

[0138] "A23" The transistor cell constitutes an IGBT cell, the control pad is connected to the control electrode of the IGBT cell, the main electrode pad is connected to the emitter electrode of the IGBT cell, the semiconductor device according to any one of "A1" to "A19", including a collector electrode formed on the back side of the SiC semiconductor layer.

[0139] "A24" The plurality of transistor cells are arranged in a lattice pattern, and the semiconductor device according to any one of "A1" to "A23".

[0140] "A25" A semiconductor layer, a plurality of transistor cells formed on the surface side of the semiconductor layer, where the control voltage input to the control pad is received by the control electrode and is turned on / off controlled, fingers extending from the control pad so as to partition the region where the plurality of transistor cells are formed into a plurality of regions, and electrically connected to the control pad, including a built-in resistor disposed on the semiconductor layer side of the control pad and the fingers, electrically connecting the control pad and the fingers, and made of a material having the same but larger resistance value than the fingers, on the surface of the control pad, a first wire region where a bonding wire is bonded, exposed from a surface insulating film formed on the outermost surface, is selectively formed, the built-in resistor is selectively disposed in a region avoiding the first wire region in a plan view seen from the normal direction of the semiconductor layer, Above the plurality of transistor cells, a main electrode pad to which one main electrode of the plurality of transistor cells is connected and which is different from the control pad is arranged. A semiconductor device, wherein a second wire region, which is exposed from the surface insulating film and to which a bonding wire is connected, is selectively formed on the surface of the main electrode pad.

[0141] "A26" The built-in resistor is made of metal, and the semiconductor device according to "A25".

[0142] "A27" A semiconductor module characterized in that a plurality of the semiconductor devices according to any one of "A1" to "A26" are connected in parallel.

Explanation of symbols

[0143] 1 Semiconductor device 2 Active region 4 Gate pad 5 Gate finger 7 Inner cell region 12 Pad peripheral part 13 First finger 14 Second finger 15 Main part 16 Branch part 18 Transistor cell 19 Gate electrode 20 Gate contact 21 Built-in resistor 22 Pad side contact 23 Cell side contact 24 Peripheral part 27 SiC substrate 28 SiC epitaxial layer 29 p - -type body region 30 n + -type body region 31 p + -type body contact region 32 Channel region 33 p + -type region 34 p -Type region 35 Gate insulating film 36 Interlayer film 37 Pad side contact 38 Pad side contact 39 Gate trench 44 Gate metal

Claims

1. A gate metal, a pad peripheral portion positioned at a distance from the gate metal, and a plurality of gate fingers extending in different directions from each other, a plurality of built-in resistors positioned below the gate metal in a plan view, each spanning the gate metal and the pad peripheral portion, wherein the plurality of built-in resistors are symmetrically positioned with respect to the planar shape of the gate metal in a plan view and are positioned at substantially equal distances from the centroid position of the planar shape of the gate metal, a semiconductor device.

2. including two built-in resistors as the plurality of built-in resistors, wherein, in a plan view, the two built-in resistors are respectively positioned on two side portions in an opposite side relationship of the gate metal, the semiconductor device according to claim 1.

3. including two built-in resistors as the plurality of built-in resistors, wherein, in a plan view, the two built-in resistors are respectively positioned on two corner portions in a diagonal relationship of the gate metal, the semiconductor device according to claim 1.

4. each of the plurality of built-in resistors has a rectangular shape in a plan view, the semiconductor device according to any one of claims 1 to 3.

5. each of the plurality of built-in resistors has a size of 200 μm□ or less, the semiconductor device according to claim 4.

6. a passivation film covering the gate metal and the gate fingers and having an opening for exposing a part of the gate metal as a gate pad, wherein the passivation film covers an area above the area where the plurality of built-in resistors are located, the semiconductor device according to any one of claims 1 to 5.

7. in a plan view, the passivation film has the opening between areas of the gate metal overlapping the plurality of built-in resistors, the semiconductor device according to claim 6.

8. the thickness of the plurality of built-in resistors is 2 μm or less, the semiconductor device according to any one of claims 1 to 7.

9. the gate metal and the gate fingers are disposed on a semiconductor layer, and the gate metal and the gate fingers face a p-type region formed in the semiconductor layer, the semiconductor device according to any one of claims 1 to 8.

10. the p-type region has the same potential as the source metal, the semiconductor device according to claim 9.

11. The gate metal and the gate fingers are disposed on the semiconductor layer, and the gate metal and the gate fingers face a p-type region formed in the semiconductor layer via the plurality of built-in resistors. The semiconductor device according to any one of claims 1 to 8.

12. The p-type region has an impurity concentration of 1×10 １９ cm ―３ or less, and the semiconductor device according to claim 11.

13. including a plurality of transistor cells, The plurality of transistor cells are MOSFET cells having a planar gate structure or MOSFET cells having a trench gate structure. The semiconductor device according to any one of claims 1 to 12.

14. A plurality of semiconductor devices according to any one of claims 1 to 13 are provided, including gate resistors connected to the gate metals of the plurality of semiconductor devices respectively, A module in which the resistance value of the parallel circuit of the plurality of built-in resistors in each semiconductor device has a resistance value larger than the gate resistance in the semiconductor device.

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