Method of manufacturing semiconductor device including wide band gap semiconductor body

Abstract

To provide a method of manufacturing a semiconductor device including a wide band gap semiconductor body.SOLUTION: The method includes: forming a first mask pattern 102 over a first surface of a wide band gap semiconductor device 100; forming a trench 108 extending from an opening in the first mask pattern into a wide band gap semiconductor body 106, where the trench includes a first sidewall 1081 and an opposite second sidewall 1082; forming a first spacer mask pattern 110 including a first spacer portion 1101 covering the first sidewall and a second spacer portion covering the second sidewall; forming a second mask pattern 112 in the trench between the first spacer portion and the second spacer portion; exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench; and introducing dopants through the trench portion into the wide band gap semiconductor body.SELECTED DRAWING: Figure 1F

Description

[Technical Field]

[0001] The present disclosure relates to methods of fabricating semiconductor devices, and more particularly to methods of fabricating semiconductor devices including wide bandgap semiconductor bodies. [Background technology]

[0002] Technological developments for new generations of wide-bandgap semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate field-effect transistors (IGFETs) like insulated-gate bipolar transistors (IGBTs), aim to improve electrical device characteristics and reduce costs by shrinking device geometries. While shrinking device geometries can reduce costs, increasing device functionality per unit area requires satisfying various tradeoffs and challenges. For example, reducing region-specific on-state resistance (RONxA) can be challenging given process-related variations in placing doped regions relative to each other or trenches relative to doped regions. Such process-related variations can be caused, for example, by process techniques involving different lithography levels.

[0003] There is a need for improved methods for manufacturing wide bandgap semiconductor devices. Summary of the Invention

[0004] An example of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes forming a first mask pattern on a first surface of a wide bandgap semiconductor body. The method further includes forming a trench extending into the wide bandgap semiconductor body from an opening in the first mask pattern. The trench includes a first sidewall and an opposite second sidewall. The method further includes forming a first spacer mask pattern including a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method further includes forming a second mask pattern in the trench between the first spacer portion of the first spacer mask pattern and the second spacer portion of the first spacer mask pattern. The method further includes removing at least a portion of the second spacer portion from the trench to expose a trench portion of the trench and introducing a dopant into the wide bandgap semiconductor body through the trench portion.

[0005] An example of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes forming a first mask pattern on a first surface of a wide bandgap semiconductor body. The method further includes forming a trench extending from an opening in the first mask pattern into the wide bandgap semiconductor body. The trench has a first sidewall and an opposite second sidewall. The method further includes forming a first spacer mask pattern including a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method further includes forming a second mask pattern covering the first spacer portion of the first spacer mask pattern and at least partially exposing the second spacer portion of the first spacer mask pattern. The method further includes exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench. The method further includes introducing a dopant into the wide bandgap semiconductor body through the trench portion.

[0006] An example of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes forming a first mask pattern on a first surface of a wide bandgap semiconductor body. The method further includes forming a trench extending into the wide bandgap semiconductor body from an opening in the first mask pattern. The trench includes a first sidewall and an opposing second sidewall. The method further includes forming a first spacer mask pattern including a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method further includes modifying a structure of the second spacer portion configured to increase selective etching ability of the second spacer portion relative to the first spacer portion. The method further includes exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench. The method further includes introducing a dopant into the wide bandgap semiconductor body through the trench portion.

[0007] An example of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes forming a first mask pattern on a first surface of a wide bandgap semiconductor body. The method further includes forming a trench extending into the wide bandgap semiconductor body from an opening in the first mask pattern. The trench includes a first sidewall and an opposite second sidewall. The method further includes forming a first spacer mask pattern including a first polycrystalline silicon spacer portion covering at least the first sidewall and a second polycrystalline silicon spacer portion covering at least the second sidewall. The method further includes exposing a trench portion of the trench by removing the second polycrystalline silicon spacer portion from the trench. The method further includes modifying a thickness of the first polycrystalline silicon spacer portion by oxidizing a portion of the first polycrystalline silicon spacer portion. The method further includes removing the component.

[0008] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

[0009] The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of fabricating wide bandgap semiconductor devices and, together with the description, serve to explain the principles of the embodiments. Further embodiments are described in the following detailed description and claims. [Brief explanation of the drawings]

[0010] [Figure 1A] 1A to 1C are cross-sectional views for schematically and exemplarily explaining features of a manufacturing process for a wide bandgap semiconductor device. [Figure 1B] 1A to 1C are cross-sectional views for schematically and exemplarily explaining features of a manufacturing process for a wide bandgap semiconductor device. [Figure 1C] 1A to 1C are cross-sectional views for schematically and exemplarily explaining features of a manufacturing process for a wide bandgap semiconductor device. [Figure 1D] 1A to 1C are cross-sectional views for schematically and exemplarily explaining features of a manufacturing process for a wide bandgap semiconductor device. [Figure 1E] 1A to 1C are cross-sectional views for schematically and exemplarily explaining features of a manufacturing process for a wide bandgap semiconductor device. [Figure 1F] 1A to 1C are cross-sectional views for schematically and exemplarily explaining features of a manufacturing process for a wide bandgap semiconductor device. [Figure 2] 1E and 1F are cross-sectional views illustrating process features related to FIG. 1E. [Figure 3] 1A-1C are cross-sectional views illustrating process features associated with forming a spacer mask pattern to form semiconductor regions that are self-aligned to trench edges. [Figure 4] 4A to 4C are cross-sectional views for explaining the characteristics of the process related to FIG. 3. [Figure 5] 1A-1C are cross-sectional views illustrating process features related to the formation of semiconductor regions that are self-aligned to the edges of trenches. [Figure 6]1A-1C are cross-sectional views illustrating process features related to the formation of semiconductor regions that are self-aligned to the edges of trenches. [Figure 7A] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 7B] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 7C] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 7D] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 7E] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 8A] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 8B] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 8C] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 8D] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 8E] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 9A] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 9B] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 9C] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 10A]1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 10B] 1A to 1C are cross-sectional views schematically and exemplarily illustrating features of a manufacturing process for a wide bandgap semiconductor device. [Figure 11] FIG. 7 is a schematic cross-sectional view illustrating an example of the configuration of an n-channel FET manufactured by the process characteristics described with reference to FIGS. 1A to 6. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific examples in which semiconductor substrates may be processed. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described with respect to one example may be used on or with other examples to yield yet another example. The present disclosure is intended to include such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements in different drawings are designated by the same reference numerals unless otherwise noted.

[0012] Terms such as "have," "contain," "include," and "comprise" are open; they indicate the presence of stated structures, elements, or features, but do not exclude the presence of additional elements or features. As defined herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise.

[0013] The term "electrically connected" can refer to a permanent, low-resistance connection between the electrically connected elements, e.g., direct contact between the associated elements or a low-resistance connection via metal and / or heavily doped semiconductor material. The term "electrically coupled" can include that one or more intervening elements adapted for signal and / or power transmission may be connected between the electrically coupled elements, e.g., elements controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0014] When two elements A and B are combined using "or", this should be understood to disclose all possible combinations, i.e., A only, B only, and A and B, unless otherwise explicitly or implicitly defined. Alternative expressions for the same combination are "at least one of A and B" or "A and / or B." The same applies, mutatis mutandis, to combinations of more than two elements.

[0015] Ranges given for physical dimensions are inclusive of the boundaries. For example, a range for a parameter y from a to b is inclusive of a ≤ y ≤ b. The same is true for ranges with a single boundary, such as "up to" and "at least."

[0016] The main components of a layer or structure made of a compound or alloy are the elements whose atoms form the compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0017] The term "on" should not be construed to mean only "directly on." Rather, when one element is disposed on another element (e.g., a layer is "on" another layer or "on" a substrate), additional components (e.g., additional layers) may be disposed between the two elements (e.g., when the layer is "on" a substrate, additional layers may be disposed between the layer and the substrate).

[0018] The description and drawings merely illustrate the principles of the present disclosure. Moreover, all examples recited herein are expressly intended for illustrative purposes only, primarily to aid the reader in understanding the principles of the present disclosure and concepts contributed by the inventors to advance the present technology. All statements herein reciting principles, aspects, and examples of the present disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.

[0019] It should be understood that the disclosure of multiple acts, processes, operations, steps, or functions disclosed in this specification or claims is not to be construed as being in a particular order unless expressly or implicitly stated otherwise, e.g., by phrases such as "then," for technical reasons. Thus, the disclosure of multiple acts or functions does not limit them to a particular order unless such acts or functions are interchangeable for technical reasons. Furthermore, in some instances, a single act, function, process, operation, or step may include or be divided into multiple sub-acts, sub-functions, sub-processes, sub-actions, or sub-steps, respectively. Such sub-acts may be included as part of the disclosure of this single act unless expressly excluded.

[0020] An example configuration of a method for manufacturing a semiconductor device may include forming a first mask pattern on a first surface of a wide bandgap semiconductor body. The method may further include forming a trench extending into the wide bandgap semiconductor body from an opening in the first mask pattern, the trench including a first sidewall and an opposite second sidewall. The method may further include forming a first spacer mask pattern including a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method may further include forming a second mask pattern in the trench between the first spacer portion of the first spacer mask pattern and the second spacer portion of the first spacer mask pattern. The method may further include removing at least a portion of the second spacer portion from the trench to expose a trench portion of the trench and introducing a dopant into the wide bandgap semiconductor body through the trench portion.

[0021] The semiconductor device may be, for example, part of an integrated circuit, or may be a discrete semiconductor device or semiconductor module. The semiconductor device may be, for example, or may include, an insulated gate field effect transistor (IGFET), such as a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The semiconductor device may be a vertical semiconductor device in which a load current flows between a first surface and a second surface opposite the first surface. The vertical power semiconductor device may be configured to conduct a current of greater than 1 A, greater than 10 A, greater than 30 A, greater than 50 A, greater than 75 A, or greater than 100 A, and may be further configured to block a voltage between load electrodes, for example, between the collector and emitter of an IGBT or the drain and source of a MOSFET, in a range from several hundred to several thousand volts, for example, 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, or 10 kV. The blocking voltage may correspond, for example, to a voltage class specified in the data sheet of the power semiconductor device.

[0022] The semiconductor device can be based on a wide-bandgap semiconductor body made of a crystalline wide-bandgap semiconductor material having a bandgap larger than that of silicon, i.e., larger than 1.12 eV. The wide-bandgap semiconductor material can have a hexagonal crystal lattice, and can be, for example, silicon carbide (SiC) or gallium nitride (GaN). For example, the semiconductor material can be 2H-SiC (2H polytype of SiC), 6H-SiC, or 15R-SiC. According to one example, the semiconductor material is silicon carbide of the 4H polytype (4H-SiC). The semiconductor body can include or consist entirely of a semiconductor substrate having one or more semiconductor layers thereon, such as epitaxially grown layers.

[0023] The first surface may be a front or top surface of the wide bandgap semiconductor body, and the wide bandgap semiconductor body may further have a second surface, which may be, for example, a back or bottom surface of the wide bandgap semiconductor body. The wide bandgap semiconductor body may be attached to a lead frame, for example, via the second surface. For example, a bond pad may be disposed on the first surface of the wide bandgap semiconductor body, and a bond wire may be bonded to the bond pad.

[0024] For example, the trench may be striped and define the dimensions of a trench gate structure formed within the trench. Forming the trench gate structure may include forming a trench gate dielectric, for example, by thermal oxidation, and forming a trench gate electrode on the trench gate dielectric within the trench. The trench may also have another layout or geometric shape in plan view, for example, a hexagonal, square, circular, or oval. The trench gate electrode structure may include one or more conductive materials, for example, metals, metal alloys, for example, Ni, Cu, Au, AlCu, Ag, Mo, Ta, W, or alloys thereof, metal compounds, for example, TiN, MoN, or highly doped semiconductor materials, such as highly doped polycrystalline silicon or silicides, for example, TiSi2. The one or more conductive materials may form, for example, a layer stack. An exemplary stacked layer may include a TiN barrier and a W fill. The trench gate electrode structure may be electrically connected to a gate pad, for example, via a gate wiring structure. The gate pad and a first load electrode pad, such as a source pad of a MOSFET or an emitter pad of an IGBT, may be part of an interconnect region on the wide bandgap semiconductor body. Forming the interconnect region may include forming one or more, e.g., two, three, four, or more, interconnect levels. Each interconnect level may be formed by a single conductive layer or a stack of conductive layers, e.g., metal layers. The interconnect levels may be patterned, for example, by lithography. An interlayer dielectric structure may be disposed between the stacked interconnect levels. Contact plugs and / or contact lines may be formed in openings in the interlayer dielectric structure to electrically connect portions of different interconnect levels, e.g., metal lines or contact regions, to each other.

[0025] To achieve a desired current-carrying capacity, a wide bandgap semiconductor device may be designed with multiple wide bandgap semiconductor device cells connected in parallel. The parallel-connected wide bandgap semiconductor device cells may be, for example, wide bandgap semiconductor device cells formed in the shape of a strip or strip segment. Of course, the wide bandgap semiconductor device cells may also have any other shape, such as a circle, an ellipse, a polygon, such as a hexagon, or an octahedron. The wide bandgap semiconductor device cells may be arranged in an active transistor region of a wide bandgap semiconductor body. The active transistor area may be an area where the emitter region of an IGBT (or the source region of a MOSFET) and the collector region of the IGBT (or the drain region of a MOSFET) are arranged opposite each other along the vertical direction. In the active transistor region, load current can enter and exit the wide bandgap semiconductor body of the semiconductor device, for example, through a contact plug on the first surface of the wide bandgap semiconductor body. The wide bandgap semiconductor device may further include an edge termination region, which may include a termination structure. In a blocking mode or reverse bias mode of the wide bandgap semiconductor device, the blocking voltage between the active transistor region and the field-free region is laterally reduced across the termination structure. The termination structure can have a higher or slightly lower voltage blocking capability than the active region. The termination structure can include, for example, a junction termination extension (JTE), one or more laterally isolated guard rings, with or without lateral doping (VLD) variations, or any combination thereof.

[0026] The first mask pattern may be formed as a first hard mask pattern, e.g., an oxide hard mask pattern. The first mask pattern may be defined, for example, by a photolithography process. The dimensions and arrangement of the openings in the first mask pattern may define, for example, a trench layout for forming a trench gate structure of the semiconductor device. The trenches may be formed, for example, by an etching process. Before forming the first mask pattern, the method may further include introducing dopants into the wide bandgap semiconductor body, for example, by ion implantation, to define a semiconductor layer, e.g., a current spreading layer or a body layer, within the wide bandgap semiconductor body.

[0027] For example, dopants may be introduced into the wide bandgap semiconductor body 106 through the bottom surface and / or second sidewall 1082 of the trench 108 by one or more ion implantation processes. Ion implantation parameters, such as ion implantation energy, ion implantation dose, implant tilt angle, and dopant species, such as n-type or -p-type dopants, can form one or more p-type and / or n-type semiconductor regions that are self-aligned to the trench edges. The first mask pattern not only defines the trenches but also functions as an ion implantation mask on the mesas confined by the opposing trenches when implanting dopants through the trench openings. Furthermore, because the first spacer mask pattern is not only formed within the trenches but may also protrude from the first surface of the wide bandgap semiconductor body, the first mask pattern can also serve as a mechanical support structure for the first spacer mask pattern. Therefore, the process features described herein can enable improvements in manufacturing methods with respect to critical dimensions. This can result in smaller transistor cell layouts or transistor cell layouts with higher manufacturing yields.

[0028] For example, the method may further include forming a third mask pattern on the first mask pattern. The third mask pattern may cover upper surfaces of the first spacer portions of the first spacer mask pattern. Upper surfaces of the second spacer portions of the first spacer mask pattern may be exposed by openings in the third mask pattern.

[0029] For example, exposing the trench portion may further include selectively etching the second spacer portion of the first spacer mask pattern relative to either the first mask pattern, or the second mask pattern, or the third mask pattern.

[0030] For example, the material of the first spacer portions of the first spacer mask pattern may be polycrystalline silicon. The material of at least one of the first mask pattern and the second mask pattern may be an oxide of silicon. According to a further example, each of the first spacer portions and the second spacer portions of the first spacer mask pattern may include a spacer of a first material and a cover layer on the spacer. The cover layer may be formed of a second material other than the first material. For example, the second material may be configured to be selectively etched relative to the first material. For example, the first material may be polycrystalline silicon, and the second material may be an oxide of silicon. For example, the cover layer may be formed by thermal oxidation of the spacer. The second mask pattern may be formed, for example, as a resist mask.

[0031] For example, introducing a dopant into the wide bandgap semiconductor body through the trench portion may include introducing the dopant into the wide bandgap semiconductor body through a bottom surface or a second sidewall of the trench by ion implantation. The dopant may define a p-doped shielding region adjacent to the bottom surface and / or the second sidewall of the trench. The p-doped shielding region is self-aligned to an edge of the trench.

[0032] For example, the method may further include removing the first mask pattern. The method may further include forming a second spacer mask pattern including first spacer portions in the trench portion between the wide bandgap semiconductor body and the second mask pattern. The second spacer mask pattern may further include second spacer portions laterally adjacent to the first spacer portions of the first spacer mask pattern.

[0033] For example, removing the first mask pattern may include forming a fourth mask pattern on the first mask pattern. The fourth mask pattern may cover an upper surface of the second mask pattern and an upper surface of the first spacer portion of the first spacer mask pattern. A portion of the first mask pattern may be exposed by an opening in the fourth mask pattern.

[0034] For example, removing the first mask pattern may further include selectively etching the first mask pattern relative to either the first spacer portions of the first spacer mask pattern or the fourth mask pattern.

[0035] For example, the material of the fourth mask pattern may be a resist material.

[0036] For example, the method may further include introducing dopants into the wide bandgap semiconductor body by ion implantation through the openings in the second spacer mask pattern, which may enable defining further semiconductor regions, such as p-doped auxiliary or contact regions for electrically connecting the shielding region to a source electrode, in a self-aligned manner at the edges of the trench by ion implantation through the openings in the second spacer mask.

[0037] For example, the method may further include forming a sixth mask pattern laterally adjacent to the first and second spacer portions of the second mask pattern. The method may further include forming a seventh mask pattern on the sixth mask pattern. The seventh mask pattern may cover a top surface of the second mask pattern and a top surface of the first spacer portion of the second spacer mask pattern. A top surface of the second spacer portion of the second spacer mask pattern may be exposed by an opening in the seventh mask pattern.

[0038] For example, the method may further include exposing a surface portion of the wide bandgap semiconductor body by selectively etching a second spacer portion of the second spacer mask pattern relative to a first spacer portion of the first spacer mask pattern or either the sixth mask pattern or the seventh mask pattern, thereby forming a surface portion of the wide bandgap semiconductor body, e.g., a n + Ion implantation through the doped source region may allow further semiconductor regions to be defined in a self-aligned manner at the edges of the trench.

[0039] For example, the material of the sixth mask pattern may be polycrystalline silicon, and the material of the seventh mask pattern or the seventh mask pattern may be an oxide of silicon or silicon nitride.

[0040] The method may further include introducing a dopant into the wide bandgap semiconductor body through a surface portion of the wide bandgap semiconductor body, for example, by ion implantation. The dopant may, for example, define an n-doped source region.

[0041] For example, the method may further include introducing a dopant into the wide bandgap semiconductor body through the first surface before forming the first mask pattern. For example, the dopant may be introduced into the wide bandgap semiconductor body by ion implantation. The ion implantation may be unmasked relative to the transistor cell region. For example, the dopant may define the body region of an FET. Additionally or alternatively, the dopant may define the current spreading region of the FET. The dopants defining the body region and the current spreading region may have different dopant conductivity types. For example, in the case of an n-channel SiC FET, an n-type dopant, such as nitrogen (N) or phosphorus (P), may define the current spreading region, and a p-type dopant, such as boron (B) or aluminum (Al), may define the body region.

[0042] For example, after forming the trench and before forming the first spacer mask pattern, the method can further include forming a liner to line the bottom and sidewalls of the trench. The liner may also cover the top and sidewalls of the first mask pattern. For example, the material of the liner may be selected for its etch selectivity to the second mask pattern.

[0043] For example, exposing the trench portion can further include removing at least a portion, such as some or all, of the second mask pattern, which can be performed, for example, by an etching process selective to the liner and spacer portions.

[0044] For example, the thickness of the first spacer portion may be increased to a target thickness. Increasing the thickness of the first spacer portion may be performed by a suitable process, such as an oxidation process, depending on the material of the first spacer portion. For example, an oxidation process may be used for a first spacer portion formed of polycrystalline silicon.

[0045] A further exemplary configuration of a method for manufacturing a semiconductor device may include forming a first mask pattern on a first surface of a wide bandgap semiconductor body. The method may further include forming a trench in the wide bandgap semiconductor body through the opening in the first mask pattern. The trench includes a first sidewall and an opposite second sidewall. The method may further include forming a first spacer mask pattern including a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method may further include forming a second mask pattern covering the first spacer portion of the first spacer mask pattern and at least partially exposing the second spacer portion of the first spacer mask pattern. The method may further include exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench. The method may further include introducing a dopant into the wide bandgap semiconductor body through the trench portion.

[0046] For example, each of the first spacer portions and the second spacer portions of the first spacer mask pattern may include a spacer of a first material and a cover layer on the spacer. The cover layer may be formed of a second material other than the first material. For example, the second material may be configured to be selectively etched relative to the first material. For example, the first material may be polycrystalline silicon and the second material may be an oxide of silicon. For example, the cover layer may be formed by thermal oxidation of the spacer.

[0047] For example, the second mask pattern may be a resist mask pattern.

[0048] For example, the cover layer in the second spacer portion may be removed by an etching process using the second mask pattern as an etching mask, followed by removing the resist of the second mask pattern, followed by removing the spacer in the second spacer portion.

[0049] A further exemplary configuration of a method for manufacturing a semiconductor device may include forming a first mask pattern on a first surface of a wide bandgap semiconductor body. The method may further include forming a trench in the wide bandgap semiconductor body through an opening in the first mask pattern. The trench includes a first sidewall and an opposing second sidewall. The method may further include forming a first spacer mask pattern including a first spacer portion covering at least the first sidewall and a second spacer portion covering at least the second sidewall. The method may further include modifying a structure of the second spacer portion configured to increase selective etching ability of the second spacer portion relative to the first spacer portion. The method may further include exposing a trench portion of the trench by removing at least a portion of the second spacer portion from the trench. The method may further include introducing a dopant into the wide bandgap semiconductor body through the trench portion. The selective etchability of the second spacer portion relative to the first spacer portion can be increased by any means that alters the lattice structure, e.g., the crystallinity by damaging the crystalline structure, and / or the lattice composition, e.g., the doping concentration.

[0050] For example, an impurity may be introduced into the second spacer portion by an angled ion implantation process to increase the selective etchability of the second spacer portion relative to the first spacer portion. This can be achieved by changing the doping concentration of the second spacer portion and / or by damaging the crystal structure. The selective etchability can be varied by changing the doping concentration and / or the crystal structure.

[0051] A further exemplary configuration of a method for manufacturing a semiconductor device may include forming a first mask pattern on a first surface of a wide bandgap semiconductor body. The method may further include forming a trench in the wide bandgap semiconductor body through an opening in the first mask pattern. The trench may include a first sidewall and an opposite second sidewall. The method may further include forming a first spacer mask pattern including a first polycrystalline silicon spacer portion covering at least the first sidewall and a second polycrystalline silicon spacer portion covering at least the second sidewall. The method may further include exposing a trench portion of the trench by removing the second polycrystalline silicon spacer portion from the trench. The method may further include modifying a thickness of the first polycrystalline silicon spacer portion by oxidizing a portion of the first polycrystalline silicon spacer portion. The method may further include removing the component.

[0052] For example, the method may further include, after exposing the trench portion, introducing a dopant into the wide bandgap semiconductor body through the trench portion and before modifying the thickness of the first polycrystalline silicon spacer portion.

[0053] For example, the method may further include repeating altering a thickness of the first polycrystalline silicon spacer portion by oxidizing a portion of the first polycrystalline silicon spacer portion and removing the portion.

[0054] For example, the method may further include introducing a dopant into the wide bandgap semiconductor body through the trench portion after modifying the reducing thickness of the first polycrystalline silicon spacer portion.

[0055] Details regarding the structure, function, or technical advantages of features described above with respect to wide bandgap semiconductor devices, such as FETs or IGBTs, apply equally to the exemplary methods described herein. Processing of the semiconductor body may include one or more optional additional features corresponding to one or more aspects of the proposed concept or mentioned in connection with one or more examples above or below.

[0056] Some of the examples above and below are described in relation to silicon carbide substrates. Alternatively, wide bandgap semiconductor substrates, such as wide bandgap wafers, can be processed, including wide bandgap semiconductor materials other than silicon carbide. Wide bandgap semiconductor wafers may have a bandgap larger than that of silicon (1.12 eV). For example, the wide bandgap semiconductor wafer may be a silicon carbide (SiC) wafer, a gallium arsenide (GaAs) wafer, or a gallium nitride (GaN) wafer.

[0057] Further details and aspects are mentioned in relation to the examples above or below. Processing a wide bandgap semiconductor body, such as a wafer, can include one or more optional additional features corresponding to the proposed concept or one or more aspects mentioned in relation to one or more examples above or below.

[0058] Further examples of field-effect transistors (FETs) are described below with reference to the accompanying drawings. The functional and structural details described with respect to the above examples equally apply to the exemplary embodiments shown in the drawings and further described below. In the illustrated examples, n-channel FETs are shown. However, the examples described herein can also be applied to p-channel devices, such as p-channel MOSFETs or p-channel IGBTs.

[0059] Details regarding the structure, function, or technical benefits of the above features apply equally to the following examples, and vice versa.

[0060] The schematic cross-sectional views of FIGS. 1A to 1F show, in a typical and exemplary manner, features of the manufacturing process of the semiconductor device 100. FIG.

[0061] Referring to the schematic cross-sectional view of FIG. 1A, a first mask pattern 102 is formed on a first surface 104, e.g., a surface, of a wide bandgap semiconductor body 106, e.g., a SiC semiconductor body. The wide bandgap semiconductor body 106 may include a semiconductor substrate and one or more semiconductor layers, e.g., a SiC semiconductor substrate and one or more SiC semiconductor layers, that are not on the semiconductor substrate. The first mask pattern 102 may be formed as a hard mask pattern, e.g., an oxide hard mask pattern, by a photolithography process. The first mask pattern 102 has an opening, e.g., opening 1021. The opening 1021 and additional openings, not shown in FIG. 1A, can define transistor cell shapes, e.g., stripe-shaped transistor cell shapes, of the semiconductor device 100. For a stripe-shaped cell geometry, the width of the openings 1021 may be several hundred nanometers, e.g., in the range of 300 nm to 2 μm, and the lateral distance between adjacent openings (e.g., defining the mesa width of a transistor cell) may also be several hundred nanometers, e.g., in the range of 300 nm to 2 μm.

[0062] 1B, a trench 108, e.g., a trench for a trench gate structure, is formed extending from opening 1021 in first mask pattern 102 into wide bandgap semiconductor body 106. For example, trench 108 may be formed by one or more etching processes, e.g., an anisotropic etching technique such as reactive ion etching (RIE). Trench 108 has a first sidewall 1081 disposed opposite a second sidewall 1082 of trench 108 along a first lateral direction x1.

[0063] 1C, a first spacer mask pattern 110 is formed in the wide bandgap semiconductor body 106 and the first mask pattern 102. Thus, the first mask pattern 102 not only serves to define the trench 108 but also serves as a mechanical support structure for the upper portion of the first spacer mask pattern 110 protruding from the first surface 104. The first spacer mask pattern 110 may be formed by a layer deposition process followed by an etching process that removes material of the deposited layer from the bottom surface of the trench 108 and the top surface of the first mask pattern 102. As a result of the spacer etching process, a first spacer portion 1101 and a second spacer portion 1102 may remain, with the first spacer portion 1101 covering at least the first sidewall 1081 and the second spacer portion 1102 covering at least the second sidewall 1082. The first spacer portion 1101 also covers a first sidewall 1026 and a second sidewall 1027 of the first mask pattern 102. The second sidewall 1027 faces the first sidewall 1026 along the first lateral direction x1. The material of the first and second spacer portions 1101 and 1102 of the first spacer mask pattern 110 may be appropriately selected so that the second spacer portion 1102 can be selectively etched with respect to both the first mask pattern 102 and the wide bandgap semiconductor body 106. For example, the first spacer portion 1101 and the second spacer portion 1102 of the first spacer mask pattern 110 may be formed of polycrystalline silicon, e.g., undoped polycrystalline silicon. The first mask pattern 102 may be formed of, e.g., an oxide of silicon.

[0064] Referring to the schematic cross-sectional view of FIG. 1D , a second mask pattern 112 is formed in the trench 108 between the first spacer portion 1101 of the first spacer mask pattern 110 and the second spacer portion 1102 of the first spacer mask pattern 110. The second mask pattern 112 may be formed by a layer deposition process followed by removing a portion of a deposition layer disposed on the first mask pattern 110 and the first and second spacer portions 1101, 1102 of the first spacer mask pattern 110. For example, the portion of the deposition layer can be removed by, for example, chemical mechanical polishing (CMP) or a combination of dry etching and CMP. For example, the deposition layer may be a tetraethyl orthosilicate (TEOS) layer. Patterning of the TEOS layer may also be performed, for example, by a spacer etching process.

[0065] 1E , removing at least a portion of second spacer portion 1102 from trench 108 exposes trench portion 1083 of trench 108. Trench portion 1083 may be exposed by selectively etching second spacer portion 1102 of first spacer mask pattern 102 relative to each of first mask pattern 110, wide bandgap semiconductor body 106, and second mask pattern 112 (see also the discussion related to FIG. 2 below).

[0066] 1F, dopants are introduced into the wide bandgap semiconductor body 106 through the exposed trench portion 1083. For example, p-doped shielding regions may be formed self-aligned to the edges of the trenches 108. The first mask 102 serves as an ion implantation mask for the mesas confined by the opposing trenches 108 when implanting dopants through the exposed trench portion 1083.

[0067] The schematic cross-sectional view of FIG. 2 relates to the process feature shown in FIG. 1E. Referring to FIG. 2, exposing the trench portion 1083 includes forming a third mask pattern 114 on the first mask pattern 102. The third mask pattern 114 covers the top surfaces of the first spacer portions 1101 of the first spacer mask pattern 110. Before removing the second spacer portions 1102 from the trench 108, the top surfaces of the second spacer portions 1102 of the first spacer mask pattern 110 are exposed by the openings 1141 of the third mask pattern 114. For example, the third mask pattern 114 may include a resist mask pattern and an auxiliary mask pattern between the resist mask pattern and the first spacer mask pattern 110. The auxiliary mask pattern may protect the first spacer portions 1102, for example, when etching the second spacer portions 1101 to expose the trench portion 1083. For example, the auxiliary mask pattern may include or be formed by a TEOS layer and / or a nitride layer.

[0068] The additional semiconductor region may be self-aligned to the trench 108 or mesa region defined by the opposing trenches. Referring to the schematic cross-sectional view of Figure 3, after removing the first mask pattern 102, a second spacer mask pattern 116 is formed. The second spacer mask pattern 116 has a first spacer portion 1161 in the trench portion 1083 between the wide bandgap semiconductor body 106 and the second mask pattern 112. The second spacer mask pattern 116 further has a second spacer portion 1162 laterally adjacent to the first spacer portion 1101 of the first spacer mask pattern 110.

[0069] With reference to the exemplary cross-sectional view of FIG. 4, features of an exemplary process for processing a wide bandgap semiconductor body from the process stage shown in FIG. 1F to the process stage shown in FIG.

[0070] Referring to FIG. 4, removing the first mask pattern 102 includes forming a fourth mask pattern 118, e.g., a resist mask pattern, on the first mask pattern 102. The fourth mask pattern 118 covers the top surface of the second mask pattern 112 and the top surfaces of the first spacer portions 1101 of the first spacer mask pattern 110. The fourth mask pattern 118 also fills or covers, without completely filling, the trench portions 1083 that were previously used to form self-aligned semiconductor regions for the trenches 108 via an ion implantation process through the bottom surfaces and / or sidewalls of the exposed trench portions 1083 (see FIG. 1F). A portion of the first mask pattern 102 is exposed by an opening 1181 in the fourth mask pattern 118. The first mask pattern 102 is selectively etched relative to either the first spacer portions 1101 of the first spacer mask pattern 110 or the fourth mask pattern 118. After removing the fourth mask pattern 118 and optionally recessing the second mask pattern 112 from its sides, a spacer patterning process is performed to form the second spacer mask pattern 116 by a spacer layer deposition process followed by a spacer etch process. The process features described above are of an exemplary process for treating the wide bandgap semiconductor body 106 during the process stages shown in Figures 1F and 3.

[0071] 3, dopants are introduced into the wide bandgap semiconductor body 106. For example, by ion implantation, dopants are introduced into the wide bandgap semiconductor body 106 through the openings 1163 of the second spacer mask pattern 116. This allows one or more n- or p-doped semiconductor regions to be formed in a self-aligned manner with respect to the edges of the trenches 108. The lateral distance of the one or more n- or p-doped semiconductor regions relative to the trenches 108 may be adjusted, for example, by the thickness of the second spacer portions 1162. Varying the ion implantation tilt angle can allow for additional flexibility in adjusting the lateral distance of the one or more n- or p-doped semiconductor regions relative to the trenches 108. For example, the p-doped semiconductor regions in an n-channel FET may be adjusted by adjusting the thickness of the second spacer portions 1162. + The doped auxiliary regions may be formed at precise lateral distances relative to the channel region on the trench sidewalls defined by the self-aligned process described above. + The doped auxiliary region may, for example, allow for the electrical connection of the p-doped shield region and / or the p-doped body region to a source electrode.

[0072] The additional semiconductor region may be self-aligned with the trench 108 or mesa region defined by the opposing trenches. Referring to the schematic cross-sectional view of FIG. 5 , a sixth mask pattern 120 is formed laterally adjacent to the first and second spacer portions 1161, 1162 of the second mask pattern 116. For example, the material of the sixth mask pattern 120 may be polycrystalline silicon. Forming the sixth mask pattern 120 may include a layer deposition process, such as a polycrystalline silicon layer deposition process. A first portion of the deposition layer fills the opening 1163 shown in FIG. 3 , and a second portion of the deposition layer covers the top surfaces of the second spacer mask pattern 116, the first spacer mask pattern 110, and the second mask pattern 112. The second portion may then be removed by CMP and / or etching. The remaining first portion of the deposition layer defines the sixth mask pattern 120.

[0073] 5, a seventh mask pattern 122 is formed on the sixth mask pattern 120. For example, the material of the seventh mask pattern 122 may be silicon or silicon nitride oxide. The seventh mask pattern 122 covers the upper surface of the second mask pattern 112 and the upper surfaces of the first spacer portions 1161 of the second spacer mask pattern 116. The upper surfaces of the second spacer portions 1162 of the second spacer mask pattern 116 are exposed through openings 1221 in the seventh mask pattern 122.

[0074] 6, selective etching of second spacer portions 1101 of second spacer mask pattern 116 relative to first spacer portions 1162 of first spacer mask pattern 110 or either sixth mask pattern 120 or seventh mask pattern 122 exposes surface portions of wide bandgap semiconductor body 106. Removal of second spacer portions 1162 leaves openings 128 exposing wide bandgap semiconductor body 106.

[0075] Dopants are introduced into wide bandgap semiconductor body 106 through opening 128, for example, by ion implantation. This allows one or more n- or p-doped semiconductor regions to be formed self-aligned to the edges of trench 102. The width of one or more n- or p-doped semiconductor regions may be adjusted, for example, by the thickness of second spacer portion 1162. For example, dopants implanted through opening 128 may cause n- or p-doped semiconductor regions to be formed. + A doped source region may be formed.

[0076] The schematic cross-sectional views of Figures 7A-7D illustrate features of an exemplary process for fabricating a wide bandgap semiconductor device.

[0077] 1B and further illustrates the formation of a liner 136 lining the bottom and sidewalls 1081, 1082 of the trench 108 and the top and sidewalls 1026, 1027 of the first mask pattern 102. The process features illustrated in FIGS. 1C and 1D can be followed prior to defining the second mask pattern 112.

[0078] 7B , similar to the process features shown in FIG. 2 , exposing trench portion 1083 includes forming a third mask pattern 114 over first mask pattern 102. Third mask pattern 114 covers the top surfaces of first spacer portions 1101 of first spacer mask pattern 110. Openings 1141 in third mask pattern 114 expose the top surfaces of second spacer portions 1102 of first spacer mask pattern 110 before removing second spacer portions 1102 and second mask pattern 112 from trench 108. For example, third mask pattern 114 may include a resist mask pattern and an auxiliary mask pattern between the resist mask pattern and first spacer mask pattern 110. The auxiliary mask pattern and second mask pattern 112 may, for example, protect first spacer portions 1102 when etching second spacer portions 1101 to expose trench portion 1083. The auxiliary mask pattern may include or be formed by an oxide layer, such as a TEOS layer. After removing the second spacer portion 1102 as shown in FIG. 7B and referring to FIG. 7C, the exposed trench portion 1083 is widened by removing the second mask pattern 112, for example, by an etching process selective to the liner 136.

[0079] Referring to the schematic cross-sectional views of FIGS. 7D and 7E, the first spacer portion 1101 may be widened, for example, by an oxidation process. In other words, the thickness of the first spacer portion 1101 may be adjusted, for example, by an appropriate process, such as oxidation, depending on the material of the first spacer portion 1101. For example, if the first spacer portion 1101 is formed of polycrystalline silicon, the widening of the first spacer portion 1101 may occur by fully oxidizing the polycrystalline silicon (see FIG. 7D) or by partially oxidizing the polycrystalline silicon (see FIG. 7E). Once the polycrystalline silicon is partially oxidized, the oxidized portion can be removed, and further process features, such as ion implantation into the semiconductor substrate through the exposed portion of the bottom of the trench, can be performed. The partial oxidation may be repeated so that multiple precisely controlled spacer thicknesses can be achieved within the trench. Each of the multiple precisely controlled spacer thicknesses may be used, for example, to process the semiconductor substrate through the exposed portion of the trench. Similar to FIG. 1E , dopants are introduced into the wide bandgap semiconductor body 106 through the exposed trench portion 1083. For example, a p-doped shielding region may be formed self-aligned to the edge of the trench 108. The first mask 102 functions as an ion implantation mask for the mesa confined by the opposing trench 108 when implanting dopants through the exposed trench portion 1083. For example, dopants introduced through the sidewalls of the trench 108 can define an interconnect region for electrically interconnecting the buried region below the bottom of the trench to a first surface contact. Alternatively or additionally, the interconnect region, or a portion thereof, may be defined, for example, by a masked ion implantation process prior to forming the trench 108.

[0080] The schematic cross-sectional view of FIG. 8A is based on the process features shown in FIG. 1B and further illustrates the formation of a liner 136 lining the bottom and sidewalls 1081 , 1082 of the trench 108 and the top and sidewalls 1026 , 1027 of the first mask pattern 102 .

[0081] 8B is based on the process features shown in FIG. 1C for defining spacers 1105, for example by a partial oxidation process of polycrystalline spacers, followed by forming a cover layer 1106 on the spacers 1105. The spacers 1105 and the cover layer 1106 define first spacer portions 1101 of the first spacer mask pattern 110 and second spacer portions 1102 of the first spacer mask pattern 110.

[0082] Referring to the cross-sectional view of Figure 8C, a second mask pattern 112 is formed as a resist mask pattern that covers the first spacer portion 1101 of the first spacer mask pattern 110 and partially exposes the second spacer portion 1102 of the first spacer mask pattern 110.

[0083] Referring to the cross-sectional view of FIG. 8D, the cover layer 1106 of the second spacer portion 1102 is removed by an etching process using the second mask pattern 112 as an etching mask.

[0084] 8E, after the second mask pattern 112 is removed, the spacers 1105 of the second spacer portions 1102 are removed. Further process features may follow, such as oxidation of the spacers 1105 of the first spacer portions 1101 and / or angled ion implantation through the exposed portions of the trenches 108.

[0085] The partial exposure of second spacer portions 1102 as shown in Figure 8D can also be achieved by a resist mask pattern including two resist sub-patterns. Starting with the cross-sectional view shown in Figure 8B and referring to Figure 9A, resist 1121 is formed over wide bandgap semiconductor body 106 and planarized.

[0086] 9B, resist 1121 is recessed leaving resist remainder 1122 in trench 108. Resist remainder 1122 is hardened, for example, by thermally curing or carbonizing resist remainder 1122.

[0087] 9C, a resist pattern 1123 is formed, covering first spacer portions 1101 of first spacer mask pattern 110 and partially exposing second spacer portions 1102 of first spacer mask pattern 110. Resist pattern 1123 and resist remnants 1122 define second mask pattern 112. Further process features may follow, for example, as shown and described with reference to FIGS.

[0088] 1C , the schematic cross-sectional view of FIG. 10A further illustrates modifying the structure of the second spacer portion 1102 to increase the selective etchability of the second spacer portion 1102 relative to the first spacer portion 1101. The selective etchability of the second spacer portion 1102 relative to the first spacer portion 1101 is increased by introducing impurities into the second spacer portion 1102 via an angled ion implantation process. This increases or decreases the doping concentration of the second spacer portion 1102 and / or increases damage to the crystalline structure of the second spacer portion 1102.

[0089] 10B, trench portion 1083 of trench 108 is exposed by removing second spacer portion 1102 from trench 108, for example, by an etching process. Further process features follow, for example, as described with reference to FIG. 7D.

[0090] The schematic cross-sectional view of FIG. 11 illustrates an example configuration of an n-channel FET 101. Fabrication of the n-channel FET 101 can be based on process features as described and illustrated herein. The n-channel FET 101 has a trench gate structure 130 extending from a first surface 104 into a wide bandgap semiconductor body 106. The trench gate structure includes a trench gate dielectric 1301 and a trench gate electrode 1302. The trench gate structure 130 can be formed in the trench 108 illustrated in FIGS. 1B-6 after defining a semiconductor region in a self-aligned manner with respect to the trench, as described in the examples above. The p-doped region 132 can be defined by multiple overlapping p-doped regions, such as a p-doped body region, a p-doped shielding region, and a p-doped auxiliary region. For example, a first critical dimension cr1 of a first portion (e.g., a p-doped shielding region) of the p-doped region 132 can be defined in a self-aligned manner with the edge of the trench 108, as described with reference to FIGS. 1A-1F. The second critical dimension cr2 of the second portion of the p-doped region 132 (e.g., the p-doped auxiliary region) may be defined in a self-aligned manner with the edge of the trench 108 as described with reference to FIG. + The third critical dimension cr3 of the doped source region 134 may be defined in a self-aligned manner relative to the edges of the trench 108 as described with reference to FIGS.

[0091] Aspects and features mentioned and described in connection with one or more of the foregoing examples and figures may also be combined with one or more of the other examples to replace similar features of the other examples or to introduce additional features into the other examples.

[0092] While specific embodiments have been illustrated and described herein, those skilled in the art will recognize that various alternative and / or equivalent implementations can be substituted for the specific embodiments illustrated and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments described herein. Accordingly, it is intended that the present invention be limited only by the claims and equivalents thereof.

Claims

1. A method of manufacturing a semiconductor device (100), comprising: forming a first mask pattern (102) on a first surface (104) of a wide bandgap semiconductor body (106); forming a trench (108) extending from the opening (1021) of the first mask pattern (102) into the wide bandgap semiconductor body (106), the trench (108) including a first sidewall (1081) and an opposite second sidewall (1082); forming a first spacer mask pattern (110) including a first spacer portion (1101) covering at least the first sidewall (1081) and a second spacer portion (1102) covering at least the second sidewall (1082); forming a second mask pattern (112) in the trench (108) between the first spacer portion (1101) of the first spacer mask pattern (110) and the second spacer portion (1102) of the first spacer mask pattern (110); removing at least a portion of the second spacer portion (1102) from the trench (108) to expose a trench portion (1083) of the trench (108); introducing a dopant into the wide bandgap semiconductor body (106) through the trench portion (1083).

2. exposing said trench portion (1083); 2. The method of claim 1, further comprising forming a third mask pattern (114) on the first mask pattern (102), wherein the third mask pattern (112) covers an upper surface of the first spacer portion (1101) of the first spacer mask pattern (110) and an upper surface of the second spacer portion (1102) of the first spacer mask pattern (110) is exposed by an opening (1141) of the third mask pattern (114).

3. exposing said trench portion (1083); 3. The method of claim 2, further comprising selectively etching the second spacer portions (1102) of the first spacer mask pattern (110) relative to either the first mask pattern (102), the second mask pattern (112), or the third mask pattern (114).

4. 2. The method of claim 1, wherein a material of the first spacer portions (1101) of the first spacer mask pattern (110) is polycrystalline silicon, and a material of at least one of the first mask pattern (102) or the second mask pattern (112) is an oxide of silicon.

5. 2. The method of claim 1, wherein introducing dopants into the wide bandgap semiconductor body through the trench portion comprises introducing dopants into the wide bandgap semiconductor body through a bottom surface or the second sidewall of the trench by ion implantation.

6. removing the first mask pattern (102); forming a second spacer mask pattern (116) including a first spacer portion (1161) in the trench portion (1083) between the wide bandgap semiconductor body (106) and the second mask pattern (112) and a second spacer portion (1162) laterally adjacent the first spacer portion (1101) of the first spacer mask pattern (110); The method of claim 1 further comprising:

7. removing the first mask pattern (102); 7. The method of claim 6, further comprising forming a fourth mask pattern (118) on the first mask pattern (102), wherein the fourth mask pattern (118) covers an upper surface of the second mask pattern (112) and an upper surface of the first spacer portion (1101) of the first spacer mask pattern (110), and a portion of the first mask pattern (102) is exposed by an opening (1181) in the fourth mask pattern (118).

8. removing the first mask pattern (102); 8. The method of claim 7, further comprising selectively etching the first mask pattern (102) relative to either the first spacer portions (1101) of the first spacer mask pattern (110) or the fourth mask pattern (118).

9. 7. The method of claim 6, further comprising introducing dopants into the wide bandgap semiconductor body (106) through openings (1163) of the second spacer mask pattern (116) by ion implantation.

10. forming a sixth mask pattern (120) laterally adjacent to the first and second spacer portions (1161, 1162) of the second mask pattern (116); forming a seventh mask pattern (122) on the sixth mask pattern (120), the seventh mask pattern (122) covering an upper surface of the second mask pattern (112) and an upper surface of the first spacer portion (1161) of the second spacer mask pattern (116), and an upper surface of the second spacer portion (1162) of the second spacer mask pattern (116) being exposed by an opening (1221) in the seventh mask pattern (122); The method of claim 6 further comprising:

11. exposing a surface portion of the wide bandgap semiconductor body (106) by selectively etching the first spacer portion (1101) of the first spacer mask pattern (110) or the second spacer portion (1162) of the second spacer mask pattern (116) relative to either the sixth mask pattern (120) or the seventh mask pattern (122); The method of claim 10 further comprising:

12. 12. The method of claim 11, further comprising introducing dopants into the wide bandgap semiconductor body (106) through the surface portion of the wide bandgap semiconductor body (106) by ion implantation.

13. 10. The method of claim 1, further comprising introducing a dopant into the wide bandgap semiconductor body through the first surface before forming the first mask pattern.

14. After forming the trench (108) and before forming the first spacer mask pattern (110), 2. The method of claim 1, further comprising forming a liner (136) that lines a bottom surface and sidewalls (1081, 1082) of the trench (108) and a top surface and sidewalls (1026, 1027) of the first mask pattern (102).

15. 2. The method of claim 1, wherein exposing the trench portion (1083) further comprises removing at least a portion of the second mask pattern (112).

16. A method of manufacturing a semiconductor device (100), comprising: forming a first mask pattern (102) on a first surface (104) of a wide bandgap semiconductor body (106); forming a trench (108) extending from the opening (1021) of the first mask pattern (102) into the wide bandgap semiconductor body (106), the trench (108) including a first sidewall (1081) and an opposite second sidewall (1082); forming a first spacer mask pattern (110) including a first spacer portion (1101) covering at least the first sidewall (1081) and a second spacer portion (1102) covering at least the second sidewall (1082); forming a second mask pattern (112) covering the first spacer portions (1101) of the first spacer mask pattern (110) and at least partially exposing the second spacer portions (1102) of the first spacer mask pattern (110); removing at least a portion of the second spacer portion (1102) from the trench (108) to expose a trench portion (1083) of the trench (108); introducing a dopant into the wide bandgap semiconductor body (106) through the trench portion (1083).

17. 17. The method of claim 16, wherein each of the first spacer portions (1101) and the second spacer portions of the first spacer mask pattern (110) includes a spacer (1105) of a first material and a cover layer (1106) on the spacer (1105), and the cover layer (1106) is formed of a second material other than the first material.

18. 18. The method of claim 17, wherein the first material is polycrystalline silicon and the second material is an oxide of silicon.

19. 17. The method of claim 16, wherein the second mask pattern (112) is a resist mask pattern.

20. 18. The method of claim 17, wherein the cover layer (1106) of the second spacer portion (1102) is removed by an etching process using the second mask pattern (112) as an etching mask, followed by removing the resist of the second mask pattern (112), and then removing the spacer (1105) of the second spacer portion (1102).

21. A method of manufacturing a semiconductor device (100), comprising: forming a first mask pattern (102) on a first surface (104) of a wide bandgap semiconductor body (106); forming a trench (108) extending from the opening (1021) of the first mask pattern (102) into the wide bandgap semiconductor body (106), the trench (108) including a first sidewall (1081) and an opposite second sidewall (1082); forming a first spacer mask pattern (110) including a first spacer portion (1101) covering at least the first sidewall (1081) and a second spacer portion (1102) covering at least the second sidewall (1082); modifying the structure of the second spacer portion (1102) configured to enhance the selective etching of the second spacer portion (1102) relative to the first spacer portion (1101); removing at least a portion of the second spacer portion (1102) from the trench (108) to expose a trench portion (1083) of the trench (108); introducing a dopant into the wide bandgap semiconductor body (106) through the trench portion (1083).

22. 22. The method of claim 21, wherein selective etching of the second spacer portion (1102) relative to the first spacer portion (1101) is increased by introducing impurities into the second spacer portion (1102) by an angled ion implantation process.

23. A method of manufacturing a semiconductor device (100), comprising: forming a first mask pattern (102) on a first surface (104) of a wide bandgap semiconductor body (106); forming a trench (108) extending from the opening (1021) of the first mask pattern (102) into the wide bandgap semiconductor body (106), the trench (108) including a first sidewall (1081) and an opposite second sidewall (1082); forming a first spacer mask pattern (110) including a first polysilicon spacer portion (1101) covering at least the first sidewall (1081) and a second polysilicon spacer portion (1102) covering at least the second sidewall (1082); removing the second polysilicon spacer portion (1102) from the trench (108) to expose a trench portion (1083) of the trench (108); and modifying a thickness of the first polysilicon spacer portion (1101) by oxidizing a portion of the first polysilicon spacer portion (1101) and removing the portion.

24. 24. The method of claim 23, further comprising, after exposing the trench portion (1083), introducing a dopant into the wide bandgap semiconductor body (106) through the trench portion (1083) and before modifying the thickness of the first polycrystalline silicon spacer portion (1101).

25. 24. The method of claim 23, further comprising repeating the process of varying the thickness of the first polysilicon spacer portion (1101) by oxidizing a portion of the first polysilicon spacer portion (1101) and removing the portion.

26. 26. The method of claim 25, further comprising introducing a dopant into the wide bandgap semiconductor body (106) through the trench portion (1083) after modifying the reducing thickness of the first polycrystalline silicon spacer portion (1101).

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