Semiconductor device

Abstract

To provide a semiconductor device suitable for high heat dissipation.SOLUTION: The semiconductor device includes a substrate on which a plurality of circuit elements is disposed and a first conductive protrusion for external connection, which is provided on the substrate and connected to the plurality of circuit elements. The substrate includes a first base material and a second base material that is disposed on the first base material and made of a material different from that of the first base material. The circuit elements are disposed on the second base material. The first base material has a higher thermal conductivity than the second base material, and the plurality of circuit elements is covered by a single first conductive protrusion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device used in a high frequency circuit and having a heat generating portion. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices have been known in which the semiconductor device is mounted on a mounting substrate via bumps, and the bumps are used as heat dissipation paths.

[0003] For example, Patent Document 1 discloses a compound semiconductor device that includes a heterojunction bipolar transistor (HBT) in which multiple unit transistors are connected in parallel on a compound semiconductor substrate. These multiple unit transistors are arranged on the compound semiconductor substrate, and bumps are electrically connected to the emitters of these multiple unit transistors. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-103540 Summary of the Invention [Problem to be solved by the invention]

[0005] MMICs (Monolithic Microwave Integrated Circuits) that form high-frequency amplifier circuits used in mobile and satellite communications, etc., have recently become faster and more sophisticated, but they are facing performance limitations due to increased RF Front-End (RFFE) losses and self-heating of power amplifier devices. For example, in bipolar transistors, heat is generated due to collector losses, and the temperature rise of the bipolar transistor itself reduces the base-emitter voltage Vbe. This in turn increases the collector current, further reducing Vbe. This positive feedback effect can lead to thermal runaway. If the MMIC's heat dissipation capabilities are poor, the power that can be used without thermal runaway is limited, so there is ultimately a trade-off between the power that can be handled and the size of the MMIC.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device suitable for high heat dissipation. [Means for solving the problem]

[0007] One aspect of the present disclosure provides a semiconductor device comprising: a substrate on which a plurality of circuit elements are arranged; and a first conductor protrusion portion for external connection provided on the substrate and connected to the plurality of circuit elements; the substrate includes a first base material and a second base material arranged on the first base material and made of a different material from the first base material; the circuit elements are arranged on the second base material; the first base material has a higher thermal conductivity than the second base material; and the plurality of circuit elements are covered by a single first conductor protrusion portion. [Effects of the Invention]

[0008] According to the present invention, a semiconductor device with high heat dissipation properties can be obtained. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device 110 according to the first embodiment. [Figure 2] 2A and 2B are cross-sectional views showing the mounting structure of the semiconductor device 110 on a mounting substrate. [Figure 3]FIG. 3A is a cross-sectional view showing the heat dissipation path of the semiconductor device 110, and FIG. 3B is a cross-sectional view showing the heat dissipation path of a semiconductor device of a comparative example. [Figure 4] FIG. 4 is a diagram showing a method for manufacturing the semiconductor device 110. [Figure 5] FIG. 5 is a cross-sectional view of a semiconductor device 111 as a modification of the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device 120 according to the second embodiment. [Figure 7] FIG. 7 is a cross-sectional view of the mounting substrate 90 after the semiconductor device 120 has been mounted thereon. [Figure 8] 8A and 8B are cross-sectional views of a semiconductor device according to the third embodiment. [Figure 9] FIG. 9 is a cross-sectional view of another semiconductor device according to the third embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor device 140 according to the fourth embodiment. [Figure 11] 11A is a cross-sectional view of the AA portion in FIG. 10, and FIG. 11B is a cross-sectional view of the BB portion in FIG. [Figure 12] 12A to 12C are perspective views showing steps in a method for manufacturing a semiconductor device according to the fifth embodiment. [Figure 13] FIG. 13 is a partial cross-sectional view of a semiconductor device formed by processing the first substrate 10 after the transfer of the semiconductor thin film pieces. [Figure 14] FIG. 14 is a cross-sectional view of a semiconductor device 160 according to the sixth embodiment. [Figure 15] 15(A) and 15(B) are cross-sectional views showing the mounting structure of the semiconductor device 160. FIG. [Figure 16] FIG. 16 is a cross-sectional view of a semiconductor device 170 according to the seventh embodiment. [Figure 17] FIG. 17 is a cross-sectional view of a semiconductor device as a comparative example mounted on a mounting board. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, several specific examples will be given with reference to the drawings to illustrate several embodiments for carrying out the present invention. The same reference numerals are used for the same parts in each drawing. For the sake of convenience, the embodiments are shown divided into several embodiments, taking into account ease of explanation and understanding of the main points, but partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0011] First Embodiment 1 is a cross-sectional view of a semiconductor device 110 according to the first embodiment. This semiconductor device 110 includes a substrate 1, a conductor pillar 23 that is in contact with and electrically connected to a second substrate-side electrode 22 provided on this substrate 1, and a solder layer 24 formed on this conductor pillar 23. This conductor pillar 23 and solder layer 24 form a conductor pillar bump PB.

[0012] The substrate 1 includes a first substrate 10 and a second substrate 20 disposed on the first substrate 10. The second substrate 20 has formed thereon a plurality of circuit elements 21 and electrodes for applying an operating voltage or passing an operating current to the plurality of circuit elements 21. The second substrate 20 is formed in a separate process, as will be described later, and the circuit elements are formed on its epitaxial layer. The epitaxial layer is, for example, about 3 μm thick, and the electrodes (wiring layer) are about 10 μm thick. In FIG. 1, the protrusions shown in the circuit element 21 area are electrodes that are electrically connected to the circuit elements.

[0013] Furthermore, in this embodiment, the semiconductor device 110 has a first-substrate-side electrode 12 formed on the surface of the first substrate 10 at a position that does not overlap with the second substrate 20. The semiconductor device 110 also includes a conductor pillar 13 connected to the first-substrate-side electrode 12, and a solder layer 14 formed on the conductor pillar 13. The conductor pillar 13 and the solder layer 14 form a conductor pillar bump PB.

[0014] The conductive pillar bump PB corresponds to the "conductive protrusion" for external connection according to the present invention.

[0015] In this example, the first substrate 10 is a material containing any one of GaAs, AlAs, InAs, InP, GaP, InSb, GaN, InN, AlN, Si, Ge, SiC, Ga2O3, diamond-like carbon (DLC), graphite, diamond, glass, sapphire, and Al2O3, or a multi-component alloy material consisting of a plurality of these materials. The second substrate 20 is a material containing any one of GaAs, AlAs, InAs, InP, GaP, InSb, GaN, InN, AlN, SiGe, SiC, Ga2O3, and GaBi, or a multi-component alloy material consisting of a plurality of these materials. However, the materials selected for the first substrate 10 and the second substrate 20 are different, and the manufacturing processes for the first substrate 10 and the second substrate 20 are different. Basically, the second substrate 20 is made of a material that can provide predetermined electrical properties such as amplification factor and cutoff frequency, and the first substrate 10 is selected to have a higher thermal conductivity than the second substrate 20. These are the same as in other embodiments described below.

[0016] In this embodiment, the first substrate 10 is a Si substrate, and the second substrate 20 is a GaAs substrate. The thermal conductivity of the Si substrate is 156, and the thermal conductivity of the GaAs substrate is 46. The circuit element 21 is, for example, a heterojunction bipolar transistor (HBT) in which a plurality of unit transistors are connected in parallel, and is formed by a process on the GaAs substrate, which is the second substrate 20. The conductor pillar bumps PB are electrically connected to the emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction (the left-right direction in FIG. 1), and the conductor pillar bumps PB are arranged to extend in the first direction.

[0017] The second base material 20 is bonded to the first base material 10 via a bonding layer 11. The bonding layer 11 is, for example, an Au film.

[0018] The conductor pillars 13 and 23 are Cu plated films, and the solder layers 14 and 24 are SnAg alloy films.

[0019] 2(A) and 2(B) are cross-sectional views showing the mounting structure of the semiconductor device 110 on a mounting substrate. Fig. 2(A) is a cross-sectional view of the semiconductor device 110 before it is mounted on the mounting substrate 90, and Fig. 2(B) is a cross-sectional view of the semiconductor device 110 after it has been mounted on the mounting substrate 90.

[0020] Mounting substrate electrodes 91 and 92 are formed on the mounting substrate 90. The solder layers 14 and 24 of the semiconductor device 110 are aligned with the mounting substrate electrodes 91 and 92, and then heated and pressurized, whereby the solder layers 14 and 24 of the semiconductor device 110 are connected to the mounting substrate electrodes 91 and 92, as shown in FIG.

[0021] Here, the structure of a semiconductor device as a comparative example is shown. Fig. 17 is a cross-sectional view of the semiconductor device as a comparative example mounted on a mounting substrate. In the semiconductor device of this comparative example, circuit elements are formed on a GaAs substrate 30. Electrodes 32 and 42 are formed on the surface of the GaAs substrate 30, a conductor pillar 43 and a solder layer 44 are formed on the electrode 42, and the conductor pillar 33 and the solder layer 34 are formed on the electrode 32. In this semiconductor device, the solder layers 34 and 44 are connected to mounting substrate-side electrodes 91 and 92, respectively.

[0022] As shown in FIG. 1, the height of the solder layer 24 differs from that of the solder layer 14 by the thickness of the second base material 20, but this level of difference in height is absorbed by the solder layers 14 and 24.

[0023] The heat dissipation performance of the semiconductor device of the comparative example and the semiconductor device 110 according to the first embodiment will be described with reference to FIGS. 3(A) and 3(B).

[0024] In the semiconductor device as a comparative example, as shown in FIG. 3(B), heat generated in the circuit element is dissipated (exhausted) to the mounting substrate side electrode 92 and the mounting substrate 90 via the electrode 42, the conductor pillar 43, and the solder layer 44, as indicated by the dashed arrows.

[0025] On the other hand, in the semiconductor device 110 of this embodiment, as shown in FIG. 3A, heat is dissipated via three heat conduction paths, as indicated by dashed arrows. The first heat conduction path is a path through which heat generated by the circuit elements is dissipated (exhausted) to the mounting-substrate-side electrode 92 and the mounting substrate 90 via the second-substrate-side electrode 22, the conductor pillar 23, and the solder layer 24. The second heat conduction path is a path through which heat generated by the circuit elements is dissipated (exhausted) to the first substrate 10. The first substrate 10 is a Si substrate with a thermal conductivity of 156 [W / cm K], while the GaAs substrate 30 has a thermal conductivity of 46 [W / cm K]. The thermal conductivity of the first substrate 10 is higher than that of the second substrate 20. Therefore, the first substrate 10 functions as a highly efficient heat radiator. The third heat conduction path is a path that dissipates (exhausts) heat generated in the circuit element to the mounting board side electrode 91 and the mounting board 90 via the first substrate 10, the first substrate side electrode 12, the conductor pillar 13, and the solder layer 14. Since the first substrate 10 acts as a heat conduction path in this way, the conductor pillar 13, the solder layer 14, and the mounting board side electrode 91 also act as heat conduction paths.

[0026] The semiconductor device 110 of this embodiment configured as described above has the following advantages.

[0027] First, by forming three heat dissipation paths, high heat dissipation is achieved. This improves the RF characteristics (output power Pout, power added efficiency PAE) that are limited by the self-heating of the HBT. In other words, a semiconductor device with high output power despite its small size can be obtained. Alternatively, a semiconductor device with high output power despite its small size can be obtained.

[0028] Furthermore, since the second substrate is a compound semiconductor substrate, the electrical insulation properties can be improved, and a circuit with excellent high frequency characteristics can be provided.

[0029] Furthermore, since the second base material 20 is thinner than the first base material 10, a high heat dissipation effect can be obtained by the first base material 10.

[0030] Furthermore, the circuit element 21 formed on the second substrate 20 is a heat generating element that generates heat during operation, and the conductive pillar bump PB is provided in close proximity to the circuit element 21 as a heat generating element, so that the conductive pillar bump forms a short heat conduction path, and the heat generated by the circuit element 21 is dissipated with high efficiency via the conductive pillar bump PB.

[0031] Furthermore, since the second substrate 20 does not extend beyond the outer edge of the first substrate 10 (since it has a smaller area than the first substrate 10), the thermal resistance of the entire substrate 1 including the first substrate 10 and the second substrate 20 is low, and a high heat dissipation effect is obtained from the first substrate 10.

[0032] Furthermore, the first substrate-side electrode 12 is formed on the surface of the first substrate 10 at a position that does not overlap the second substrate 20, and the conductive pillar bump PB is connected to the first substrate-side electrode 12, so a heat dissipation effect is obtained from the conductive pillar bump PB connected to the first substrate-side electrode 12. Furthermore, the efficiency of heat conduction to the circuit board on which the device is mounted is improved via the conductive pillar bump PB, and the heat dissipation performance of the circuit board is also improved.

[0033] Next, a method for manufacturing the semiconductor device 110 will be illustrated. Figure 4 is a diagram showing the method for manufacturing the semiconductor device 110. Figures (1) to (7) in Figure 4 are cross-sectional views of the semiconductor device 110 at intermediate stages in the manufacturing process, and (8) is a cross-sectional view of the completed semiconductor device 110. Although actual manufacturing is performed in wafer units, Figure 4 illustrates a single semiconductor device.

[0034] First, as shown in FIG. 4(1), an Au film is formed as a bonding layer 11 on the surface of a first base material 10 made of a Si base material using a general semiconductor process.

[0035] Next, as shown in (2), the second base material 20 is bonded onto the bonding layer 11. Circuit elements and electrodes have already been formed on the second base material 20 in a separate process.

[0036] Next, as shown in (3), the second substrate side electrode 22 is formed on the second substrate 20, and the first substrate side electrode 12 is formed on the bonding layer 11 by a general semiconductor process.

[0037] Next, as shown in (4), a resist film 85 having openings in the areas where the conductor pillars 13 and the solder layers 14 (FIGS. 1 and 2(A)) are to be formed is formed. The electrodes 12 and 22 are exposed in the openings of the resist film 85.

[0038] Thereafter, as shown in (5) and (6), conductive pillars 13 and 23 and solder layers 14 and 24 are deposited by plating on the electrodes 12 and 22 exposed in the openings of the resist film 85. The conductive pillars 13 and 23 are formed of Cu and have a thickness of, for example, 40 μm. In this way, a CPB (Copper Pillar Bump) is formed. The solder layers 14 and 24 are formed of a SnAg alloy and have a thickness of, for example, 30 μm.

[0039] Thereafter, as shown in (7), the resist film 85 is removed, and finally, a reflow process is performed to melt the solder layers 14, 24, and then solidify them, thereby obtaining the semiconductor device 110 as shown in (8).

[0040] According to the above manufacturing method, since the second base material 20 is a semiconductor thin film, a semiconductor device with a low height and high heat dissipation properties (high thermal conductivity) can be obtained.

[0041] 1 to 4, an Au film is formed as the bonding layer 11, but other metal films such as a Pt film or a Pd film can also be used. The bonding layer 11 preferably has a higher thermal conductivity than the second substrate 20. This allows heat from the second substrate 20 to be efficiently dissipated to the first substrate 10 via the bonding layer 11. For example, the thermal conductivity of the GaAs substrate that is the second substrate 20 is 46 [W / mK], whereas the thermal conductivity of the Au film is 319 [W / mK], the thermal conductivity of the Pt film is 70 [W / mK], and the thermal conductivity of the Pd film is 70 [W / mK], all of which have higher thermal conductivities than the second substrate 20.

[0042] Furthermore, it is more preferable that the bonding layer 11 has a lower elastic modulus than the second substrate 20. There is a difference in the linear expansion coefficient between the first substrate 10 and the second substrate 20, and thermal stress occurs due to the difference in linear expansion coefficient when the temperature changes. However, since the bonding layer 11 has a lower elastic modulus than the second substrate 20, the thermal stress is reduced. This ensures a substantial bonding strength between the first substrate 10 and the second substrate 20 via the bonding layer 11. For example, the elastic modulus of a GaAs substrate is 85.5 GPa, while the elastic modulus of an Au film is 78 GPa, the elastic modulus of an Al film is 68.3 GPa, and the elastic modulus of an In film is 10.8 GPa, all of which are lower than the elastic modulus of the second substrate 20.

[0043] When the bonding layer 11 is made of a metal, it is preferable to form an alloy layer between the bonding layer 11 and the second base material 20. This provides higher adhesion and higher thermal conductivity.

[0044] The bonding layer 11 may be a dielectric made of an organic material such as a polyimide (PI) film, polybenzoxazole (PBO), or benzocyclobutene (BCB). The bonding layer 11 preferably has a lower dielectric constant than the second substrate 20. The high-frequency characteristics of the circuit elements formed on the second substrate 20 include the transmission loss characteristics of high-frequency signals. If the dielectric constant of the bonding layer 11 is higher than that of the second substrate 20, the proximity of the bonding layer 11 reduces the transmission loss characteristics of the high-frequency signals of the circuit elements. If the dielectric constant of the bonding layer 11 is lower than that of the second substrate 20, this reduction in transmission loss characteristics can be avoided. For example, the relative dielectric constant of the GaAs substrate used as the second substrate 20 is 12.9, whereas the dielectric constant of polyimide (PI) is 3.3, the dielectric constant of polybenzoxazole (PBO) is 2.9, and the dielectric constant of benzocyclobutene (BCB) is 2.7, all of which have lower dielectric constants than the second substrate 20.

[0045] It is preferable that the bonding layer 11 has a smaller dielectric dissipation factor than the second substrate 20. If the dielectric dissipation factor of the bonding layer 11 is large, the high-frequency loss caused by the bonding layer 11 increases. If the dielectric dissipation factor of the bonding layer 11 is smaller than the dielectric dissipation factor of the second substrate 20, this increase in high-frequency loss can be avoided. For example, the dielectric dissipation factor of the GaAs substrate, which is the second substrate 20, is 0.3, whereas the dielectric dissipation factor of polyimide (PI) is 0.0020, the dielectric dissipation factor of polybenzoxazole (PBO) is 0.0100, and the dielectric dissipation factor of benzocyclobutene (BCB) is 0.0008, all of which have smaller dielectric dissipation factors than the second substrate 20.

[0046] Furthermore, even when the bonding layer 11 is made of an organic material, it is more preferable that the bonding layer 11 has a lower modulus of elasticity than the second substrate 20. This ensures substantial bonding strength between the first substrate 10 and the second substrate 20 via the bonding layer 11. For example, the modulus of elasticity of a GaAs substrate is 85.5 GPa, whereas the modulus of elasticity of polyimide (PI) is 2.5, the modulus of elasticity of polybenzoxazole (PBO) is 2.8, and the modulus of elasticity of benzocyclobutene (BCB) is 2.1, all of which have lower moduli of elasticity than the second substrate 20.

[0047] Furthermore, the bonding layer 11 may be an insulator such as AlN, SiC, or diamond. It is preferable that the bonding layer 11 has a higher electrical resistivity than the first substrate 10. If the electrical resistivity of the bonding layer 11 is higher than that of the first substrate 10, induced currents and eddy currents flowing in the bonding layer 11 and the first substrate 10 are suppressed, and therefore, good high-frequency characteristics of the circuit elements formed on the second substrate 20 can be maintained.

[0048] Furthermore, even when the bonding layer 11 is an insulator, it is preferable that the bonding layer 11 has a higher thermal conductivity than the first substrate 10. This allows heat from the second substrate 20 to be dissipated to the first substrate 10 with high efficiency via the bonding layer 11. For example, the thermal conductivity of the Si substrate that is the first substrate 10 is 156 [W / cm K], whereas the thermal conductivity of the AlN film is 170 [W / cm K], the thermal conductivity of the SiC film is 270 [W / cm K], and the thermal conductivity of the diamond film is 2000 [W / cm K], all of which have higher thermal conductivities than the first substrate 10.

[0049] Next, a modification of the first embodiment will be described. Fig. 5 is a cross-sectional view of a semiconductor device 111 as this modification. This semiconductor device 111 does not include the bonding layer 11 shown in Fig. 1. The second substrate 20 is directly bonded to the first substrate 10. This bonding is by van der Waals bonding or hydrogen bonding. Alternatively, bonding may be by electrostatic force, covalent bonding, eutectic alloy bonding, or the like.

[0050] The first substrate side electrode 12 is formed directly on the upper surface of the first substrate 10, and on this first substrate side electrode 12, a conductive pillar bump PB made of a conductive pillar 13 and a solder layer 14 is formed.

[0051] In this way, the second base material 20 may be bonded to the first base material 10 without an adhesive layer therebetween.

[0052] Second Embodiment In the second embodiment, a semiconductor device having a different configuration of the conductor protrusion from that of the first embodiment will be described.

[0053] Fig. 6 is a cross-sectional view of a semiconductor device 120 according to the second embodiment. Unlike the example shown in Fig. 1, the semiconductor device 120 does not include the first substrate-side electrode 12 and the conductor protrusions (conductor pillars 13 and solder layers 14) for external connection connected to the first substrate-side electrode 12.

[0054] 7 is a cross-sectional view of the semiconductor device 120 after it has been mounted on the mounting substrate 90. Mounting substrate electrodes 92 are formed on the mounting substrate 90. The semiconductor device 120 has its conductive pillar bumps PB aligned with the mounting substrate electrodes 92, and the solder layers 24 are connected to the mounting substrate electrodes 92 by applying heat and pressure.

[0055] Even with this structure, heat is dissipated (exhausted) in two directions from the heat-generating portion, as shown by the dashed arrows in the figure.

[0056] Third Embodiment In the third embodiment, several semiconductor devices including a planarizing resin layer will be exemplified.

[0057] 8(A) and 8(B) are cross-sectional views of semiconductor devices 130A and 130B according to the third embodiment. These semiconductor devices 130A and 130B include a first substrate 10 and a second substrate 20 disposed on the first substrate 10. The second substrate 20 includes a semiconductor substrate 20N made of a compound semiconductor and an epitaxial layer 20D formed on the surface thereof. A plurality of circuit elements 21 are formed on the epitaxial layer 20D.

[0058] A second substrate-side electrode 22 that is electrically connected to the circuit element 21 is formed on the upper surface of the epitaxial layer 20D. A planarizing resin layer 15 is formed on the surfaces of the first substrate 10 and the second substrate 20. A conductor pillar bump PB made of a conductor pillar 23 and a solder layer 24 is formed on the upper portion of the second substrate-side electrode 22.

[0059] In the example shown in FIG. 8(B), a bonding layer 11 is formed on the upper surface of the first base material 10, and the second base material 20 is bonded to the first base material 10 via the bonding layer 11.

[0060] 9 is a cross-sectional view of another semiconductor device 131 of the third embodiment. This semiconductor device 131 includes a first substrate 10 and a second substrate 20 disposed on the first substrate 10. A plurality of circuit elements are configured on the second substrate 20. A bonding layer 11 is formed on the upper surface of the first substrate 10. A planarizing resin layer 15 is formed on the surfaces of the bonding layer 11 and the second substrate 20. A conductive pillar bump PB made of a conductive pillar 13 and a solder layer 14 is formed on the upper portion of the first substrate-side electrode 12.

[0061] The planarizing resin is, for example, a polyimide (PI) film, polybenzoxazole (PBO), benzocyclobutene (BCB), etc. By forming the planarizing resin layer 15 on the surfaces of the first substrate 10 and the second substrate 20 in this manner, it becomes easy to form the relatively thick conductor pillars 23 and solder layers 24. In addition, the surfaces of the first substrate 10 and the second substrate 20 are repassivated.

[0062] Fourth Embodiment In the fourth embodiment, an example of one semiconductor device having conductor protrusions for external connection at multiple locations will be described.

[0063] Fig. 10 is a plan view of a semiconductor device 140 according to the fourth embodiment. Fig. 11(A) is a cross-sectional view of the AA portion in Fig. 10, and Fig. 11(B) is a cross-sectional view of the BB portion in Fig. 10.

[0064] In the semiconductor device 140 of this embodiment, solder layers 14, 24 are formed on a plurality of conductor pillars. As shown in Figures 10 and 11(A), heterojunction bipolar transistors (HBTs) 51A, 51B are formed in predetermined locations on the semiconductor device 140, each of which has a plurality of unit transistors arranged in the left-right direction in Figure 10 and connected in parallel. A conductor pillar bump PB made of a conductor pillar 23 and a solder layer 24 is formed on top of the HBTs 51A, 51B. The configurations of the HBTs 51A, 51B, the conductor pillar 23, and the solder layer 24 are as shown in the first embodiment.

[0065] Conductive pillar bumps PB made of conductive pillars 13 and solder layers 14 are formed on both sides of the two HBTs 51A and 51B.

[0066] 10, the conductive pillar bumps PB are also formed in cross sections other than the AA cross section. These conductive pillar bumps PB are arranged in the vicinity of the HBTs 51A and 51B. With this configuration, heat generated by the HBTs 51A and 51B is dissipated with high efficiency.

[0067] In addition to the HBTs 51A and 51B, the semiconductor device 140 includes an LCR circuit formed of an inductor formed by a spiral conductor pattern, a capacitor formed by electrodes facing each other across a dielectric layer, and a resistor element formed by a resistor film pattern.

[0068] As shown in Figures 10 and 11(B), a bonding layer 11 is formed on the surface of a first base material 10, and an insulator layer 16 is formed at a predetermined location on the surface of this bonding layer 11. A spiral inductor 52 is formed on the surface of this insulator layer 16. Adjacent to this spiral inductor 52, a conductor pillar bump PB made of a conductor pillar 13 and a solder layer 14 is formed. Also, a MIMC (Metal-Insulator-Metal-Capacitor) 53 is formed at a predetermined location on the semiconductor device 140 shown in Figures 10 and 11(B). Adjacent to this MIMC 53, a conductor pillar bump PB made of a conductor pillar 13 and a solder layer 14 is formed.

[0069] Fifth Embodiment In the fifth embodiment, a method for manufacturing a second base material and a method for joining the second base material to the first base material will be described.

[0070] 12A to 12C are perspective views showing steps in the fifth embodiment. Although actual manufacturing is performed in wafer units, FIG. 12A to 12C show a single semiconductor device.

[0071] 12(1), a release layer 29 is first formed on a mother substrate 200, which is a compound semiconductor substrate, and then a semiconductor thin film is formed on the release layer 29 by epitaxial growth. A plurality of circuit elements and electrodes connected to the circuit elements are then formed on the semiconductor thin film. This portion becomes the second substrate 20.

[0072] Next, as shown in (2), the second base material 20 (semiconductor thin film piece) is peeled off from the mother substrate 200 by selectively etching only the peeling layer 29.

[0073] As shown in (3), in a separate process, a bonding layer 11 is formed on the first substrate 10, and as shown in (4), the second substrate 20 is pressed against and adhered to the surface of the bonding layer 11, thereby bonding the second substrate 20 to the first substrate 10. In other words, the semiconductor thin film piece is transferred from the mother substrate 200 to the first substrate 10. For example, the Au of the bonding layer 11 diffuses into the GaAs of the second substrate and forms a eutectic, thereby forming a bond.

[0074] The formation of circuit elements and electrodes on the second substrate 20 can be performed not only in the step shown in (1), but also by a process (photolithography and etching process) on the second substrate 20 after bonding the second substrate 20 to the first substrate 10, as shown in (4).

[0075] The method of peeling and transferring the semiconductor thin film flakes can be the method disclosed in Japanese Patent No. 5132725. That is, as shown in FIG. 12 (2), when peeling the second substrate 20 (semiconductor thin film flakes) from the mother substrate 200, the second substrate 20 is peeled from the mother substrate 200 while being supported by a support. Also, as shown in FIG. 12 (3), when bonding the second substrate 20 to the first substrate 10, it is done while being supported by the support. In FIG. 12 (2) and (3), the support is omitted for the sake of clarity of the second substrate 20.

[0076] 13 is a partial cross-sectional view of a semiconductor device formed by processing the first substrate 10 after the transfer of the semiconductor thin film pieces. The second substrate 20 comprises a semiconductor substrate 20N and a circuit element 21, which is a bipolar transistor, formed on the surface thereof. A second substrate-side electrode 22 is formed on the upper part of the second substrate 20. In this example, the second substrate-side electrode 22 is an emitter wiring. A planarizing resin layer 15 is formed on the bonding layer 11 of the first substrate and on the surface of the second substrate 20.

[0077] A conductor pillar bump PB made of a conductor pillar 23 and a solder layer 24 is formed on the second substrate side electrode 22, which is the emitter wiring.

[0078] Both the semiconductor substrate 20N and the epitaxial layer 20D have a thickness of several μm. For example, the semiconductor substrate 20N is 1 μm, and the epitaxial layer 20D is 3 μm. Conventionally, when wire bonding to a compound semiconductor element, the semiconductor substrate 20N and the epitaxial layer 20D need to have a total thickness of 75 μm or more. However, in this embodiment, the thickness of the second substrate 20 added to the upper part of the first substrate 10 is only several μm, so that a semiconductor device that is very thin (low profile) overall can be configured.

[0079] Sixth Embodiment In the sixth embodiment, a semiconductor device characterized by the structure of a bonding layer that bonds a first base material 10 and a second base material 20 together will be described.

[0080] 14 is a cross-sectional view of a semiconductor device 160 according to a sixth embodiment. This semiconductor device 160 includes a first substrate 10 and a second substrate 20 disposed on the first substrate 10. The second substrate 20 includes a semiconductor substrate made of a compound semiconductor and an epitaxial layer formed on the surface thereof, and a plurality of circuit elements 21 are formed in the epitaxial layer. In this example, the first substrate 10 is a Si substrate, and the second substrate 20 is a GaAs substrate.

[0081] A bonding layer 19 is provided between the first substrate 10 and the second substrate 20. That is, the first substrate 10 and the second substrate 20 are bonded via the bonding layer 19. A first substrate-side electrode 12 is formed on the surface of the bonding layer 19. A second substrate-side electrode 22 is formed on the surface of the second substrate 20. A planarizing resin layer 15 is formed on the surfaces of the first substrate 10 and the second substrate 20. A conductor pillar bump PB made of a conductor pillar 13 and a solder layer 14 is formed on the top of the first substrate-side electrode 12. A conductor pillar bump PB made of a conductor pillar 23 and a solder layer 24 is formed on the top of the second substrate-side electrode 22.

[0082] The bonding layer 19 is a layer of a composite material including an insulator layer 17 and a metal layer 18. The insulator layer 17 is, for example, a layer of a Si compound such as an SiO2 film or an SiN film, or a layer of a resin such as a polyimide (PI) film. The metal layer 18 is, for example, a Cu film or an Al film. The bonding layer 19 has a three-layer structure. In this bonding layer 19, an insulator layer 17 as a first layer is formed on the surface of the first substrate 10, a metal layer 18 as a second layer is formed on the surface of this insulator layer 17, and an insulator layer 17 as a third layer is formed on the surface of this metal layer 18. The metal layer 18 is patterned, and patterns of the metal layer 18 are formed near the second substrate 20 and near the first substrate-side electrode 12, respectively.

[0083] Because the bonding layer 19 is a composite material layer including the insulator layer 17 and the metal layer 18, the bonding layer 19 reduces stress caused by the difference in the linear expansion coefficients between the first substrate 10 and the second substrate 20. The linear expansion coefficients of the first substrate 10, the second substrate 20, and the bonding layer 19 are as follows: For example, the linear expansion coefficient of the Si substrate serving as the first substrate 10 is 2.60 [ppm / °C], and the linear expansion coefficient of the GaAs substrate serving as the second substrate 20 is 5.73 [ppm / °C]. In contrast, the linear expansion coefficient of a SiO2 film made of tetraethoxysilane (TEOS) is 0.57 [ppm / °C], and the linear expansion coefficient of a SiN film is 2.30 [ppm / °C], which are lower than those of the first substrate 10 and the second substrate 20. In addition, the linear expansion coefficient of a Cu film serving as the metal layer 18 is 17.0 [ppm / °C], which is higher than those of the first substrate 10 and the second substrate 20. Therefore, the linear expansion coefficient of the bonding layer 19 is an intermediate value between the linear expansion coefficient of the first substrate 10 and the linear expansion coefficient of the second substrate 20, and stress at the interface between the second substrate 20 and the first substrate 10 is alleviated.

[0084] If the insulator layer 17 is a layer of a Si compound such as an SiO2 film or an SiN film, it becomes easier to form the insulator layer 17 on the first base material 10, and the bonding strength between the first base material 10 and the insulator layer 17 can be increased.

[0085] Only the uppermost layer of the insulator layer 17 may be a resin layer. In this way, when at least a part of the insulator layer 17 is a layer made of a resin film, the above-mentioned stress is absorbed by the flexibility of the insulator layer 17, regardless of the magnitude relationship of the linear expansion coefficient. In addition, the insulator layer 17 can also relieve the stress generated between the metal layer 18 and the insulator layer 17 in the bonding layer 19.

[0086] The second substrate 20 expands and contracts due to the generation and stopping of heat in the circuit elements 21 formed on the second substrate 20, but this expansion and contraction is more severe than the expansion and contraction of the first substrate 10 which is distant from the circuit elements 21. This tendency remains the same even if the linear expansion coefficients of the first substrate 10, the second substrate 20, and the bonding layer 19 do not have the above-mentioned relationship. According to this embodiment, the presence of the bonding layer 19 alleviates stress at the interface between the second substrate 20 and the first substrate 10.

[0087] 15(A) and 15(B) are cross-sectional views showing the mounting structure of the semiconductor device 160. Fig. 15(A) is a cross-sectional view at a stage before the semiconductor device 160 is mounted on the mounting substrate 90, and Fig. 15(B) is a cross-sectional view after the semiconductor device 160 has been mounted on the mounting substrate 90.

[0088] Mounting substrate electrodes 91 and 92 are formed on the mounting substrate 90. The solder layers 14 and 24 of the semiconductor device 160 are aligned with the mounting substrate electrodes 91 and 92, and then heated and pressurized, whereby the solder layers 14 and 24 of the semiconductor device 160 are connected to the mounting substrate electrodes 91 and 92, as shown in FIG.

[0089] In this way, the conductive pillar bumps PB formed on the second substrate-side electrodes 22 act as terminals that connect the circuit elements 21 formed on the second substrate 20 to the circuit of the mounting board. In addition, the conductive pillar bumps PB formed on the second substrate-side electrodes 22 also act as heat dissipation bumps that dissipate heat generated by the circuit elements 21 formed on the second substrate 20 to the mounting board.

[0090] The metal layer 18 in the bonding layer 19 increases the thermal conductivity of the bonding layer 19. Therefore, heat generated by the circuit element 21 formed on the second substrate 20 is also dissipated to the first substrate 10 via the bonding layer 19. In addition, the metal layer 18 in the bonding layer 19 increases the thermal conductivity in the surface direction (lateral direction) of the bonding layer 19, so the heat generated by the circuit element 21 is also dissipated to the mounting board 90 via the metal layer 18 near the first substrate-side electrode 12 and the conductive pillar bump PB formed on the first substrate-side electrode 12. In addition, the heat generated by the circuit element 21 is also dissipated to the first substrate 10 via the metal layer 18 near the first substrate-side electrode 12.

[0091] 14, the metal layer 18 is an independent entity, but it may be connected to the first substrate-side electrode 12. It may also be connected to a circuit formed on the first substrate 10.

[0092] Seventh Embodiment In the seventh embodiment, a semiconductor device characterized by the structure of a bonding layer that bonds a first base material 10 and a second base material 20 together will be described.

[0093] 16 is a cross-sectional view of a semiconductor device 170 according to the seventh embodiment. This semiconductor device 170 includes a first base material 10 and a second base material 20 disposed on the first base material 10. The configuration of the bonding layer 19 differs from the example shown in FIG. 14 of the sixth embodiment. The other configurations are the same as those shown in the sixth embodiment.

[0094] The bonding layer 19 is a layer of a composite material including an insulator layer 17 and a metal layer 18. The insulator layer 17 is, for example, a layer of a Si compound such as an SiO2 film or an SiN film, or a resin layer such as a polyimide (PI) film. The metal layer 18 is, for example, a Cu film or an Al film. The bonding layer 19 has a five-layer structure. As in the example shown in FIG. 14, the patterns of the metal layer 18 are formed near the second substrate 20 and near the first substrate-side electrode 12, respectively.

[0095] The bonding layer 19 is formed in the next step. (1) An insulating layer 17 is formed as a first layer on the surface of the first base material 10. (2) A metal layer 18A is formed as a second layer on the surface of the insulating layer 17. (3) An insulating layer 17 is formed as a third layer on the surface of this metal layer 18. (4) An opening is formed in a predetermined position of the insulating layer 17 (where the underlying metal layer 18A will be formed). (5) A metal layer 18C is formed on the insulating layer 17, and a metal layer 18B is formed in the opening. (6) An insulating layer 17 is formed as the top layer.

[0096] According to this embodiment, since the metal layer 18 has a multilayer structure, the thermal resistance of the bonding layer 19 can be kept low even if the thickness of the bonding layer 19 is large. This improves the heat dissipation of the circuit element 21. Furthermore, since the heat capacity of the bonding layer 19 is large, the effect of suppressing the temperature rise is high even if the circuit element 21 suddenly generates heat.

[0097] As described in the sixth embodiment, the metal layer 18 may be connected to the first substrate-side electrode 12. The metal layer 18 may also be connected to a circuit formed on the first substrate 10.

[0098] The configurations and effects of each embodiment have been described above, and the aspects disclosed in the embodiments can be listed as follows.

[0099] A semiconductor device according to one embodiment of the present disclosure comprises a substrate 1 having a circuit element 21 on its surface and an electrode connected to the circuit element, and a conductive pillar bump PB for external connection provided on the substrate 1 and connected to the electrode or the circuit element 21, the substrate 1 including a first substrate 10 and a second substrate 20 disposed on the first substrate 10 and made of a different material from the first substrate 10, the circuit element 21 and the electrode being formed on the second substrate 20, and the first substrate 10 having a higher thermal conductivity than the second substrate 20.

[0100] With the above configuration, heat is dissipated via the conductive pillar bumps PB and the first substrate 10. In other words, high heat dissipation is achieved by forming heat dissipation paths from both sides. Furthermore, since circuit elements are provided in the semiconductor region formed in the second substrate 20, which is not limited by the level of thermal conductivity, a circuit is configured that effectively utilizes the physical properties of the second substrate 20, and high heat dissipation by the first substrate 10 is maintained.

[0101] In a semiconductor device according to one embodiment of the present disclosure, the first substrate 10 is a substrate made of an elemental semiconductor, and the second substrate 20 is a substrate made of a compound semiconductor. In this way, since the first substrate 10 is a substrate made of an elemental semiconductor, high heat dissipation performance is achieved overall by heat dissipation via the first substrate 10. Furthermore, since the second substrate 20 is a substrate made of a compound semiconductor, its electrical insulation is improved, and a circuit with excellent high-frequency characteristics can be provided.

[0102] In the semiconductor device according to one aspect of the present disclosure, the second base material 20 is thinner than the first base material 10. This allows the first base material 10 to achieve a high heat dissipation effect.

[0103] In a semiconductor device according to one aspect of the present disclosure, the circuit element 21 is a heat-generating element that generates heat during operation, and the conductive pillar bump PB is provided in close proximity to the heat-generating circuit element 21. With this configuration, the conductive pillar bump PB forms a short heat conduction path, and heat generated in the circuit element 21 is effectively dissipated via the conductive pillar bump PB.

[0104] In a semiconductor device according to one aspect of the present disclosure, the second base material 20 does not protrude from the outer edge of the first base material 10. This configuration reduces the thermal resistance of the substrate including the first base material 10 and the second base material 20, and provides a high heat dissipation effect from the first base material 10.

[0105] A semiconductor device according to one embodiment of the present disclosure includes a bonding layer 11 between a first substrate 10 and a second substrate 20, the bonding layer 11 bonding the first substrate 10 and the second substrate 20 together, the bonding layer 11 being made of a metal having a higher thermal conductivity than the second substrate 20. This configuration ensures thermal conductivity from the second substrate 20 to the first substrate 10, and maintains heat dissipation (heat exhaust) from the first substrate 10. In addition, heat dissipation from the first substrate 10 via the bonding layer 11 is ensured. In other words, heat dissipation from the first substrate 10 is not hindered by the bonding layer 11.

[0106] In a semiconductor device according to one embodiment of the present disclosure, the bonding layer 11 is made of metal and has a lower elastic modulus than the second substrate 20. This configuration alleviates thermal stress caused by the difference in the linear expansion coefficient between the first substrate 10 and the second substrate 20.

[0107] In a semiconductor device according to one embodiment of the present disclosure, the bonding layer 11 is made of metal, and an alloyed layer between the bonding layer 11 and the first substrate 10 is formed between the bonding layer 11 and the first substrate 10. This configuration provides high adhesion and high thermal conductivity between the first substrate 10 and the second substrate 20.

[0108] A semiconductor device according to one embodiment of the present disclosure includes a bonding layer 11 between a first substrate 10 and a second substrate 20, and the bonding layer 11 is a dielectric material having a lower dielectric constant than the second substrate 20. This configuration suppresses high-frequency loss due to the first substrate 10, allowing a circuit with excellent high-frequency characteristics to be provided.

[0109] In a semiconductor device according to one embodiment of the present disclosure, the bonding layer 11 is a dielectric and has a lower elastic modulus than the second substrate 20. This configuration alleviates thermal stress caused by the difference in the linear expansion coefficient between the first substrate 10 and the second substrate 20.

[0110] A semiconductor device according to one embodiment of the present disclosure includes a bonding layer 11 between a first substrate 10 and a second substrate 20, and this bonding layer 11 is an insulator having a higher electrical resistivity than the first substrate 10. This increases the electrical insulation between the first substrate 10 and the second substrate 20, suppresses high-frequency loss due to the first substrate 10, and enables the provision of a circuit with excellent high-frequency characteristics.

[0111] In the semiconductor device according to one aspect of the present disclosure, the bonding layer 11 has a higher thermal conductivity than the first base material 10. This reduces the effective thermal resistance of the portion formed by the bonding layer 11 and the first base material 10, thereby achieving high heat dissipation.

[0112] A semiconductor device according to one embodiment of the present disclosure includes a bonding layer 19 between a first substrate 10 and a second substrate 20, and the bonding layer 19 is a layer of a composite material including an insulator layer 17 and a metal layer 18. This allows for the relaxation of stress between the first substrate 10 and the second substrate 20, which occurs due to the difference in linear expansion coefficient between the first substrate 10 and the second substrate 20. Furthermore, although the expansion and contraction of the second substrate 20 is more severe than that of the first substrate 10 due to the heating and cooling of the circuit elements 21 formed on the second substrate 20, the resulting stress at the interface between the second substrate 20 and the first substrate 10 is relaxed.

[0113] In a semiconductor device according to one embodiment of the present disclosure, the first base material 10 is a Si base material, and the insulator layer 17 in the bonding layer 19 is a layer of a Si compound. This makes it easier to form the insulator layer 17 on the first base material 10, and also increases the bonding strength between the first base material 10 and the insulator layer 17.

[0114] In a semiconductor device according to one embodiment of the present disclosure, at least a portion of the insulator layer 17 is made of resin, which allows the insulator layer 17 to relieve stress generated between the metal layer 18 and the insulator layer 17 in the bonding layer 19.

[0115] In a semiconductor device according to one embodiment of the present disclosure, a first-substrate-side electrode 12 is formed on the surface of the first substrate 10 at a position that does not overlap the second substrate 20, and a conductive pillar bump PB is connected to the first-substrate-side electrode 12. This configuration provides a heat dissipation effect from the conductive pillar bump PB connected to the first-substrate-side electrode 12. Furthermore, the conductive pillar bump PB improves the efficiency of heat conduction to the circuit board on which the semiconductor device is mounted, thereby improving heat dissipation on the circuit board.

[0116] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes a substrate 1 having a circuit element 21 and an electrode connected to the circuit element 21 on its surface, and a conductive pillar bump PB for external connection provided on the substrate 1 and electrically connected to the electrode or the circuit element 21, the substrate 1 including a first base material 10 and a second base material 20 disposed on the first base material 10, the circuit element 21 and the electrode being formed on the second base material 20, the method comprising the steps of: forming a semiconductor thin film having the circuit element 21 and the electrode on its surface on a compound semiconductor mother substrate 200 via a release layer 29; removing the release layer 29 by etching to release the semiconductor thin film from the compound semiconductor mother substrate 200; bonding the semiconductor thin film constituting the second base material 20 to a predetermined position on the first base material 10, which is a single semiconductor substrate constituting the first base material 10; and forming a conductive pillar bump PB for external connection provided on the second base material 20 and connected to the electrode or the circuit element 21.

[0117] According to the above manufacturing method, a semiconductor device that is small in size yet has high output, or a semiconductor device that is high in output yet has a small size, can be obtained.

[0118] Finally, the above-described embodiments are illustrative in all respects and are not restrictive. Variations and modifications are possible for those skilled in the art. The scope of the present invention is defined not by the above-described embodiments but by the claims. Furthermore, the scope of the present invention includes modifications from the embodiments within the scope of the claims and their equivalents. [Explanation of symbols]

[0119] PB: Conductive pillar bump 1...Substrate 10...First base material 11...Joining layer 12...First base material side electrode 15...Flattened resin layer 16...Insulator layer 20…Second base material 20D...epitaxial layer 20N...Semiconductor substrate 21...Circuit element 22…Second base material side electrode 13,23...Conductor pillars 14,24...Solder layer 29...Peeling layer 30...GaAs substrate 32,42...electrode 33, 43...Conductor pillars 34, 44...Solder layers 51A, 51B...Heterojunction bipolar transistor 52...Spiral inductor 53…MIMC 85...Resist film 90...Mounting board 91, 92...Electrodes on mounting board 110, 111, 120, 130A, 130B, 131, 140, 160, 170...Semiconductor device 200...Motherboard

Claims

1. a substrate on which a plurality of circuit elements are arranged; a first conductor protrusion for external connection provided on the substrate and connected to the plurality of circuit elements; Equipped with the substrate includes a first substrate and a second substrate disposed on the first substrate and made of a different material from the first substrate; the plurality of circuit elements are disposed on the second substrate; the first substrate has a higher thermal conductivity than the second substrate; the plurality of circuit elements are covered by one of the first conductor protrusions; Semiconductor device.

2. The second substrate is bonded to the first substrate via a bonding layer. The semiconductor device according to claim 1 .

3. The bonding layer is formed using only metal. The semiconductor device according to claim 2 .

4. The bonding layer is formed using only an insulator. The semiconductor device according to claim 2 .

5. The bonding layer is formed using a metal and an insulator. The semiconductor device according to claim 2 .

6. the plurality of circuit elements are disposed on a surface of the second substrate; 6. The semiconductor device according to claim 1.

7. the plurality of circuit elements are disposed embedded in the second substrate; 6. The semiconductor device according to claim 1.

8. a first heat conduction path that dissipates heat generated by the plurality of circuit elements via the conductor protrusion; a second heat conduction path that dissipates heat generated by the plurality of circuit elements via the substrate; a third heat conduction path that dissipates heat generated by the plurality of circuit elements via a second conductor protrusion that is disposed at a position on the substrate different from that of the plurality of circuit elements; Equipped with 6. The semiconductor device according to claim 1.

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