Signal processing apparatus and method

Abstract

To suppress or reduce an increase in scale and power consumption of an entire circuit.SOLUTION: A signal processing apparatus includes: an operation processing unit to perform operation processing on D-bits data (D is a positive integer greater than or equal to three) represented in a two's complement representation as a representation format: and a storage processing unit to perform storage processing on D-bits data represented in a second representation format. The second representation format for a positive or 0 value of the D-bits data is identical to the two's complement representation and the second representation format for a negative value of the D-bits data has a representation format in which (D-N-1) bits of the D-bits data in the two's complement representation are bit-wise inverted (N is a positive integer smaller than or equal to D-2), the (D-N-1) bits being remaining bits obtained by excluding a most significant bit indicating a sign and N consecutive lower bits including a least significant bit.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a signal processing device and method. [Background technology]

[0002] Fast Fourier Transform (FFT) processing is one of the important processes in digital signal processing. Frequency domain equalization (FDE) is also known as a technique for compensating for waveform distortion during signal transmission in wireless and wired communications.

[0003] In frequency domain equalization, first, signal data in the time domain is converted to data in the frequency domain using a fast Fourier transform. Next, filtering is performed for equalization. The filtered data is then reconverted to signal data in the time domain using an inverse fast Fourier transform (hereinafter abbreviated as "IFFT"). This compensates for waveform distortion in the original time domain signal. Hereafter, when there is no need to distinguish between FFT and IFFT, the term "FFT / IFFT" will be used.

[0004] Generally, "butterfly operations" are used in FFT / IFFT processing. For example, Reference 1 describes an FFT device using butterfly operations. Reference 1 also describes "twiddle multiplication," which will be described later, i.e., multiplication using a twiddle coefficient or twiddle factor.

[0005] Furthermore, for example, Reference 2 describes the Cooley-Tukey butterfly operation as an efficient FFT / IFFT processing method. However, Cooley-Tukey FFT / IFFT with a large number of points requires a complex circuit. Therefore, the FFT / IFFT processing is decomposed into two smaller FFTs / IFFTs based on the Prime Factor method described in Reference 3, for example.

[0006] 18 shows a data flow 500 of a 64-point FFT decomposed into two stages of radix-8 butterfly processing using the Prime Factor method. The data flow 500 includes a data rearrangement unit 501, butterfly operation units 502 and 503, which perform a total of 16 radix-8 butterfly operation processes, and a twiddle multiplication unit 504 that multiplies by a twiddle coefficient {Wk} (W=exp(-2πj / N), j2=-1) (in FIG. 18, the twiddle coefficients are (W0, W1, ..., W7), ..., (W0, W7, ..., W49)).

[0007] In the data flow 500 shown in Fig. 18, input time domain data x(n) (n = 0, 1,..., 63) is Fourier transformed into a frequency domain signal X(k) (k = 0, 1,..., 63) by FFT processing. Note that part of the data flow is not shown in Fig. 18. The basic configuration of the data flow 500 shown in Fig. 18 is the same even when IFFT processing is performed.

[0008] When the number of FFT points is large, implementing all of the data flow 500 shown in Fig. 18 using a circuit would result in an enormous scale. Therefore, when the number of FFT points is large, a method is generally adopted in which the entire FFT processing is implemented by repeatedly using circuits that implement processing of a portion of the data flow, depending on the required processing performance.

[0009] For example, in the data flow of Figure 18, if an FFT device that performs FFT processing on eight pieces of data in parallel (hereinafter simply referred to as "8 data in parallel") is created as a physical circuit, 64-point FFT processing can be achieved by repeating the process a total of eight times.

[0010] The eight repeated processes are performed in order by performing the processes corresponding to the partial data flows 505a to 505h on the eight data items, and are specifically performed as follows: In the first iteration, the process corresponding to the partial data flow 505a is The second time, the process corresponding to the partial data flow 505b is In the third time, the process corresponding to the partial data flow 505c (not shown) is The same process is carried out for each of the subsequent partial data flows up to the eighth partial data flow 505h. The above process achieves 64-point FFT processing.

[0011] In butterfly computation, data arranged in sequential order is read out and processed in an order that follows a predetermined rule. Therefore, data rearrangement is required for butterfly computation. For this purpose, a RAM (Random Access Memory) circuit is mainly used. For example, Reference 4 discloses an FFT device that rearranges data using a RAM circuit for butterfly computation.

[0012] As a low power consumption technology, for example, Patent Document 1 discloses a configuration including an arithmetic processing unit that performs arithmetic processing such as butterfly operations on data expressed in two's complement representation, and a storage processing unit such as a RAM (Random Access Memory) circuit that performs storage processing on data expressed in a second representation format, "sign absolute value representation," in which the "sign absolute value representation" is the same as the two's complement representation when the data value is positive or 0, and when the data value is negative, is a representation format in which all bits lower than the most significant bit indicating the sign of the two's complement representation are inverted. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] WO 2019 / 131754 (page 7, Figure 1) Summary of the Invention [Problem to be solved by the invention]

[0014] Two's complement representation is widely used as a binary representation method for signal data in digital signal processing. Two's complement representation has the advantage that it can represent subtraction processing as addition processing, allowing addition / subtraction processing circuits to be implemented on a small circuit scale.

[0015] On the other hand, in two's complement representation, there is a large difference in bit-wise values between small positive values and small negative values near 0. For this reason, when a signal whose value frequently changes between positive and negative near 0 is represented in two's complement, it has the characteristic of having a high bit-wise operation rate (toggle rate). The dynamic power consumption P of a digital signal processing circuit realized using a CMOS (Complementary Metal Oxide Semiconductor) circuit can be expressed by the following equation (1). P=(1 / 2)*a*C*V2*f … (1) where: a:Circuit activity (percentage-activity), C: Load capacity, V: voltage, f: operating frequency The percentage activity of a circuit is given by the ratio of an estimate of the number of switching times in a certain time period to the number of clock cycles in that period.

[0016] Since the bit-wise operation rate (toggle rate) of signal data determines the circuit operation rate a, reducing the bit-wise operation rate is effective in reducing power consumption. Meanwhile, signal data in communication signal processing often changes between positive and negative values frequently near the value 0. Furthermore, in fast Fourier transform (FFT) processing, which is one of the important processes in digital signal processing, the internal data often takes small values near the value 0.

[0017] In these processes, the use of two's complement representation increases the bit-by-bit activity rate, resulting in increased power consumption. In two's complement representation, of the 2^n (^ is the exponentiation operator) values that can be expressed as an n-digit binary number, "000...0" to "011...1" are assigned to the value 0 and positive values, and the remaining half, "100...0" to "111...1," are assigned to negative values. Figure 19 shows an example of two's complement representation, showing the binary representation of signal values from +15 to -16 for 5-bit signal data. In two's complement representation, the bit values of the most significant bits differ significantly between positive and negative values, with the value 0 as the boundary. Therefore, when a signal that frequently changes between positive and negative values near the value 0 is represented, the bit-by-bit activity rate increases. In two's complement representation, for example, when a value changes from +1 ("00001") to -1 ("11111"), all of the four most significant bits except the least significant bit (LSB) undergo a transition. To address this issue, sign-magnitude representation is a digital data representation method with a small bit-by-bit activity rate near the value 0. In sign-magnitude representation, the most significant bit (MSB) represents the sign, and the remaining bits represent the absolute value of the value. Figure 19 shows an example of sign-magnitude representation, corresponding to two's complement representation, showing the binary representation of signal values from +15 to -16 for 5-bit signal data. The maximum value that can be represented in an n-digit binary signed absolute value representation is 2^(n-1)-1, and the minimum value is -2^(n-1)+1. There are two ways to represent an integer with a value of 0: "00000" and "10000." Note that for positive integers, sign-magnitude representation is the same as two's complement representation. In sign-magnitude representation, the difference in bit values between positive and negative values is small, with the value 0 as the boundary. Therefore, even when a signal that frequently changes between positive and negative values near the value 0 is represented, this representation has the characteristic of a small bit-by-bit activity rate. For example, when the signal value changes from +1 ("00001") to -1 ("10001"), only the most significant bit transitions.

[0018] However, in sign-magnitude representation, subtraction cannot be expressed as an addition, so separate circuits for addition and subtraction are required. As a result, the size of the circuit that implements addition and subtraction increases. Since the circuit size determines the load capacitance C in the dynamic power consumption P shown in equation (1), an increase in circuit size increases power consumption.

[0019] That is, while the sign-magnitude representation can reduce the circuit operation rate a compared to the two's complement representation, it increases the load capacitance C of the adder-subtractor circuit. This results in a problem of increased power consumption, especially in signal processing that involves a lot of addition and subtraction operations.

[0020] It is also possible to use two's complement representation for addition and subtraction operations, which allows for efficient circuit implementation, and sign-magnitude representation for operations other than addition and subtraction, which can reduce the operating rate. However, converting between two's complement representation and sign-magnitude representation requires bit inversion and adding one (increment). Therefore, for circuits that require many conversion processes, there is the problem that the power consumption increases due to the conversion circuitry.

[0021] 20 shows an example of the configuration of a conversion circuit 600 between two's complement representation and sign-magnitude representation. The conversion circuit 600 is configured by connecting a bit inversion circuit 601 and a 1-increment circuit 602. The bit inversion circuit 601 inputs the sign bit IN[N-1] of the MSB (Most Significant Bit) directly to the N-1 bit of the 1-increment circuit 602, and outputs XOR circuits 6071 to 6072 to which the sign bit IN[N-1] and each bit IN[i] (i=0, ..., N-2) are input. N-1 The output of the XOR circuit 6071 is input to the i-bit (i=0, ..., N-2) of the 1-adder circuit 602. The 1-adder circuit 602 adds 1 to the output of the XOR circuit 6071 and outputs the result as the output bit OUT[i] (i=0, ..., N-2). In the conversion circuit 600, the circuit size of the 1-adder circuit 602 in particular is not negligible compared to the other logic processing circuits and arithmetic processing circuits. For this reason, when many conversion processes are required, there is a problem that the circuit size and power consumption of the entire circuit increase by the amount of the conversion circuits.

[0022] Therefore, the present disclosure has been devised in consideration of the above-mentioned problems, and aims to provide a signal processing device and method that can suppress or reduce increases in the circuit size and power consumption of the entire circuit. [Means for solving the problem]

[0023] A signal processing device according to one aspect of the present disclosure includes an arithmetic processing unit that performs arithmetic processing on D-bit data (D is a positive integer satisfying D≧3) expressed in two's complement representation as a data representation format, and a storage processing unit that performs storage processing on D-bit data expressed in a second representation format as a data representation format. The second representation format is the same as the two's complement representation when the data value is positive or 0, and when the data value is negative, it is a representation format in which (DN−1) bits excluding the most significant bit indicating the sign and N bits (where N is a positive integer satisfying N≦D−2) arranged from the least significant bit to the most significant bit in the two's complement representation are inverted.

[0024] A signal processing method according to one aspect of the present disclosure includes performing an arithmetic operation on D-bit data (D is a positive integer greater than or equal to 3) expressed in two's complement notation as a data representation format, A storage process is performed on D-bit data expressed in a second representation format as a data representation format, and the second representation format is the same as the two's complement representation when the data value is positive or 0, and when the data value is negative, it is a representation format in which the most significant bit indicating the sign and (DN-1) bits excluding the least significant bit and N bits arranged higher from the least significant bit (where N is a positive integer such that N≦D-2) are inverted in the two's complement representation. [Effects of the Invention]

[0025] According to the present disclosure, it is possible to realize a signal processing device that can suppress or reduce increases in the circuit size and power consumption of the entire circuit. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1 is a diagram schematically illustrating an example of a configuration of a signal processing device according to some embodiments of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating an example of a configuration of a storage processing unit according to some embodiments of the present disclosure. [Figure 3] FIG. 1 illustrates, in tabular form, an example of a data representation format according to some embodiments of the present disclosure. [Figure 4] FIG. 1 is a diagram illustrating an example of a configuration of a conversion circuit according to some embodiments of the present disclosure. [Figure 5] FIG. 10 is a graph illustrating the effects of some embodiments of the present disclosure. [Figure 6] FIG. 1 is a diagram schematically illustrating an example of a configuration of a signal processing device according to some embodiments of the present disclosure. [Figure 7] FIG. 2 is a diagram illustrating an example of a configuration of a processing unit according to some embodiments of the present disclosure. [Figure 8] FIG. 10 is a diagram illustrating an example of a configuration of a lower-order bit mask circuit according to some embodiments of the present disclosure. [Figure 9] FIG. 1 is a diagram illustrating an example of a configuration of an FFT device according to some embodiments of the present disclosure. [Figure 10] FIG. 2 is a diagram illustrating a data set following a sequential order in an FFT process according to some embodiments of the present disclosure. [Figure 11] FIG. 2 is a diagram illustrating a data set in bit-reverse order in an FFT process according to some embodiments of the present disclosure. [Figure 12] FIG. 2 is a diagram schematically illustrating an example of the configuration of a butterfly calculation processing unit according to some embodiments of the present disclosure. [Figure 13] FIG. 10 is a diagram schematically illustrating an example of a configuration of a twiddle multiplication processing unit according to some embodiments of the present disclosure. [Figure 14] FIG. 10 is a diagram schematically illustrating an example of the configuration of a data rearrangement processing unit according to some embodiments of the present disclosure. [Figure 15] 10 is a time chart illustrating the operation of a data rearrangement unit according to some embodiments of the present disclosure. [Figure 16] 2A and 2B are diagrams illustrating states of RAM circuits 210a to 210h according to some embodiments of the present disclosure. [Figure 17] 2A and 2B are diagrams illustrating states of RAM circuits 210a to 210h according to some embodiments of the present disclosure. [Figure 18] FIG. 10 is a diagram illustrating an example of a data flow of 64-point FFT processing. [Figure 19] FIG. 10 is a diagram showing an example of a data representation format in a table format. [Figure 20] FIG. 2 is a block diagram showing an example of the configuration of a conversion circuit. [Figure 21] FIG. 2 is a block diagram showing an example of the configuration of a conversion circuit. DETAILED DESCRIPTION OF THE INVENTION

[0027] Several embodiments of the present disclosure will be described. First, as a premise of the present disclosure, the "sign magnitude--representation" proposed in Patent Document 1 will be described as a data representation format for reducing the circuit size and power consumption of the conversion circuit shown in FIG. 20. In addition to the two's complement representation and the sign magnitude representation, FIG. 19 shows a binary representation of signal values of +15 to -16 for 5-bit signal data as an example of the "sign magnitude--representation." The "sign magnitude--representation" is the same as the two's complement representation when the data value is positive or 0, and is a representation in which bits other than the most significant bit indicating the sign are inverted from the two's complement representation when the data value is negative. In the above, the "sign magnitude--representation" is a term used in Patent Document 1 and is not a general technical term, so it is written in parentheses. However, hereinafter, the parentheses will be removed.

[0028] 21 shows an example of the configuration of a conversion circuit 610 between two's complement representation and sign-magnitude representation. The sign bit IN[N-1] of the MSB (Most Significant Bit) is output as is as the output bit OUT[N-1], and XOR circuits 6071 to 6077 receive the sign bit IN[N-1] and each bit IN[i] (i=0, ..., N-2) as input. N-1Let the output be output bits OUT[i] (i = 0, …, N−2). The conversion between two's complement representation and sign-magnitude representation can be realized only by bit inversion processing by a bit inversion circuit 601. Since the addition-by-1 processing by an addition-by-1 circuit 602 (Fig. 20) required for the conversion between two's complement representation and sign-magnitude representation is not necessary, the circuit scale and power consumption of the conversion circuit can be reduced.

[0029] However, even when sign-magnitude representation is applied, there is a problem that when the number of conversion circuits is large, the circuit scale and power consumption of the entire circuit still increase.

[0030] Also, there is a problem that it is difficult to use sign-magnitude representation in combination with lower-bit mask technology, which is one of the low-power technologies.

[0031] Lower-bit mask technology suppresses bit transitions by fixing the values of some of the lower bits in signal data. Although the arithmetic accuracy decreases, power consumption can be expected to decrease by the amount of reduced bit transitions.

[0032] However, when conversion processing according to sign-magnitude representation is performed by a conversion circuit 610 in Fig. 21 after lower-bit mask processing, the values of the fixed lower bits will undergo bit transitions again. For example, when the values of lower m bits IN[0]~IN[m−1] (m < N−2) are fixed to 0, when the sign bit IN[N−1] is 1, the outputs of m XOR circuits 6071~607 m will be 1. For this reason, the suppression of bit transitions by lower-bit mask processing becomes invalid, and there is a problem that the power increases accordingly.

[0033] FIG. 1 is a diagram illustrating an example of the configuration of a signal processing device 10 according to some exemplary embodiments of the present disclosure. The signal processing device 10 includes storage processing units 11a, 11b, and 11c that perform storage processing such as buffering, retiming, and rearrangement of signal data, and arithmetic processing units 12a and 12b that perform arithmetic processing such as addition, subtraction, multiplication, and division. Note that arrows in FIG. 1 illustrate an example of data flow in processing (it should not be interpreted as meaning that signals between units are always unidirectional). Furthermore, hereinafter, the storage processing units 11a, 11b, 11c, etc. will be referred to as the storage processing unit 11, with the symbols a, b, c, etc. omitted, unless it is necessary to specifically describe each unit. The same applies to other elements.

[0034] The storage processing unit 11a receives signal data expressed in two's complement notation from outside the signal processing device 10 (not shown), performs storage processing on the received signal data, and outputs the result to the arithmetic processing unit 12a.

[0035] The arithmetic processing unit 12a receives signal data expressed in two's complement notation from the storage processing unit 11a, performs arithmetic processing on the data, and outputs the result to the storage processing unit 11b.

[0036] The storage processing unit 11b receives signal data expressed in two's complement notation from the arithmetic processing unit 12a, performs storage processing on the data, and outputs the data to the arithmetic processing unit 12b.

[0037] The arithmetic processing unit 12b receives the signal data expressed in two's complement notation from the storage processing unit 11b, performs arithmetic processing on the data, and outputs the result to the storage processing unit 11c.

[0038] The storage processing unit 11c receives signal data expressed in two's complement notation from the arithmetic processing unit 12b, performs storage processing, and outputs the data to the outside of the signal processing device .

[0039] The storage processing units 11a, 11b, and 11c can be realized by the storage processing unit 11 shown in FIG. 2, for example.

[0040] Referring to FIG. 2, the storage processing unit 11 includes a first conversion circuit 13a, a storage circuit 14, and a second conversion circuit 13b.

[0041] The first conversion circuit 13a converts input signal data expressed in two's complement representation into signal data expressed in a "partial sign absolute value representation" and outputs the converted signal data. The "partial sign absolute value representation" is a term newly coined by the inventor (used only in this specification and is not a general technical term). The "partial sign absolute value representation" corresponds to the "second representation form" in the claims of this patent application. The "partial sign absolute value representation" is identical to the two's complement representation when a data value consisting of D bits (D is a positive integer such that D≧3) is positive or 0. When the data value is negative, the "partial sign absolute value representation" is a representation in which the bits excluding the most significant bit and the least significant bit (N is a positive integer such that N≦D−2) from the two's complement representation are inverted. Hereinafter, the "partial sign absolute value representation" will be referred to without parentheses.

[0042] Figure 3 shows the partial sign magnitude-- representation for N=2 in D=6-bit signal data, and for comparison, the binary representations of signal values from +15 to -16 using the two's complement representation, the sign magnitude-- representation, and the sign magnitude-- representation. In Figure 3, when the data value is positive, the partial sign magnitude-- representation, the two's complement representation, the sign magnitude-- representation, and the sign magnitude-- representation are all the same binary representation (bit representation).

[0043] If the data value is 0, the partial sign-magnitude representation and the two's complement representation are identical bit representations.

[0044] If the data value is negative, the partial sign magnitude-- representation is a representation in which the three bits other than the most significant bit and the two least significant bits indicating the sign are inverted from the two's complement representation. Similarly, if the data value is negative, the two's complement representation is a representation in which the three bits other than the most significant bit and the two least significant bits indicating the sign are inverted from the partial sign magnitude-- representation. Therefore, if the data value is negative, the partial sign magnitude-- representation differs from the sign magnitude-- representation in the two bits from the least significant bit.

[0045] As shown in Figure 3, the partial sign-magnitude-- representation, like the sign-magnitude-- representation and the sign-magnitude--- representation, has a small difference in bit values between positive and negative values with the value 0 as the boundary. Therefore, even when expressing a signal that frequently changes between positive and negative values near the value 0, it has the characteristic of having a small bit-wise operation rate.

[0046] For example, if the signal value changes from +1 to -1, the partial code absolute value -- representation changes from +1 ("000001") to -1 ("100011"), so a total of two bits transition: the most significant bit and the second bit from the least significant bit.

[0047] On the other hand, in two's complement representation, the change is from +1 ("000001") to -1 ("111111"), so a total of five bits other than the least significant bit transition. In sign-magnitude representation, the change is from +1 ("000001") to -1 ("100000"), so a total of two bits, the most significant bit and the least significant bit, transition.

[0048] Referring again to FIG. 2, the memory circuit 14 is a circuit that receives the signal data expressed in the partial code absolute value representation output by the first conversion circuit 13a, stores the signal data in the partial code absolute value representation, and outputs the signal data in the partial code absolute value representation to the second conversion circuit 13b.

[0049] The second conversion circuit 13b is a circuit that converts the signal data expressed in the partial sign absolute value representation output by the storage circuit 14 into signal data expressed in two's complement representation and outputs the converted signal data. The first and second conversion circuits 13a and 13b have the same configuration and can be realized by, for example, the conversion circuit 13 shown in FIG.

[0050] 4, conversion circuit 13 is a circuit that receives D-bit signal data (IN[0] to IN[D-1]) in two's complement representation in parallel (D is a positive integer greater than or equal to 3), converts the data from the two's complement representation to a partial code absolute value representation, and outputs D-bits (OUT[0] to OUT[D-1]) in parallel. Conversion circuit 13 also receives D-bit signal data (IN[0] to IN[D-1]) in partial code absolute value representation in parallel, converts the data from the partial code absolute value representation to a two's complement representation, and outputs D-bits (OUT[0] to OUT[D-1]) in parallel.

[0051] The conversion circuit 13 outputs the most significant bit indicating the code input from the input IN[D-1] as it is to OUT[D-1] as the code bit.

[0052] The conversion circuit 13 outputs the N bits arranged from the least significant bit to the most significant side, which are input in parallel from the inputs IN[0] to IN[N-1], in parallel to the outputs OUT[0] to OUT[N-1] as they are.

[0053] The conversion circuit 13 receives (DN-1) bits in parallel from the inputs IN[N] to IN[D-2] and converts them into exclusive OR (XOR) circuits 171 to 177. D-1-N The result of the exclusive OR operation with the most significant bit indicating the code input from input IN[D-1] is output in parallel to outputs OUT[N] to OUT[D-2].

[0054] If the input data value is positive or 0, the most significant bit indicating the sign input from input IN[D-1] is 0, and the data values input to inputs IN[0] to IN[D-2] are output as is to outputs OUT[0] to OUT[D-2], respectively.

[0055] On the other hand, if the input data value is negative, the most significant bit indicating the sign input from input IN[D-1] is a value of 1, and the data values input to inputs IN[0] to IN[N-1] are output unchanged to outputs OUT[0] to OUT[N-1]. Also, the results of exclusive ORing the data values input to inputs IN[N] to IN[D-2] with the most significant bit of 1, i.e., the inverted values of inputs IN[N] to IN[D-2], are output to outputs OUT[N] to OUT[D-2].

[0056] By the above-described processing, the conversion circuit 13 realizes conversion processing from the two's complement representation to the partial sign magnitude representation, or from the partial sign magnitude representation to the two's complement representation.

[0057] As described above, in the conversion circuit 13, conversion between two's complement representation and partial sign-magnitude-value representation can be achieved only by bit inversion processing, and does not require the increment-by-1 processing required for conversion between two's complement representation and sign-magnitude-value representation. Because the bit inversion processing can be achieved using only an exclusive OR (XOR circuit), it can be achieved with a circuit scale that is significantly smaller than other logic processing circuits or arithmetic processing circuits. Furthermore, fewer XOR circuits are required than in the conversion circuit (610 in FIG. 21) that converts between two's complement representation and sign-magnitude-value representation, and the circuit scale of the conversion circuit 13 can be reduced accordingly.

[0058] As described above, in this embodiment, the signal processing device 10 converts data expressed in two's complement representation into partial sign-magnitude-value representation in the storage processing units 11a, 11b, and 11c, performs storage processing, and then converts it back into two's complement representation. As shown in FIG. 3, the partial sign-magnitude-value representation, like the sign-magnitude-value representation, has a small difference in bit value between positive and negative values with the value 0 as the boundary. Therefore, even when expressing a signal that frequently changes between positive and negative values near the value 0, it has the characteristic of having a small bit-wise operation rate. As a result, the operation rate of the circuits in the storage processing units 11a, 11b, and 11c can be reduced compared to processing the data in two's complement representation as is.

[0059] Furthermore, the conversion process between two's complement representation and partial sign-magnitude-value representation by the conversion circuit 13 can be realized only by bit inversion processing, and does not require the 1 addition processing (increment processing) required for the sign-magnitude-value representation. The bit inversion processing can be realized only by an XOR circuit. Therefore, it can be realized with a circuit scale that is overwhelmingly smaller than other logic processing circuits or arithmetic processing circuits. Furthermore, since fewer XOR circuits are required compared to conversion between two's complement representation and sign-magnitude-value representation, the circuit scale of the conversion circuit 13 can be reduced accordingly.

[0060] Fig. 5 is a graph showing the effect of applying the partial sign absolute value representation to two example circuits, Circuit A and Circuit B, whose signal data bit width is 8 bits (D=8), in the storage processing section of an FFT processing circuit. In Fig. 5, the number of inverted bits (DN-1) on the horizontal axis is the number of bits (DN-1 in Fig. 3) that are inverted in the conversion process between the two's complement representation and the partial sign absolute value representation.

[0061] If the number of inverted bits (DN-1) is 0 (N=D-1), no bits are inverted and it is equivalent to two's complement representation.

[0062] If the number of bits to be inverted (DN-1) is 7 bits (=D-1), N=0, and all bits except the sign bit are inverted, which is equivalent to the sign-magnitude-- representation.

[0063] When the number of inverted bits (DN-1 in FIG. 3) is 1 to 6 bits, it corresponds to the partial code magnitude -- representation.

[0064] In Figure 5, the left vertical axis represents the reduction rate of the bitwise operation rate, and shows a relative value based on the operation rate in two's complement representation. The right vertical axis represents the circuit size of the conversion circuit, and shows a relative value based on the circuit size of the conversion circuit in sign-magnitude representation.

[0065] 5, when the number of bits to be inverted is 4 in the partial sign-magnitude-value-- representation, it can be seen that the bitwise operation rate of Circuit A and Circuit B is reduced to about 20 to 30% of the case where the two's complement representation is applied, which is equivalent to the case where the sign-magnitude-value-- representation is applied. On the other hand, it can be seen that the circuit scale is reduced to about 40% of the case where the sign-magnitude-value-- representation is applied. In other words, according to this embodiment, the bitwise operation rate can be reduced to the same level as the sign-magnitude-value-- representation with a conversion circuit smaller than that of the sign-magnitude-value-- representation.

[0066] Therefore, in this embodiment, the operation rate of the circuits in the memory processing units 11a, 11b, and 11c can be reduced even when processing a signal that frequently changes between positive and negative values near the value 0. This makes it possible to reduce the power consumption in the memory processing units 11a, 11b, and 11c.

[0067] On the other hand, in this embodiment, the arithmetic processing is performed in the arithmetic processing units 12a and 12b using the two's complement representation. Therefore, the operation rate of the circuits involved in the arithmetic processing is not reduced. However, unlike the case where the sign-magnitude representation is applied, the conversion between data representation formats does not increase the circuit size. Therefore, according to this embodiment, the power consumption of the entire signal processing device can be reduced by the amount that the power consumption of the storage processing units 11a, 11b, and 11c is reduced.

[0068] In this embodiment, the configuration has been exemplified in which the storage processing such as buffering processing, retiming processing, and rearrangement processing of signal data is performed by processing data in the partial code absolute value representation in the storage processing units 11a, 11b, and 11c, and arithmetic processing such as addition, subtraction, multiplication, and division of data is performed by the arithmetic processing units 12a and 12b in two's complement representation, but if a desired result can be obtained by processing data in the partial code absolute value representation, the storage processing units 11a, 11b, and 11c may perform arithmetic processing such as addition, subtraction, multiplication, and division of data based on the partial code absolute value representation, in addition to the storage processing.

[0069] Another example of some embodiments of the present disclosure will be described. Fig. 6 is a diagram showing an example of the configuration of a signal processing device 20 according to some embodiments of the present disclosure. This example of the signal processing device 20 includes storage processing units 11a, 11b, and 11c that perform storage processing such as buffering, retiming, and rearrangement of signal data, and arithmetic processing units 22a and 22b that perform arithmetic processing such as addition, subtraction, multiplication, and division. The storage processing units 11a, 11b, and 11c have the same configuration as the storage processing units in the signal processing device 10 according to the above-described embodiment, and are denoted by the same reference numerals. Meanwhile, the arithmetic processing units 22a and 22b input a mask control signal 28, which is a control signal provided from a higher-level control circuit (not shown), such as a central processing unit (CPU), not shown.

[0070] Referring to FIG. 7, the arithmetic processing unit 22 constituting the arithmetic processing units 22a and 22b includes an arithmetic circuit 24 and a lower-order bit mask circuit 23. The arithmetic circuit 24 is an arithmetic circuit such as an adder circuit, subtractor circuit, multiplier circuit, or divider circuit. The lower-order bit mask circuit 23 fixes the values of some of the lower-order bits of the output signal data of the arithmetic circuit 24. Fixing the values of some of the lower-order bits suppresses bit-by-bit operations, thereby reducing power consumption. Although the arithmetic accuracy decreases by the amount that some of the lower-order bits of the data are fixed, fixing some of the bits reduces the bit-by-bit operation rate. Therefore, a corresponding reduction in power consumption can be expected.

[0071] The lower bit mask circuit 23 can be realized, for example, by the configuration shown in Fig. 8. Referring to Fig. 8, the lower bit mask circuit 23 receives D-bit (D is a positive integer satisfying D≧3) signal data (IN[0] to IN[D−1]) in two's complement representation in parallel, fixes all M bits (M is a positive integer satisfying M≧1) from the least significant bit to the most significant bit to 0 according to the value of the input mask control signal 28, and outputs D bits (OUT[0] to OUT[D−1]) in parallel.

[0072] Specifically, the DM bits (M is a positive integer greater than or equal to 1) input from inputs IN[M] to IN[D-1] are output as is to outputs OUT[M] to OUT[D-1], respectively. The least significant bit to the most significant M bits input from inputs IN[0] to IN[M-1] are ANDed with the mask control signal 28 input by AND circuits 27-1 to 27-M, respectively, and then output to outputs OUT[0] to OUT[M-1], respectively. In other words, when the mask control signal 28 has a value of 1, the signal data input from inputs IN[0] to IN[M-1] is output as is to outputs OUT[0] to OUT[M-1].

[0073] On the other hand, when the mask control signal 28 has a value of 0, the value 0 is output to the outputs OUT[0] to OUT[M-1] regardless of the value of the signal data input from the inputs IN[0] to IN[M-1]. Therefore, by fixing the M-bit values of the outputs OUT[0] to OUT[M-1] to 0, the calculation accuracy decreases, but power consumption can be expected to be reduced by the amount of bit transitions that become 0. In other words, it is possible to control whether to prioritize calculation accuracy or low power consumption depending on whether the value of the mask control signal 28 is 1 or 0.

[0074] In FIG. 6, storage processors 11a, 11b, and 11c have the same configuration as storage processor 11 shown in FIG. 2. Conversion circuit 13 constituting storage processor 11 has the same configuration as that shown in FIG. 4, but the range of the least significant bit to N bits that are not inverted is restricted. Specifically, in lower-bit mask circuit 23, M and N are set so that N≧M is always satisfied for the least significant bit to M most significant bits whose values are fixed, and for the least significant bit to N bits that are not inverted in conversion circuit 13. Specifically, for D-bit data, M and N are set so that 1≦M≦N≦D−2 is satisfied. That is, for the M most significant bits from the least significant bit whose value is fixed to 0 in lower-bit mask circuit 23, the conversion circuit 13 does not invert the bits. Therefore, even when partial code magnitude value -- representation is applied, the values of the least significant bit to M most significant bits remain fixed to 0. Therefore, the lower-bit mask circuit 23 does not nullify the effect of reducing the circuit's operation rate.

[0075] As described above, in the signal processing device 20 of this embodiment, similar to the previously described signal processing device 10, the partial sign absolute value -- representation can reduce the operation rate of the circuits in the storage processing units 11a, 11b, and 11c even when processing a signal that frequently changes between positive and negative values near the value 0. This makes it possible to reduce power consumption in the storage processing units 11a, 11b, and 11c.

[0076] In this embodiment, the arithmetic processing unit 12 uses the lower bit mask circuit 23 to fix the values of the lower bits, thereby suppressing bit-by-bit operations. Furthermore, unlike the sign absolute value -- representation, the partial sign absolute value -- representation in this embodiment does not invert the bits of the fixed bits, but keeps them fixed. Therefore, it is possible to enjoy both the power consumption reduction effect of the lower bit masking process and the power consumption reduction effect of the partial sign absolute value -- representation.

[0077] As a further example of some embodiments of the present disclosure, an example of application to an FFT device will be described. The FFT device includes a butterfly operation processing unit that performs butterfly operation processing, a twiddle multiplication processing unit that performs twiddle multiplication processing, and a data rearrangement processing unit that rearranges the order of multiple data, where the butterfly operation processing unit and the twiddle multiplication processing unit perform processing on D-bit data (D is a positive integer D≧3) expressed in two's complement representation, and the data rearrangement processing unit performs storage processing on D-bit data expressed in partial sign magnitude-- representation.

[0078] FIG. 9 is a diagram schematically illustrating an example of an FFT device 30 according to an embodiment of the present disclosure. The FFT device 30 processes a 64-point FFT decomposed into two stages of radix-8 butterfly processing using a pipeline circuit according to the data flow 500 shown in FIG. 18. The FFT device 30 inputs time-domain data x(n) (n=0, 1, . . . , N-1) and performs a Fourier transform on x(n) using FFT processing to generate and output a frequency-domain signal X(k) (k=0, 1, . . . , N-1). Here, N is a positive integer representing the FFT block size. Although not particularly limited, it is assumed that the FFT device 30 performs 64-point FFT processing with eight data in parallel (N=64). In this case, the FFT device 30 inputs time-domain data x(n) and performs a Fourier transform on the x(n) using FFT processing to generate and output a frequency-domain signal X(k). At this time, a total of 64 pieces of data are input as input data x(n), 8 pieces of data at a time, over a period of 8 cycles, in the order shown in Fig. 10. Note that the numbers 0 to 63 shown as the contents of the table (elements of 8 rows and 8 columns) in Fig. 10 represent the subscript n of x(n).

[0079] Specifically, in the first cycle, eight pieces of data x(0), x(1), . . . , x(7) that make up the data set P1 are input.

[0080] Then, in the second cycle, eight pieces of data x(8), x(9), ..., x(15) that make up data set P2 are input. Similarly, from the third to eighth cycles, data that make up data sets P3 to P8 are input.

[0081] Similarly, 64 pieces of data are output as output data X(k), eight pieces of data at a time over a period of eight cycles, in the order shown in Fig. 10. Note that the numbers 0 to 63 shown as the contents of the table in Fig. 10 represent the subscript k of X(k).

[0082] Specifically, in the first cycle, eight pieces of data x(0), x(1), . . . , x(7) that make up the data set P1 are output.

[0083] In the second cycle, eight pieces of data x(8), x(9), . . . , x(15) that make up data set P2 are output. Similarly, from the third to eighth cycles, data that make up data sets P3 to P8 are output.

[0084] As shown in FIG. 9, the FFT device 30 includes a first data rearrangement unit 200a, a first butterfly calculation unit 32a, a second data rearrangement unit 200b, a twiddle multiplication unit 33, a second butterfly calculation unit 32b, and a third data rearrangement unit 200c.

[0085] The FFT device 30 performs pipeline processing of the first data rearrangement process, the first butterfly operation process, the second data rearrangement process, the twiddle multiplication process, the second butterfly operation process, and the third data rearrangement process.

[0086] The first data rearrangement unit 200a and the second data rearrangement unit 200b are buffer circuits for rearranging data. The first data rearrangement unit 200a and the second data rearrangement unit 200b rearrange the data sequence before and after the first butterfly calculation unit 32a, respectively, based on the data dependency in the FFT processing algorithm.

[0087] The third data rearrangement unit 200c is also a buffer circuit for rearranging data, and rearranges the data sequence after the second butterfly operation unit 32b based on the data dependency in the FFT processing algorithm.

[0088] Specifically, the first data rearrangement unit 200a rearranges the input order of the input data x(n) from the "sequential order" shown in FIG. 10 to the "bit reverse order" shown in FIG. 11, which is the order in which the data is input to the first butterfly calculation unit 32a.

[0089] The bit reverse order shown in FIG. 11 corresponds to the input data set to the radix-8 butterfly calculation processing unit 502 in the first stage in the data flow diagram shown in FIG.

[0090] in particular, In the first cycle, eight pieces of data x(0), x(8), . . . , x(56) that make up the data set Q1 are input. Then, in the second cycle, eight pieces of data x(1), x(9), . . . , x(57) that make up the data set Q2 are input. Thereafter, in the same manner from the third cycle to the eighth cycle, data constituting the data sets Q3 to Q8 are input.

[0091] The sequential order refers to the order of the eight data sets P1, P2, P3, P4, P5, P6, P7, and P8 shown in Fig. 10. Each data set Ps (s is a value that indicates the order of the processing cycle, s = 1, 2, ..., 8) consists of eight data items arranged in order from ps(0) to ps(7).

[0092] Assuming that a total of 64 pieces of data x(0) to x(63) are input in the order shown in FIG. 10, with 8 pieces of data each over a period of 8 cycles, ps(i) (i=0, . . . , 7) is given by the following: ps(i)=x[8×(s-1)+i]

[0093] The data sets are arranged in the order of P1, P2, P3, P4, P5, P6, P7, and P8 in accordance with the progress of the processing cycle. "Sequential order" means that s sets of data sets are created by arranging is data items in order of i items from the beginning, and then arranging each data set in cycle order.

[0094] The bit reverse order refers to the order of the eight data sets Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 shown in Figure 11. Each data set Qs (where s is a value representing the order of the processing cycle, and s = 1, 2, ..., 8) consists of eight data items arranged in order from qs(0) to qs(7). For 64 data items x(0) to x(63) input in sequential order, qs(i) (i = 0, ..., 7) is given by: qs(i)=x[(s-1)+8×i]

[0095] The data sets are arranged in the order of Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8, corresponding to the progress of the processing cycle. The bit-reverse order is where is data items input in sequential order are arranged in cycle order, starting from the beginning, with s items at a time, and i data items in the same cycle are grouped together and arranged in data order.

[0096] Each data set in bit reverse order is uniquely determined once each set in sequential order is set. Among the data constituting each data set Qs (s=1,...,8) in bit reverse order, the i-th data Qs(i) (i=0,...,7) is the s-1-th data Pi+1(s-1) in the i+1-th cycle in sequential order. That is, Qs(i)=Pi+1(s-1)

[0097] Here, if the i-th data of Ps and Qs (s=1,...,8) is expressed as Ps(i) and Qs(i) (i=1,...,8), the above formula becomes Qs(i)=Pi(s) This becomes:

[0098] That is, for the data in each data set, Qs(i) and Pi(s) have a relationship in which the order of the cycle progression and the order of the data positions are interchanged. Therefore, if data input in bit reverse order is rearranged according to the bit reverse order, it will be in sequential order.

[0099] Each row ps(i) in Fig. 10 and each of the eight rows qs(i) in Fig. 11 indicate the data to be input at the i-th stage in the next stage. The eight numbers included in each data set are identification information that specifies one of the FFT points, specifically the value of the subscript n in x(n).

[0100] The sequential order and bit-reverse order are not limited to those exemplified in Figures 10 and 11. That is, each data set in the sequential order may be created by arranging data in order according to the number of FFT points, the number of cycles, and the number of data to be processed in parallel, as described above. And each data set in the bit-reverse order may be created by swapping the order of the data input in the sequential order with respect to the progression of cycles and the order with respect to the data positions, as described above.

[0101] The first butterfly computation unit 32a is a butterfly computation unit that processes the first butterfly computation 502 (first butterfly computation) of the radix-8 butterfly computations that are performed twice in the data flow 500 of FIG.

[0102] The first butterfly operation processing unit 32a outputs the results of the butterfly operation processing as data y(n) (n=0, 1, . . . , 63) in the sequential order shown in FIG.

[0103] The second data rearrangement unit 200b rearranges the data y(n) output in sequential order by the first butterfly operation unit 32a into the bit-reverse order shown in FIG. 11 for input to the second butterfly operation unit 32b.

[0104] The twiddle multiplication processing unit 33 is a circuit that processes complex rotation on the complex plane in the FFT calculation after the first butterfly calculation processing, and corresponds to the twiddle multiplication processing unit 504 in the data flow 500 in Fig. 18. Note that in the twiddle multiplication processing, data rearrangement is not performed.

[0105] The second butterfly operation unit 32b corresponds to the butterfly operation processing circuit that performs the second processing in the radix-8 butterfly operation unit 503 in the data flow diagram of Fig. 18. The second butterfly operation unit 32b performs butterfly operation on the post-twiddle multiplication data y'(n) (n = 0, 1,..., 63) that is input in bit-reverse order, and outputs the resultant data X(k) (n = 0, 1,..., 63), also in bit-reverse order.

[0106] The third data rearrangement unit 200c rearranges the data X(k) output in bit reverse order by the second butterfly computation unit 32b into the sequential order shown in FIG.

[0107] Referring to FIG. 12, the butterfly operation processing units 32 constituting the first butterfly operation processing unit 32a and the second butterfly operation processing unit 32b include a butterfly operation circuit 34 and a lower bit mask circuit 23.

[0108] The first butterfly calculation processing unit 32a fixes the values of the least significant bit to the upper M bits (M is a positive integer such that M≧1) in the signal data to be output under the control of the mask control signal 28, thereby reducing the bit-wise operation rate of the signal data in the second data rearrangement processing unit 200b and the twiddle multiplication processing unit 33.

[0109] Similarly, the second butterfly operation processing unit 32b fixes the values of the least significant bit to the upper M bits in the signal data to be output under the control of the mask control signal 28, thereby reducing the bit-by-bit operation rate of the signal data in the third data rearrangement processing unit 200c.

[0110] 13, the twiddle multiplication processing unit 33 includes a twiddle operation circuit 35 and a lower bit mask circuit 23. The twiddle multiplication processing unit 33 fixes the values of the M most significant bits from the least significant bit in the signal data to be output under the control of a mask control signal 28, thereby reducing the bit-by-bit operation rate of the signal data in the second data rearrangement processing unit 200b and the twiddle multiplication processing unit 33.

[0111] The data rearrangement unit 200 temporarily stores input data and controls the selection and output of the stored data, thereby realizing data rearrangement processing in accordance with either the sequential order shown in Fig. 10 or the bit-reverse order shown in Fig. 11. A specific example of the data rearrangement unit 200 is shown below.

[0112] Referring to FIG. 14, the data rearrangement processing unit 200 includes a first conversion circuit 231, a first data distribution unit 202, eight RAM circuits 210a, 210b, 210c, 210d, 210e, 210f, 210g, and 210h, a second data distribution unit 203, a write address control unit 212, a read address control unit 213, and the second conversion circuit 232.

[0113] The first conversion circuit 231 simultaneously (in parallel) inputs eight data (D-bit data in two's complement representation) from eight inputs in0 to in7 input in the sequential order shown in FIG. 10, and converts the data expressed in two's complement representation into partial code absolute value -- representation.

[0114] The first conversion circuit 231 is composed of eight conversion circuits 13a1 to 13h1 corresponding to eight inputs in0 to in7. The conversion circuits 13a1 to 13h1 convert the data input in parallel, expressed in two's complement notation, into a partial code absolute value -- notation. Specifically, in the input D-bit data, bits other than the most significant bit and the most significant N bits (N is a positive integer satisfying M≦N≦D−2) indicating the sign are inverted to convert into a partial code absolute value -- notation. Here, M is the number of lower bits whose values are fixed by the lower bit mask circuit 23.

[0115] The first data distribution unit 202 performs distribution processing on the eight pieces of data converted into the partial code absolute value -- representation by the first conversion circuit 231, and outputs the data to eight outputs (data lines) 205a to 205h.

[0116] Each of the eight RAM circuits 210a-210h can store eight pieces of data. Therefore, the RAM circuits 210a-210h can store a total of 64 pieces of data (8 x 8: 8 in parallel, 8 deep), which is equal to the number of points in a 64-point FFT. The RAM circuits 210a-210h are dual-port RAM circuits with independent write and read ports. When write and read operations occur at the same time for the same address, read operations take priority. That is, data stored at the addresses targeted for write and read operations is read first, followed by the data targeted for write operations. The RAM circuits 210a-210h may be configured as dual-port static random access memory (SRAM) or dynamic random access memory (DRAM). Control terminals such as chip enable (CE), output enable (OE), and write enable (WE), as well as the control signals input to these control terminals, are omitted from the RAM circuits 210a-210h.

[0117] The RAM circuit 210a stores the data output by the first data distribution unit 202 to the data line (D bit) 205a at the address output by the write address control unit 212 to the address line 207a, and reads out the stored data from the address output by the read address control unit 213 to the address line 208a and outputs it to the data line 206a.

[0118] Similarly, the RAM circuit 210b stores the data output by the first data distribution unit 202 to the data line 205b at the address output by the write address control unit 212 to the address line 207b, and reads out the stored data from the address output by the read address control unit 213 to the address line 208b and outputs it to the data line 206b.

[0119] The RAM circuit 210c stores the data output by the first data distribution unit 202 to the data line 205c at the address output by the write address control unit 212 to the address line 207c, and reads out the stored data from the address output by the read address control unit 213 to the address line 208c and outputs it to the data line 206c.

[0120] The RAM circuit 210d stores the data output by the first data distribution unit 202 to the data line 205d at the address output by the write address control unit 212 to the address line 207d, and reads out the stored data from the address output by the read address control unit 213 to the address line 208d and outputs it to the data line 206d.

[0121] The RAM circuit 210e stores the data output by the first data distribution unit 202 to the data line 205e at the address output by the write address control unit 212 to the address line 207e, and reads out the stored data from the address output by the read address control unit 213 to the address line 208e and outputs it to the data line 206e.

[0122] The RAM circuit 210f stores the data output by the first data distribution unit 202 to the data line 205f at the address output by the write address control unit 212 to the address line 207f, and reads out the stored data from the address output by the read address control unit 213 to the address line 208f and outputs it to the data line 206f.

[0123] The RAM circuit 210g stores the data output by the first data distribution unit 202 to the data line 205g at the address output by the write address control unit 212 to the address line 207g, and reads out the stored data from the address output by the read address control unit 213 to the address line 208g and outputs it to the data line 206g.

[0124] The RAM circuit 210h stores the data output by the first data distribution unit 202 to the data line 205h at the address output by the write address control unit 212 to the address line 207h, and reads out the stored data from the address output by the read address control unit 213 to the address line 208h and outputs it to the data line 206h.

[0125] The second data distribution unit 203 simultaneously receives eight pieces of data from eight inputs (data lines) 206a to 206h, performs data distribution processing, and outputs the data to the second conversion circuit 232.

[0126] Next, the second conversion circuit 232 converts each of the eight pieces of data expressed in the partial code absolute value representation, which have been rearranged in the "bit reverse order" by the second data sorting unit 203, into a two's complement representation. The second conversion circuit 232 is composed of eight conversion circuits 13a2 to 13h2 corresponding to eight inputs. Each of the conversion circuits 13a2 to 13h2 converts the data expressed in the two's complement representation input thereto into a partial code absolute value representation.

[0127] Specifically, in the input D-bit data, (DN-1) bits excluding the most significant bit indicating the sign and the N bits (N is a positive integer satisfying M≦N≦D-2) arranged on the most significant side from the least significant bit are inverted and converted into a partial sign absolute value-- representation, where M is the number of lower bits whose value is fixed by the lower bit mask circuit 23.

[0128] The write address control section 212 refers to the input operation mode 201 and outputs addresses to which the RAM circuits 210a to 210h write data to the address lines 207a to 207h, respectively.

[0129] The read address control section 213 refers to the input operation mode 201 and outputs addresses from which the RAM circuits 210a to 210h read data to the address lines 208a to 208h, respectively.

[0130] Next, a specific operation of the data rearrangement unit 200 will be described.

[0131] The data rearrangement unit 200 During the eight cycles from t0 to t7, 64 pieces of data from 0a to 63a are input in sequential order from inputs in0 to in7 in eight parallel inputs. In the eight cycles from t8 to t15, 64 pieces of data 0a to 63a are output in bit reverse order to eight outputs out0 to out7 in parallel.

[0132] The data rearrangement unit 200 similarly During the eight cycles from t8 to t15, 64 pieces of data from 0b to 63b are input in sequential order from input in0 to in7 in eight parallel inputs. During the eight cycles from t16 to t23, 64 pieces of data from 0b to 63b are output in bit reverse order to eight outputs out0 to out7 in parallel.

[0133] The data rearrangement unit 200 further During the eight cycles from t16 to t23, 64 pieces of data from 0c to 63c are input in sequential order from input in0 to in7 in eight parallel inputs. In the eight cycles from t24 to t31, 64 pieces of data 0c to 63c are output in bit reverse order to the outputs out0 to out7 in eight parallel arrangements (not shown).

[0134] First, the input operation of data 0a to 63a in the eight cycles from t0 to t7 in the data rearrangement processing unit 200 will be described in detail.

[0135] The first data distribution unit 202 In cycle t0, Data 0a is input from in0 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231, and output to the data line 205a. The data 1a input from in1 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205b. The data 2a input from in2 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205c, The data 3a input from in3 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205d, The data 4a input from in4 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205e, The data 5a input from in5 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205f, The data 6a input from in6 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205g, The data 7a input from in7 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205h.

[0136] In cycle t1, The data 8a input from in0 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205b. The data 9a input from in1 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205c, The data 10a input from in2 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205d, The data 11a input from in3 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205e, The data 12a input from in4 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205f, The data 13a input from in5 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205g, The data 14a input from in6 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205h, The data 15a input from in7 and converted from two's complement representation to partial code magnitude code -- by the first conversion circuit 231 is output to the data line 205a.

[0137] In cycle t2, The data 16a input from in0 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205c, The data 17a input from in1 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205d, The data 18a input from in2 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205e, The data 19a input from in3 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205f, The data 20a input from in4 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205g, The data 21a input from in5 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205h, The data 22a input from in6 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205a, The data 23a input from in7 and converted from two's complement representation to partial code magnitude code by the first conversion circuit 231 is output to the data line 205b.

[0138] In cycle t3, The data 24a input from in0 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205d, The data 25a input from in1 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205e, The data 26a input from in2 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205f, The data 27a input from in3 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205g, The data 28a input from in4 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205h, The data 29a input from in5 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205a, The data 30a input from in6 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205b, The data 31a input from in7 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205c.

[0139] In cycle t4, The data 32a input from in0 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205e, The data 33a input from in1 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205f, The data 34a input from in2 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205g, The data 35a input from in3 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205h, The data 36a input from in4 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205a, The data 37a input from in5 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205b. The data 38a input from in6 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205c, The data 39a input from in7 and converted from two's complement representation to partial code magnitude code -- by the first conversion circuit 231 is output to the data line 205d.

[0140] In cycle t5, The data 40a input from in0 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205f, The data 41a input from in1 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205g. The data 42a input from in2 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205h, The data 43a input from in3 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205a, The data 44a input from in4 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205b. The data 45a input from in5 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205c, The data 46a input from in6 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205d, The data 47a input from in7 and converted from two's complement representation to partial code magnitude code -- by the first conversion circuit 231 is output to the data line 205e.

[0141] In cycle t6, The data 48a input from in0 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205g. The data 49a input from in1 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205h, The data 50a input from in2 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205a, The data 51a input from in3 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205b, The data 52a input from in4 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205c, The data 53a input from in5 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205d, The data 54a input from in6 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205e, The data 55a input from in7 and converted from two's complement representation to partial code magnitude code -- by the first conversion circuit 231 is output to the data line 205f.

[0142] In cycle t7, The data 56a input from in0 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205h, The data 57a input from in1 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205a, The data 58a input from in2 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205b, The data 59a input from in3 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205c, The data 60a input from in4 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205d, The data 61a input from in5 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205e, The data 62a input from in6 and converted from two's complement representation to partial code absolute value code by the first conversion circuit 231 is output to the data line 205f, The data 63a input from in7 and converted from two's complement representation to partial code magnitude code -- by the first conversion circuit 231 is output to the data line 205g.

[0143] As described above, the first data distribution unit 202 rotates and outputs eight pieces of data that are input simultaneously in parallel, and can be easily realized by, for example, a shift circuit.

[0144] Similarly, the first data distribution unit 202 In cycles t9 to t15, data 0b to 63b are sorted. In the cycles from t16 to t23, the allocation operation is performed on data 0c to 63c.

[0145] Next, the write and read operations of the write address control unit 212, the read address control unit 213, and the RAM circuits 210a to 210h controlled by them will be described.

[0146] The write address control unit 212 and the read address control unit 213 operate by referring to the input operation mode 201. Here, the operation mode 201 is a control signal given from a higher-level control circuit (not shown) such as a CPU (Central Processing Unit), and is either a first or second operation mode.

[0147] The operation mode 201 indicates the same operation mode for eight consecutive cycles in which data corresponding to the number of points of the 64-point FFT is input, and indicates a different operation mode every eight cycles.

[0148] Specifically, in FIG. 15, the operation mode 201 indicates the operation mode 0, which is the first operation mode, during the eight cycles from t0 to t7 in which data 0a to 63a are input.

[0149] The eight cycles from t8 to t15 in which data 0b to 63b are input indicate the second operation mode, operation mode 1. In the eight cycles from t8 to t15, data is read in operation mode 1, which is the second operation mode, from the RAM circuits 210a to 210h to which data was written in operation mode 0, which is the first operation mode, in the eight cycles from t0 to t7.

[0150] In the eight cycles from t16 to t23 in which data 0c to 63c are input, the first operation mode, operation mode 0, is again indicated. In the eight cycles from t16 to t23 in which data 0c to 63c are input, data is read in operation mode 0, the first operation mode, from the RAM circuits 210a to 210h in which data was written in operation mode 1, the second operation mode, in the eight cycles from cycles t8 to t15.

[0151] Thereafter, in a similar manner, the operation mode 201 is a signal that alternately indicates operation mode 0 or operation mode 1 every eight cycles.

[0152] When the input operation mode 201 is operation mode 0, which is the first operation mode, the write address control section 212 generates write addresses in accordance with the first address order.

[0153] When the input operation mode 201 is operation mode 1, which is the second operation mode, the write address control section 212 generates write addresses in accordance with the second address order.

[0154] The first address sequence is an address sequence that always specifies different addresses for each of the RAM circuits 210a to 210h. That is, in the first operation mode, different addresses are always output to the address lines 207a to 207h.

[0155] On the other hand, the second address order is an address order that always specifies the same address for each of the RAM circuits 210a to 210h. That is, in the second operation mode, the same addresses are always output to the address lines 207a to 207h.

[0156] The read address control unit 213 also performs the same operation as the write address control unit 212. That is, when the input operation mode 201 is operation mode 0, which is the first operation mode, the read address control unit 213 generates read addresses (mutually different addresses) for each of the RAM circuits 210a to 210h in accordance with the first address order. When the input operation mode 201 is operation mode 1, which is the second operation mode, the read address control unit 213 generates read addresses (mutually identical addresses) for each of the RAM circuits 210a to 210h in accordance with the second address order.

[0157] A specific example of the write and read operations of the write address control unit 212, the read address control unit 213, and the RAM circuits 210a to 210h will be described with reference to FIG.

[0158] first, In the eight cycles from t0 to t7, data 0a to 63a are written to the RAM circuits 210a to 210h.

[0159] In the eight cycles from t8 to t15, the data 0a to 63a written to the RAM circuits 210a to 210h are read out, and the data 0b to 63b are written to the RAM circuits 210a to 210h.

[0160] In eight cycles from t16 to t23, data 0b to 63b written to the RAM circuits 210a to 210h are read, and data 0c to 63c are written to the RAM circuits 210a to 210h. Note that in the eight cycles from t0 to t7, a read operation of the data written in the previous eight cycles from t0 to t7 is also performed, but this is not shown in the figure.

[0161] 15, writing and reading in the RAM circuits 210a to 210h are always performed to the same address in the same cycle. When writing and reading occur at the same timing to the same address, the RAM circuits 210a to 210h prioritize reading. Therefore, in the RAM circuits 210a to 210h, data 0a to 63a are read and then data 0b to 63b are written in each of the cycles t8 to t15.

[0162] Similarly, in each of the cycles t16 to t23, data 0b to 63b are read, and then data 0c to 63c are written.

[0163] Next, details of the write operations of the write address control unit 212 and the RAM circuits 210a to 210h controlled by it in cycles t0 to t7 will be shown.

[0164] Referring to Figure 15, In the eight cycles from t0 to t7, the operation mode 201 indicates the operation mode 0, which is the first operation mode, and the write address control unit 212 generates write addresses in accordance with the first address order.

[0165] The RAM circuits 210a to 210h write the data output by the first data distribution unit 202 to 207a to 207h to the write addresses generated by the write address control unit 212.

[0166] in particular, In cycle t0, The RAM circuit 210a writes data 0a to the address 0 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes data 1a to address 1 output by the write address control unit 212 onto the address line 207b. The RAM circuit 210c writes data 2a to address 2 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes data 3a to address 3 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes data 4a to address 4 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes data 5a to address 5 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes data 6a to the address 6 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes data 7a to the address 7 output by the write address control unit 212 to the address line 207h.

[0167] In cycle t1, The RAM circuit 210a writes data 15a to address 7 output by the write address control unit 212 onto the address line 207a. The RAM circuit 210b writes the data 8a to the address 0 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 9a to the address 1 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 10a to the address 2 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 11a to the address 3 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 12a to the address 4 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 13a to the address 5 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 14a to the address 6 output by the write address control unit 212 to the address line 207h.

[0168] In cycle t2, The RAM circuit 210a writes the data 22a to the address 6 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 23a to the address 7 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 16a to the address 0 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 17a to the address 1 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 18a to the address 2 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 19a to the address 3 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 20a to the address 4 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 21a to the address 5 output by the write address control unit 212 to the address line 207h.

[0169] In cycle t3, The RAM circuit 210a writes the data 29a to the address 5 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 30a to the address 6 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 31a to the address 7 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 24a to the address 0 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 25a to the address 1 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 26a to the address 2 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 27a to the address 3 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 28a to the address 4 output by the write address control unit 212 to the address line 207h.

[0170] In cycle t4, The RAM circuit 210a writes the data 36a to the address 4 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 37a to the address 5 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 38a to the address 6 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 39a to the address 7 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 32a to the address 0 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 33a to the address 1 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 34a to the address 2 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 35a to the address 3 output by the write address control unit 212 to the address line 207h.

[0171] In cycle t5, The RAM circuit 210a writes the data 43a to the address 3 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 44a to the address 4 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 45a to the address 5 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 46a to the address 6 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 47a to the address 7 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 40a to the address 0 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 41a to the address 1 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 42a to the address 2 output by the write address control unit 212 to the address line 207h.

[0172] In cycle t6, The RAM circuit 210a writes the data 50a to the address 2 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 51a to the address 3 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 52a to the address 4 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes data 53a to address 5 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 54a to the address 6 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 55a to the address 7 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 48a to the address 0 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 49a to the address 1 output by the write address control unit 212 to the address line 207h.

[0173] In cycle t7, The RAM circuit 210a writes the data 57a to the address 1 output by the write address control unit 212 to the address line 207a. The RAM circuit 210b writes the data 58a to the address 2 output by the write address control unit 212 to the address line 207b. The RAM circuit 210c writes the data 59a to the address 3 output by the write address control unit 212 to the address line 207c. The RAM circuit 210d writes the data 60a to the address 4 output by the write address control unit 212 to the address line 207d. The RAM circuit 210e writes the data 61a to the address 5 output by the write address control unit 212 to the address line 207e. The RAM circuit 210f writes the data 62a to the address 6 output by the write address control unit 212 to the address line 207f. The RAM circuit 210g writes the data 63a to the address 7 output by the write address control unit 212 to the address line 207g. The RAM circuit 210h writes the data 56a to the address 0 output by the write address control unit 212 to the address line 207h.

[0174] As described above, in the first address order, different addresses are output to the address lines 207a to 207h that indicate the write addresses of the RAM circuits 210a to 210h.

[0175] Also, different addresses are output to the address lines 207a to 207h in each of the cycles t0 to t7. For example, different addresses 0 to 7 are output to the address line 207a in the cycles t0 to t7.

[0176] Next, a specific example of the read operation of the read address control unit 213 and the RAM circuits 210a to 210h controlled by it in the cycles t8 to t15 will be shown.

[0177] As a result of the write operations in cycles t0 to t7, at the time of cycle t8, data 0a to 63a are stored in the RAM circuits 210a to 210h, respectively, as shown in FIG.

[0178] In eight cycles from t8 to t15, the operation mode 201 indicates the second operation mode, operation mode 1, and the read address control unit 213 generates read addresses in accordance with the second address order. The RAM circuits 210a to 210h output the stored data from the read addresses generated by the read address control unit 213 to the data lines 206a to 206h.

[0179] in particular, In cycle t8, The read address control unit 213 outputs an address 0 to all of the address lines 208a to 208h. The RAM circuit 210a reads data 0a from address 0. The RAM circuit 210b reads data 8a from address 0. The RAM circuit 210c reads the data 16a from address 0. The RAM circuit 210d reads the data 24a from address 0. The RAM circuit 210e reads the data 32a from address 0. The RAM circuit 210f reads the data 40a from address 0. The RAM circuit 210g reads the data 48a from address 0. The RAM circuit 210h reads the data 56a from address 0.

[0180] In cycle t9, The read address control unit 213 outputs the address 1 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 57a from address 1. The RAM circuit 210b reads data 1a from address 1. The RAM circuit 210c reads data 9a from address 1. The RAM circuit 210d reads the data 17a from address 1. The RAM circuit 210e reads the data 25a from the address 1. The RAM circuit 210f reads the data 33a from address 1. The RAM circuit 210g reads the data 41a from address 1. The RAM circuit 210h reads the data 49a from address 1.

[0181] In cycle t10, The read address control unit 213 outputs the address 2 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 50a from address 2. The RAM circuit 210b reads the data 58a from address 2. The RAM circuit 210c reads data 2a from address 2. The RAM circuit 210d reads the data 10a from address 2. The RAM circuit 210e reads the data 18a from address 2. The RAM circuit 210f reads the data 26a from the address 2. The RAM circuit 210g reads the data 34a from address 2. The RAM circuit 210h reads the data 42a from address 2.

[0182] In cycle t11, The read address control unit 213 outputs the address 3 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 43a from address 3. The RAM circuit 210b reads the data 51a from address 3. The RAM circuit 210c reads the data 59a from address 3. The RAM circuit 210d reads data 3a from address 3. The RAM circuit 210e reads the data 11a from the address 3. The RAM circuit 210f reads the data 19a from address 3. The RAM circuit 210g reads the data 27a from address 3. The RAM circuit 210h reads the data 35a from address 3.

[0183] In cycle t12, The read address control unit 213 outputs the address 4 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 36a from address 4. The RAM circuit 210b reads the data 44a from address 4. The RAM circuit 210c reads the data 52a from address 4. The RAM circuit 210d reads the data 60a from address 4. The RAM circuit 210e reads data 4a from address 4. The RAM circuit 210f reads the data 12a from the address 4. The RAM circuit 210g reads the data 20a from address 4. The RAM circuit 210h reads the data 28a from address 4.

[0184] In cycle t13, The read address control unit 213 outputs the address 5 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 29a from address 5. The RAM circuit 210b reads the data 37a from address 5. The RAM circuit 210c reads the data 45a from address 5. The RAM circuit 210d reads data 53a from address 5. The RAM circuit 210e reads the data 61a from address 5. The RAM circuit 210f reads data 5a from address 5. The RAM circuit 210g reads the data 13a from the address 5. The RAM circuit 210h reads the data 21a from address 5.

[0185] In cycle t14, The read address control unit 213 outputs the address 6 to all of the address lines 208a to 208h. The RAM circuit 210a reads the data 22a from address 6. The RAM circuit 210b reads the data 30a from address 6. The RAM circuit 210c reads the data 38a from address 6. The RAM circuit 210d reads the data 46a from address 6. The RAM circuit 210e reads the data 54a from address 6. The RAM circuit 210f reads the data 62a from the address 6. The RAM circuit 210g reads data 6a from address 6. The RAM circuit 210h reads the data 14a from the address 6.

[0186] In cycle t15, The read address control unit 213 outputs the address 7 to all of the address lines 208a to 208h. The RAM circuit 210a reads data 15a from address 7. The RAM circuit 210b reads the data 23a from the address 7. The RAM circuit 210c reads the data 31a from address 7. The RAM circuit 210d reads the data 39a from address 7. The RAM circuit 210e reads the data 47a from the address 7. The RAM circuit 210f reads the data 55a from the address 7. The RAM circuit 210g reads the data 63a from the address 7. The RAM circuit 210h reads data 7a from address 7.

[0187] As described above, in the second address order, the same address is output to all of the address lines 208a-208h, which indicate the read addresses of the RAM circuits 210a-210h. Also, different addresses are output to the address lines 208a-208h in the cycles t8-t15. For example, different addresses, addresses 0-7, are output to the address line 208a in the cycles t8-t15.

[0188] Next, a specific example of the write operation of the write address control unit 212 and the RAM circuits 210a to 210h controlled by it in the cycles t8 to t15 will be shown.

[0189] In the eight cycles from t8 to t15, the operation mode 201 indicates the operation mode 1, which is the second operation mode, and the write address control unit 212 generates write addresses in accordance with the second address order.

[0190] The RAM circuits 210a to 210h write the data that the first data distribution unit 202 has output to the data lines 205a to 205h to the write addresses generated by the write address control unit 212.

[0191] in particular, In cycle t8, The write address control unit 212 outputs an address 0 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 0b to address 0. The RAM circuit 210b writes data 1b to address 0. The RAM circuit 210c writes data 2b to address 0. The RAM circuit 210d writes data 3b to address 0. The RAM circuit 210e writes data 4b to address 0. The RAM circuit 210f writes data 5b to address 0. The RAM circuit 210g writes data 6b to address 0. The RAM circuit 210h writes data 7b to address 0.

[0192] In cycle t9, The write address control unit 212 outputs the address 1 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 15b to address 1. The RAM circuit 210b writes data 8b to address 1. The RAM circuit 210c writes data 9b to address 1. The RAM circuit 210d writes data 10b to address 1. The RAM circuit 210e writes the data 11b to the address 1. The RAM circuit 210f writes data 12b to address 1. The RAM circuit 210g writes data 13b to address 1. The RAM circuit 210h writes data 14b to address 1.

[0193] In cycle t10, The write address control unit 212 outputs address 2 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 22b to address 2. The RAM circuit 210b writes data 23b to address 2. The RAM circuit 210c writes data 16b to address 2. The RAM circuit 210d writes the data 17b to the address 2. The RAM circuit 210e writes the data 18b to the address 2. The RAM circuit 210f writes the data 19b to the address 2. The RAM circuit 210g writes the data 20b to the address 2. The RAM circuit 210h writes the data 21b to the address 2.

[0194] In cycle t11, The write address control unit 212 outputs the address 3 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 29b to address 3. The RAM circuit 210b writes data 30b to address 3. The RAM circuit 210c writes data 31b to address 3. The RAM circuit 210d writes data 24b to address 3. The RAM circuit 210e writes data 25b to address 3. The RAM circuit 210f writes the data 26b to the address 3. The RAM circuit 210g writes the data 27b to the address 3. The RAM circuit 210h writes the data 28b to the address 3.

[0195] In cycle t12, The write address control unit 212 outputs the address 4 to all of the address lines 207a to 207h. The RAM circuit 210a writes the data 36b to address 4. The RAM circuit 210b writes data 37b to address 4. The RAM circuit 210c writes the data 38b to address 4. The RAM circuit 210d writes data 39b to address 4. The RAM circuit 210e writes data 32b to address 4. The RAM circuit 210f writes the data 33b to the address 4. The RAM circuit 210g writes the data 34b to the address 4. The RAM circuit 210h writes the data 35b to the address 4.

[0196] In cycle t13, The write address control unit 212 outputs the address 5 to all of the address lines 207a to 207h. The RAM circuit 210a writes the data 43b to the address 5. The RAM circuit 210b writes the data 44b to the address 5. The RAM circuit 210c writes data 45b to address 5. The RAM circuit 210d writes the data 46b to the address 5. The RAM circuit 210e writes the data 47b to the address 5. The RAM circuit 210f writes the data 40b to the address 5. The RAM circuit 210g writes the data 41b to the address 5. The RAM circuit 210h writes the data 42b to the address 5.

[0197] In cycle t14, The write address control unit 212 outputs the address 6 to all of the address lines 207a to 207h. The RAM circuit 210a writes the data 50b to the address 6. The RAM circuit 210b writes data 51b to address 6. The RAM circuit 210c writes data 52b to address 6. The RAM circuit 210d writes data 53b to address 6. The RAM circuit 210e writes the data 54b to the address 6. The RAM circuit 210f writes data 55b to address 6. The RAM circuit 210g writes the data 48b to the address 6. The RAM circuit 210h writes data 49b to address 6.

[0198] In cycle t15, The write address control unit 212 outputs the address 7 to all of the address lines 207a to 207h. The RAM circuit 210a writes data 57b to address 7. The RAM circuit 210b writes data 58b to address 7. The RAM circuit 210c writes data 59b to address 7. The RAM circuit 210d writes the data 60b to the address 7. The RAM circuit 210e writes the data 61b to the address 7. The RAM circuit 210f writes the data 62b to the address 7. The RAM circuit 210g writes the data 63b to the address 7. The RAM circuit 210h writes data 56b to address 7.

[0199] As described above, in the second address order, the same address is output to all of the address lines 207a to 207h that indicate the write addresses of the RAM circuits 210a to 210h.

[0200] Also, different addresses are output to address lines 207a to 207h in cycles t8 to t15, respectively. For example, different addresses 0 to 7 are output to address line 207a in cycles t0 to t7.

[0201] Next, a specific example of the read operation of the read address control unit 213 and the RAM circuits 210a to 210h controlled by it in the cycles t16 to t23 will be shown.

[0202] As a result of the write operation in cycles t8 to t15, at the time of cycle t16, data 0b to 63b are stored in the RAM circuits 210a to 210h as shown in FIG.

[0203] In the eight cycles from t16 to t23, the operation mode 201 indicates the first operation mode, operation mode 0, and the read address control unit 213 generates read addresses according to the first address order. The RAM circuits 210a to 210h output the stored data from the read addresses generated by the read address control unit 213 to the data lines 206a to 206h.

[0204] Specifically, in cycle t16, The RAM circuit 210a reads data 0b from the address 0 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 8b from address 1 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads out data 16b from address 2 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads the data 24b from the address 3 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 32b from address 4 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads the data 40b from the address 5 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 48b from the address 6 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads data 56b from address 7 output by the read address control unit 213 to the address line 208h.

[0205] In cycle t17, The RAM circuit 210a reads data 57b from address 7 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 1b from address 0 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 9b from address 1 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads out data 17b from address 2 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 25b from address 3 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads the data 33b from the address 4 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 41b from the address 5 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads out data 49b from address 6 output by the read address control unit 213 to the address line 208h.

[0206] In cycle t18, The RAM circuit 210a reads out data 50b from address 6 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 58b from address 7 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 2b from address 0 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads out data 10b from address 1 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out the data 18b from the address 2 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads the data 26b from the address 3 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 34b from the address 4 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads the data 42b from the address 5 output by the read address control unit 213 to the address line 208h.

[0207] In cycle t19, The RAM circuit 210a reads out the data 43b from the address 5 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads out data 51b from address 6 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 59b from address 7 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads data 3b from address 0 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 11b from address 1 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads out the data 19b from the address 2 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 27b from the address 3 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads out the data 35b from the address 4 output by the read address control unit 213 to the address line 208h.

[0208] In cycle t20, The RAM circuit 210a reads the data 36b from the address 4 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 44b from address 5 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 52b from address 6 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads data 60b from address 7 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 4b from address 0 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads data 12b from the address 1 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 20b from the address 2 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads the data 28b from the address 3 output by the read address control unit 213 to the address line 208h.

[0209] In cycle t21, The RAM circuit 210a reads data 29b from address 3 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 37b from address 4 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 45b from address 5 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads out data 53b from address 6 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out the data 61b from the address 7 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads data 5b from address 0 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out data 13b from address 1 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads the data 21b from the address 2 output by the read address control unit 213 to the address line 208h.

[0210] In cycle t22, The RAM circuit 210a reads out data 22b from address 2 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 30b from address 3 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads the data 38b from the address 4 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads data 46b from address 5 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out the data 54b from the address 6 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads out the data 62b from the address 7 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads data 6b from address 0 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads out data 14b from address 1 output by the read address control unit 213 to the address line 208h.

[0211] In cycle t23, The RAM circuit 210a reads data 15b from address 1 output by the read address control unit 213 to the address line 208a. The RAM circuit 210b reads data 23b from address 2 output by the read address control unit 213 to the address line 208b. The RAM circuit 210c reads data 31b from address 3 output by the read address control unit 213 to the address line 208c. The RAM circuit 210d reads data 39b from address 4 output by the read address control unit 213 to the address line 208d. The RAM circuit 210e reads out data 47b from address 5 output by the read address control unit 213 to the address line 208e. The RAM circuit 210f reads out data 55b from address 6 output by the read address control unit 213 to the address line 208f. The RAM circuit 210g reads out the data 63b from the address 7 output by the read address control unit 213 to the address line 208g. The RAM circuit 210h reads data 7b from address 0 output by the read address control unit 213 to the address line 208h.

[0212] As described above, in the first address order, different addresses are output to the address lines 208a to 208h that indicate the read addresses of the RAM circuits 210a to 210h.

[0213] Also, different addresses are output to the address lines 208a to 208h in each of the cycles t16 to t23. For example, different addresses 0 to 7 are output to the address line 208a in the cycles t16 to t23.

[0214] Next, the operation of the second data distribution unit 203 in the cycle from t8 to t15 will be described.

[0215] Specifically, in cycle t8, The data 0a input from the data line 206a is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out0. The data 8a input from the data line 206b is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out1; The data 16a input from the data line 206c is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out2. The data 24a input from the data line 206d is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out3. The data 32a input from the data line 206e is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out4. The data 40a input from the data line 206f is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out5. The data 48a input from the data line 206g is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out6. The data 56a input from the data line 206h is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out7.

[0216] In cycle t9, The data 57a input from the data line 206a is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out7. The data 1a input from the data line 206b is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out0. The data 9a input from the data line 206c is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out1; The data 17a input from the data line 206d is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out2; The data 25a input from the data line 206e is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out3. The data 33a input from the data line 206f is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out4. The data 41a input from the data line 206g is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out5. The data 49a input from the data line 206h is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out6.

[0217] In cycle t10, The data 50a input from the data line 206a is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out6. The data 58a input from the data line 206b is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out7. The data 2a input from the data line 206c is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out0. The data 10a input from the data line 206d is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out1; The data 18a input from the data line 206e is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out2; The data 26a input from the data line 206f is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out3. The data 34a input from the data line 206g is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out4. The data 42a input from the data line 206h is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out5.

[0218] In cycle t11, The data 43a input from the data line 206a is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out5. The data 51a input from the data line 206b is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out6. The data 59a input from the data line 206c is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out7. The data 3a input from the data line 206d is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out0. The data 11a input from the data line 206e is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out1; The data 19a input from the data line 206f is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out2. The data 27a input from the data line 206g is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out3. The data 35a input from the data line 206h is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out4.

[0219] In cycle t12, The data 36a input from the data line 206a is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out4. The data 44a input from the data line 206b is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out5. The data 52a input from the data line 206c is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out6. The data 60a input from the data line 206d is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out7. The data 4a input from the data line 206e is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out0. The data 12a input from the data line 206f is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out1; The data 20a input from the data line 206g is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out2; The data 28a input from the data line 206h is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out3.

[0220] In cycle t13, The data 29a input from the data line 206a is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out3. The data 37a input from the data line 206b is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out4. The data 45a input from the data line 206c is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out5. The data 53a input from the data line 206d is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out6. The data 61a input from the data line 206e is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out7. The data 5a input from the data line 206f is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out0. The data 13a input from the data line 206g is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out1; The data 21a input from the data line 206h is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out2.

[0221] In cycle t14, The data 22a input from the data line 206a is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out2; The data 30a input from the data line 206b is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out3. The data 38a input from the data line 206c is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out4. The data 46a input from the data line 206d is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out5. The data 54a input from the data line 206e is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out6. The data 62a input from the data line 206f is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out7. The data 6a input from the data line 206g is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out0. The data 14a input from the data line 206h is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out1.

[0222] In cycle t15, The data 15a input from the data line 206a is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out1; The data 23a input from the data line 206b is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out2; The data 31a input from the data line 206c is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out3. The data 39a input from the data line 206d is converted by the second conversion circuit 232 from the partial sign absolute value representation to a two's complement representation, and output to out4. The data 47a input from the data line 206e is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out5. The data 55a input from the data line 206f is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out6. The data 63a input from the data line 206g is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out7. The data 7a input from the data line 206h is converted by the second conversion circuit 232 from the partial sign absolute value representation to the two's complement representation, and output to out0.

[0223] As described above, as a result of the data distribution process by the second data distribution unit 203, data 0a to 63a are output to out0 to out7 in bit reverse order in cycles t8 to t15.

[0224] The second data distribution unit 203, like the first data distribution unit 202, rotates and outputs eight pieces of data that are input in parallel at the same time, and can be easily realized by, for example, a shift circuit.

[0225] The second data distribution unit 203 also performs a similar distribution operation on data 0b to 63b in the cycles t16 to t23, and outputs data 0b to 63b to out0 to out7 in bit reverse order.

[0226] The data rearrangement process has been described above using an example of rearrangement from sequential order to bit-reverse order, but rearrangement from bit-reverse order to sequential order can also be similarly realized.

[0227] As described above, in this embodiment, the data rearrangement unit 200 included in the FFT device 30 realizes the data rearrangement process required for the butterfly computation, such as rearrangement from "sequential order" to "bit-reverse order" and rearrangement from "bit-reverse order" to "sequential order," by controlling the write and read operations of the RAM circuits 210a to 210h using two types of address orders, first and second.

[0228] For example, data written to a RAM circuit in a first address order is read out in a second address order, and data written in the second address order is read out in the first address order.

[0229] As a result, in this embodiment, even when FFT processing is performed on signals that are input continuously, data rearrangement processing can be achieved with a RAM circuit having a storage capacity equal to the number of FFT points.

[0230] Therefore, compared to double-buffer technology, which requires a memory capacity of at least twice the number of FFT points for data rearrangement, the RAM circuit's memory capacity can be halved, thereby reducing the circuit scale and power consumption of the RAM circuit. As a result, the circuit scale and power consumption of the entire FFT device, including the data rearrangement processing unit, can be reduced.

[0231] Furthermore, in this embodiment, the FFT device 30 performs the data rearrangement required for the butterfly computation, such as rearrangement from "sequential order" to "bit-reverse order" or rearrangement from "bit-reverse order" to "sequential order," after converting to the partial code absolute value -- representation. Therefore, compared to performing the rearrangement process using the two's complement representation as is, it is possible to reduce the operation rate of circuits such as flip-flop circuits and selector circuits that constitute the RAM circuits 210a to 210h and the first data distribution unit 202 and second data distribution unit 203.

[0232] Furthermore, the conversion process between two's complement representation and partial sign-magnitude-value representation can be realized only by bit inversion processing, and does not require the 1 addition process (increment process) required for sign-magnitude-value representation. Because the bit inversion processing circuit can be realized using only XOR circuits, it can be realized with an overwhelmingly smaller circuit scale than other logic processing circuits or arithmetic processing circuits. Furthermore, compared to the conversion process between two's complement representation and partial sign-magnitude-value representation, fewer XOR circuits are required, so it can be realized with an even smaller circuit scale.

[0233] Therefore, in this embodiment, even when processing a signal that frequently changes between positive and negative values near the value 0, the operation rate of the circuit in the data rearrangement process can be reduced, thereby reducing power consumption in the data rearrangement processing unit.

[0234] In this embodiment, the butterfly operation processing and twiddle multiplication processing are performed in the butterfly operation processing unit and the twiddle multiplication processing unit using the two's complement representation as they are. Therefore, the operation rate of the circuits related to these operation processing is not reduced, but the circuit size is not increased by conversion between data representation formats as in the case where the sign-magnitude representation is applied.

[0235] Therefore, in this embodiment, the power consumption of the entire FFT device can be reduced by the amount of power consumed by the data rearrangement process. Furthermore, since the circuit scale of the transform circuit is smaller than that of the sign-magnitude representation, more transform processing can be performed at more optimal locations. Therefore, the power consumption of the entire FFT device can be further reduced.

[0236] The above-mentioned embodiments are further described as follows (but are not limited to the following):

[0237] (Supplementary Note 1) The signal processing device includes: an arithmetic processing unit that performs arithmetic processing on D-bit (D is a positive integer greater than or equal to 3) data expressed in two's complement notation as a data representation format; a storage processing unit that performs storage processing on D-bit data expressed in a second representation format as a data representation format, wherein the second representation format is If the data value is positive or 0, it is the same as the two's complement representation above. If the data value is negative, then in the two's complement representation, This is a representation format in which (DN-1) bits excluding the most significant bit indicating the sign and the N bits (where N is a positive integer such that N≦D-2) arranged from the least significant bit to the most significant side are inverted.

[0238] (Supplementary Note 2) The signal processing device of Supplementary Note 1 is provided with a lower bit mask circuit that inputs D-bit data, sets all M bits (M is a positive integer satisfying 1≦M≦N) arranged from the least significant bit to the most significant bit, and outputs the set values.

[0239] (Supplementary Note 3) In the signal processing device of Supplementary Note 1 or 2, the storage processing unit includes a data rearrangement processing unit that rearranges a plurality of data input in a first order into a second order. The data rearrangement processing unit includes a memory circuit, a first control unit that writes a plurality of data items to the memory circuit according to one of a first address order and a second address order, and a second control unit that reads the plurality of data items written to the memory circuit according to one of the first address order and the second address order from the memory circuit according to the other of the first address order and the second address order.

[0240] (Supplementary Note 4) In the memory processing unit of the signal processing device of Supplementary Note 3, the memory circuit includes a plurality of memory elements that store the plurality of data for a plurality of cycles, and the first address order is such that the addresses simultaneously supplied to the plurality of memory elements are different from one another, and the second address order is such that the addresses simultaneously supplied to the plurality of memory elements are the same.

[0241] (Supplementary Note 5) In the signal processing device of Supplementary Note 4, the arithmetic processing unit includes a butterfly arithmetic processing unit that performs butterfly arithmetic processing and a twiddle multiplication processing unit that performs twiddle multiplication processing. The storage processing unit includes a first conversion unit that receives the plurality of data in two's complement representation and converts the input plurality of data from the two's complement representation to the second representation format and outputs the converted data; The digital signal processing device further includes a first data allocation unit that inputs and performs allocation processing on the plurality of data in the second representation format output from the first conversion unit, a second data allocation unit that inputs and performs allocation processing on the plurality of data in the second representation format that are read from the plurality of memory elements according to addresses from the second control unit and the plurality of data in the second representation format that are allocated by the first data allocation unit and written to the plurality of memory elements according to addresses from the second control unit, and a second conversion unit that inputs and converts the plurality of data in the second representation format that are allocated by the second data allocation unit, and outputs the plurality of data in the second representation format that are input to the two's complement representation.

[0242] (Appendix 6) A signal processing device that performs n×n point fast Fourier transform or inverse fast Fourier transform, first to third data rearrangement units; first and second butterfly calculation processing units; a twiddle multiplication processing unit that performs processing to multiply the data by a twiddle coefficient; It is equipped with: The first data rearrangement processing unit receives n pieces of data input in parallel in sequential order for n cycles, rearranges the data in bit-reverse order, and outputs n pieces of the data rearranged in bit-reverse order in parallel for n cycles. The first butterfly computation unit performs butterfly computation on the n pieces of data output in parallel from the first data rearrangement unit, and outputs the n pieces of data resulting from the butterfly computation in parallel. The second data rearrangement processing unit inputs n pieces of data output in parallel in sequential order from the first butterfly calculation processing unit for n cycles, rearranges the data in the bit-reverse order, and outputs n pieces of data rearranged in the bit-reverse order in parallel for n cycles. The twiddle multiplication processing unit multiplies the data output from the second data rearrangement processing unit by a corresponding twiddle coefficient. The second butterfly calculation unit performs butterfly calculations on the n pieces of data output from the twiddle multiplication unit, and outputs the n pieces of data resulting from the butterfly calculations in parallel. The third data rearrangement processing unit inputs n pieces of data output in parallel in the bit reverse order from the second butterfly calculation processing unit for n cycles, rearranges the data into the sequential order, and outputs n pieces of data rearranged in the sequential order in parallel for n cycles. The first and second butterfly calculation processing units and the twiddle multiplication processing unit perform calculation processing on the data expressed in two's complement notation. The first to third data rearrangement units rearrange the order of a plurality of data represented in the second representation format. the second representation format is identical to two's complement representation when the data value is positive or 0; If the data value is negative, the representation format is such that the bits between the most significant bit indicating the sign and a predetermined number of bits from the least significant bit to the most significant bit are inverted in comparison to the two's complement representation.

[0243] (Appendix 7) In the signal processing device of Appendix 6, The first to third data rearrangement units each include: a memory circuit including n memory elements for storing the n pieces of data for n cycles; a first control unit that performs control to write n pieces of data into the n storage elements for n cycles in accordance with one of a first address sequence and a second address sequence; and a second control unit that controls reading n pieces of data for n cycles written to the n storage elements according to one of the first address order and the second address order from the n storage elements according to the other of the first address order and the second address order, wherein the first address order provides different addresses to the storage elements in each cycle, and the second address order provides the same addresses to the storage elements in each cycle.

[0244] (Supplementary Note 8) In the signal processing device of Supplementary Note 7, the first control unit and the second control unit alternately switch between the first address order and the second address order every n cycles.

[0245] (Supplementary Note 9) In the signal processing device of any one of Supplementary Notes 6 to 8, at least one of the first and second butterfly calculation processing units and the twiddle multiplication processing unit includes a lower bit mask circuit that sets all of a second number of lower bits (the second number being 1 or more and the first number or less) arranged from the least significant bit to the upper side of the data to a predetermined fixed value and outputs the set value.

[0246] (Appendix 10) The signal processing method is Performing arithmetic processing on D-bit (D is a positive integer greater than or equal to 3) data expressed in two's complement notation, performing a storage process on the D-bit data expressed in the second representation format as a data representation format; The second expression form is If the data value is positive or 0, it is the same as the two's complement representation above. If the data value is negative, then in the two's complement representation, This is a representation format in which (DN-1) bits excluding the most significant bit indicating the sign and the N bits (where N is a positive integer such that N≦D-2) arranged from the least significant bit to the most significant side are inverted.

[0247] (Supplementary Note 11) In the signal processing method of Supplementary Note 10, D-bit data is input, and all M bits (M is a positive integer satisfying 1≦M≦N) arranged from the least significant bit to the most significant bit are set to predetermined fixed values and output.

[0248] (Appendix 12) In the signal processing method of appendix 10 or 11, The storage process includes: a data sorting process for sorting a plurality of data input in a first order into a second order; The data rearrangement process includes: writing a plurality of data to the storage circuit according to one of a first address sequence and a second address sequence; The plurality of data written to the storage circuit in accordance with one of the first address sequence and the second address sequence is read from the storage circuit in accordance with the other of the first address sequence and the second address sequence.

[0249] (Appendix 13) In the signal processing method of Appendix 12, the plurality of data are stored in the plurality of memory elements of the memory circuit for a plurality of cycles; In the first address order, the addresses simultaneously supplied to the storage elements are different from one another, and in the second address order, the addresses simultaneously supplied to the storage elements are the same.

[0250] (Appendix 14) In the signal processing method of Appendix 13, The calculation process includes performing a butterfly calculation process and a twiddle multiplication process, The storage process includes: a first conversion process for inputting the plurality of data in the two's complement representation, converting the input plurality of data from the two's complement representation to the second representation format, and outputting the converted data; a first data sorting process that inputs the plurality of data in the second representation format output from the first conversion process and performs sorting; a second data allocation process in which the plurality of data in the second representation format allocated in the first data allocation process is written to the plurality of memory elements in one of the first address order and the second address order, and the plurality of data in the second representation format read from the plurality of memory elements in the other of the first address order and the second address order is input and allocated; The method includes a second conversion process of converting the plurality of data in the second representation format allocated in the second data allocation process into the two's complement representation and outputting the data.

[0251] [Reference 1] Japanese Patent Application Laid-Open No. 8-137832 (pages 3-5, Figure 25) [Reference 2] JWCooley, JWTukey, "An Algorithm for the Machine Calculation of Complex Fourier Series," Mathematics of Computation, US, American Mathematical Society, Apr. 1965, Vol.19, No. 90, pp. 297-301 [Reference 3] DPKolba, "A Prime Factor FFT Algorithm Using High-Speed Convolution," IEEE Trans. on Acoustics, US, IEEE Signal Processing Society, Aug. 1977, Vol.29, No.4, pp. 281-294 [Reference 4] JP 2001-56806 A (page 5, Figure 1)

[0252] The disclosures of Patent Document 1 and References 1-4 are incorporated herein by reference. Modifications and adjustments of the embodiments and examples are possible within the scope of the entire disclosure (including the claims) and based on the basic technical ideas. Furthermore, various combinations and selections of the various disclosed elements (including each element of each claim, each element of each example, each element of each drawing, etc.) are possible within the scope of the claims. In other words, it goes without saying that various modifications and alterations that a person skilled in the art would be able to make based on the entire disclosure and technical ideas are included. [Explanation of symbols]

[0253] 10. Signal Processing Device 11, 11a, 11b, 11c Memory Processing Unit 12a, 12b Processing unit 13, 13a, 13b, 13a1 to 13h1, 13a2 to 13h2 conversion circuit 14 Memory circuit 171~17 D-N-1 XOR circuit 20 Signal Processing Device 22, 22a, 22b Processing unit 23 Lower bit mask circuit 24 Arithmetic circuit 27 AND Circuit 28 Mask Control Signal 30 FFT equipment 32, 32a, 32b Butterfly calculation processing unit 33 Twist multiplication processing unit 34 Butterfly calculation circuit 35 Twist operation circuit 131 first conversion circuit 132 Second conversion circuit 200, 200a, 200b, 200c data sorting processing unit 201 Operation Mode 202 First Data Distribution Unit 203 Second Data Distribution Unit 205a~205h data line 206a~206h data line 207a~207h Address lines 208a~208h Address lines 210a~210h RAM circuit 212 Write address control section 213 Read address control unit 231 first conversion circuit 232 Second conversion circuit 500 Data Flow 501 Data sorting processing unit 502, 503 butterfly calculation processing unit 504 Twist multiplication processing unit 505a~505h Partial data flow 600 conversion circuit 601 Bit Inversion Circuit 602 1 Addition Circuit 6071~607 N-1 XOR circuit 610 Conversion Circuit

Claims

1. a processing unit that performs arithmetic operations on D-bit data (D is a positive integer greater than or equal to 3) expressed in two's complement notation as a data representation format; a storage processing unit that performs storage processing on D-bit data expressed in a second representation format as a data representation format; Equipped with The second expression form is If the data value is positive or 0, it is the same as the two's complement representation. If the data value is negative, then in the two's complement representation, A signal processing device characterized in that the representation format is one in which (D-N-1) bits excluding the most significant bit indicating the sign and N bits (where N is a positive integer such that N≦D-2) arranged from the least significant bit to the most significant bit are inverted.

2. 2. The signal processing device according to claim 1, further comprising a lower bit mask circuit that inputs D-bit data, sets all M bits (M is a positive integer satisfying 1≦M≦N) arranged from the least significant bit to a predetermined fixed value, and outputs the set value.

3. The storage processing unit a data rearrangement processing unit that rearranges a plurality of data input in a first order into a second order; The data rearrangement processing unit A memory circuit; a first control unit that writes a plurality of data items to the memory circuit in accordance with one of a first address sequence and a second address sequence; a second control unit that reads the plurality of data written to the storage circuit in accordance with one of the first address sequence and the second address sequence from the storage circuit in accordance with the other of the first address sequence and the second address sequence; 2. The signal processing device according to claim 1, further comprising:

4. In the storage processing unit, the memory circuit includes a plurality of memory elements for storing the plurality of data for a plurality of cycles; the first address order is such that the addresses simultaneously supplied to the memory elements are different from one another; 4. The signal processing device according to claim 3, wherein the second address order is such that the addresses simultaneously supplied to the storage elements are the same.

5. The arithmetic processing unit a butterfly calculation processing unit that performs butterfly calculation processing; a twiddle multiplication processing unit that performs twiddle multiplication processing; Equipped with The storage processing unit a first conversion unit that receives the plurality of data in the two's complement representation, converts the received plurality of data from the two's complement representation to the second representation format, and outputs the converted data; a first data sorting unit that receives the plurality of data in the second representation format output from the first conversion unit and performs sorting processing; the plurality of data in the second representation format allocated by the first data allocation unit are written into the plurality of memory elements at addresses from the first control unit; a second data sorting unit that inputs the plurality of data in the second representation format read from the plurality of storage elements according to addresses from the second control unit and performs sorting processing; a second conversion unit that receives the plurality of data in the second representation format sorted by the second data sorting unit, converts the received plurality of data in the second representation format into the two's complement representation, and outputs the converted data; 5. The signal processing device according to claim 4, further comprising:

6. A signal processing device for performing an n×n point fast Fourier transform or an inverse fast Fourier transform, first to third data rearrangement units; first and second butterfly calculation processing units; a twiddle multiplication processing unit that performs processing to multiply the data by a twiddle coefficient; Equipped with The first data rearrangement processing unit n pieces of data input in parallel in sequential order are input for n cycles, rearranged in bit reverse order, and the n pieces of data rearranged in bit reverse order are output in parallel for n cycles; The first butterfly calculation processing unit performing a butterfly operation on the n pieces of data output in parallel from the first data rearrangement unit, and outputting the n pieces of data resulting from the butterfly operation in parallel; the second data rearrangement unit receives n pieces of data output in parallel in sequential order from the first butterfly operation unit for n cycles, rearranges the pieces of data in the bit reverse order, and outputs n pieces of data rearranged in the bit reverse order in parallel for n cycles; the twiddle multiplication processing unit multiplies the data output from the second data rearrangement processing unit by a corresponding twiddle coefficient; the second butterfly calculation unit performs butterfly calculations on the n pieces of data output from the twiddle multiplication unit, and outputs the n pieces of data resulting from the butterfly calculations in parallel; the third data rearrangement unit receives n cycles of n pieces of data output in parallel in the bit reverse order from the second butterfly operation unit, rearranges the n pieces of data into the sequential order, and outputs n pieces of the data rearranged in the sequential order in parallel for n cycles; the first and second butterfly calculation units and the twiddle multiplication unit perform calculations on the data expressed in two's complement representation, the first to third data rearrangement units rearrange the order of a plurality of data represented in a second representation format; The second expression form is If the data value is positive or 0, is identical to the two's complement representation, If the data value is negative, A signal processing device in which, compared to the two's complement representation, the representation format is such that bits between the most significant bit and a predetermined number of bits arranged on the upper side from the least significant bit indicating the sign are inverted, excluding the most significant bit and a first number of bits arranged on the upper side from the least significant bit.

7. The first to third data rearrangement processing units each include: a memory circuit including n memory elements for storing the n pieces of data for n cycles; a first control unit that performs control to write n pieces of data into the n memory elements for n cycles in accordance with one of a first address sequence and a second address sequence; a second control unit that controls reading n pieces of data for n cycles that have been written to the n storage elements in accordance with one of the first address sequence and the second address sequence from the n storage elements in accordance with the other of the first address sequence and the second address sequence; Equipped with the first address order is such that addresses supplied to the plurality of storage elements in the cycle are different from one another; 7. The signal processing device according to claim 6, wherein the second address order is such that the addresses supplied to the plurality of storage elements in the cycle are the same.

8. 8. The signal processing device according to claim 7, wherein the first control unit and the second control unit alternately switch between the first address sequence and the second address sequence every n cycles.

9. At least one of the first and second butterfly calculation processing units and the twiddle multiplication processing unit is 7. The signal processing device according to claim 6, further comprising a lower bit mask circuit that sets all of a second number of lower bits (the second number being 1 or more and the first number or less) arranged from the least significant bit of the data to a predetermined fixed value and outputs the set value.

10. Performing an arithmetic operation on D-bit data (D is a positive integer greater than or equal to 3) expressed in two's complement notation as a data representation format, performing a storage process on the D-bit data expressed in the second representation format as the data representation format; The second expression form is If the data value is positive or 0, it is the same as the two's complement representation. If the data value is negative, then in the two's complement representation, A signal processing method characterized in that the representation format is one in which (D-N-1) bits excluding the most significant bit indicating the sign and N bits (where N is a positive integer such that N≦D-2) arranged from the least significant bit to the most significant bit are inverted.

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