Electroplating seed layer buildup and repair

Abstract

To provide methods related to electroplating operations in semiconductor processing.SOLUTION: Exemplary methods of electroplating may include delivering a current from a power supply through a plating bath of an electroplating chamber for a first period of time. The current delivered may be or include a pulsed current at a duty cycle of about 50% or less. The methods may include plating a first amount of metal on a substrate within the plating bath. The substrate may define a via within the substrate. The methods may include, subsequent to the first period of time, transitioning the power supply to a continuous DC current delivery for a second period of time. The methods may include plating a second amount of metal on the substrate.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 17 / 079,127, entitled "ELECTROPLATING SEED LAYER BUILDUP AND REPAIR," filed October 23, 2020, which is incorporated herein by reference in its entirety.

[0002] The present technology relates to electroplating operations in semiconductor processing, and more particularly to systems and methods for performing seed layer build-up in electroplating systems. [Background technology]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on a substrate surface. After forming, etching, and other processing on the substrate, metal or other conductive materials are often deposited or formed to make electrical connections between components. Because this metallization can occur after many manufacturing steps, problems caused during metallization can result in the scrapping of expensive substrates or wafers.

[0004] Electroplating occurs in an electroplating chamber, with the target side of the wafer immersed in a bath of liquid electrolyte and electrical contacts on a contact ring in contact with a conductive layer, such as a seed layer, on the wafer surface. Electrical current flows from a power source through the electrolyte and the conductive layer. Metal ions in the electrolyte precipitate on the wafer, producing a metal layer on the wafer. If the wafer has non-planar features defined across its surface, the seed layer may be incomplete or may be characterized by thickness variations along the wafer features. These variations can pose challenges to electroplating operations that benefit from a uniformly thick and sufficiently conductive seed layer. Plating onto a seed layer with thin or missing metal can result in voids or an uneven plated layer.

[0005] Therefore, there is a need for improved systems and methods that can be used to fabricate high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0006] An exemplary method of electroplating can include supplying a current from a power supply through a plating bath in an electroplating chamber for a first period of time. The supplied current can be or can include a pulsed current with a duty cycle of about 50% or less. The method can include plating a first amount of metal onto a substrate in the plating bath. The substrate can define vias therein. Following the first period of time, the method can include transitioning the power supply to a continuous DC current supply for a second period of time. The method can include plating a second amount of metal onto the substrate.

[0007] In some embodiments, the current supplied during the first period is characterized by an operating frequency of about 1,000 Hz or less. The average current density during the first period is about 3 mA / cm. 2 The average current density during the second time period may be equal to or less than the average current density during the first time period. The peak current during the second time period may be equal to or less than about 2 amperes. The peak current during the first time period may be equal to or greater than about 2 amperes. The average current density may increase over time during the second time period. The via defined in the substrate may be characterized by a depth of equal to or greater than about 10 μm. A barrier layer may be formed along the walls of the via defined in the substrate. The barrier layer may be or include one or more of tantalum or titanium, and the deposited metal may be or include copper.

[0008] Some embodiments of the present technology may include a method of electroplating. The method may include supplying a current from a power supply through a plating bath in an electroplating chamber for a first period of time. The power supply may be operated with a pulsed DC supply at a frequency of about 750 Hz or less during the first period of time. The method may include plating a first amount of copper onto a substrate in the plating bath. Following the first period of time, the method may include transitioning the power supply to a continuous DC current supply for a second period of time. The method may include plating a second amount of copper onto the substrate.

[0009] In some embodiments, the on-time during the first period of each pulse may be approximately 100 ms or less. During the first period, the power supply may be operated at a duty cycle of approximately 20% or less. The average current density during the first period may be less than the average current density during the second period. The peak current density during the first period may be greater than the peak current density during the second period. The peak current density during the first period may be greater than, or approximately twice, the peak current density during the second period. The substrate may define a via characterized by a depth-to-width ratio of approximately 10 or greater. The via may be lined with a barrier layer and a copper seed layer. During the second period, the average current density may be increased in a series of plating operations.

[0010] Some embodiments of the present technology may include a method of electroplating. The method may include supplying a current from a power supply through a plating bath in an electroplating chamber for a first period of time. The power supply may be operated with a pulsed DC supply at a frequency of about 1000 Hz or less with a duty cycle of about 50% or less during the first period of time. The method may include plating a first amount of copper on a substrate in the plating bath. The substrate may define vias lined with a barrier layer and a copper seed layer. The plated first amount of copper may be characterized by a thickness of about 500 nm or less. Following the first period of time, the method may include transitioning the power supply to a continuous DC current supply for a second period of time longer than the first period of time. The average current density during the second period of time may be greater than the average current density during the first period of time. The method may include plating the second amount of copper on the substrate.

[0011] Such techniques can offer numerous advantages over conventional techniques. For example, the techniques can enhance seed layer coverage prior to electroplating operations, thereby improving plating uniformity. Additionally, the techniques can be performed within the plating chamber where electroplating occurs, which can improve throughput compared to other techniques that attempt seed layer repair within a separate processing chamber. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed embodiments may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a schematic perspective view of an electroplating system in accordance with some embodiments of the present technique; [Figure 2] 1 is a partial cross-sectional view of an electroplating system in accordance with some embodiments of the present technique; [Figure 3] 1 is an exemplary operation in a method of electroplating according to some embodiments of the present technique. [Figure 4A] 1 is a schematic cross-sectional view of a substrate during seed layer construction, in accordance with some embodiments of the present technique; [Figure 4B] 1 is a schematic cross-sectional view of a substrate during seed layer construction, in accordance with some embodiments of the present technique; DETAILED DESCRIPTION OF THE INVENTION

[0014] Some of the figures are included as schematic diagrams. It is understood that the figures are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Additionally, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0015] In the figures, similar components and / or features may have the same reference numeral label. Furthermore, various components of the same type may be distinguished by following the reference label with a letter that distinguishes between the similar components and / or features. When only a first numeric reference label is used herein, the description is applicable to any one of the similar components and / or features having the same first numeric reference label, regardless of the letter suffix.

[0016] Various operations in semiconductor manufacturing and processing are performed to create a vast amount of features across a substrate. As layers of semiconductor are formed, vias, trenches, and other pathways are created within the structure. These features are then filled with conductive or metallic materials that allow electrical current to travel from layer to layer through the device.

[0017] Electroplating operations may be performed to provide conductive material within vias and other features on a substrate. Electroplating utilizes an electrolyte bath containing ions of the conductive material to electrochemically deposit the conductive material onto the substrate and within features defined thereon. The substrate onto which the metal is plated acts as the cathode. Electrical contacts, such as rings or pins, may allow current to flow through the system. During electroplating, the substrate may be clamped to a head and immersed in an electroplating bath to form the metallization. In the systems described below, the substrate may also be chucked within a seal that may be coupled with the head during processing.

[0018] The provided substrate may include a barrier layer formed along a feature, such as along the sidewalls and bottom of a via, and may include a metal seed layer. The seed layer may provide a conductive path that promotes nucleation for metal ions to precipitate from solution. Formation of the seed layer may be performed by physical vapor deposition, which may be plasma-enhanced or other methods, and may depend at least in part on line-of-sight access within the feature. For example, when vias are formed in the substrate and are characterized by a high aspect ratio, forming a conformal seed layer may be challenging, especially in the lower sidewall and corner regions of the feature. In this case, these regions may be characterized by extremely thin seed layer coverage, even if they do not expose the barrier layer. During subsequent electroplating, these regions may not be able to adequately conduct current at the plating current density, and voids may form within the feature, which may increase impedance or prevent a conductive path through the feature.

[0019] Conventional techniques have struggled with repairing seed layers within high-aspect-ratio features. For example, to ensure continuous coverage along the sidewalls, the seed layer may be formed to a greater thickness during physical vapor deposition. However, increased coverage across the neck of the feature and the entire top surface of the wafer can pinch off the feature or limit access for plating fluids, further limiting plating. Conventional repair techniques may attempt to perform currentless processes in an attempt to create favorable surface conditions in areas along the feature for deposit formation. However, these processes typically require additional processing chambers to perform the repair, and because material adhesion may be poor, a subsequent annealing operation may be required before electroplating. This can further reduce throughput, even if the repair can be performed.

[0020] The present technology overcomes these problems by incorporating seed layer buildup or repair within the electroplating chamber in a process operation that can occur prior to electroplating. The system can utilize high-power pulses to overcome conductivity limitations across the surface of a substrate feature, thereby producing sufficient seed layer thickness in all areas of the substrate. Because current density can be more uniform across the feature surface, subsequent plating can occur to uniformly fill the feature. After describing an exemplary chamber system in which embodiments of the present technology can be implemented, the remainder of the disclosure will discuss system and process aspects of the present technology.

[0021] FIG. 1 shows a schematic perspective view of an electroplating system 100 in which methods and cleaning systems according to embodiments of the present technology can be utilized and implemented. The electroplating system 100 illustrates an exemplary electroplating system including a system head 110 and a bowl 115. During an electroplating operation, a wafer may be clamped to the system head 110, inverted, and extended into the bowl 115 for electroplating. The electroplating system 100 may include a head lifter 120, which may be configured to lift and rotate the head 115 or otherwise position the head within the system, including tilting operations. The head and bowl may be part of a larger system incorporating multiple electroplating systems 100 and may be mounted on a deck plate 125 or other structure that may share electrolyte and other materials. A rotor may enable a substrate clamped to the head to rotate within or outside the bowl in different operations. The rotor may include a contact ring that can provide conductive contact with the substrate. A seal 130, discussed further below, may be connected to the head. The seal 130 can contain a chucked wafer to be processed. Figure 1 shows an electroplating chamber that can include components that are cleaned directly on the platform. An exemplary in situ rinse system 135 is also shown with the system 100, although it should be understood that other configurations are possible, including a platform that moves the head to an additional module to perform cleaning of the seal or other components.

[0022] Referring to FIG. 2 , a partial cross-sectional view of a chamber including aspects of an electroplating apparatus 200 in accordance with some embodiments of the present technology is shown. The electroplating apparatus 200 may be incorporated into an electroplating system, including the system 20 described above. As shown in FIG. 2 , a plating bath vessel 205 of the electroplating system is shown with a head 210 to which a substrate 215 is coupled. In some embodiments, the substrate may be coupled with a seal 212 integrated on the head. A rinse frame 220 may be coupled above the plating bath vessel 205 and configured to receive the head within the vessel during plating. The rinse frame 220 may include a rim 225 extending circumferentially around the top surface of the plating bath vessel 205. A rinse channel 227 may be defined between the rim 225 and the top surface of the plating bath vessel 205. For example, the rim 225 may include an interior sidewall 230 characterized by a sloped profile. As described above, rinsing fluid shaken off the substrate may contact the sidewalls 230 and may be received in a plenum 235 extending around the rim for collecting rinsing fluid from the electroplating apparatus 200.

[0023] The electroplating apparatus 200, in some embodiments, can further include one or more cleaning components. These components can include one or more nozzles used to deliver fluid to or toward the substrate 215 or head 210. Figure 2 illustrates various embodiments in which an improved rinse assembly can be used to protect the bath and substrate during a rinse operation. In some embodiments, a side rinse nozzle 250 extends through the rim 225 of the rinse frame 220 and may be oriented to rinse the seal 212 as well as the sides of the substrate 215.

[0024] The aforementioned chambers or systems can be used in performing exemplary methods, including electroplating methods. Referring to FIG. 3 , exemplary operations in a method 300 according to an embodiment of the present technology are shown. Method 300 can include one or more operations prior to the start of the method, including front-end processing, deposition, gate formation, etching, polishing, cleaning, or any other operations that may occur before the described operations. The method may include several optional operations that may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many of the operations are described to provide a broader scope of processes that may be performed, but are not critical to the present technology or may be performed by alternative methodologies, as discussed further below. Method 300 can describe operations shown generally in FIGS. 4A-4B , which illustrations will be described in conjunction with the operations of method 300. It should be understood that the figures are only partial schematic views, and that the substrate may include any number of additional materials and features having various properties and aspects as shown in the figures.

[0025] Method 300 may or may not include optional operations to tailor the semiconductor structure to a specific manufacturing process. It should be understood that method 300 may be performed on any number of semiconductor structures or substrates 405, including the exemplary structure capable of performing an electroplating operation, as shown in FIG. 4A . The exemplary semiconductor structure may include trenches, vias, or other recessed features that may include one or more materials. For example, the exemplary substrate may include silicon, silicon oxide, or some other semiconductor substrate material, as well as an interlayer dielectric material in which the recesses, trenches, vias, or insulating structures may be formed. In some embodiments, the exemplary substrate may include a barrier layer 410, such as tantalum, tantalum nitride, titanium, or any other barrier material, including any refractory material, that can limit the diffusion of the fill material or its interaction with the underlying substrate. The barrier layer may also facilitate deposition of a seed layer 415, in some embodiments, and the barrier layer may also be or include an adhesion layer to facilitate the formation of the seed layer. The seed layer 415 may include any metal or conductive material, such as copper. Although the remainder of the disclosure will discuss copper electroplating operations, it should be understood that additional materials may also be plated utilizing embodiments of the present technology.

[0026] As previously described, the seed layer 415 may be formed by physical vapor deposition, and the process performed can provide limited coverage along certain areas of the via, such as the bottom corners or sidewalls adjacent to the bottom of the trench. The deposition can be performed for longer periods of time, which, while not preventing access to the trench for the electroplating fluid, can cause pinch-off at the top of the trench, making electrodeposition difficult. It should be understood that the aforementioned structures are not intended to be limiting, and any of a variety of other semiconductor structures incorporating seed layer materials are equally encompassed. Other exemplary structures may include two-dimensional and three-dimensional structures common in semiconductor manufacturing, and the present technique can build or repair seed layers in any number of structures, thereby forming vias or features within the structures and depositing seed layers along the vias or features. Additionally, while high aspect ratio structures can benefit from the present technique, the technique may be equally applicable to lower aspect ratios and any other structures.

[0027] For example, features according to the present technology may be characterized by any aspect ratio or depth-to-width ratio of the structure, although in some embodiments, materials may be characterized by larger aspect ratios where sufficient seed layer coverage throughout the feature may be a challenge. For example, in some embodiments, the aspect ratio of any via or feature of the exemplary structure may be about 10:1 or greater, about 20:1 or greater, about 30:1 or greater, about 40:1 or greater, about 50:1 or greater, or greater. Additionally, each feature may be characterized by a reduced width or diameter at the neck or opening of the feature, such as about 10 μm or less, about 8 μm or less, about 6 μm or less, about 5 μm or less, about 4 μm or less, about 3 μm or less, about 2 μm or less, about 1 μm or less, or less. This combination of high aspect ratio and minimal width can cause many conventional seed layer deposition operations to fail, which can lead to void formation or incomplete filling in subsequent electroplating operations. By utilizing processes according to embodiments of the present technique, seed layers along features of virtually any aspect ratio can be built or repaired prior to additional electroplating operations.

[0028] Method 300 can be performed in an electroplating system, such as those described above, which can include a substrate that has already been processed to a certain extent. For example, any number of processing operations can be performed to fabricate any number of semiconductor structures before the substrate features are immersed in a plating bath. Vias, such as through-silicon vias or any other high-aspect-ratio features, can be formed through the substrate. A liner, such as liner 410, can be formed along the feature or conformally formed using any number of processes or techniques. A seed layer 415 can be formed, which, as shown, can be characterized by incomplete or uneven coverage across the entire surface of the feature. It should be understood that the illustrations are included for illustrative purposes only and should not be considered to scale. For example, gaps can appear in the seed layer coverage or minimum thicknesses can appear in certain areas, which can be characterized by thicknesses of tens of angstroms or less. If left unprocessed, these minimum coverage areas can cause voids to appear during the fill process.

[0029] This technique can build or repair a seed layer in the electroplating chamber itself. After performing a wetting process, such as a vacuum prewet, across the substrate's features, the substrate can be clamped in the electroplating system and placed in a plating bath, as previously described. The plating bath can be an acid bath containing copper or other metal ions for plating, and any number of additional materials can be included in the bath. For example, levelers, suppressors, accelerators, or any other materials can be included in the plating bath to facilitate the plating operation. The method can also include an optional dwell time in the plating bath before performing the above operations of method 300, which can allow diffusion of bath materials within the feature. As explained above, attempting to increase the seed layer using additional physical vapor deposition can pinch off the neck of the feature due to continued deposition. However, this technique can utilize accelerators and suppressors in the plating bath during the method. Low-mobility suppressors can limit plating along the outer surface of the substrate and the neck of the feature, allowing high-mobility accelerators to fully penetrate the feature and promote repair. Therefore, the technique may not be limited by the same line-of-sight or pinch-off problems as continuous physical vapor deposition.

[0030] Typical electroplating can be performed by applying a DC current at a specific average current density, typically about 3.0 mA / cm. 2 Below, approximately 2.5mA / cm 2 Below, approximately 2.0mA / cm 2 Below, approximately 1.5mA / cm 2 Below, approximately 1.0mA / cm 2 Below, approximately 0.5mA / cm 2The current density may be kept relatively low, such as at or below 1000 kJ / cm2. Maintaining a low current density controls plating growth to limit or prevent dendrite formation and ensures that the additive can function within its nominal current window. Because direct current can be utilized, the peak current may be substantially below the average current density. However, this low-current process can result in insufficient conductivity along areas of low seed coverage, which can cause several problems. For example, plating may not occur in these areas, and current may be unevenly distributed to adjacent areas, which can affect the plating in these areas as well as the functionality of the additive. This can result in voids, which can grow and close as plating continues. The present technique can perform a repair process that can overcome the conductivity limitations associated with insufficient seed layer coverage.

[0031] In operation 305, an electroplating operation can be performed by pulsing a DC power supply that provides a pulsed current to the process chamber and plating bath. The power supply can thus operate without pulse reversal, thus operating in a forward direction throughout the entire operation, ensuring plating and not de-plating. Pulsing may be performed at a frequency and duty cycle that increases the peak current density during the power supply on-time. While operating a continuous DC power supply at higher power can result in uneven plating that leads to dendrite growth, this technique can limit high-power operation to create starting conditions that can overcome low-conductivity regions caused by poor seed layer coverage or voids. This can be done by utilizing an average current density that is maintained similar to or lower than that of standard electroplating operations.

[0032] For example, the DC power source may be pulsed at a pulse frequency of about 1 Hz or greater, or at frequencies of about 10 Hz or greater, about 50 Hz or greater, about 100 Hz or greater, about 250 Hz or greater, about 500 Hz or greater, about 750 Hz or greater, about 1000 Hz or greater, or even higher. However, as the pulse frequency increases, the plating operation may become too similar to the operation of a continuous DC power source, which may result in excessive plating during each on-time operation and lead to dendrite formation. Therefore, in some embodiments, the power source may be pulsed at about 1000 Hz or less, about 900 Hz or less, about 800 Hz or less, about 700 Hz or less, or less. Additionally, the duty cycle may be adjusted to shorten the on-time of the power source. For example, in some embodiments, the duty cycle may be maintained at about 10% or greater, about 15% or greater, about 20% or greater, about 25% or greater, about 30% or greater, about 35% or greater, about 40% or greater, about 45% or greater, about 50% or greater, about 55% or greater, about 60% or greater, about 65% or greater, about 70% or greater, about 75% or greater, or greater. Again, as the duty cycle increases and the power supply begins to closely resemble continuous DC operation, ions adjacent to the seed layer may precipitate rapidly, causing dendrite formation. Thus, in some embodiments, the duty cycle may be maintained at about 80% or less, about 70% or less, about 60% or less, about 50% or less, or less.

[0033] By operating the power supply in a low duty cycle pulsed state, the peak current density can be increased while maintaining a low enough average current density to control plating from the bath. For example, during operation 305, the average current density may be about 2.0 mA / cm. 2 It may be maintained at or below approximately 1.5 mA / cm 2 Below, approximately 1.0mA / cm 2 Below, approximately 0.5mA / cm 2However, the peak current during on-time operation may be about 0.5 A or greater, and may be about 1.0 A or greater, about 1.5 A or greater, about 2.0 A or greater, about 2.5 A or greater, about 3.0 A or greater, about 3.5 A or greater, about 4.0 A or greater, about 4.5 A or greater, about 5.0 A or greater, or greater. Additionally, the peak current density may be about 2 mA / cm 2 It may be more than about 5mA / cm 2 or more, about 10mA / cm 2 Above, about 20mA / cm 2 Above, about 50mA / cm 2 Although this high density can cause problems during continuous power operation as discussed above, in some embodiments of the present technology, the on-time may be kept to about 500 ms or less, about 250 ms or less, about 100 ms or less, about 50 ms or less, about 25 ms or less, about 10 ms or less, about 5 ms or less, about 1 ms or less, or even less, to ensure controlled plating without dendrite growth.

[0034] Operation 305 may be performed for a first period of time during which a first amount of plating may occur in operation 310. The first period of time may be any amount of time to produce sufficient coverage, such as about 2 minutes or more, about 5 minutes or more, about 10 minutes or more, or more. Plating may be limited to about 500 nm or less, about 250 nm or less, about 200 nm or less, about 150 nm or less, about 100 nm or less, or less, to ensure sufficient coverage across the entire surface of the feature to be plated. It should be understood that operation times and coverage may vary depending on the aspect of the feature and the amount of build being performed. While formation may be uniform, in some embodiments, because the process occurs in a plating bath, coverage may occur preferentially in areas distal to the wafer's surface, which may also be an issue of insufficient pre-seeding. This may occur because suppressor additives can limit deposition at the neck of the feature, while accelerator additives can promote further deposition into the feature. As a result, this operation can advantageously limit pinching at the neck of the feature to be filled, thus improving coverage along the bottom and corner regions of the feature while controlling formation at the entrance or neck of the feature, as shown in FIG.

[0035] After the pulsed operation is completed, in operation 315, the power supply can be switched to a continuous DC current supply, which may occur for a second period of time during which a second amount of metal can be plated in operation 320. Thus, while pulsing is no longer occurring, the average current density may be maintained or slightly increased, which may prevent excessive deposition during the transition from pulsed to continuous operation. In some embodiments, the average current density during the second operation may be greater than or approximately the same as the average current density during the first period, such as during pulsed operation. However, the peak current or peak current density may be maintained less than the peak current or peak current density during the first period. Thus, while the peak current may exceed 2 A or more during the first period, the peak current may be maintained at 2 A or less during the second period, and may be maintained at about 1.5 A or less, about 1.0 A or less, about 0.5 A or less, or less during the second period. This may allow plating to occur uniformly throughout the feature, which may limit or prevent void formation.

[0036] The second period may also vary depending on the aspects of the feature being filled, and in some embodiments, the second period may be greater than the first period. Additionally, in some embodiments, the second period may include several subperiods during which the current or average current density may be increased as equilibrium is achieved in plating and growth through the feature may increase as the feature is filled. For example, any number of increase steps, each capable of increasing the average current density, may be performed in optional operation 325. Each period may be any of the periods previously described, and each period may, in some embodiments, be the same or different. Similarly, the current increase may be a linear increase in each subperiod, or each increase may be greater or less than any previous increase in current or current density. In some embodiments, during each subperiod, the average current density may be equal to or greater than the average current density during the first period. Additionally, the peak current or peak current density may be less than the peak current or peak current density during the first period. Performing a pulsed operation according to embodiments of the present technology can ensure improved seed layer coverage, which may improve via or feature filling operations while limiting or preventing void formation.

[0037] In the preceding description, for purposes of explanation, numerous details are set forth to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details. For example, other substrates that may benefit from the wetting techniques described may also be used with the present technology.

[0038] Although some embodiments have been disclosed, it will be recognized by those skilled in the art that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the above description should not be construed as limiting the scope of the technology.

[0039] Where a range of values is provided, unless the context clearly indicates otherwise, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated or unstated intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may or may not independently be included within the range, and each range in which either limit, neither limit, or both limits are included within the smaller range is also encompassed within the scope of the technology, subject to any specifically excluded limits within the stated range. Where a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included. Where multiple values are provided in a list, any range including or based on any of those values is likewise specifically disclosed.

[0040] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, a reference to "a material" includes a plurality of such materials, a reference to "the period of time" includes a reference to one or more periods and equivalents thereof known to those skilled in the art, and so forth.

[0041] Additionally, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and the claims that follow, are intended to specify the presence of stated features, integers, components, or operations, but they do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. supplying a current from a power supply through a plating bath in an electroplating chamber for a first period of time, the supplied current comprising a pulsed current having a duty cycle of about 50% or less; plating a first amount of metal onto a substrate in the plating bath, the substrate defining a via therein; transitioning the power supply to a continuous DC current supply for a second time period following the first time period; plating a second amount of metal onto the substrate; A method of electroplating comprising:

2. 10. The electroplating method of claim 1, wherein the current supplied during the first period is characterized by an operating frequency of less than or equal to about 1,000 Hz.

3. The average current density during the first period is about 3 mA / cm 2 2. The electroplating method of claim 1, wherein:

4. 4. The electroplating method of claim 3, wherein the average current density during said second period is equal to or greater than said average current density during said first period.

5. 5. The electroplating method of claim 4, wherein the peak current during the second period is less than or equal to about 2 amps.

6. 6. The electroplating method of claim 5, wherein the peak current during the first period is greater than or equal to about 2 amps.

7. 10. The electroplating method of claim 1, wherein the average current density increases over time during said second period of time.

8. 10. The electroplating method of claim 1, wherein the vias defined in the substrate are characterized by a depth of about 10 μm or greater.

9. a barrier layer formed along the walls of the via defined in the substrate; The electroplating method of claim 1 further comprising:

10. 10. The electroplating method of claim 9, wherein the barrier layer comprises one or more of tantalum or titanium, and the deposited metal comprises copper.

11. supplying a current from a power supply through a plating bath in an electroplating chamber for a first period of time, the power supply operating with a pulsed DC supply at a frequency of about 750 Hz or less during the first period of time; plating a first amount of copper onto a substrate in the plating bath; transitioning the power supply to a continuous DC current supply for a second time period following the first time period; plating a second amount of copper onto the substrate; A method of electroplating comprising:

12. 12. The electroplating method of claim 11, wherein the on-time during the first period of each pulse is about 100 ms or less.

13. 12. The electroplating method of claim 11, wherein during the first period of time, the power supply operates at a duty cycle of about 20% or less.

14. 12. The electroplating method of claim 11, wherein the average current density during the first period is less than the average current density during the second period.

15. 12. The electroplating method of claim 11, wherein a peak current density during the first period of time is greater than a peak current density during the second period of time.

16. 16. The electroplating method of claim 15, wherein the peak current density during the first period of time is greater than or equal to about twice the peak current density during the second period of time.

17. 12. The electroplating method of claim 11, wherein the substrate defines vias characterized by a depth-to-width ratio of about 10 or greater.

18. The electroplating method of claim 11 , wherein the via is lined with a barrier layer and a copper seed layer.

19. 12. The electroplating method of claim 11, wherein during the second period, the average current density is increased in the series of plating operations.

20. supplying current from a power supply through a plating bath in an electroplating chamber for a first period of time, the power supply operating during the first period as a pulsed DC supply at a frequency of about 1000 Hz or less with a duty cycle of about 50% or less; plating a first amount of copper onto a substrate in the plating bath, the substrate defining a via lined with a barrier layer and a copper seed layer, the plated first amount of copper being characterized by a thickness of about 500 nm or less; transitioning the power supply to a continuous DC current supply for a second time period subsequent to the first time period, the second time period being longer than the first time period, wherein an average current density during the second time period is greater than an average current density during the first time period; plating a second amount of copper onto the substrate; A method of electroplating comprising:

Images