Generation method, search method, and generation device

Abstract

To provide a method of generating index information that enables a search operation with a reduced memory usage amount, a search method using the index information, and a generation device.SOLUTION: A generation method includes setting and writing. The setting is to set, as a second node, one of multiple first nodes corresponding to multiple first vectors included in a search range. The writing is to write an information piece that includes: a second vector; and an ID and a third vector being a vector corresponding to a third node, for each of one or more third nodes being out-neighbor nodes of the second node. The second vector is the first vector corresponding to the second node out of the multiple first vectors. The information piece is an element related to the second node out of index information corresponding to a directed graph.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present embodiment relates to a generation method, a search method, and a generation device. [Background technology]

[0002] One known graph-based approximate nearest neighbor search algorithm is DiskANN (Disk-based Approximate Nearest Neighbor search). According to DiskANN, a directed graph is created by regarding each multidimensional vector in the group of multidimensional vectors that constitute the search range as a node, and index information generated based on the structure of this directed graph is stored in a storage device. Then, a search operation is performed along the directed graph based on the index information in the storage device. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Suhas Jayaram Subramanya, Devvrit, Rohan Kadekodi, Ravishankar Krishaswamy, and Harsha Vardhan Simhadri, “DiskANN: Fast Accurate Billion-point Nearest Neighbor Search on a Single Node”, [online], November 2019, NeurIPS, [retrieved on 2022-12-11], retrieved from the Internet:<URL: https: / / suhasjs.github.io / files / diskann_neurips19.pdf> Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a method for generating index information that enables search operations with low memory usage, a search method using the index information, and a generation device. [Means for solving the problem]

[0005] According to one embodiment, a generation method is performed by a processor configured to process data represented by a directed graph. The generation method includes setting and writing. The setting step is to set one of a plurality of first nodes corresponding to a plurality of first vectors included in a search range as a second node. The plurality of first nodes are a plurality of nodes included in the directed graph, each of which is assigned an ID. The writing step is to write an information piece including the second vector and a third vector, which is a vector corresponding to each of one or more third nodes and the ID and the third node. The second vector is a first vector corresponding to the second node of the plurality of first vectors. The one or more third nodes are all out-adjacent nodes of the second node of the plurality of first nodes. The information piece is an element of index information corresponding to the second node of the directed graph. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic diagram illustrating an example of a configuration of a search device according to an embodiment. [Figure 2] 3A and 3B are diagrams for explaining the configuration of a directed graph and index information according to the embodiment; [Figure 3] 3A and 3B are schematic diagrams illustrating an example of information stored in an SSD and a DRAM when a search device according to an embodiment executes a search. [Figure 4] FIG. 1 is a schematic diagram illustrating an example of the configuration of a generating device according to an embodiment. [Figure 5] FIG. 2 is a schematic diagram illustrating an example of functions implemented by a processor included in the generating device according to the embodiment. [Figure 6] 10 is a flowchart illustrating an example of an operation of the generating device according to the embodiment. [Figure 7] FIG. 2 is a schematic diagram illustrating an example of functions implemented by a processor included in the search device of the embodiment. [Figure 8] 10 is a flowchart illustrating an example of an operation of the searching device according to the embodiment. [Figure 9] FIG. 10 is a diagram showing an example of the configuration of node information according to the first modification. [Figure 10] FIG. 10 is a diagram showing an example of the configuration of node information according to Modification 2. DETAILED DESCRIPTION OF THE INVENTION

[0007] A generating method, a searching method, and a generating device according to embodiments will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0008] (Embodiment) First, an example of an apparatus (referred to as a search apparatus) that executes a search method according to an embodiment will be described. Fig. 1 is a schematic diagram illustrating an example of the configuration of the search apparatus according to an embodiment.

[0009] 1, the searching device 2 includes a processor 21, an interface 22, a solid state drive (SSD) 23, a dynamic random access memory (DRAM) 24, and a bus 25. The processor 21, the interface 22, the SSD 23, and the DRAM 24 are electrically connected to the bus 25.

[0010] The interface 22 is a device for inputting and outputting information to the search device 2. The interface 22 includes an interface for communication via a network, an interface to which a storage device can be connected, an interface to which an input device such as a keyboard can be connected, etc. The search device 2 can accept query input via the interface.

[0011] The SSD 23 is a large-capacity nonvolatile memory device that functions as a storage device in the searching device 2. The SSD 23 includes a NAND flash memory as a storage device. Note that storage devices applicable to the searching device 2 are not limited to SSDs. The searching device 2 may include a magnetic disk device as a storage device. An example of a magnetic disk device is an HDD (Hard Disk Drive).

[0012] The DRAM 24 is a memory that operates faster than a storage device. The DRAM 24 functions as a cache area, a buffer area, a work area, etc. Note that the memory that can be applied to the search device 2 and operates faster than a storage device is not limited to DRAM.

[0013] The processor 21 is an arithmetic device capable of executing a computer program and realizes functions defined by the computer program. The processor 21 is, for example, a CPU (Central Processing Unit). Note that one or more processors 21 may be provided depending on the functions to be realized. In the search device 2, the processor 21 executes a search operation in accordance with DiskANN based on a search program (search program SPG, described below). The search program SPG is stored, for example, in the SSD 23 or a device external to the search device 2. The processor 21 loads the search program SPG from the SSD 23 or a device external to the search device 2 into the DRAM 24 under an environment provided by the operating system. The processor 21 then executes the search program SPG loaded into the DRAM 24.

[0014] A search operation is an operation to identify data that is closest to a query among a group of data. Each data has N elements (where N is an integer greater than or equal to 1). In other words, each data is an N-dimensional vector. Each data is an image, a document, or any other type of data, or data generated from these. In one example, each data is N features extracted from an image. The number of elements N is the same for all data and queries described below. Hereinafter, data will be referred to as a vector or a full-precision vector. Furthermore, a group of data (i.e., vectors) that constitute the search range will be referred to as a vector set.

[0015] For the vector set, a directed graph is generated in advance in which each vector constituting the vector set is regarded as a node. In the search operation, the processor 21 searches for a vector that is closest to the query along the directed graph.

[0016] A technology compared with the embodiment will be described. The technology compared with the embodiment will be referred to as a comparative example. According to the comparative example, a compressed vector is generated for each vector included in a vector set, and compressed vectors for all vectors included in the vector set are stored in DRAM. In other words, a set of compressed vectors corresponding to the vector set is stored in DRAM. The configuration of a directed graph generated from the vector set is recorded in index information. A search path is selected node by node according to the directed graph defined by the index information. Each time a search path is selected, a necessary compressed vector is selected from the compressed vectors for all vectors stored in DRAM, and the next search path is selected according to the result of a distance calculation using the selected compressed vector.

[0017] The comparative example described above allows for high-speed search operations, but requires a DRAM with a very large capacity, and the amount of DRAM used increases with the number of vectors in the search range.

[0018] In the embodiment, in order to reduce the amount of DRAM used, the compressed vectors required for distance calculation are recorded in the index information.

[0019] FIG. 2 is a diagram illustrating the configuration of the directed graph GF and the index information IDX according to the embodiment.

[0020] Each vector V included in the vector set is assigned a node ID (hereinafter simply referred to as NID). The method of assigning an NID to each vector V is not limited to a specific method. Hereinafter, a vector V (in other words, a node) to which x (where x is numerical information) is assigned as its node ID will be referred to as node NIDx.

[0021] FIG. 2 shows a directed graph GF generated from a vector set. In this example, an edge with node NID20 as its head, an edge with node NID7 as its head, an edge with node NID13 as its head, and an edge with node NID12 as its head are connected to node NID1. An edge with node NID3 as its head, an edge with node NID6 as its head, an edge with node NID15 as its head, and an edge with node NID11 as its head are connected to node NID20. An edge with node NID10 as its head, an edge with node NID19 as its head, an edge with node NID16 as its head, and an edge with node NID5 as its head are connected to node NID13. An edge with node NID8 as its head, an edge with node NID21 as its head, an edge with node NID4 as its head, and an edge with node NID2 as its head are connected to node NID13. To the node NID12, an edge with the node NID14 as its head, an edge with the node NID17 as its head, an edge with the node NID9 as its head, and an edge with the node NID18 as its head are connected.

[0022] If the nodes NIDA and NIDB are connected by an edge with the node NIDB as its head, the node NIDB is called an out-neighbor of the node NIDA. The number of neighboring nodes of the node NIDA is called the out-degree of the node NIDA. In this specification, an out-neighbor node is referred to as an adjacent node.

[0023] In the example shown in FIG. 2, the directed graph GF has a tree-like shape. The shape of the directed graph GF is not limited to a tree-like shape. Multiple nodes do not need to have a common out-degree. Multiple nodes may be connected in a circular fashion. Many nodes have an out-degree of 1 or more, but there may be nodes with an out-degree of 0. In the embodiment, for simplicity of explanation, a case will be described in which all nodes have an out-degree of 1 or more and all nodes have a common out-degree.

[0024] In the search operation, the processor 21 performs a calculation to search for a node closest to the query based on an arbitrary search algorithm in accordance with the directed graph GF defined by the index information IDX. Any algorithm, including greedy search and beam search, may be adopted as the calculation algorithm for the search. Briefly explaining an example, the processor 21 sequentially switches search target nodes, which are candidates for the node closest to the query, among multiple nodes along the directed graph GF. Each time the search target node is switched, the processor 21 calculates the distance between each adjacent node of the search target node and the query. The processor 21 then sets the node closest to the query among one or more adjacent nodes of one or more search target nodes currently close to the query as the next new search target node. The processor 21 sequentially switches search target nodes along the directed graph GF until it reaches a vector V estimated to be closest to the query. This process of switching search target nodes along the directed graph GF may be referred to as a "hop operation."

[0025] In this specification, distance is a measure of similarity between data (including vectors and queries). Mathematically, distance is, for example, Euclidean distance. Note that the mathematical definition of distance is not limited to Euclidean distance. Furthermore, the index used to evaluate distance is not limited to Euclidean distance, and any index corresponding to distance can be used.

[0026] The processor 21 refers to the index information IDX corresponding to the directed graph GF in order to identify each adjacent node of the search target node. That is, the index information IDX has a data structure that enables the structure of the directed graph GF to be derived.

[0027] The index information IDX is a set of node information. Each piece of node information is an information piece that is an element of the index information IDX. Each piece of node information corresponds one-to-one with one node. The index information IDX has a structure in which all the node information is arranged in the order of NID.

[0028] All node information has a common structure. As a representative of all node information, the structure of the node information of a certain node NIDi will be explained.

[0029] The node information of node NIDi includes a vector (i.e., a full-precision vector) of node NIDi. Furthermore, the node information of node NIDi includes the NIDs and compressed vectors for all adjacent nodes of node NIDi. The compressed vector is a vector generated from the full-precision vector assigned to node NIDi. If the out-degree of each node is denoted as R, the node information of node NIDi includes the NIDs and compressed vectors for each of the R adjacent nodes.

[0030] The compressed vector is generated by compressing the full-precision vector. The compression algorithm is not limited to a specific algorithm. In one example, product quantization is used as the compression algorithm.

[0031] FIG. 3 is a schematic diagram illustrating an example of information stored in the SSD 23 and the DRAM 24 when the searching device 2 of the embodiment executes a search.

[0032] The SSD 23 stores the index information IDX shown in FIG.

[0033] A search program SPG is loaded into the DRAM 24. The processor 21 executes a search operation in accordance with the search program SPG loaded into the DRAM 24.

[0034] In addition, the DRAM 24 is allocated a cache area 241, which is a storage area for temporarily storing information required for search operations.

[0035] The processor 21 executes a search operation under control according to the search program SPG. In the search operation, the processor 21 searches for a vector in the vector set that has the shortest distance to an externally input query.

[0036] As described above, the index information IDX has a configuration in which the compressed vectors of all adjacent nodes are recorded in each node information. The processor 21 reads one piece of node information for the node to be searched from the SSD 23 and stores it in the cache area 241 of the DRAM 24. The processor 21 then completes one hop operation based on the compressed vectors of all adjacent nodes included in the stored node information. The processor 21 repeats the hop operation to identify the vector with the shortest distance to the query.

[0037] As described above, according to the embodiment, the index information IDX has a configuration in which the compressed vectors of all adjacent nodes required for one hop operation are recorded in each node information. Therefore, it is not necessary to store compressed vectors for all vectors in the search range in the DRAM 24. This enables search operations with reduced memory usage.

[0038] When reading index information IDX under control according to the search program SPG, the processor 21 issues an IO request for reading from the SSD 23. Specifically, the storage area of the SSD 23 as viewed from the processor 21 under control according to the search program SPG is subdivided into multiple unit storage areas of a common size. An IO request is a request to access (read or write) a desired one of the multiple unit storage areas. In other words, a unit storage area can be considered a unit of access to the SSD 23. A unit storage area may be a page, block, cluster, or sector in a NAND flash memory, or may be something different from any of these. When the SSD 23 includes one or more flash memory dies, a unit storage area may be one page or a portion of a page included in a single flash memory die. When the SSD 23 includes multiple flash memory dies, a unit storage area may be a group of pages or a portion of each page included in two or more flash memory dies from which data can be read simultaneously or in parallel. If the searching device 2 is provided with an HDD instead of an SSD 23 as its storage device, a unit storage area may be a positionally contiguous data storage area within a single data track. One or multiple positionally contiguous data sectors within a single data track may be a unit storage area. Alternatively, a unit storage area may be multiple adjacent data tracks that can be linked together and from which data can be read. The processor 21 can obtain information stored in a target unit storage area of the index information IDX with a single IO request.

[0039] 2, in the embodiment, the index information IDX has a configuration in which only one piece of node information is stored in one unit storage area. With this configuration, only one piece of node information acquired with one IO request is stored in the cache area 241 of the DRAM 24. The processor 21 can acquire the node information required for the hop operation in the cache area 241 with one IO request, and can acquire only one piece of node information in the cache area 241, so that the efficiency of access to the SSD 23 is high and the amount of usage of the DRAM 24 can be reduced.

[0040] Next, a device (referred to as a generating device 1) that realizes the method for generating index information IDX will be described.

[0041] FIG. 4 is a schematic diagram illustrating an example of the configuration of the generating device 1 according to the embodiment.

[0042] The generation device 1 includes a processor 11, a first interface 12, a second interface 13, a DRAM 14, and a bus 15. The first interface 12, the processor 11, the DRAM 14, and the second interface 13 are electrically connected to the bus 15.

[0043] The first interface 12 is a circuit that receives data from an external device of the generation device 1. In this example, the first interface 12 is a device for communicating with an external device via the network 3. For example, the first interface 12 is an Ethernet TM adapter, or Wi-Fi TM adapters, etc.

[0044] The second interface 13 is a circuit that outputs data to an external device. In this example, the second interface 13 is an adapter for connecting to the storage device 4. The type of the storage device 4 is not limited to a specific type. The storage device 4 may be, for example, an SSD, an HDD, or a Universal Flash Storage (UFS).

[0045] The processor 11 is a computing device having a function of generating index information IDX. The processor 11 may be, for example, a CPU. When the processor 11 is a CPU, the processor 11 realizes the function of generating index information IDX by executing a predetermined program. Specifically, the processor 11 obtains a generation program GPG from a predetermined location and loads the obtained generation program GPG into the DRAM 14. The processor 11 then executes the search program SPG loaded into the DRAM 14. The processor 11 generates the index information IDX under control in accordance with the search program SPG. Note that one or more processors 11 may be provided depending on the functions to be realized.

[0046] 4, the generating device 1 receives data from an external device via the network 3 and the first interface 12, and outputs the data to the external device (here, the storage device 4) via the second interface 13. The data reception and output may be performed via the same interface. The generating device 1 may also include a storage device, and may acquire data from the storage device or output data to the storage device.

[0047] 4, the generating device 1 is a device different from the searching device 2. The searching device 2 may function as the generating device 1 by executing the generating program GPG in the searching device 2.

[0048] FIG. 5 is a schematic diagram showing an example of functions realized by the processor 11 included in the generating device 1 according to the embodiment.

[0049] The processor 11 functions as a target node setting unit 101 , an information acquisition unit 102 , a compressed vector acquisition unit 103 , a node information generation unit 104 , and a storage write unit 105 .

[0050] The processor 11 can obtain the directed graph GF and the vector set via the network 3 and the first interface 12 .

[0051] The target node setting unit 101 sets one node from the acquired directed graph GF as a target node. Index information IDX is generated by repeatedly executing a loop process that generates one piece of node information. The target node is a node that is temporarily set as a target for generating node information in one loop process.

[0052] The target node setting unit 101 transmits the NID of the target node to the information acquisition unit 102 .

[0053] When the information acquisition unit 102 recognizes the target node based on the NID received from the target node setting unit 101, it acquires the NIDs of all adjacent nodes of the target node from the directed graph GF. Then, the information acquisition unit 102 transmits the acquired NIDs of all adjacent nodes to the compressed vector acquisition unit 103 and the node information generation unit 104.

[0054] The information acquiring unit 102 also acquires the full-precision vector of the target node from the vector set, and transmits the acquired full-precision vector of the target node to the node information generating unit 104.

[0055] The compressed vector acquisition unit 103 acquires full-precision vectors of adjacent nodes from the vector set and compresses the acquired full-precision vectors. As described above, the compression algorithm is not limited to a specific algorithm. The compressed vector acquisition unit 103 acquires compressed vectors for all adjacent nodes of the target node and transmits the acquired compressed vectors of all adjacent nodes to the node information generation unit 104.

[0056] Note that the generation of the compressed vector does not necessarily have to be performed by the compressed vector acquisition unit 103. A compressed vector may be prepared in advance for each full-precision vector included in the vector set, and the compressed vector acquisition unit 103 may acquire the compressed vector via the network 3 and the first interface 12.

[0057] The node information generation unit 104 generates node information for the target node, including the full-precision vector of the target node, the NIDs of all adjacent nodes of the target node, and the compressed vectors of all adjacent nodes of the target node. The node information generation unit 104 transmits the generated node information for the target node to the storage write unit 105.

[0058] The storage write unit 105 writes the node information of the target node to the storage device 4 via the second interface 13. The storage write unit 105 writes the node information of the target node to an area in a storage device (for example, the SSD 23 of the searching device 2) corresponding to a unit storage area of the storage destination. More specifically, the storage device 4 is provided with a plurality of areas, each corresponding to a different unit storage area. The storage write unit 105 writes the node information of a different node to each of the plurality of areas, thereby completing index information IDX in the storage device 4. According to the index information IDX written in this way, when the index information IDX is transferred to the SSD 23, each piece of node information is stored in a different unit storage area.

[0059] In addition, some or all of the target node setting unit 101, information acquisition unit 102, compressed vector acquisition unit 103, node information generation unit 104, and storage write unit 105 may be realized by hardware circuits such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0060] FIG. 6 is a flowchart showing an example of the operation of the generating device 1 according to the embodiment.

[0061] First, the target node setting unit 101 sets one node as a target node based on the directed graph GF (S101). The method for setting the target node is not limited to a specific method. For example, the target node setting unit 101 may set the target nodes in order of NID.

[0062] The information acquisition unit 102 acquires the NID of the target node, the NIDs of all adjacent nodes of the target node, and a full-precision vector of the target node (S102). The information acquisition unit 102 recognizes the target node by receiving the NID of the target node from the target node setting unit 101. The information acquisition unit 102 acquires the NIDs of all adjacent nodes of the target node from the directed graph GF. The information acquisition unit 102 acquires the full-precision vector of the target node from the vector set.

[0063] The information acquiring unit 102 may acquire the NIDs of all adjacent nodes of the target node via the network 3 and the first interface 12. Alternatively, the directed graph GF may be transferred to the DRAM 14 via the network 3 and the first interface 12, and then the information acquiring unit 102 may acquire the NIDs of all adjacent nodes of the target node from the directed graph GF stored in the DRAM 14.

[0064] Similarly, the information acquiring unit 102 may acquire the full-precision vector of the target node via the network 3 and the first interface 12. Alternatively, the vector set may be transferred to the DRAM 14 via the network 3 and the first interface 12, and then the information acquiring unit 102 may acquire the full-precision vector of the target node from the vector set stored in the DRAM 14.

[0065] The compressed vector acquisition unit 103 acquires compressed vectors of all adjacent nodes of the target node based on the NIDs of all adjacent nodes of the target node (S103).

[0066] The node information generation unit 104 generates node information of the target node (S104). The node information generation unit 104 generates, as the node information of the target node, an information piece including the full precision vector of the target node, the NIDs of all adjacent nodes of the target node, and the compressed vectors of all adjacent nodes of the target node.

[0067] The storage write unit 105 writes the generated node information of the target node to an area in a storage device (for example, the SSD 23 of the searching device 2) that corresponds to the unit storage area of the storage destination (S105).

[0068] The target node setting unit 101 determines whether or not there is a node that has never been set as a target node among the multiple nodes included in the directed graph GF (S106). If there is a node that has never been set as a target node (S106: Yes), the target node setting unit 101 sets the node that has never been set as a target node as a target node (S107), and the control transitions to S102.

[0069] If there is no node that has never been set as a target node (S106: No), the operation of the generating device 1 ends.

[0070] FIG. 7 is a schematic diagram illustrating an example of functions implemented by the processor 21 included in the search device 2 of the embodiment.

[0071] The processor 21 functions as a start node acquisition unit 201 , a node information acquisition unit 202 , and a calculation unit 203 .

[0072] The start node acquisition unit 201 acquires the NID of the start node, and then transmits the acquired NID of the start node to the node information acquisition unit 202.

[0073] The method for acquiring the NID of the start node is not limited to a specific method. The start node acquisition unit 201 may regard the node with the smallest NID numerical value as the start node and acquire node information of the start node from the index information IDX. The NID of the start node may be provided from outside the searching device 2, or may be stored in advance in the SSD 23, and the start node acquisition unit 201 may acquire this NID.

[0074] As described above, in the search operation, a hop operation is executed in which the search target node is sequentially switched along the directed graph GF defined by the index information IDX. The start node is a node set as the search target node of the first hop operation. The node information acquisition unit 202 and the calculation unit 203 start the first hop operation by regarding the start node as the search target node in the first hop operation.

[0075] The node information acquisition unit 202 acquires node information of the search target node from index information IDX pre-stored in the SSD 23. Before the first hop operation is performed, the node indicated by the NID received from the start node acquisition unit 201 is regarded as the search target node. After the first hop operation is performed, the node indicated by the NID received from the calculation unit 203 is regarded as the search target node.

[0076] The node information acquisition unit 202 stores the acquired node information in the cache area 241. In addition, the node information acquisition unit 202 transmits to the calculation unit 203 the NID of the node to be searched for and the NIDs of all adjacent nodes of the node to be searched for.

[0077] The calculation unit 203 obtains the compressed vector and full-precision vector of the search target node and the compressed vectors of all adjacent nodes from the cache area 241. Then, the calculation unit 203 calculates the distance to the query for the search target node and all adjacent nodes of the search target node based on the compressed vectors of each node. The distance obtained by such calculation using the compressed vectors is referred to as the first distance.

[0078] The compressed vector of the current search target node is not included in the node information of the current search target node. The compressed vector of the current search target node is included in the node information of the previous search target node as the compressed vector of one adjacent node of the previous search target node. Therefore, in each hop operation, the cache area 241 maintains a valid state for at least the compressed vector of the hop destination node among all the compressed vectors of adjacent nodes included in the node information of the search target node. That is, in one hop operation, in addition to the node information of the current search target node, the compressed vector of the current search target node that was included in the node information of the previous search target node can be obtained from the cache area 241.

[0079] When data in the cache area 241 is "valid," it means that the data can be read. When data in the cache area 241 is "invalid," it means that the data cannot be read from the cache area 241. When data in the cache area 241 is "invalid," it specifically means that the data has been erased from the cache area 241, or the location where the data is stored is available for storing other data.

[0080] The calculation unit 203 determines whether to terminate the hop operation based on, for example, the first distance calculated for the search target node and all of the adjacent nodes of the search target node. If the first distance from the search target node to the query is shorter than the first distance from any of the adjacent nodes of the search target node to the query, the calculation unit 203 determines to terminate the hop operation. If there is an adjacent node of the search target node whose first distance from any of the adjacent nodes to the query is shorter than the first distance from the search target node to the query, the calculation unit 203 determines not to terminate the hop operation. Note that the method of determining whether to terminate the hop operation is not limited to this.

[0081] If it is determined not to end the hopping operation, the calculation unit 203 determines a hop destination node from among all adjacent nodes of the search target node. The calculation unit 203 determines the adjacent node with the shortest first distance from among all adjacent nodes of the search target node as the hop destination node. The calculation unit 203 transmits the NID of the hop destination node to the node information acquisition unit 202.

[0082] The calculation unit 203 also calculates the distance from the search target node to the query using the full-precision vector of the search target node. Such a distance obtained by calculation using the full-precision vector is referred to as the second distance. The calculation unit 203 stores the second distance in the cache area 241.

[0083] Until the hopping operation is terminated, the second distances for all nodes on the route of the hopping operation are stored in the cache area 241 in a valid state. When it is determined that the hopping operation is to be terminated, the calculation unit 203 identifies the node closest to the query from among all nodes on the hopping route based on the second distances of all nodes on the hopping route. Then, the calculation unit 203 outputs information indicating the identified node as a search result.

[0084] The search result output by the calculation unit 203 is not limited to specific information as long as it corresponds to the node identified as the node closest to the query. For example, the calculation unit 203 can output the NID or full-precision vector of the node identified as the node closest to the query as the search result. Here, as an example, the calculation unit 203 outputs the full-precision vector of the node identified as the node closest to the query as the search result.

[0085] Note that some or all of start node acquisition unit 201, node information acquisition unit 202, and calculation unit 203 may be realized by a hardware circuit such as an FPGA or an ASIC.

[0086] FIG. 8 is a flowchart showing an example of the operation of the searching device 2 according to the embodiment.

[0087] When the calculation unit 203 receives a query (S201), the start node acquisition unit 201 acquires the NID of the start node (S202). When the node information acquisition unit 202 recognizes the start node by the NID of the start node, it sets the start node as a search target node (S203).

[0088] The node information acquisition unit 202 reads the node information of the search target node from the index information IDX from the SSD 23, and stores the read node information of the search target node in the cache area 241 (S204).

[0089] The calculation unit 203 calculates the distance (first distance) between the query and the search target node and each of all adjacent nodes of the search target node (S205). In S205, the calculation unit 203 calculates the first distance for each node using the compressed vector of the search target node and the compressed vectors of all adjacent nodes of the search target node included in the node information stored in the cache area 241.

[0090] Furthermore, the calculation unit 203 calculates the distance (second distance) between the search target node and the query using the full precision vector of the search target node included in the node information stored in the cache area 241 (S206).

[0091] The calculation unit 203 determines whether or not to end the hopping operation (S207). If it is determined not to end the hopping operation (S207: No), the calculation unit 203 determines a hop destination node (S208). The calculation unit 203 determines the hop destination node based on the first distance to each node calculated by the process of S205.

[0092] The calculation unit 203 stores the second distance to the search target node in the cache area 241 (S209). The process of S209 may be executed after the process of S206 and before the process of S207. Then, the calculation unit 203 invalidates the data in the cache area 241 except for the second distance to each node on the hop route and the compressed vector of the hop destination (S210).

[0093] The NID of the hop destination node is transmitted from the calculation unit 203 to the node information acquisition unit 202, and the node information acquisition unit 202 sets the hop destination node as a search target node (S211). Then, the control shifts to S204.

[0094] Note that if control transitions to S204 after passing through S211, the first distance between the new search target node and the query has already been obtained by the previously executed process of S205. Therefore, the calculation unit 203 may omit the calculation of the first distance between the new search target node and the query in the process of S205.

[0095] If it is determined that the hopping operation is to be ended (S207: Yes), the calculation unit 203 identifies the node closest to the query based on the second distance to each node on the hop route (S212).The calculation unit 203 then outputs the full precision vector of the identified node as the search result (S213), and the operation of the search device 2 ends.

[0096] As described above, according to the embodiment, the generating device 1 sets one of the multiple nodes included in the directed graph GF as a target node (see, for example, S101 and S107 in FIG. 6). The generating device 1 writes node information including the full-precision vector of the target node in the vector set and a compressed vector generated by compressing the ID and the corresponding full-precision vector for each of all adjacent nodes of the target node in the vector set (see, for example, S102 to S105 in FIG. 6).

[0097] The index information IDX generated as described above has a configuration in which the compressed vectors of all adjacent nodes required for one hop operation are recorded in each node information. This eliminates the need to store compressed vectors for all vectors in the search range in DRAM. This enables search operations with reduced memory usage.

[0098] Furthermore, according to the embodiment, the generating device 1 executes a loop process (for example, S102 to S107 in FIG. 6) multiple times, which includes setting a target node and writing node information of the target node. In each of the multiple loop processes, the generating device 1 writes the node information to a different area among a plurality of areas of the storage device 4, each of which corresponds to a unit of access to the storage device (i.e., a unit storage area).

[0099] Therefore, during a search operation, the processor 21 of the searching device 2 can obtain only the node information necessary for the hop operation from the index information IDX with a single IO request to the storage device SSD 23. This makes it possible to improve the efficiency of access to the storage device during the search operation.

[0100] Also, according to the embodiment, the search device 2 acquires a query (see, for example, S201 in FIG. 8). The search device 2 sets a search target node that is a candidate for the node closest to the query along the directed graph GF defined by the index information IDX (see, for example, S203, S208, and S211 in FIG. 8). Every time the search device 2 sets a search target node, it reads node information of the search target node from the SSD 23, which is a storage device, and stores the read node information of the search target node in the DRAM 24, which is a memory that has a faster access operation than a storage device (see, for example, S204 in FIG. 8), determines a hop destination node based on the compressed vectors of all adjacent nodes included in the node information of the search target node stored in the DRAM 24 (see, for example, S205 and S208 in FIG. 8), and sets the hop destination node as a new search target node (see, for example, S211 in FIG. 8).

[0101] Therefore, it is possible to perform each hop operation for all vectors in the search range without storing compressed vectors in DRAM, which means that search operations can be performed with reduced memory usage.

[0102] Furthermore, according to the first embodiment, the searching device 2 calculates the second distance using the full precision vector included in the node information of the search target node stored in the DRAM 24 (see, for example, S206 in FIG. 8). The searching device 2 identifies the vector closest to the query based on the second distance of each node that has been set as a search target node, that is, each node on the hop route (see, for example, S212 in FIG. 8).

[0103] Therefore, it is possible to perform each hop operation for all vectors in the search range without storing compressed vectors in DRAM, which means that search operations can be performed with reduced memory usage.

[0104] Several modifications of the embodiment will be described below. In each modification, differences from the embodiment will be described. Explanations of the same matters as the embodiment will be omitted or will be explained briefly.

[0105] (Variation 1) In the first modification, the node information generation unit 104 generates, as node information, an information piece that includes the full-precision vector of the target node, the IDs and compressed vectors of all of the target node's adjacent nodes, and the compressed vector of the target node. The compressed vector of the target node is generated by compressing the full-precision vector of the target node. The compressed vector of the target node is acquired by the compressed vector acquisition unit 103. The compressed vector acquisition unit 103 may acquire the compressed vector of the target node from an external source, or may acquire the compressed vector of the target node by generating it by compressing the full-precision vector of the target node.

[0106] Fig. 9 is a diagram showing an example of the configuration of node information according to Modification 1. Fig. 9 shows the configuration of the node information of node NIDi as a representative of all node information. As shown in Fig. 9, the node information according to Modification 1 has a configuration in which a compressed vector of node NIDi is added to the node information according to the embodiment shown in Fig. 2.

[0107] In this way, each node information includes the full precision vector of the target node, the IDs and compressed vectors of all of the target node's neighboring nodes, and the compressed vector of the target node. Therefore, the calculation unit 203 of the searching device 2 can invalidate all of the node information of the search target node in the cache area 241 when each hop operation is completed.

[0108] (Variation 2) 10 is a diagram showing an example of the configuration of node information according to Modification 2. This diagram shows the configuration of the node information of node NIDi as a representative of all node information. As shown in this diagram, the node information according to Modification 2 has a configuration in which the out-degree R of node NIDi is added to the node information according to the embodiment shown in FIG.

[0109] As mentioned above, only one piece of node information is stored in one unit storage area. However, the size of the node information does not necessarily match the capacity of the unit storage area. There may be free space remaining in a unit storage area where one piece of node information is stored. Such free space may be padded. Furthermore, the out-degree R may differ for each node.

[0110] When reading the node information of a node to be searched from a unit storage area, the node information acquisition unit 202 of the searching device 2 needs to identify the end of the node information stored in that unit storage area. According to the second modification, the node information acquisition unit 202 can identify the end of the node information based on the out-degree R included in the node information.

[0111] For example, let the size of a full precision vector be bfull Bytes, the size of one compressed vector is b comp Byte, the size of the numeric information of NID is b NID Byte, the size of the numerical information of the out-degree R is b R In terms of bytes, the size of the node information in Modification 2 is b ND can be expressed by the following equation (1). b ND =b full +R×(b comp +b NID )+b R ···(1)

[0112] The node information acquisition unit 202 calculates the size b of the node information using the formula (1). ND Then, the node information acquisition unit 202 calculates b ND The information stored in the range up to the position offset by 1 byte is acquired as the node information of the node to be searched.

[0113] In the second modification, the out-degree R is recorded in the node information of each node. When the out-degree R is common to all nodes, the out-degree R may be omitted from the node information of each node, and the out-degree R may be stored in the SSD 23, which is a storage device, as a parameter common to all nodes.

[0114] (Variation 3) When generating a directed graph GF, the designer may or may not set the out-degree to be common to all nodes. After determining the maximum out-degree, the designer may determine the capacity of the unit memory area.

[0115] The following description will be given according to the modified example 2. max Then, the maximum size of node information is b NDmax can be expressed by the following equation (2). b NDmax =b full +R max ×(b comp +b NID )+b R ···(2)

[0116] The designer determines the maximum size of the node information b NDmax Then, the designer calculates the maximum size of the node information b NDmax is set as the capacity of the unit storage area. Then, it becomes possible to store one node information item in each unit storage area.

[0117] The designer may first determine the capacity of the unit storage area, and then determine the maximum outdegree based on the capacity of the unit storage area.

[0118] In the embodiment, Modification 1, Modification 2, and Modification 3, only one piece of node information is stored in one unit storage area. However, the number of node information stored in one unit storage area is not limited to one. Multiple pieces of node information may be stored in one unit storage area. The size of one piece of node information may be larger than the capacity of the unit storage area, and one piece of node information may be stored in a range spanning two or more unit storage areas. However, one piece of node information is stored in a logically continuous range of the SSD 23.

[0119] A logically contiguous range is a range that is contiguous in the logical address space that a storage device provides to a processor. Generally, storage devices such as SSDs and magnetic disk drives have a faster response speed when reading data from a logically contiguous range than when reading data from two or more ranges that are not logically contiguous. Therefore, by storing each piece of node information in a logically contiguous range in the SSD 23, the time required to read each piece of node information from the SSD 23 is reduced.

[0120] In the description of the embodiment, Modification 1, Modification 2, and Modification 3, the node information includes a compressed vector for each adjacent node. The vector for each adjacent node included in the node information is not limited to a compressed vector. The node information may include a full-precision vector for each adjacent node instead of or in addition to the compressed vector for each adjacent node.

[0121] According to the above-described embodiment, modified example 1, modified example 2, and modified example 3, the configurations of Supplementary Notes 1 to 3 below can also be obtained.

[0122] (Appendix 1) 1. A method of generating by a processor configured to process data represented by a directed graph, comprising: setting one of a plurality of first nodes, each of which is assigned an ID and included in the directed graph, corresponding to a plurality of first vectors included in a search range, as a second node; writing a piece of information including a second vector, which is a first vector corresponding to the second node among the plurality of first vectors, and an ID and a third vector for each of one or more third nodes that are all out-adjacent nodes of the second node among the plurality of first nodes; the third vector is a vector corresponding to the third node, and the piece of information is an element related to the second node among index information corresponding to the directed graph; A generation method including:

[0123] (Appendix 2) the writing includes adding a fourth vector generated by compressing the second vector to the piece of information; The method of generation described in Appendix 1.

[0124] (Appendix 3) the writing includes generating the piece of information with the second vector placed at the beginning. The method of generation described in Appendix 1.

[0125] (Appendix 4) The piece of information does not include the ID of the second vector; 4. The method of any one of claims 1 to 3.

[0126] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0127] 1 Generation device, 2 Search device, 3 Network, 4 Storage device, 11 Processor, 12 First interface, 13 Second interface, 14 DRAM, 15 Bus, 21 Processor, 22 Interface, 23 SSD, 24 DRAM, 25 Bus, 101 Target node setting unit, 102 Information acquisition unit, 103 Compressed vector acquisition unit, 104 Node information generation unit, 105 Storage write unit, 201 Start node acquisition unit, 202 Node information acquisition unit, 203 Calculation unit, 241 Cache area, GF directed graph, GPG generation program, IDX index information, SPG search program.

Claims

1. 1. A method of generating by a processor configured to process data represented by a directed graph, comprising: setting one of a plurality of first nodes, each of which is assigned an ID and included in the directed graph, corresponding to a plurality of first vectors included in a search range, as a second node; writing a piece of information including a second vector, which is a first vector corresponding to the second node among the plurality of first vectors, and an ID and a third vector for each of one or more third nodes which are all out-adjacent nodes of the second node among the plurality of first nodes; the third vector is a vector corresponding to the third node, and the piece of information is an element related to the second node among index information corresponding to the directed graph; A generation method including:

2. the third vector is the first vector corresponding to the third node or a vector generated by compressing the first vector corresponding to the third node; The method of claim 1 .

3. performing a plurality of first operations, each of the plurality of first operations including the setting and the writing; In each of the plurality of first operations, the setting includes setting a first node that has not yet been set as the second node among the plurality of first nodes; the first operation is performed multiple times until there is no first node that has not been set as the second node; The method of claim 1 .

4. the writing includes adding the number of out-neighboring nodes of the second node to the piece of information; The method of claim 1 .

5. performing a plurality of first operations, each of the plurality of first operations including the setting and the writing; the writing in each of the plurality of first operations is writing the piece of information to a different first storage area among a plurality of first storage areas, each of the plurality of first storage areas corresponds to a unit of access to the storage device; The method of any one of claims 1 to 4.

6. Obtaining a query; setting a candidate first node closest to the query along a directed graph defined by index information, the directed graph including a plurality of first nodes corresponding to a plurality of first vectors that are a search range, the index information being stored in a storage device, the index information including a plurality of first information pieces, each of the plurality of first information pieces including a second vector that is a first vector corresponding to one first node of the plurality of first vectors, and an ID and a third vector for each of one or more second nodes that are all out-adjacent nodes of the one first node of the plurality of first nodes, the third vector being a vector corresponding to the second node; Including, Setting the candidate includes reading a second piece of information, which is a first piece of information related to a third node that is a first node of the candidate, from a first storage area corresponding to a unit of access to the storage device, and storing the read second piece of information in a memory that has a higher access speed than the storage device; setting a new candidate first node based on one or more of the third vectors included in the second piece of information stored in the memory; A search method including:

7. the third vector is the first vector corresponding to the second node or a vector generated by compressing the first vector corresponding to the second node; The searching method according to claim 6.

8. After the second piece of information is stored in the memory, calculating a distance between the first node of the candidate and the query using a first vector included in the stored second piece of information; Identifying a vector closest to the query based on a plurality of distances between the query and each of a plurality of first nodes that have been set as the candidate; The method of claim 6 further comprising:

9. an interface circuit configured to receive a directed graph including a plurality of first nodes each assigned an ID and a plurality of first vectors included in a search range, the plurality of first nodes corresponding to the plurality of first vectors; setting one of the plurality of first nodes as a second node; writing a piece of information including a second vector, which is a first vector corresponding to the second node among the plurality of first vectors, and an ID and a third vector for each of one or more third nodes which are all out-adjacent nodes of the second node among the plurality of first nodes; the third vector is a vector corresponding to the third node, and the piece of information is an element related to the second node among index information corresponding to the directed graph; a processor configured to execute A generating device comprising:

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