Display device

Abstract

To provide a display device having excellent light transmittance.SOLUTION: A display device comprises: a first pixel disposed in a display region for displaying an image; a transmission region disposed in the display region; and a partition wall including a conductive lower portion and an upper portion having an end protruding from a side surface of the lower portion and disposed in the display region. The first pixel includes a plurality of sub-pixels surrounded by the partition wall. The transmission region includes a plurality of sub-regions surrounded by the partition wall and transmitting at least a part of light incident on the transmission region.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. A common voltage is applied to the upper electrodes of each display element through wiring arranged in the display area.

[0003] Furthermore, light transmittance may be required in at least a part of the display region where the display elements are arranged. However, if the lower electrode or the wiring is made of a material having a light-shielding property such as a metal, the light transmittance of the display device may be significantly reduced. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device with excellent light transmittance. [Means for solving the problem]

[0006] A display device according to one embodiment includes a first pixel arranged in a display region that displays an image, a transmissive region arranged in the display region, and a partition wall arranged in the display region, the partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. The first pixel includes a plurality of sub-pixels surrounded by the partition wall. The transmissive region includes a plurality of sub-regions surrounded by the partition wall that transmit at least a portion of light incident on the transmissive region. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a configuration applicable to the pixel circuit included in each sub-pixel. [Figure 3] FIG. 3 is a schematic plan view showing an example of the layout of sub-pixels in one pixel. [Figure 4] FIG. 4 is a schematic cross-sectional view of the display panel taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a schematic plan view showing a part of the first region. [Figure 6] FIG. 6 is a schematic plan view showing a part of the second region. [Figure 7] FIG. 7 is another schematic plan view showing a part of the second region. [Figure 8] FIG. 8 is a schematic cross-sectional view of the second region taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing another configuration applicable to the second region. [Figure 10] FIG. 10 is a schematic plan view showing still another configuration applicable to the second region. [Figure 11]FIG. 11 is a schematic plan view showing another example of openings in the rib layer. [Figure 12] FIG. 12 is a schematic cross-sectional view of the second region taken along line XII-XII in FIG. [Figure 13A] FIG. 13A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 13B] FIG. 13B is a schematic cross-sectional view showing a step subsequent to FIG. 13A. [Figure 13C] FIG. 13C is a schematic cross-sectional view showing a step subsequent to FIG. 13B. [Figure 13D] FIG. 13D is a schematic cross-sectional view showing a step subsequent to FIG. 13C. [Figure 13E] FIG. 13E is a schematic cross-sectional view showing a step subsequent to FIG. 13D. [Figure 13F] FIG. 13F is a schematic cross-sectional view showing a step subsequent to FIG. 13E. [Figure 13G] FIG. 13G is a schematic cross-sectional view showing a step subsequent to FIG. 13F. [Figure 13H] FIG. 13H is a schematic cross-sectional view showing a step subsequent to FIG. 13G. [Figure 13I] FIG. 13I is a schematic cross-sectional view showing a step subsequent to FIG. 13H. [Figure 14] FIG. 14 is a schematic plan view showing a part of the second region according to the second embodiment. [Figure 15] FIG. 15 is a schematic plan view showing a part of the second region according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that can be easily conceived by a person skilled in the art while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the purpose of clarifying the description, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes three subpixels SP1, SP2, and SP3 (first to third subpixels). For example, the subpixel SP1 displays green, the subpixel SP2 displays blue, and the subpixel SP3 displays red. However, the colors displayed by the subpixels SP1, SP2, and SP3 are not limited to this example. The pixel PX may also include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The display area DA includes a first area A1 and a second area A2 having higher light transmittance than the first area A1. For example, a camera CR is disposed on the rear side of the second area A2. This camera CR can capture an image of an object on the display surface side through the second area A2. Note that instead of the camera CR, other types of light receiving elements, such as an illuminance sensor that detects external light, may be disposed. Furthermore, the display area DA may include multiple second areas A2 facing the camera CR or the illuminance sensor.

[0015] For example, the second region A2 is smaller than the first region A1. In the example of FIG. 1, the second region A2 is located near the edge of the display region DA and is surrounded by the first region A1. However, the arrangement position of the second region A2 is not limited to this example. The second region A2 does not necessarily have to be surrounded entirely by the first region A1, and may be arranged so that one or two sides face the peripheral region SA. The second region A2 is, for example, rectangular, but may also be other shapes such as circular.

[0016] 2 is a circuit diagram showing an example of a configuration applicable to the pixel circuit PC included in each of the subpixels SP (SP1, SP2, SP3). The pixel circuit PC shown in this diagram includes seven transistors TR1 to TR7 and one storage capacitor Cst.

[0017] In the following description, one of the source-drain electrodes of each of the transistors TR1 to TR7 is referred to as a first electrode, and the other as a second electrode. Similarly, one of the pair of electrodes constituting the storage capacitor Cst is referred to as a first electrode, and the other as a second electrode.

[0018] A first electrode of the transistor TR1 is connected to the node n1. A second electrode of the transistor TR1 is connected to a signal line SL that supplies a video signal Sdata. The video signal Sdata is a signal that is written to a pixel to display an image.

[0019] The transistor TR2 corresponds to a drive transistor that supplies current to the light-emitting element DE included in the subpixel SP. A first electrode of the transistor TR2 is connected to the node n1. A second electrode of the transistor TR2 is connected to the node n2.

[0020] A first electrode of the transistor TR3 is connected to the node n3, and a second electrode of the transistor TR3 is connected to the node n2.

[0021] A first electrode of the transistor TR4 is connected to the node n2, and a second electrode of the transistor TR4 is connected to a power supply line PL1 that supplies a power supply voltage VDDEL.

[0022] A first electrode of the transistor TR5 is connected to the node n4, and a second electrode of the transistor TR5 is connected to the node n1.

[0023] A first electrode of the transistor TR6 is connected to the node n4, and a second electrode of the transistor TR6 is connected to the initialization line IL that supplies the initialization voltage Vini.

[0024] A first electrode of the transistor TR7 is connected to the node n2, and a second electrode of the transistor TR7 is connected to a power supply line PL2 that supplies a power supply voltage VSH.

[0025] A first electrode of the storage capacitor Cst is connected to the node n3, and a second electrode of the storage capacitor Cst is connected to the node n4.

[0026] The gate electrode of transistor TR1 is connected to scan line GL1 that supplies scan signal Sg1. The gate electrode of transistor TR3 is connected to scan line GL2 that supplies scan signal Sg2. The gate electrodes of transistors TR4, TR5, and TR6 are connected to scan line GL3 that supplies scan signal Sg3. The gate electrode of transistor TR7 is connected to scan line GL4 that supplies scan signal Sg4.

[0027] The anode of the display element DE is connected to node n4. The cathode of the display element DE is connected to a power supply line PL3 that supplies a power supply voltage VSSEL. The power supply voltage VDDEL corresponds to the anode voltage supplied to the display element DE, and the power supply voltage VSSEL corresponds to the cathode voltage supplied to the display element DE.

[0028] The configuration of the pixel circuit PC is not limited to the example shown in Figure 2. For example, the pixel circuit PC may include six or fewer transistors or eight or more transistors. The pixel circuit PC may also include multiple storage capacitors Cst. The number of scanning lines and power supply lines connected to the pixel circuit PC may increase or decrease depending on the configuration of the pixel circuit PC.

[0029] 3 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3 in one pixel PX. In the example of FIG. 3, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction. Note that the layout of subpixels SP1, SP2, and SP3 is not limited to the example of FIG. 3.

[0030] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of Fig. 3, the pixel aperture AP1 is larger than the pixel aperture AP2, and the pixel aperture AP2 is larger than the pixel aperture AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio and the subpixel SP3 has the smallest aperture ratio.

[0031] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel aperture AP3. In FIG. 3, the lower electrodes LE1, LE2, and LE3 are indicated by hatched patterns.

[0032] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0033] Conductive partition walls 6 are disposed on the rib layer 5. In FIG. 3, the partition walls 6 have a dotted pattern. The partition walls 6 entirely overlap the rib layer 5 and have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in the subpixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition walls 6 have a lattice shape in a planar view and surround the subpixels SP1, SP2, and SP3 (display elements DE1, DE2, and DE3), respectively. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0034] 3, the ends of the lower electrodes LE1, LE2, LE3 entirely overlap with the rib layer 5 and the partition wall 6. As another example, at least a portion of the ends of the lower electrodes LE1, LE2, LE3 may not overlap with the partition wall 6.

[0035] 4 is a schematic cross-sectional view of the display panel PNL taken along line IV-IV in FIG. 3. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits PC, scanning lines GL1 to GL4, signal lines SL, power supply lines PL1 to PL3, and initialization lines IL shown in FIG. 2. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0036] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 4, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit PC of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0037] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0038] In the example of FIG. 4, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Also, in the example of FIG. 4, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0039] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0040] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0041] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0042] A portion of the laminated film FL1 is located on the upper portion 62. This portion is separated from a portion of the laminated film FL1 that is located around the partition wall 6 (a portion that constitutes the display element DE1). Similarly, a portion of the laminated film FL2 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL2 that is located around the partition wall 6 (a portion that constitutes the display element DE2). Furthermore, a portion of the laminated film FL3 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL3 that is located around the partition wall 6 (a portion that constitutes the display element DE3).

[0043] Sealing layers SE11, SE12, and SE13 (first sealing layers) are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0044] 4, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE12 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE13 on the partition wall 6.

[0045] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1 (first resin layer). The resin layer RS1 is covered with a sealing layer SE2 (second sealing layer). The sealing layer SE2 is covered with a resin layer RS2 (second resin layer). The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously at least over the entire display area DA, with portions thereof extending into the peripheral area SA.

[0046] A cover member such as a polarizing plate, a touch panel, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0047] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0048] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0049] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0050] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0051] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0052] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0053] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. Examples of the metal material that can be used to form the lower layer include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the upper layer include ITO and IZO. The upper portion 62 may also have a single-layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0054] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits PC of the subpixels SP1, SP2, and SP3, respectively.

[0055] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0056] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0057] 5 is a schematic plan view showing a portion of the first region A1. In this figure, the rib layer 5, the partition walls 6, and the lower electrodes LE1, LE2, and LE3 are shown, and other elements are omitted. The partition walls 6 are given a dotted pattern, and the lower electrodes LE1, LE2, and LE3 are given a diagonal line pattern.

[0058] In the first region A1, a plurality of pixels PX are arranged in the X and Y directions. The layout of the subpixels SP1, SP2, and SP3 in each pixel PX is the same as the example in FIG. 2. As a result, in the first region A1, a column in which a plurality of subpixels SP1 are repeatedly arranged in the Y direction and a column in which subpixels SP2 and SP3 are alternately arranged in the Y direction are formed. These columns are arranged alternately in the X direction.

[0059] Fig. 6 is a schematic plan view showing a part of the second region A2. As in Fig. 5, Fig. 6 also shows the rib layer 5, the partition walls 6, and the lower electrodes LE1, LE2, and LE3, and omits other elements. In addition, the partition walls 6 are given a dotted pattern, and the lower electrodes LE1, LE2, and LE3 are given a diagonal line pattern.

[0060] The second region A2 has a plurality of pixels PX and a plurality of transmission regions TA. The layout of the subpixels SP1, SP2, and SP3 in the pixels PX in the second region A2 is the same as that of the pixels PX in the first region A1.

[0061] The transmissive region TA has the same size as the pixel PX. In the example of FIG. 6, the pixels PX and the transmissive regions TA are arranged alternately in the X direction and the Y direction. That is, the pixels PX are arranged in the second region A2 at half the density of the first region A1. This example is not limiting, and for example, a plurality of transmissive regions TA may be arranged between two pixels PX adjacent in the X direction or the Y direction. Also, a plurality of pixels PX may be arranged between two transmissive regions TA adjacent in the X direction or the Y direction.

[0062] The transmissive region TA includes a plurality of sub-regions AS each surrounded by a partition wall 6. The sub-regions AS transmit at least a portion of light incident on the transmissive region TA from, for example, the display surface side of the display device DSP to the rear surface side of the display device DSP. This makes the second region A2 more translucent than the first region A1, as described above in the description of FIG.

[0063] 6, three sub-regions AS1, AS2, and AS3 (first to third sub-regions) are formed in the transmissive region TA. That is, the number of sub-pixels SP (SP1, SP2, and SP3) in one pixel PX and the number of sub-regions AS (AS1, AS2, and AS3) in one transmissive region TA are both three. However, the number of sub-pixels SP in one pixel PX and the number of sub-regions AS in one transmissive region TA do not necessarily have to be the same.

[0064] 6, subpixel SP1 and subregion AS1 have the same shape, subpixel SP2 and subregion AS2 have the same shape, and subpixel SP3 and subregion AS3 have the same shape. The shapes of the subpixels and subregions here refer to the shapes of the regions surrounded by partition wall 6 in a plan view.

[0065] 6, the sub-regions AS2 and AS3 are aligned in the Y direction. Furthermore, each of the sub-regions AS2 and AS3 is aligned with the sub-region AS1 in the X direction. That is, the positional relationship between the sub-regions AS1, AS2, and AS3 is the same as the positional relationship between the sub-pixels SP1, SP2, and SP3.

[0066] The partition wall 6 has a first portion P1 that divides the subpixels SP1, SP2, and SP3 in each pixel PX and a second portion P2 that divides the subregions AS1, AS2, and AS3 in each transmissive region TA. In the example of FIG. 6, the first portion P1 and the second portion P2 have the same shape. That is, the first portion P1 has a portion extending in the Y direction between the subpixel SP1 and the subpixels SP2 and SP3, and a portion extending in the X direction between the subpixel SP2 and the subpixel SP3. The second portion P2 has a portion extending in the Y direction between the subregion AS1 and the subregions AS2 and AS3, and a portion extending in the X direction between the subregion AS2 and the subregion AS3.

[0067] As described above, the lower electrodes LE1, LE2, and LE3 are arranged in the subpixels SP1, SP2, and SP3. Furthermore, pixel openings AP1, AP2, and AP3 overlapping with the lower electrodes LE1, LE2, and LE3, respectively, are provided in the rib layer 5.

[0068] In contrast, the lower electrodes LE1, LE2, and LE3 are not arranged in the sub-regions AS1, AS2, and AS3. Also, in the example of Fig. 6, the rib layer 5 does not have openings in the sub-regions AS1, AS2, and AS3. That is, the sub-regions AS1, AS2, and AS3 entirely overlap with the rib layer 5.

[0069] 7 is another schematic plan view showing a portion of the second region A2. Various wirings for driving the subpixels SP1, SP2, and SP3 are arranged in the second region A2. These wirings include a plurality of wirings Lx extending in the X direction and a plurality of wirings Ly extending in the Y direction. Both wirings Lx and Ly are formed from a metal layer included in the circuit layer 11 shown in FIG. 4.

[0070] In one example, the multiple wirings Lx include the scanning lines GL1 to GL4, power supply lines PL2 and PL3, and initialization line IL shown in Fig. 2. The multiple wirings Ly include the signal line SL and power supply line PL1 shown in Fig. 2.

[0071] 7, most of the wirings Lx cross the subpixels SP1, SP2, SP3 and the subregions AS1, AS2, AS3 in the X direction, and most of the wirings Ly cross the subpixels SP1, SP2, SP3 and the subregions AS1, AS2, AS3 in the Y direction.

[0072] The wirings Lx and Ly formed of a metal layer have light-shielding properties. In the sub-regions AS1, AS2, and AS3, light is transmitted through the portions that do not overlap with the wirings Lx and Ly. On the other hand, in the sub-pixels SP1, SP2, and SP3, most of the light incident on the display device DSP is reflected or absorbed by the lower electrodes LE1, LE2, and LE3.

[0073] Fig. 8 is a schematic cross-sectional view of the second region A2 taken along line VIII-VIII in Fig. 6. In this figure, the substrate 10 and the circuit layer 11 are omitted.

[0074] As described above, the rib layer 5 does not have openings in the sub-regions AS1, AS2, and AS3. Furthermore, the lower electrodes LE1, LE2, and LE3 are not arranged in the sub-regions AS1, AS2, and AS3.

[0075] 8, none of the stacked films FL1, FL2, FL3 (organic layers OR1, OR2, OR3, upper electrodes UE1, UE2, UE3, and cap layers CP1, CP2, CP3) and sealing layers SE11, SE12, SE13 are arranged in the subregion AS1. As a result, the rib layer 5 and the resin layer RS1 are in contact with each other in the subregions AS1. Similarly, none of the stacked films FL1, FL2, FL3 and sealing layers SE11, SE12, SE13 are arranged in the subregions AS2 and AS3, and the rib layer 5 and the resin layer RS1 are in contact with each other.

[0076] With this configuration, at least a portion of the light L incident on the second area A2 from the display surface side is transmitted through the subareas AS1, AS2, and AS3, making it possible to detect the light L using a light receiving element such as the camera CR shown in FIG.

[0077] 9 is a schematic cross-sectional view showing another configuration applicable to the second region A2. In this example, a stacked film FL1 and a sealing layer SE11 are disposed in the subregion AS1. The stacked film FL1 is divided by a partition wall 6 around the periphery of the subregion AS1. The sealing layer SE11 continuously covers the divided stacked film FL1 and the partition wall 6.

[0078] Even with this configuration, at least a portion of the light L incident on the second region A2 is transmitted through the subregion AS1. However, because the light L passes through the stacked film FL1 and the sealing layer SE11, the transmittance may be lower than in the example of FIG. 8. From this perspective, the configuration shown in FIG. 8 is advantageous.

[0079] 9 can also be applied to the subregions AS2 and AS3. That is, the stacked film FL2 and the sealing layer SE12 may be disposed in the subregion AS2, and the stacked film FL3 and the sealing layer SE13 may be disposed in the subregion AS3.

[0080] 10 is a schematic plan view showing yet another configuration applicable to the second area A2, in which the rib layer 5 and the partition walls 6 in the vicinity of the transmissive area TA are shown, and other elements are omitted.

[0081] The rib layer 5 may have openings 50 overlapping with at least one of the subregions AS1, AS2, and AS3. In the example of Fig. 10, as an example of the openings 50, a plurality of linear openings 50x extending in the X direction and a plurality of linear openings 50y extending in the Y direction are shown.

[0082] Specifically, four linear openings 50x aligned in the Y direction are provided in sub-region AS1, one linear opening 50y is provided in sub-region AS2, and two linear openings 50y aligned in the X direction are provided in sub-region AS3. The linear opening 50y in sub-region AS2 has a larger width in the X direction than the linear opening 50y in sub-region AS3.

[0083] The number, shape, and arrangement of the linear openings 50x, 50y provided in the subregions AS1, AS2, and AS3 are not limited to the example in Fig. 10. For example, the linear opening 50x may be provided in each of the subregions AS1, AS2, and AS3. Alternatively, the linear opening 50y may be provided in each of the subregions AS1, AS2, and AS3.

[0084] 11 is a schematic plan view showing another example of the aperture 50. In the example shown in this figure, a plurality of dot apertures 50d are provided, dispersed in each of the sub-regions AS1, AS2, and AS3.

[0085] In the example of Fig. 11, each dot opening 50d is a perfect circle with the same diameter. However, the dot openings 50d may have other shapes, such as an oval or a square. The diameter (or width) of each dot opening 50d may also be different. The dot openings 50d may be provided in the sub-regions AS1, AS2, and AS3 together with the linear openings 50x and 50y shown in Fig. 10.

[0086] Fig. 12 is a schematic cross-sectional view of the second region A2 taken along line XII-XII in Fig. 10. In the example of Fig. 12, similar to Fig. 8, none of the stacked films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 are disposed in the subregion AS1. Therefore, each linear opening 50x is filled with the resin layer RS1. The resin layer RS1 is in contact with the organic insulating layer 12 through each linear opening 50x.

[0087] 9, the stacked film FL1 and the sealing layer SE11 may be disposed in the subregion AS1. In this case, the stacked film FL1 (specifically, the organic layer OR1) contacts the organic insulating layer 12 through each linear opening 50x. Similarly, the stacked films FL2 and FL3 and the sealing layers SE12 and SE13 may or may not be disposed in the subregions AS2 and AS3.

[0088] When the rib layer 5 is provided with openings 50 such as linear openings 50x and 50y or dot openings 50d in the sub-regions AS1, AS2, and AS3, it is possible to suppress a decrease in transmittance due to the rib layer 5. This further improves the translucency of the transmissive region TA.

[0089] Next, an example of a manufacturing method of the display device DSP will be described. Figures 13A to 13I are schematic cross-sectional views showing the manufacturing process of the display device DSP. Figures 13A to 13I mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0090] In forming the display device DSP, first, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Next, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12, as shown in Fig. 13A.

[0091] 13B, a rib layer 5 is formed to cover the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The rib layer 5 can be formed by, for example, CVD (Chemical Vapor Deposition).

[0092] 13C, the partition wall 6 is formed on the rib layer 5. Specifically, first, layers that will become the bases of the bottom layer 63, the axis layer 64, and the upper portion 62 are formed, and these layers are patterned by etching.

[0093] After the partition walls 6 are formed, pixel openings AP1, AP2, and AP3 are formed in the rib layer 5 by dry etching, as shown in FIG. 13D.

[0094] Next, a process for forming display elements DE1, DE2, and DE3 is performed. In this embodiment, it is assumed that display element DE1 is formed first, display element DE2 is formed next, and display element DE3 is formed last. However, the order in which display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0095] To form the display element DE1, first, as shown in FIG. 13E, a laminated film FL1 and a sealing layer SE11 are formed. As shown in FIG. 4, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition. The sealing layer SE11 is formed by CVD.

[0096] The stacked film FL1 and the sealing layer SE11 are formed not only in the display area DA but also in the peripheral area SA. The stacked film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the stacked film FL1 and the partition walls 6.

[0097] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist R is disposed on the sealing layer SE11, as shown in Fig. 13F. The resist R covers the subpixel SP1 and part of the partition wall 6 around it.

[0098] Then, as shown in FIG. 13G, etching is performed using the resist R as a mask to remove the portions of the stacked film FL1 and the sealing layer SE11 that are exposed by the resist R. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 in the subpixel SP1. The etching may include wet etching or dry etching that is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching steps, the resist R is removed.

[0099] The display element DE2 is formed in the same manner as the display element DE1. That is, when forming the display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire display area DA and the peripheral area SA. As shown in FIG. 4, the stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0100] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by vapor deposition. The sealing layer SE12 is formed by CVD. The stacked film FL2 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE12 continuously covers each divided part of the stacked film FL2 and the partition walls 6. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 13H.

[0101] The display element DE3 is formed in the same manner as the display elements DE1 and DE2. That is, when forming the display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire display area DA and peripheral area SA. As shown in FIG. 4, the stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0102] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by vapor deposition. The sealing layer SE13 is formed by CVD. The stacked film FL3 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the stacked film FL3 and the partition walls 6. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 13I.

[0103] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Fig. 4 are formed in this order, thereby completing the display device DSP having the structure shown in Fig. 4.

[0104] In the present embodiment, the second area A2 having light-transmitting properties is formed in the display area DA. As a result, even if a light-receiving element such as a camera CR is disposed on the back side of the second area A2 as shown in Fig. 1, the light-receiving element can detect light incident on the display area DA.

[0105] Furthermore, the laminated films FL1, FL2, and FL3 formed by vapor deposition may have poor adhesion to the substrate. As a result, the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them may peel off from the substrate during the manufacturing of the display device DSP. In this case, the peeled laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 may adhere to the substrate or contaminate the chamber of the manufacturing equipment.

[0106] The peeling is likely to occur when the stacked films FL1, FL2, and FL3 are formed continuously over a wide area. In the pixel PX, the stacked films FL1, FL2, and FL3 are finely divided by the partition wall 6 that surrounds the subpixels SP1, SP2, and SP3. This prevents the peeling.

[0107] In this embodiment, the transmissive region TA is divided into a plurality of sub-regions AS (AS1, AS2, AS3) by the partition wall 6. As a result, the stacked films FL1, FL2, FL3 are divided into small portions in the transmissive region TA as in the pixel PX, and the peeling is suppressed.

[0108] In this way, peeling of the stacked films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 during manufacturing is suppressed, and it is possible to improve the yield of the display device DSP.

[0109] [Second embodiment] In the second embodiment, other structures that can be applied to the second region A2 will be disclosed. The same as in the first embodiment can be applied to configurations not mentioned in this embodiment.

[0110] 14 is a schematic plan view showing a part of the second region according to the second embodiment. In this figure, the rib layer 5, the partition walls 6, and the lower electrodes LE1, LE2, and LE3 are shown, as in FIG. 6, and other elements are omitted. In addition, the partition walls 6 are given a dotted pattern, and the lower electrodes LE1, LE2, and LE3 are given a diagonal line pattern.

[0111] In this embodiment, the number of sub-pixels SP included in one pixel PX is different from the number of sub-regions AS included in one transmissive region TA. Specifically, in the example of Fig. 14, the pixel PX has three sub-pixels SP (SP1, SP2, SP3), and the transmissive region TA has four sub-regions AS (AS1, AS2, AS3, AS4). That is, in the example of Fig. 14, the number of sub-regions AS included in one transmissive region TA is greater than the number of sub-pixels SP included in one pixel PX.

[0112] 14, sub-regions AS1 and AS2 are aligned in the X direction, and sub-regions AS3 and AS4 are aligned in the X direction. Sub-regions AS1 and AS3 are aligned in the Y direction, and sub-regions AS2 and AS4 are aligned in the Y direction. Furthermore, sub-regions AS1, AS2, AS3, and AS4 have the same shape.

[0113] The partition wall 6 has a first portion P1 that divides the sub-pixels SP1, SP2, and SP3 in each pixel PX, and a second portion P2 that divides the sub-regions AS1, AS2, AS3, and AS4 in each transmissive region TA. In the example of Figure 14, the first portion P1 and the second portion P2 have different shapes.

[0114] 6, the first portion P1 has a portion extending in the Y direction between the subpixel SP1 and the subpixels SP2 and SP3, and a portion extending in the X direction between the subpixels SP2 and SP3. On the other hand, the second portion P2 is cross-shaped. Specifically, the second portion P2 has a portion extending in the Y direction between the subregions AS1 and AS3 and the subregions AS2 and AS4, and a portion extending in the X direction between the subregions AS1 and AS2 and the subregions AS3 and AS4.

[0115] The subregions AS1, AS2, AS3, and AS4 can have a structure similar to that of the subregion AS1 shown in Figures 8, 9, and 12. When openings 50 are provided in the rib layer 5 in the subregions AS1, AS2, AS3, and AS4, linear openings 50x and 50y as shown in Figure 10 or dot openings 50d as shown in Figure 11 can be used for these openings 50.

[0116] In this embodiment, the number of sub-pixels SP included in one pixel PX is different from the number of sub-regions AS included in one transmissive region TA, and yet the same effects as those of the first embodiment can be achieved. Furthermore, in the example of FIG. 14, the transmissive region TA is divided into smaller sections by the second portions P2 of the partition walls 6, compared to the first embodiment. This allows the stacked films FL1, FL2, and FL3 formed in the transmissive region TA to be divided into smaller sections during the manufacture of the display device DSP. This further reduces the peeling described above.

[0117] [Third embodiment] In the third embodiment, still another structure that can be applied to the second region A2 will be disclosed. The same structures as those in the first and second embodiments can be applied to configurations not mentioned in this embodiment.

[0118] 15 is a schematic plan view showing a part of the second region A2 according to the third embodiment. In this figure, the partition wall 6, the lower electrodes LE1, LE2, and LE3, and the multiple wirings Lx extending in the X direction are shown, and other elements are omitted. In addition, the partition wall 6 is given a dotted pattern, and the lower electrodes LE1, LE2, and LE3 are given a diagonal line pattern.

[0119] The structure of the first region A1 in this embodiment is similar to that shown in, for example, FIG. 5. Furthermore, the scales of FIGS. 5 and 15 are the same. That is, as is clear from a comparison of the two figures, in this embodiment, the size of the pixels PX (first pixels) arranged in the second region A2 is different from the size of the pixels PX (second pixels) arranged in the first region A1. Specifically, the pixels PX arranged in the second region A2 are smaller than the pixels PX arranged in the first region A1.

[0120] In one example, the density of the pixels PX in the second region A2 is equal to the density of the pixels PX in the first region A1. Here, the density of the pixels PX means the number of pixels PX contained per unit area.

[0121] 15, the pixel PX arranged in the second region A2 has the same subpixels SP1, SP2, and SP3 as the pixel PX arranged in the first region A1. However, the subpixels SP1, SP2, and SP3 in the second region A2 have rounded corners.

[0122] The transmissive region TA has four subregions AS1, AS2, AS3, and AS4. In the example of FIG. 15, these subregions AS1, AS2, AS3, and AS4 are pentagonal. The second portion P2 of the partition wall 6 is cross-shaped and separates these subregions AS1, AS2, AS3, and AS4. Note that the shapes of the subregions AS1, AS2, AS3, and AS4 are not limited to this example, and various other shapes may be used.

[0123] The subregions AS1, AS2, AS3, and AS4 can have a structure similar to that of the subregion AS1 shown in Figures 8, 9, and 12. When openings 50 are provided in the rib layer 5 in the subregions AS1, AS2, AS3, and AS4, linear openings 50x and 50y as shown in Figure 10 or dot openings 50d as shown in Figure 11 can be used for these openings 50.

[0124] 15, no transmissive region TA is disposed between pixels PX adjacent in the X direction or between pixels PX adjacent in the Y direction. Each transmissive region TA is located between pixels PX adjacent in a diagonal direction intersecting the X and Y directions. From another perspective, the transmissive region TA is disposed at a position shifted in the X and Y directions relative to the pixels PX disposed around it.

[0125] 15, the area of each of the sub-regions AS1, AS2, AS3, and AS4 is larger than the area of any of the sub-pixels SP1, SP2, and SP3. However, this example is not limiting, and the area of at least one of the sub-regions AS1, AS2, AS3, and AS4 may be smaller than the area of any of the sub-pixels SP1, SP2, and SP3.

[0126] Each wiring Lx is arranged so as not to overlap with the sub-regions AS1, AS2, AS3, and AS4. That is, each wiring Lx entirely overlaps with the partition wall 6. In the example of Fig. 15, the spacing between the multiple wirings Lx narrows between two transmissive regions TA aligned in the Y direction, and widens between two pixels PX aligned in the Y direction.

[0127] Although not shown in Fig. 15, the same shape as the wires Lx can also be applied to the multiple wires Ly (see Fig. 7) extending in the Y direction. That is, each wire Ly may be arranged so as not to overlap with a transmissive region TA. In this case, the spacing between the multiple wires Ly may be narrowed between two transmissive regions TA aligned in the X direction and widened between two pixels PX aligned in the X direction.

[0128] In this embodiment, the pixels PX are made smaller in the second region A2, and thus the pixels PX are arranged in the second region A2 at the same density as in the first region A1, thereby improving the display quality of the second region A2. In addition, the light-shielding wiring Lx and Ly made of a metal material are arranged so as not to overlap with the sub-regions AS1, AS2, AS3, and AS4, thereby further improving the light transmittance of the transmissive region TA.

[0129] In the first to third embodiments described above, the transmissive region TA has three or four sub-regions AS. However, this is not limiting, and each transmissive region TA may have five or more sub-regions AS or two or less sub-regions AS. Furthermore, the multiple sub-regions AS of each transmissive region TA may have different shapes.

[0130] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0131] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of each of the above-described embodiments, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0132] Furthermore, with regard to other effects brought about by the aspects described in each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0133] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, DE1, DE2, DE3...display element, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, TA...transmissive area, AS1, AS2, AS3, AS4...sub-area, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer.

Claims

1. a first pixel disposed in a display area for displaying an image; a transmissive region disposed in the display region; a partition wall disposed in the display area, the partition wall including a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; Equipped with the first pixel includes a plurality of sub-pixels surrounded by the partition wall, the transmissive region includes a plurality of subregions that are surrounded by the partition walls and transmit at least a portion of light that enters the transmissive region; Display device.

2. Each of the plurality of sub-pixels is A lower electrode; an organic layer covering the lower electrode and emitting light in response to application of a voltage; an upper electrode covering the organic layer and in contact with the lower portion of the partition wall; Including, The lower electrode is not disposed in the plurality of sub-regions. The display device according to claim 1 .

3. the organic layer and the upper electrode are not disposed in the plurality of sub-regions; The display device according to claim 2 .

4. Each of the plurality of sub-pixels further includes an optical adjustment layer covering the upper electrode, The optical adjustment layer is not disposed in the plurality of sub-regions. The display device according to claim 3 .

5. each of the plurality of sub-pixels further includes a first sealing layer formed of an inorganic insulating material and covering the optical adjustment layer; The first sealing layer is not disposed in the plurality of sub-regions. The display device according to claim 4 .

6. a rib layer formed of an inorganic insulating material and positioned below the partition wall, the rib layer having a pixel opening in each of the plurality of sub-pixels; the plurality of sub-regions overlapping the rib layer; The display device according to claim 1 .

7. the rib layer has an opening overlapping at least one of the plurality of sub-regions; The display device according to claim 6.

8. The opening includes a plurality of linear openings aligned in one of the sub-regions. The display device according to claim 7 .

9. The apertures include a plurality of dot apertures distributed in one of the sub-regions. The display device according to claim 7 .

10. a first resin layer covering the display area; the first resin layer is in contact with the rib layer in the plurality of sub-regions; The display device according to claim 6.

11. a second sealing layer formed of an inorganic insulating material and covering the first resin layer; The display device according to claim 10.

12. Further comprising a second resin layer covering the second sealing layer. The display device according to claim 11.

13. the number of the plurality of sub-pixels is the same as the number of the plurality of sub-regions; The display device according to claim 1 .

14. the plurality of subpixels include a first subpixel, a second subpixel, and a third subpixel; the plurality of sub-regions include a first sub-region, a second sub-region, and a third sub-region that are arranged in the same positional relationship as a positional relationship between the first sub-pixel, the second sub-pixel, and the third sub-pixel; The display device according to claim 13.

15. The partition wall is a first portion that partitions the first subpixel, the second subpixel, and the third subpixel; a second portion that defines the first sub-region, the second sub-region, and the third sub-region; Including, The display device according to claim 14.

16. The first portion and the second portion have the same shape. The display device according to claim 15.

17. the number of the plurality of sub-pixels is different from the number of the plurality of sub-regions; The display device according to claim 1 .

18. the number of the plurality of sub-regions is greater than the number of the plurality of sub-pixels; The display device according to claim 17.

19. a plurality of pixel circuits arranged in the display region and configured to drive the plurality of sub-pixels, respectively; a plurality of wirings for supplying voltages or signals to the plurality of pixel circuits; Furthermore, At least one of the plurality of wirings overlaps the partition wall but does not overlap the plurality of sub-regions. The display device according to claim 1 .

20. the display region has a first region including a second pixel and a second region including the first pixel and the transmissive region; The first pixel is smaller than the second pixel.

20. The display device according to claim 19.

Images