Monolithic PV panel with microphotovoltaic cell and integrated monolithic bypass diode

Abstract

To provide a PV panel made from many micro photovoltaic (PV) cells to avoid the reduction in the solar panel's potential power output due to a circuit requiring a large number of solar cells.SOLUTION: Each micro PV cell is a multi-junction solar cell approximately 1 cm on a side. An array of approximately 50 micro PV cells, all connected in series, creates a single "PV device" that produces 90 to 100 V at low current. A PV panel contains a plurality of strings of these PV devices connected in parallel, which produces high photocurrent at 90 to 100 V. Multi-junction micro PV cells can be made with stacked layers of Ge, GaAs, and InGaPPN. Each micro PV cell has its own integrated monolithic bypass diode.SELECTED DRAWING: Figure 6B

Description

[Technical Field]

[0001] This disclosure relates to multi-junction PV micro-PV cell arrays with integrated monolithic bypass diodes for use in photovoltaic (PV) panels. In particular, this disclosure relates to multi-junction PV cells used in PV panels for satellites and spacecraft. [Background technology]

[0002] FIG. 1 shows a schematic plan view of an example of a PV panel 2 using large PV cells 4, 4′ etc. mounted on a substrate 6. Each PV cell 4, 4′ etc. is approximately half of a circular wafer with a diameter of 150 mm and an area of 75 cm 2As cells get larger, problems arise with high photocurrent and electrostatic discharge (ESD), as well as the difficulty of finding a useful layout for a given panel. This example shows the solar cell locations for a 15x5 layout, with three cells removed for a "stayout zone" 7 (comprising tubular structural member 8). A total of 72 solar cells can fit on the panel. System output voltage and mission specifications may require connecting 20 to 60 solar cells in series. Here, an example is sketched in which 28 cells are connected in series to form a circuit with a voltage of approximately 56 V (2 volts per cell). The 72-cell configuration is divided into three circuits (identified by three different shadings). There are two circuits of 28 cells (Circuits A and B) and one circuit of 16 cells (Circuit C). The 16 cells in Circuit C generate only about half the required voltage (i.e., 32 V). Therefore, the batteries in Circuit C can be removed from Panel 2 because they do not provide any power to the system. Complex arrangements can also be designed that combine partial circuits across multiple panels. This can help somewhat, but it is still best to have a string of 14 cells, and two cells can be removed from the panel. This shows that it can be difficult to fully utilize the solar power from the entire area of a space PV panel. The challenge is that a PV panel is made up of circuits that require many solar cells. Each circuit requires a certain area. The area of the panel is set by several other constraints. There is a high chance that the circuit will not be able to completely fill the area of the solar panel, reducing the potential power output. Summary of the Invention

[0003]

[0003] In one embodiment, a micro PV cell includes a right side and a left side, a first layer including a first semiconductor material, a second layer disposed on the first layer, a multi-junction micro PV cell stack disposed on a portion of the second layer, a first trench extending downward into the first layer, the first trench disposed to the left of the micro PV cell, a second trench extending downward into the first layer, the second trench disposed to the right of the micro PV cell, a third trench disposed adjacent the second trench and extending downward into the second layer, the third trench disposed to the right of the micro PV cell adjacent to the left of the second trench, a left first shoulder disposed to the left of the micro PV cell at a bottom of the first trench, a right second shoulder disposed to the right of the micro PV cell at a bottom of the second trench, a right third shoulder disposed to the right of the micro PV cell at a bottom of the third trench, and an integrated monolithic bypass diode including the second layer disposed on the first layer.

[0004]

[0004] In another embodiment, a photovoltaic (PV) micro PV cell comprises, on a left side and a right side, a first layer comprising a first semiconductor material, a second layer comprising the first semiconductor material disposed on the first layer, a third layer comprising the first semiconductor material disposed on the second layer, a fourth layer comprising the first semiconductor material disposed on the third layer, a fifth layer comprising the second semiconductor material disposed on the fourth layer, a sixth layer comprising the second semiconductor material disposed on the fifth layer, a seventh layer comprising a third semiconductor material disposed on the sixth layer, an eighth layer comprising the third semiconductor material disposed on the seventh layer, a first trench extending downward into the first layer, the first trench disposed on the left side of the micro PV cell, an integrated monolithic bypass diode including a second trench extending downward into the first layer, the second trench disposed to the right of the micro PV cell; a third trench extending downward into the second layer, the third trench disposed to the left of the micro PV cell adjacent the first trench; a fourth trench extending downward into the fourth layer, the fourth trench disposed to the right of the micro PV cell adjacent the second trench; a first left shoulder disposed to the left of the micro PV cell at a bottom of the second trench; a second right shoulder disposed to the right of the micro PV cell at a bottom of the fourth trench; and a fourth layer disposed on the third layer.

[0005] In a further embodiment, a PV device includes a string of three identical micro PV cells connected in series, the string including a first micro PV cell disposed on a common substrate, a second micro PV cell disposed on the common substrate and electrically connected in series with the first micro PV cell, and a third micro PV cell disposed on the common substrate and electrically connected in series with the second micro PV cell. Each of the first, second, and third micro PV cells includes a right and left side, a first layer including a first semiconductor material, a second layer disposed on the first layer, a multi-junction micro PV cell stack disposed on a portion of the second layer, a first trench extending downward into the first layer, the first trench disposed to the left of the micro PV cell, a second trench extending downward into the first layer, the second trench disposed to the right of the micro PV cell, and a third trench disposed adjacent the second trench and extending downward into the second layer. The micro PV cell includes a first layer and a third trench disposed to the right of the micro PV cell adjacent to the left of the second trench, a first left shoulder disposed to the left of the micro PV cell at a bottom of the first trench, a second right shoulder disposed to the right of the micro PV cell at a bottom of the second trench, a third right shoulder disposed to the right of the micro PV cell at a bottom of the third trench, and an integrated monolithic bypass diode including a buried PN junction disposed between the second layer and the first layer. The first micro PV cell includes a first top surface. The second micro PV cell includes a second top surface. The third micro PV cell includes a third top surface. The string further includes a first conductor electrically connecting the first layer to the first top surface of the first micro PV cell, a second conductor electrically connecting a third right shoulder of the first micro PV cell to the second top surface of the second micro PV cell, and a third conductor electrically connecting a third right shoulder of the second micro PV cell to a third right shoulder of the third micro PV cell. The common material is the first layer.

[0006] A PV device includes a string of three identical micro PV cells connected in series, the string including a first micro PV cell disposed on a common substrate, a second micro PV cell disposed on the common substrate and electrically connected in series with the first micro PV cell, and a third micro PV cell disposed on the common substrate and electrically connected in series with the second micro PV cell. Each of the first, second, and third micro PV cells comprises, on a left and right side, a first layer comprising a first semiconductor material, a second layer comprising the first semiconductor material disposed on the first layer, a third layer comprising the first semiconductor material disposed on the second layer, a fourth layer comprising the first semiconductor material disposed on the third layer, a fifth layer comprising the second semiconductor material disposed on the fourth layer, a sixth layer comprising the second semiconductor material disposed on the fifth layer, a seventh layer comprising the third semiconductor material disposed on the sixth layer, an eighth layer comprising the third semiconductor material disposed on the seventh layer, and a first train extending downward into the first layer and disposed on the left side of the micro PV cell. a second trench extending downward into the first layer and disposed to the right of the micro PV cell; a third trench extending downward into the second layer and disposed to the left of the micro PV cell adjacent to the first trench; a fourth trench extending downward into the fourth layer and disposed to the right of the micro PV cell adjacent to the second trench; a first left shoulder disposed to the left of the micro PV cell at a bottom of the second trench; a second right shoulder disposed to the right of the micro PV cell at a bottom of the fourth trench; and an integrated monolithic bypass diode including a buried PN junction disposed between the fourth layer and the third layer. The first micro PV cell includes a first top surface. The second micro PV cell includes a second top surface. The third micro PV cell includes a third top surface.The string includes a first conductor electrically connecting the first layer to the first top surface of the first micro PV cell, a second conductor electrically connecting the second right shoulder of the first micro PV cell to the second top surface of the second micro PV cell, a third conductor electrically connecting the second right shoulder of the second micro PV cell to the third top surface of the third micro PV cell, a fourth conductor electrically connecting the second right shoulder of the first micro PV cell to the first left shoulder of the second micro PV cell, and a fifth conductor electrically connecting the second right shoulder of the second micro PV cell to the first left shoulder of the third micro PV cell. The integrated monolithic bypass diode of each micro PV cell includes a PN junction disposed between the fourth layer and the third layer of each micro PV cell. The common material is the first layer.

[0007] In another embodiment, a PV device includes an array of micro PV cells disposed on a common substrate and electrically connected in series. Each micro PV cell includes a right and left side, a first layer including a first semiconductor material, a second layer disposed on the first layer, a multi-junction micro PV cell stack disposed on a portion of the second layer, a first trench extending downward into the first layer, the first trench disposed to the left of the micro PV cell, a second trench extending downward into the first layer, the second trench disposed to the right of the micro PV cell, a third trench disposed adjacent the second trench and extending downward into the second layer, the third trench disposed to the right of the micro PV cell adjacent to the left of the second trench, a left first shoulder disposed to the left of the micro PV cell at a bottom of the first trench, a right second shoulder disposed to the right of the micro PV cell at a bottom of the second trench, a right third shoulder disposed to the right of the micro PV cell at a bottom of the third trench, and an integrated monolithic bypass diode including the second layer disposed on the first layer. The common substrate is the first layer.

[0008] In another embodiment, a PV device includes an array of micro PV cells disposed on a common substrate and electrically connected in series, each micro PV cell having a left and right side, a first layer including a first semiconductor material, a second layer including the first semiconductor material disposed on the first layer, a third layer including the first semiconductor material disposed on the second layer, a fourth layer including the first semiconductor material disposed on the third layer, a fifth layer including the second semiconductor material disposed on the fourth layer, a sixth layer including the second semiconductor material disposed on the fifth layer, a seventh layer including a third semiconductor material disposed on the sixth layer, an eighth layer including the third semiconductor material disposed on the seventh layer, a first trench extending downward into the first layer and extending downward into the first layer, a first trench disposed on the first layer, a second trench extending downward into the first layer and disposed to the right of the micro PV cell, a third trench extending downward into the second layer and disposed to the left of the micro PV cell adjacent the first trench, a fourth trench extending downward into the fourth layer and disposed to the right of the micro PV cell adjacent the second trench, a first left shoulder disposed to the left of the micro PV cell at a bottom of the second trench, a second right shoulder disposed to the right of the micro PV cell at a bottom of the fourth trench, and a fourth layer disposed on the third layer. The common material is the first layer.

[0009] In another embodiment, a PV panel includes an array of PV devices, each PV device including an array of micro PV cells disposed on a common substrate and electrically connected in series. Each micro PV cell includes a right and left side, a first layer including a first semiconductor material, a second layer disposed on the first layer, a multi-junction micro PV cell stack disposed on a portion of the second layer, a first trench extending downward into the first layer, the first trench disposed to the left of the micro PV cell, a second trench extending downward into the first layer, the second trench disposed to the right of the micro PV cell, a third trench disposed adjacent the second trench and extending downward into the second layer, the third trench disposed to the right of the micro PV cell adjacent to the left of the second trench, a left first shoulder disposed to the left of the micro PV cell at a bottom of the first trench, a right second shoulder disposed to the right of the micro PV cell at a bottom of the second trench, a right third shoulder disposed to the right of the micro PV cell at a bottom of the third trench, and an integrated monolithic bypass diode including the second layer disposed on the first layer. Common equipment is the first tier.

[0010] In another embodiment, a PV panel includes an array of PV devices, each including an array of micro PV cells disposed on a common substrate and electrically connected in series, each micro PV cell having, on a left and right side, a first layer including a first semiconductor material, a second layer including the first semiconductor material disposed on the first layer, a third layer including the first semiconductor material disposed on the second layer, a fourth layer including the first semiconductor material disposed on the third layer, a fifth layer including the second semiconductor material disposed on the fourth layer, a sixth layer including the second semiconductor material disposed on the fifth layer, a seventh layer including a third semiconductor material disposed on the sixth layer, an eighth layer including the third semiconductor material disposed on the seventh layer, a first trench extending downward into the first layer, the first trench disposed to the left of the micro PV cell, a second trench extending downward into the second layer, the second trench disposed to the right of the micro PV cell, a third trench extending downward into the second layer, the third trench disposed to the left of the micro PV cell adjacent the first trench, a fourth trench extending downward into the fourth layer, the fourth trench disposed to the right of the micro PV cell adjacent the second trench, a first left shoulder disposed to the left of the micro PV cell at a bottom of the second trench, a second right shoulder disposed to the right of the micro PV cell at a bottom of the fourth trench, and an integrated monolithic bypass diode including a fourth layer disposed on the third layer. The common material is the first layer. [Brief explanation of the drawings]

[0011] [Figure 1] 1 shows a schematic plan view of an embodiment of a PV panel. [Figure 2A]

[0012] 1 shows a schematic plan view of one embodiment of a PV panel according to the present disclosure. [Figure 2B]

[0013] 2B shows a schematic plan view of one embodiment of an underlying electrical interconnection of the PV panel of FIG. 2A in accordance with the present disclosure. [Figure 3]

[0014] 2B shows a schematic cross-sectional side view of one embodiment of the PV panel of FIG. 2A in accordance with the present disclosure. [Figure 4A]

[0015] 1 shows a schematic plan view of one embodiment of a PV device according to the present disclosure. [Figure 4B]

[0016] 4B shows a schematic plan view of one example of a PV device according to the present disclosure, showing 45 micro PV cells connected in series of the device shown in FIG. 4A. [Figure 4C]

[0017] FIG. 4C shows a schematic plan view of one example of a PV device according to the present disclosure showing the continuous photocurrent path I flowing through the 45 serially serpentine-connected micro PV cells of the device shown in FIG. 4B. [Figure 5A]

[0018] 1 shows a schematic plan view of one embodiment of a pair of adjacent PV devices according to the present disclosure. [Figure 5B]

[0019] 5B shows a schematic enlarged plan view of one embodiment of an electrical connection between a pair of adjacent PV devices shown in FIG. 5A according to the present disclosure. [Figure 6A]

[0020] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure. [Figure 6B]

[0021] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure. [Figure 7A]

[0022] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a PV cell device comprising three multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series, according to the present disclosure. [Figure 7B]

[0023] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a PV cell device comprising three multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series, according to the present disclosure. [Figure 8A]

[0024] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure. [Figure 8B]

[0025] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure. [Figure 9A]

[0026] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a PV cell device comprising three multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series, according to the present disclosure. [Figure 9B]

[0027] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a PV cell device comprising three multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series, according to the present disclosure. [Figure 10A]

[0028] FIG. 1 shows a schematic cross-sectional side view of one embodiment of five multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series, according to the present disclosure. [Figure 10B]

[0029] FIG. 1 shows a schematic cross-sectional side view of one embodiment of five multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series (with a shadow micro PV cell) according to the present disclosure. [Figure 11]

[0030] 1 shows a schematic perspective view of an embodiment of an extraterrestrial satellite having a pair of satellite-mounted PV panels, where each PV panel comprises multiple multi-junction micro PV devices with integrated monolithic bypass diodes (too small to be seen) in accordance with the present disclosure. [Figure 12]

[0031] 1 illustrates an example of a flowchart showing steps for manufacturing a PV panel according to the present disclosure. [Figure 13A]

[0032] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure. [Figure 13B]

[0033] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure. [Figure 14A]

[0034] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a PV cell device comprising three multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series, according to the present disclosure. [Figure 14B]

[0035] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a PV cell device comprising three multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series, according to the present disclosure. [Figure 15A]

[0036] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure. [Figure 15B]

[0037] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell with an integrated monolithic bypass diode according to the present disclosure. [Figure 16A]

[0038] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a PV cell device comprising three multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series, according to the present disclosure. [Figure 16B]

[0039] FIG. 1 shows a schematic cross-sectional side view of one embodiment of a PV cell device comprising three multi-junction micro PV cells with integrated monolithic bypass diodes, all connected in series, according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012]

[0041] The terms "PV solar cell," "solar cell," and "cell" are used interchangeably. The terms "micro-PV cell" and "micro-cell" are used interchangeably. The terms "PV solar device," "solar device," and "device" are used interchangeably. Terms such as "first," "second," etc. refer to different positions in a structural element. The terms "right" and "right side" are interchangeable, and the terms "left" and "left side" are interchangeable, both of which refer to their respective positions when shown in the drawings.

[0013]

[0042] FIG. 2A shows a schematic plan view of one embodiment of a PV panel 58 according to the present disclosure. The PV panel 58 comprises a plurality of individual PV devices 64, 64′, 64″, etc. arranged in a regular array across a substrate 60. The graduated shading of each PV device 64, 64′, 64″, etc. indicates the presence of a local voltage gradient that varies across each device 64, 64′, 64″ from V− (lightly shaded zone) to V+ (heavily shaded zone). In other words, the shading from light to heavy follows the voltage gradient across an individual device (e.g., device 64). In this embodiment, the PV panel 58 includes five parallel rows and eight columns of devices 64, 64′, 64″, etc. for a total of 38 PV devices (note: two PV devices have been removed from the “stay-out zone” 68 to allow space for a tubular structural member 70). Each individual PV device 64, 64′, 64″, etc. is very small (e.g., less than 1 cm 2 ) "micro" PV cells (e.g., 45 micro PV cells not shown in this drawing), all connected in series to generate a high output voltage (e.g., 90V) across all devices 64, 64', 64", etc. In some embodiments, the devices fabricated may be approximately 150 cm 24A, 4B, and 4C. Each PV device 64, 64', 64" etc. includes a pair of electrical connectors (voltage tabs) 90 and 90' located at opposite corners of the device 64, and voltage tabs 91 and 91' located at opposite corners of the device 64'. Voltage tabs 90 and 91 conduct negative voltage, voltage tabs 90' and 91' conduct positive voltage, etc. Each PV device 64, 64', 64" etc. is illustrated as having a square shape with corners truncated. Other shapes of PV devices 64, 64', 64" etc. (including rectangular, triangular, or hexagonal shapes, or combinations thereof) can also be used.

[0014]

[0043] Still referring to FIG. 2A , the orientation of each row of eight devices 64, 64′, 64″, etc. is reversed in this example on alternate rows. In other words, the devices 64, 64′, 64″, etc. are arranged such that the V− regions of adjacent devices 66, 66′, 66″, etc. abut one another, and the V+ regions of adjacent devices abut one another. This alternating configuration minimizes problems with electrostatic discharge (ESD). An interdigitated array of electrical interconnects (obscured by the PV devices 64, 64′, 64″, etc.) comprising negative and positive electrical buses 62 and 63, respectively (shown in more detail in FIG. 2B below) is arranged underneath the 40 PV devices. The negative electrical bus 62 has a voltage=V−, while the positive electrical bus 63 has a voltage=V+. In this example, V−=0V and V+=90V. Each PV device 64, 64', 64" etc. produces a relatively higher voltage and a relatively lower photocurrent than a conventional PV cell. The devices are then connected in parallel, so that the entire solar panel produces a high voltage and a high photocurrent. The positive voltage tab 90' (V+) of each PV device 64, 64', 64" etc. is connected together across a given row of eight devices, and the negative voltage tab 90 (V-) of each PV device 64, 64', 64" etc. is connected together across the same row of eight devices. The entire PV panel 58 therefore produces a relatively high photocurrent at a high voltage (e.g., 90V).

[0015]

[0044] FIG. 2B shows a schematic plan view of one embodiment of an underlying electrical interconnect structure 71 of the PV panel 58 of FIG. 2A in accordance with the present disclosure. The interconnect structure 71 comprises pairs of interdigitated conductors disposed on an insulated structure 60 connected to a positive electrical bus 63 and a negative electrical bus 62. The positive bus 63 comprises three parallel stripes 72, 72′, and 72″ connected to the positive bus 63. The negative bus 62 comprises three parallel stripes 74, 74′, and 74″ connected to the negative bus 62. The three parallel stripes 74, 74′, and 74″ are disposed between (i.e., alternate between) the three positive parallel stripes 72, 72′, and 72″. A pair of PV devices 64 and 64′ is shown. Negative voltage tabs 90 and 91 are electrically connected to the negative stripes 74, and positive voltage tabs 90′ and 91″ are electrically connected to the positive stripes 72.

[0016]

[0045] FIG. 3 shows a schematic cross-sectional side view of one embodiment of the PV panel 58 of FIG. 2A in accordance with the present disclosure. By placing a conductor under the device 64, a larger exposed area can be devoted to power generation. The PV device 64 is adhered to the insulated substrate 60 at two locations with left and right strips of adhesive 80 and 80′, respectively. The adhesive strips 80 and 80′ can be, for example, approximately 6-10 mils thick. A gap 78 is defined by the device 64 and the substrate 60. A copper conductor 50 (which can be "2 oz." copper foil, ribbon, or wire) is positioned in the middle of the gap 78. The copper conductor 50 rests on an insulated polymer layer 86 (e.g., a polyimide such as Kapton®). The insulated polymer layer 86 can be, for example, approximately 1-2 mils thick. The copper conductor 50 is encased within an upper layer of adhesive 84. The upper adhesive layer 84 can be, for example, approximately 2-4 mils thick. An upper layer 82 of insulating polymer (e.g., Kapton®) is disposed on an upper layer 84 of adhesive. The insulating upper layer 82 may be, for example, approximately 1-2 mils thick. The insulated copper conductor 50 is partially embedded within the right strip of adhesive 80'. Materials such as DuPont Pyralux AP are suitable for Cu-clad Kapton®. This may be laminated with DuPont Pyralux LF, which is the adhesive layer on Kapton®. This material set is widely available from multiple suppliers and can be processed into this assembly. Similar materials based on polyimide, as well as PEEK and ETFE plastics, are available from multiple other vendors. Many adhesives are available for attaching such flexible circuits to panels. These may be acrylic-based adhesives such as 3M 9460PC or 3M 966, or silicone-based adhesives such as NUSIL CV4-1161-5. The thickness of the upper layer of adhesive 84 may be greater than that of the copper conductor 50 .

[0017]

[0046] 4A shows a schematic plan view of one embodiment of a PV device 64 according to the present disclosure. The device 64 comprises a plurality of semiconductor-based multi-layer junction micro PV cells 100, 102, 104, ..., 188 (i.e., two by two) defined by a square network of vertical trenches 92 and horizontal trenches 94. Electrically conducting voltage tabs 90 and 90' are located at opposite corners of the device 64.

[0018]

[0047] FIG. 4B shows a schematic plan view of one embodiment of a PV device according to the present disclosure, showing 45 micro PV cells 100, 102, 104, ..., 188, all connected in series, of the device shown in FIG. 4A. Electrically conductive voltage tabs 90 and 90' are located at the corners on either side of the device 64. Electrically conductive voltage tabs 96, 96', 96", etc. interconnect adjacent micro PV cells 100, 102, and 104, etc., respectively. Electrically conductive voltage tabs 98 and 98' interconnect pairs of corner micro PV cells 108-110 and 178-180, respectively. These voltage tabs may be metal conductors added to the completed PV device, for example, by wire or ribbon bonding. Alternatively, these conductors may be realized through multiple steps of patterning insulators and conductors during wafer fabrication.

[0019]

[0048] FIG. 4C illustrates a continuous photocurrent path 190I flowing through the 45 serially serpentine-connected micro PV cells 100, 102, 104, ..., 188 of the device shown in FIG. 4B in accordance with the present disclosure. device 1 shows a schematic plan view of an example of a PV device showing the structure of a multi-junction battery, for example, where each microbattery 100 is 1 cm in size. 2, each microcell 100 can generate approximately 20 mA of photocurrent. Thus, each microcell 100 generates approximately 20 mA of photocurrent, adding 2 V at an output of 0.04 W of power per microcell 100. This continues across 45 micro PV cells connected in series. Thus, in the lower right corner, the output voltage tab 90' of device 64 can provide power at 90 V with 20 mA flowing through the circuit at, for example, 1.8 W of power per device 64. For example, with eight devices 64, 64', etc. connected in parallel across a single horizontal row of PV panel 58 (see FIG. 2A), the parallel array of eight devices can generate 0.16 A at 90 V or 14 W of power. A solar panel 58 with five rows (with eight devices per row) can generate 0.8 A at 90 V or 72 W of power. A series array such as 45 micro PV cells 100, 102, 104 producing 90V is called a "device" and each subunit producing 2V is called a "micro PV cell" or "microbattery." The term "microbattery" refers to a cell measuring approximately 1 cm 2 This refers to a solar cell of this size (area).

[0020]

[0049] Solar cells can be shadowed in orbit. When shadowed, the circuit voltage reverse-biases the cell. Thus, typical shadowing would result in reverse-biasing the solar cell device by 40V in this example. The breakdown voltage of a triple-junction PV cell is ∼20V, so reverse biasing would damage the device. Bypass diodes for each solar cell device can prevent this damage, as will be further explained in Figure 6.

[0021]

[0050] FIG. 5A shows a schematic plan view of one embodiment of a pair of adjacent PV devices 64 and 64′ according to the present disclosure. The area defined by the dashed circle 200 is shown enlarged in FIG. 5B. The pair of devices 64 and 64′ are electrically interconnected to extensions 97 and 97′ of the negative stripe 74 via voltage tabs 90 and 91, respectively. The pair of devices 64 and 64′ are electrically interconnected to the positive stripe 72 via tabs 90′ and 91′. The electrical stripes 74 and 72 are disposed on polymer strips 95 and 95′, respectively. A discrete blocking diode 218 is connected to the right ribbon 216′, which is connected to the conductive extension 212 of the positive stripe 72.

[0022]

[0051] 5B shows a schematic, enlarged, top view of one embodiment of an electrical connection 200 between a pair of adjacent PV devices 64 and 64′ shown in FIG. 5A in accordance with the present disclosure. PV device 64 is connected to positive electrical stripe 72 via voltage tab 90′. Voltage tab 90′ is connected to conductor 220. Conductor 220 is connected to left ribbon 216. Left ribbon 216 is connected to individual blocking diodes 218. Individual blocking diodes 218 are connected to right ribbon 216′. Right ribbon 216′ is connected to conductive extension 212 of positive stripe 72. Blocking diodes placed between the PV device and the bus are an industry standard used to protect parallel devices in the event that one of these devices fails.

[0023]

[0052] FIG. 6A shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell 100 having an integrated monolithic bypass diode 10 according to the present disclosure. The P-doped first layer 12 having a width = E includes a first semiconductor material and serves as a substrate for fabricating the micro cell 100 thereon. The N-doped second layer 14 having a width = A includes the first semiconductor material and is disposed on the P-doped first layer 12. The multi-junction PV cell stack 16 having a width = B is disposed on the N-doped second layer 14. The first vertical trench 22 having a width = D extends downward into the left side of the P-doped first layer 12. The second vertical trench 22' having a width = D extends downward into the right side of the P-doped first layer 12. The third vertical trench 52 having a width = C extends downward into the N-doped second layer 14 on the right side of the layer 14. Solar light 20 impinges on the upper surface 18 of the PV cell stack 16 and generates a photocurrent I pc thereby. The PN junction 15 is disposed between the P-doped first layer 12 and the N-doped second layer 14. The bypass diode 10 includes the PN junction 15. The first shoulder 26 is disposed on the left side of the N-doped second layer 14, and the second shoulder 24 is disposed on the right side of the N-doped second layer 14. The multi-junction PV cell stack 16 may include one or two or three or more PN junctions. A < E, B < A, C < B, D < B, A = B + C, and E = B + C + 2D.

[0024]

[0053] FIG. 6B shows a schematic cross-sectional side view of one embodiment of a single multijunction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure. The stack shows two solar cell PN junctions on top of the bypass diode PN junction. Both the solar cell and the bypass junction have N-on-P polarity. A P-doped first layer 12 having a width=E includes germanium (Ge) and serves as a substrate for fabricating the microbattery 100 thereon. An N-doped second layer 14 having a width=A includes Ge and is disposed on the P-doped first layer 12. A multijunction PV cell stack 16 having a width=B is disposed on the N-doped second layer 14. The PV cell stack 16 includes four stacked semiconductor layers 42, 44, 46, and 48. A P-doped third layer 42 having a width=B comprises gallium arsenide (GaAs) and is disposed on the N-doped second layer 14. An N-doped fourth layer 44 having a width=B comprises gallium arsenide (GaAs) and is disposed on the P-doped third layer 42. A P-doped fifth layer 46 having a width=B comprises indium gallium phosphide (InGaP) and is disposed on the N-doped fourth layer 44. An N-doped sixth layer 48 having a width=B comprises indium gallium phosphide (InGaP) and is disposed on the P-doped fifth layer 46.

[0025]

[0054] The embodiment shown in FIG. 6B is nearly identical to a typical triple-junction solar cell. The difference is the wiring. The negative connection is typically from the sun-facing surface (N-side). The positive connection is from the N-side of the bottom PN junction (24) rather than the typical bottom P-side. This wiring configuration allows the bottom PN junction to function as a bypass diode. The Ge structure of the triple-junction solar cell has now changed. The Ge layer no longer acts as a third solar cell, but rather is used to fabricate the bypass diode 10. The top and middle PN junctions, comprised of layers 48 and 46 and 44 and 42, are constructed with the N-side of the PN junction facing toward the sun. Light absorbed within the top and middle PV cells generates a photocurrent I that flows toward the P-doped (Ge) first layer 12. pc The top and middle cells are joined by a tunnel junction (not shown). Similarly, the bottom P-side of the middle cell is followed by a tunnel junction connection to the N-doped (Ge) second layer 14. Thus, photocurrent flows into the N-doped (Ge) second layer 14.

[0026]

[0055] Still referring to FIG. 6B , the Ge wafer (first layer 12) is etched and fabricated with micro PV cells 100 on their own mesas. Each mesa is an individual multijunction micro PV cell 100. The P-doped Ge first layer 12 is underneath the N-doped Ge second layer 14. This PN Ge diode blocks photocurrent flow from the multijunction micro PV cell 100 from entering the P-doped Ge first layer 12. The mesas are etched into and through the N-doped Ge second layer 14. Thus, each multijunction microcell 100 generates photocurrent individually. The sides of the mesas will have stepped edges (shoulders 24) where a portion of the N-doped Ge second layer 14 is exposed. An electrical connection is made between the N-doped Ge second layer 14 and the top surface 18' of the N-type upper cell electrode of an adjacent micro PV cell 102 (see FIG. 7B). This allows many multi-junction micro PV cells 100, 102, 104, etc. to be connected in series to produce higher output voltages. These micro PV cells 100, 102, 104, etc. are all disposed on a single common Ge substrate 12. This common Ge substrate defines a device 64 having many multi-junction micro PV cells 100, 102, 104, etc. connected in series.

[0027]

[0056] Still referring to FIG. 6B , a first vertical trench 22 having a width=D extends into the left side of the P-doped first Ge layer 12. A second vertical trench 22′ having a width=D extends into the right side of the P-doped first germanium layer 12. A third vertical trench 52 having a width=C extends into the N-doped second Ge layer 14 on the right side of layer 14. Sunlight 20 impinges on the top surface 18 of the PV cell stack 16. A PN junction 15 is disposed between the P-doped first Ge layer 12 and the N-doped second Ge layer 14. A bypass diode 10 includes the PN junction 15. A first shoulder 26 is disposed on the left side of the N-doped second Ge layer 14, and a second shoulder 24 is disposed on the right side of the N-doped second Ge layer 14.

[0028]

[0057] FIG. 7A shows a schematic cross-sectional side view of an embodiment of a PV cell device 64 comprising three multi-junction micro PV cells 100, 102, 104 having integrated monolithic bypass diodes 10, 10', 10'' all connected in series. A P-doped first layer 12 having a width = F and containing a first semiconductor material is used as a common substrate 600 (i.e., the P-doped first layer 12) for supporting the three micro PV cells 100, 102, 104. The first micro cell 100 comprises a first PV cell stack 16 having a width = B disposed on an N-doped second layer 14 having a width = A. The N-doped second layer is disposed on the P-doped first layer 12. The micro PV cells 102 and 104 are identical to the macro cell 100 and their description will not be repeated.

[0029]

[0058] Still referring to FIG. 7A, a first conductor 28 connects a first shoulder 26 on the left side of the P-doped first layer 12 to the upper surface 18 of the PV cell stack 16. A second conductor 30 connects a right shoulder 24 on the N-doped second layer 14 to the upper surface 18' of a second PV cell stack 16' (of the micro cell 102). A third conductor 30' connects a right shoulder 24' on the N-doped second layer 14' to the upper surface 18'' of a third PV cell stack 16'' (of the micro cell 104). Thus, the micro PV cells 100, 102, and 104 are all connected in series. Note that V1 < V2 < V3. Conductor 30'' is the positive voltage end of this circuit and extends to an electrical load, which is not shown. Conductor 31 is the negative voltage end of this circuit and extends to an electrical load, which is not shown.

[0030]

[0059] 7B shows a schematic cross-sectional side view of one embodiment of a PV cell device 64 comprising three multi-junction micro PV cells 100, 102, 104, all connected in series, with integrated monolithic bypass diodes, in accordance with the present disclosure. The micro PV cells 100, 102, and 104 and interconnections are identical to the micro PV cells 100, 102, and 104 shown in FIG. 7A, with the following differences: The PV cell stacks 16, 16', and 16" of FIG. 7B are identical to the PV stack 16 previously described in FIG. 6B; therefore, those details will not be repeated here.

[0031]

[0060] Still referring to FIG. 7B, the multi-junction micro PV cells 100, 102, 104 each have their own integrated monolithic bypass diode 10, 10', 10" built in, respectively. A P-doped substrate 12 is placed under each micro PV cell 100, 102, 104 and is connected to a V-bus (not shown, this is realized by an added wire 31 alongside the conductor 28). The N-doped Ge second layer 14 of each micro PV cell is at a more positive voltage. Therefore, the Ge PN junction is reverse biased and no photocurrent flows. When any micro PV cell is in shadow, photocurrent no longer flows through the micro cell. The device is then negatively biased from the other illuminated micro PV cells of the device, and the Ge PN junction of the dark micro cell becomes forward biased with photocurrent flow. The photocurrent I of the circuit pcis maintained by the Ge PN bypass diodes, preventing a dangerous reverse bias condition of the microbattery. The Ge bypass diodes 10, 10', 10" bypass all batteries from the V- side of the circuit to the dark (shaded) microbattery (e.g., microbattery 102). If a microbattery is shaded, the output voltage of the circuit will drop. Devices 64, 64', etc. will be protected, and if the light comes back on, the output voltage and power will return. In other words, a shaded microbattery 100 risks having a dangerous reverse bias of the circuit minus the dark microbattery or microPV battery. Thus, one embodiment of a device with 45 microbatteries might have one dark microbattery with a reverse bias of 88V. The bypass diodes reduce this reverse bias to the voltage of the bypass diode, which for a Ge diode is ∼0.2V.

[0032]

[0061] A bypass junction composed of a Ge PN junction is similar to a conventional multijunction solar cell and is easily formed. The Ge PN junction may have limited capability as a bypass diode. The Ge bypass diode may not need to be photoactive. Also, the bypass diode may require a reverse breakdown voltage greater than the circuit voltage. When all three micro PV cells in FIG. 7B are operated, the operating bias diode 10″ will be reverse biased at 4 V. In practical applications, the circuit voltage may be 20 V, 100 V, or even higher. It is difficult to have a Ge PN junction with a breakdown voltage at this level. A bypass diode made from GaAs or InGaP would have a greater breakdown voltage than Ge. Therefore, the second layer 14 can be replaced with a GaAs or InGaP PN junction. Replacing the P-doped first layer 12 with a semi-insulating (SI) GaAs first layer 12 further improves circuit protection and operation.

[0033]

[0062] FIG. 8A shows a schematic cross-sectional side view of an example of a single multi-junction micro PV cell 100 having an integrated monolithic bypass diode 10 according to the present disclosure. A first semi-insulating (SI) layer 412 having a width = G includes a first semiconductor material and serves as a substrate for fabricating the micro cell 100 thereon. By changing to a semi-insulating substrate (the first SI layer 412), the flow of photocurrent between adjacent micro PV cells 100, 102, 104, etc. is prevented. An N-doped second layer 14 having a width = A includes the first semiconductor material and is disposed on the first SI layer 412. A P-doped third layer 32 having a width = E includes a second semiconductor material and is disposed on the N-doped second layer 14. An N-doped fourth layer 34 having a width = E includes a second semiconductor material and is disposed on the P-doped third layer 32. A multi-junction PV cell stack 16 having a width = B is disposed on the N-doped fourth layer 34 and may include one or two or three PN junctions.

[0034]

[0063] Still referring to FIG. 8A, a first vertical trench 22 having a width = F extends into the left side of the first SI layer 412. A second vertical trench 22' having a width = F extends into the right side of the first SI layer 412. A third vertical trench 36 having a width = C extends into the N-doped second layer 14 on the right side of layer 14. A fourth vertical trench 38 having a width = D extends into the N-doped fourth layer 34 on the right side of layer 34. Sunlight 20 impinges on the upper surface 18 of the PV cell stack 16. A PN junction 17 is disposed between the P-doped third layer 32 and the N-doped fourth layer 34. The bypass diode 10 includes the PN junction 17. A first shoulder 26 is disposed on the left side of the first SI layer 412, and a second shoulder 26' is disposed on the right side of the first SI layer 412. A third shoulder 54 is disposed on the left side of the N-doped second layer 14. A fourth shoulder 40 is disposed on the right side of the N-doped fourth layer 34. The multi-junction PV cell stack 16 may include one, two, or three PN junctions. A < E, B < A, C < B, D < B, E < G, E = B + D, A = C + B + D + 2F, and G = B + C + 2F.

[0035]

[0064] 8B shows a schematic cross-sectional side view of one embodiment of a single multijunction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure. A multijunction PV cell stack 16 having a width=B is disposed on an N-doped fourth layer 34 and includes four semiconductor layers 42, 44, 46, and 48. A P-doped fifth layer 42 having a width=B comprises gallium arsenide (GaAs) and is disposed on the N-doped GaAs fourth layer 34. An N-doped sixth layer 44 having a width=B comprises gallium arsenide (GaAs) and is disposed on the P-doped GaAs fifth layer 42. A P-doped seventh layer 46 having a width=B comprises indium gallium phosphide (InGaP) and is disposed on the N-doped GaAs sixth layer 44. An N-doped eighth layer 48 having a width=B comprises indium gallium phosphide (InGaP) and is disposed on the P-doped seventh layer 46 of InGaP.

[0036]

[0065] Still referring to FIG. 8B, this embodiment achieves a higher breakdown voltage, and each micro PV cell 100 is independently bypassed. This is achieved by using a semi-insulating GaAs substrate 412. Each micro PV cell 100 is an InGaP+GaAs multi-junction N-on-P micro PV cell. The bypass diode 10 is an N-on-P GaAs diode. Each mesa has a micro PV cell 100 electrically connected in parallel with the bypass diode 10. When the micro PV cell 100 does not conduct photocurrent, the bypass diode 10 allows photocurrent to flow. The substrate (first SI layer 412) can be lightly doped or semi-insulating GaAs to prevent photocurrent flow within the substrate (first SI layer 412). Note that shoulders 40 and 54 are used for electrical connection to adjacent micro PV cells. The micro PV cells (~1 cm 2) travels laterally to these connection points. Therefore, the sheet resistance of layers 34 and 14 needs to be low to have low voltage losses. The mobility of n-GaAs is much higher than that of p-GaAs, resulting in a much lower sheet resistance for n-GaAs when carrying current laterally. Connection 54 could also be made to layer 32, but would have a higher voltage loss across p-GaAs layer 32. The addition of the tunnel junction and n-GaAs layer 14 reduces this resistance and voltage drop.

[0037]

[0066] FIG. 9A shows a schematic cross-sectional side view of one embodiment of a PV cell device 64 comprising three multi-junction micro PV cells 100, 102, 104, all connected in series, each with an integrated monolithic bypass diode 10, 10′, 10″, in accordance with the present disclosure. Each micro PV cell 100, 102, 104 has the same design as that shown in FIG. 8A, except that the semiconductor layer 412 of the first SI extends across the base of all three micro PV cells 100, 102, 104 (i.e., common substrate 600). In FIG. 9A, the first conductor 28 is connected to the third junction of the first micro PV cell 100. The microcell 100 has a shoulder 54 interconnected to the top surface 18 of the PV cell stack 16. A second conductor 76 interconnects the fourth shoulder 40 of the microcell 100 to the top surface 18' of the second microcell 102. A third conductor 78 interconnects the fourth shoulder 40 to the third shoulder 54' of the second microcell 102. The conductor 76 carries the photocurrent between the series-connected solar cells, while the conductor 78 connects the micro PV cell 100 to the bypass diode 10'. These interconnections are repeated for the next set of connections between the second microcell 102 and the third microcell 104, which are all connected in series. Note, V1 <V2<V3である。

[0038]

[0067] 9B shows a schematic cross-sectional side view of one embodiment of a PV cell device 64 comprising three multi-junction micro PV cells 100, 102, 104, all connected in series, with integrated monolithic bypass diodes, in accordance with the present disclosure. The micro PV cells 100, 102, and 104 and interconnections are identical to the micro PV cells 100, 102, and 104 shown in FIG. 9A, with the following differences: The PV cell stacks 16, 16', and 16" of FIG. 9B are identical to the PV stack 16 previously described in FIG. 8B; therefore, those details will not be repeated here.

[0039]

[0068] The wiring between the micro PV cells and the bypass diodes can be achieved by wafer fabrication processes, by wire or ribbon bonding processes, printed metal, or other approaches known for device fabrication. Each micro PV cell 100, 102, 104 has a GaAs PN bypass diode 10, 10', 10", respectively, below the PV cell stack 16.

[0040]

[0069] FIG. 10A shows a schematic cross-sectional side view of one embodiment of a PV cell device 64 comprising five multi-junction micro PV cells 100, 102, 104, 106, and 108 with integrated monolithic bypass diodes 10, 10′, 10″, 10′′, and 10′″, respectively, all connected in series in accordance with the present disclosure. The five micro PV cells 100, 102, 104, 106, and 108 have the same structure and electrical interconnections as previously described in FIGS. 6A and 7A and will not be described further here. Each micro cell produces approximately 2 volts per cell, and the final voltage of the last micro cell 108 in the series of five micro PV cells 100, 102, 104, 106, and 108 is equal to 10 V when all micro PV cells are fully illuminated with light.

[0041]

[0070] FIG. 10B shows a schematic cross-sectional side view of one embodiment of a PV cell device 64 comprising five multi-junction micro PV cells 100, 102, 104, 106, and 108, each with an integrated monolithic bypass diode 10, 10', 10", 10"', 10"", all connected in series (with a single shaded micro PV cell 106), in accordance with the present disclosure. In this embodiment, the bypass diode 10"' is activated when the fourth micro cell 106 is shaded. The bypass diode 10"' prevents reverse biasing of the shaded micro cell 106 in this situation. This reduces the photocurrent I pc This results in current flowing in a bypass through the shaded microcell 106. The p-Ge SI first layer 412 is common to all bypass diodes. Thus, all micro PV cells are bypassed from the V-side to the dark microcell. In this example, the bypass current flows along the dashed arrow line through the p-Ge SI first layer 412, which bypasses the microcells 100, 102, 104, 106. The bypass current flows through the first layer 412 of p-Ge SI, and then the dark microcell 106 forward biases 10", and then the bypass current transfers to the remaining illuminated micro PV cell, which in this example is microcell 108. Assuming V minus is 0V, the voltage drop across the bypass diode results in a negative voltage on the negative side of the microcell 108. If the bypass diode is GaAs, the voltage will be close to -1V. The illuminated microcell 108 then adds 2V, resulting in the circuit producing 1V. This is a much lower voltage and much lower output power. But this is only when it is shaded. Since the circuit is fully protected, when the shade is removed the circuit will return to full power. Also, with this novel configuration, the 90V circuit can be driven at 150cm 2 This area is much smaller than that of a conventional solar array.

[0042]

[0071] In some embodiments with a semi-insulated substrate, each micro PV cell has one wire carrying the photocurrent at the negative and positive ends. The bypass current is carried through the substrate 412 to the dark cell. Because the SI substrate 412 does not allow current to flow, a third conductor 78 is needed between the micro PV cells. Each bypass diode is now independent of the substrate 412, and it is easier to use GaAs or InGaP materials to fabricate high-quality bypass diodes with low leakage current and high breakdown voltage. Each bypass diode is now connected to the adjacent cell. When the circuit is operating normally, each bypass diode will be reverse-biased by the micro cell, which is close to 2 V. Any reverse-bias leakage current through the bypass diode reduces the power output of the circuit, and it is important to minimize this. The SI substrate 412 results in a reverse bias of the bypass diode at 2 V, where the leakage current is low. A configuration with a P-doped Ge substrate 412 results in a reverse bias of the bypass diode as high as the circuit voltage, leading to a larger leakage current.

[0043]

[0072] In some embodiments, a metallization on the backside of the P-doped first layer 12 is not used or needed.

[0044]

[0073] In some embodiments, each micro PV cell has an embedded Ge PN junction that is a bypass diode.

[0045]

[0074] 11 shows a schematic perspective view of one embodiment of an extraterrestrial satellite 500 having a pair of PV panels 510, 510' mounted on the satellite 500, each having a pair of structural members 520, 520', in accordance with the present disclosure, where each PV panel 510, 510' comprises a plurality of multi-junction micro PV devices 64, 64', etc. with integrated monolithic bypass diodes (too small to be seen). The PV devices 64, 64', etc. are fabricated using the same configurations and semiconductor processes disclosed herein.

[0046]

[0075] One example of method steps for manufacturing a PV panel 58 using micro PV cells 100, 102, 104, etc. with integrated monolithic bypass diodes 10, 10′, and 10″, respectively, is as follows (with reference to FIGS. 6A and 7A):

[0076] Step 300: Provide a P-doped Ge wafer.

[0077] Step 310 forms a second layer of N-doped Ge on the P-doped Ge wafer.

[0078] Step 320: Fabricate a multi-junction PV cell stack having 1 to 3 PNs. Step 330 Epitaxially etch pads for subsequent ribbon bonding.

[0080] Step 340 mesa cuts trenches through the second layer of N-doped Ge down into the P-doped Ge wafer.

[0081] Step 350 deposits frontside metal on the second layer of N-doped Ge.

[0082] Step 360 ribbon-bonds multiple micro PVs in series.

[0083] Step 370 Dice individual devices into a plurality of cut squares from the fabricated P-doped Ge wafer.

[0084] Step 380 welds interconnects between the cut out squares.

[0085] Step 390 assembles the interconnected devices into a solar panel.

[0086] Step 400: Encapsulate the assembled solar panel.

[0047]

[0087] FIG. 12 shows one embodiment of a flow chart illustrating the steps 300 through 400 outlined above for manufacturing a PV panel 58.

[0048]

[0088] FIG. 13A shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure. This embodiment is identical to that shown in FIG. 6A with the following differences: An additional semiconductor layer (layer 56) is inserted between the second layer 14 and the PV cell stack 16. In this embodiment, the second layer 14 may include a P-doped second semiconductor material, and the additional layer 56 may include an N-doped layer of the same second semiconductor material. A PN junction 19 can be seen, located at the interconnection of the second layer 14 and the third layer 56. The multi-junction PV cell stack 16 may include one, two, or three PN junctions.

[0049]

[0089] FIG. 13B shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure. This embodiment is identical to that shown in FIG. 6B, with the following differences: Here, an additional layer (i.e., third layer 56) is inserted between the second layer 14 and the bottom layer 42 of the PV cell stack 16. In this embodiment, the second semiconductor material is GaAs. The first layer 12 is P-doped Ge, the second layer 14 is P-doped GaAs (rather than N-doped Ge as in previous embodiments), and the third layer 56 is N-doped GaAs. The total number of layers is increased to seven because of the additional layer 56 inserted in the micro PV cell 100. The bypass diode 10 includes a GaAs PN junction 19. The GaAs PN junction 19 comprises the interconnection of the second layer 14 of P-doped GaAs and the third layer 56 of N-doped GaAs.

[0050]

[0090] Still referring to FIG. 13B, the use of the GaAs bypass diode 10 in FIG. 13B provides a significantly higher breakdown voltage than the Ge PN diode 10 previously used in FIG. 6B. To prevent light from illuminating the GaAs bypass diode 10, the GaAs second micro PV cell (i.e., layers 42 and 44) may have a sufficient thickness to effectively block incident light 20 from reaching the GaAs bypass diode 10. Alternatively, or in addition, a distributed Bragg reflector (DBR) (not shown) may be inserted above the GaAs bypass diode 10 to prevent unwanted illumination of the GaAs bypass diode 10. The P-doped GaAs of the bypass diode 10 allows photocurrent flow into the Ge substrate 12. This may be achieved using the P-doped Ge substrate layer 12.

[0051]

[0091] FIG. 14A shows a schematic cross-sectional side view of one embodiment of a PV cell device 64 comprising three multi-junction micro PV cells 100, 102, 104 with integrated monolithic bypass diodes 10, 10′, 10″, all connected in series, in accordance with the present disclosure. FIG. 14A is identical to FIG. 7A with the following difference: an additional semiconductor layer (layer 56) is inserted between the second layer 14 and the PV cell stack 16. In this embodiment, the second layer 14 may comprise a P-doped second semiconductor material, and the additional layer 56 may comprise an N-doped layer of the same second semiconductor material.

[0052]

[0092] FIG. 14B shows a schematic cross-sectional side view of one embodiment of a PV cell device 64 comprising three multijunction micro PV cells 100, 102, 104 with integrated monolithic bypass diodes 10, 10′, 10″ all connected in series according to the present disclosure. FIG. 14B is identical to FIG. 7A with the following difference: in this embodiment, the second semiconductor material is GaAs. Here, an N-doped GaAs layer 56 is inserted between the P-doped GaAs second layer 14 and the P-doped GaAs fourth layer 42. The total number of layers is increased to seven because of the additional layer 56 inserted in the micro PV cell 100.

[0053]

[0093] 15A shows a schematic cross-sectional side view of one embodiment of a single multijunction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure. A semi-insulating (SI) first layer 412 having a width = G includes a first semiconductor material and serves as a substrate for fabricating the microbattery 100 thereon. An N-doped second layer 14 having a width = A includes a second semiconductor material and is disposed on the SI first layer 12. A P-doped third layer 32 having a width = E includes a P-doped second semiconductor material and is disposed on the N-doped second layer 14. An N-doped fourth layer 34 having a width = E includes a second semiconductor material and is disposed on the P-doped third layer 32. A multijunction PV cell stack 16 having a width = B is disposed on the N-doped fourth layer 34, and the stack 16 may include one, two, or three PN junctions. Other features of Figure 15A are the same as Figure 8A and will not be repeated here.

[0054]

[0094] Figure 15B shows a schematic cross-sectional side view of one embodiment of a single multi-junction micro PV cell 100 with an integrated monolithic bypass diode 10 according to the present disclosure. This embodiment is identical to that shown in Figure 8B, with the following differences: In this embodiment, the first and second semiconductor materials are both GaAs. The second layer 14 is P-doped GaAs (rather than N-doped GaAs as in Figure 8B).

[0055]

[0095] Figure 16A shows a schematic cross-sectional side view of an embodiment of a PV cell device 64 comprising three multi-junction micro PV cells 100, 102, 104 each having integrated monolithic bypass diodes 10, 10', 10'' all connected in series. Each micro PV cell 100, 102, 104 has the same design as that shown in Figure 8A, but differs as follows. That is, the first SI semiconductor layer 12 extends across the bases of all three micro PV cells 100, 102, 104 (i.e., a common substrate 600). In Figure 16A, a first conductor 28 interconnects the third shoulder 54 of the first micro cell 100 to the upper surface 18 of the PV cell stack 16. A second conductor 76 interconnects the fourth shoulder 40 of micro cell 100 to the upper surface 18' of the second micro cell 102. A third conductor 78 interconnects the fourth shoulder 40 to the third shoulder 54' of the second micro cell 102. These interconnects are repeated for the next set of connections between the second micro cell 102 and the third micro cell 104. These are all connected in series. Note, V1 < V2 < V3. In this embodiment, the second layers 14, 14', 14'' contain a P-doped second semiconductor material.

[0056]

[0096] Figure 16B shows a schematic cross-sectional side view of an embodiment of a PV cell device 64 comprising three multi-junction micro PV cells 100, 102, 104 having integrated monolithic bypass diodes all connected in series. The micro PV cells 100, 102, and 104 and the interconnects are the same as the micro PV cells 100, 102, and 104 shown in Figure 9A, but have the following differences. The PV cell stacks 16, 16', and 16'' in Figure 16B are the same as the PV stack 16 previously described in Figure 9B. In this embodiment, the second layers 14, 14', 14'' are P-doped GaAs (not N-doped GaAs as in Figure 9B).

[0057]

[0097] In some embodiments, the surface area of an individual micro PV cell exposed to the sun (or other light source) is about 0.5 to about 2 cm 2 In some embodiments, the surface area of an individual micro PV cell can range from about 1 cm 2 It can be the following:

[0058]

[0098] In some embodiments, the surface area of an individual PV device exposed to the sun (or other light source) is between about 20 and about 100 cm 2 In some embodiments, the surface area of an individual PV device may range from about 45 cm 2 It could be more than that.

[0059]

[0099] Furthermore, the present disclosure provides the following embodiments.

[0060] [000100] Example 1. A photovoltaic (PV) micro PV cell having a right side and a left side, a first layer including a P-doped first semiconductor material, a second layer including an N-doped first semiconductor material disposed on the first layer, a multi-junction micro PV cell stack disposed on a portion of the second layer, a first trench extending downward into the first layer, the first trench disposed to the left of the micro PV cell, a second trench extending downward into the first layer, the second trench disposed to the right of the micro PV cell, a third trench disposed adjacent to and extending downward into the second layer, the third trench disposed to the right of the micro PV cell adjacent to the left of the second trench; a first left shoulder disposed to the left of the micro PV cell at a bottom of the first trench; a second right shoulder disposed to the right of the micro PV cell at a bottom of the third trench; and an integrated monolithic bypass diode including a buried PN junction disposed between the second layer and the first layer.

[0061] [000101] Example 2. The micro PV cell of embodiment 1, wherein the multi-junction micro PV cell stack includes one, two, or three PN junctions.

[0062] [000102] Example 3. The micro PV cell of Examples 1 or 2, wherein no metal is disposed on a backside of the first layer.

[0063] [000103] Example 4. 4. The micro PV cell of any one of Examples 1 to 3, further comprising: a third layer comprising a P-doped second semiconductor material disposed on the second layer; a fourth layer comprising an N-doped second semiconductor material disposed on the third layer; a fifth layer comprising a P-doped third semiconductor material disposed on the fourth layer; and a sixth layer comprising an N-doped third semiconductor material disposed on the fifth layer.

[0064] [000104] Example 5a. 5. The micro PV cell of example 4, wherein the first layer comprises P-doped Ge, the second layer comprises N-doped Ge, the third layer comprises P-doped GaAs, the fourth layer comprises N-doped GaAs, the fifth layer comprises P-doped InGaP, and the sixth layer comprises N-doped InGaP.

[0065] [000105] Example 5b. 5. The micro PV cell of example 4, wherein the first layer comprises P-doped Ge, the second layer comprises N-doped GaAs on P-doped GaAs, the third layer comprises P-doped GaAs, the fourth layer comprises N-doped GaAs, the fifth layer comprises P-doped InGaP, and the sixth layer comprises N-doped InGaP.

[0066] [000106] Example 6. 1. A photovoltaic (PV) micro PV cell, comprising: a left and right side, a first layer comprising a semi-insulating first semiconductor material; a second layer disposed on the first layer, the second layer comprising an N-doped first semiconductor material; a third layer disposed on the second layer, the second layer comprising a P-doped first semiconductor material; a fourth layer disposed on the third layer, the fourth layer comprising an N-doped first semiconductor material; a fifth layer disposed on the fourth layer, the fifth layer comprising a P-doped second semiconductor material; a sixth layer disposed on the fifth layer, the fifth layer comprising an N-doped second semiconductor material; a seventh layer disposed on the sixth layer, the sixth layer comprising a P-doped third semiconductor material; an eighth layer disposed on the seventh layer, the eighth layer comprising an N-doped third semiconductor material; a first trench extending downward into the first layer, the eighth trench being disposed on the left side of the micro PV cell. a first trench, a second trench extending downward into the first layer and disposed to the right of the micro PV cell; a third trench extending downward into the second layer and disposed to the left of the micro PV cell adjacent the first trench; a fourth trench extending downward into the fourth layer and disposed to the right of the micro PV cell adjacent the second trench; a first left shoulder disposed to the left of the micro PV cell at a bottom of the second trench; a second right shoulder disposed to the right of the micro PV cell at a bottom of the fourth trench; and an integrated monolithic bypass diode including a buried PN junction disposed between the fourth layer and the third layer.

[0067] [000107] Example 7. The micro PV cell of example 6, wherein the first semiconductor material comprises GaAs, the second semiconductor material comprises GaAs, and the third semiconductor material comprises InGaP.

[0068] [000108] Example 8. 8. The micro PV cell of Examples 6 or 7, wherein the first layer comprises semi-insulating GaAs, the second layer comprises N-doped GaAs, the third layer comprises P-doped GaAs, the fourth layer comprises N-doped GaAs, the fifth layer comprises P-doped GaAs, the sixth layer comprises N-doped GaAs, the seventh layer comprises P-doped InGaP, and the eighth layer comprises N-doped InGaP.

[0069] [000109] Example 9. 9. The micro PV cell of any one of Examples 6 to 8, wherein the first layer comprises semi-insulating GaAs, the second layer comprises P-doped GaAs, the third layer comprises P-doped GaAs, the fourth layer comprises N-doped GaAs, the fifth layer comprises P-doped GaAs, the sixth layer comprises N-doped GaAs, the seventh layer comprises P-doped InGaP, and the eighth layer comprises N-doped InGaP.

[0070] [000110] Example 10. A photovoltaic (PV) device comprising a string of at least three micro PV cells having identical layer structures connected in series, the string comprising a first micro PV cell disposed on a common substrate, a second micro PV cell disposed on the common substrate and electrically connected in series with the first micro PV cell, and a third micro PV cell disposed on the common substrate and electrically connected in series with the second micro PV cell, each of the first, second, and third micro PV cells having a right side, a left side, a P-doped a first layer including a first semiconductor material that is N-doped; a second layer including a first semiconductor material that is N-doped and disposed on the first layer; a multi-junction micro PV cell stack disposed on a portion of the second layer; a first trench extending downward into the first layer, the first trench disposed to the left of the micro PV cell; a second trench extending downward into the first layer, the second trench disposed to the right of the micro PV cell; a third trench disposed adjacent the second trench and extending downward into the second layer. a third trench disposed on a right side of the micro PV cell adjacent to a left side of the second trench; a first left shoulder disposed on a left side of the micro PV cell at a bottom of the first trench; a second right shoulder disposed on a right side of the micro PV cell at a bottom of the third trench; an integrated monolithic bypass diode including a buried PN junction disposed between the second layer and the first layer, wherein the first micro PV cell includes a first top surface; and the second micro PV cell includes: a third micro PV cell including a third top surface, the string further including a first conductor electrically connecting the first layer to the first top surface of the first micro PV cell, a second conductor electrically connecting the right second shoulder of the first micro PV cell to the second top surface of the second micro PV cell, and a third conductor electrically connecting the right second shoulder of the second micro PV cell to the third surface of the third micro PV cell, and the common material is the first layer.

[0071] [000111] Example 11. The PV device of example 10, wherein the PV device is configured to be mounted on a photovoltaic microsolar panel of an extraterrestrial satellite.

[0072] [000112] Example 12. 12. The PV device of example 10 or 11, wherein the multi-junction micro PV cell stack of each micro PV cell comprises: a third layer comprising a P-doped second semiconductor material disposed on the second layer; a fourth layer comprising an N-doped second semiconductor material disposed on the third layer; a fifth layer comprising a P-doped third semiconductor material disposed on the fourth layer; and a sixth layer comprising an N-doped third semiconductor material disposed on the fifth layer.

[0073] [000113] Example 13. 13. The PV device of example 12, wherein the first layer comprises P-doped Ge and the second layer of each micro PV cell comprises N-doped Ge.

[0074] [000114] Example 14. 14. The PV device of example 12 or 13, wherein the second semiconductor material comprises GaAs and the third semiconductor material comprises GaAs.

[0075] [000115] Example 15. 15. The PV device of any one of Examples 12 to 14, wherein the first layer comprises P-doped Ge, the second layer of each micro PV cell comprises N-doped Ge, the third layer of each micro PV cell comprises P-doped GaAs, the fourth layer of each micro PV cell comprises N-doped GaAs, the fifth layer of each micro PV cell comprises P-doped InGaP, and the sixth layer of each micro PV cell comprises N-doped InGaP.

[0076] [000116] Example 16. 1. A photovoltaic (PV) device comprising: a string of at least three identical micro PV cells connected in series, the string comprising: a first micro PV cell disposed on a common substrate; a second micro PV cell disposed on the common substrate and electrically connected in series with the first micro PV cell; and a third micro PV cell disposed on the common substrate and electrically connected in series with the second micro PV cell, each of the first, second, and third micro PV cells having a right side and a left side, a first layer comprising a first semiconductor material, a second layer comprising a first semiconductor material, and a third layer comprising a second semiconductor material. a second layer including the first semiconductor material disposed on the first layer, a third layer including the first semiconductor material disposed on the second layer, a fourth layer including the first semiconductor material disposed on the third layer, a fifth layer including a second semiconductor material disposed on the fourth layer, a sixth layer including the second semiconductor material disposed on the fifth layer, a seventh layer including a third semiconductor material disposed on the sixth layer, an eighth layer including the third semiconductor material disposed on the seventh layer, extending downward into the first layer and disposed to the left of the micro PV cell. a first trench extending downward into the first layer and disposed to the right of the micro PV cell; a second trench extending downward into the second layer and disposed to the left of the micro PV cell adjacent to the first trench; a fourth trench extending downward into the fourth layer and disposed to the right of the micro PV cell adjacent to the second trench; a left first shoulder disposed to the left of the micro PV cell at a bottom of the second trench; and a right second shoulder disposed to the right of the micro PV cell at a bottom of the fourth trench. and an integrated monolithic bypass diode including a shoulder on the right side of the first micro PV cell and a buried PN junction disposed between the fourth layer and the third layer, wherein the first micro PV cell includes a first top surface, the second micro PV cell includes a second top surface, and the third micro PV cell includes a third top surface, and the string includes a first conductor electrically connecting the first layer to the first top surface of the first micro PV cell, a second conductor electrically connecting the right second shoulder of the first micro PV cell to the second top surface of the second micro PV cell;a third conductor electrically connecting the second right shoulder of the second micro PV cell to the third top surface of the third micro PV cell, a fourth conductor electrically connecting the second right shoulder of the first micro PV cell to the first left shoulder of the second micro PV cell, and a fifth conductor electrically connecting the second right shoulder of the second micro PV cell to the first left shoulder of the third micro PV cell, wherein the integrated monolithic bypass diode of each micro PV cell includes a PN junction disposed between the fourth layer and the third layer of each micro PV cell, and the common material is the first layer.

[0077] [000117] Example 17. 17. The PV device of example 16, wherein the first layer comprises semi-insulating GaAs, the second layer of each micro PV cell comprises N-doped GaAs, the third layer of each micro PV cell comprises P-doped GaAs, the fourth layer of each micro PV cell comprises N-doped GaAs, the fifth layer of each micro PV cell comprises P-doped GaAs, the sixth layer of each micro PV cell comprises N-doped GaAs, the seventh layer of each micro PV cell comprises P-doped InGaP, and the eighth layer of each micro PV cell comprises N-doped InGaP.

[0078] [000118] Example 18. 1. A photovoltaic (PV) device comprising an array of micro PV cells disposed on a common substrate and electrically connected in series, each micro PV cell having a right and a left side, a first layer including a P-doped first semiconductor material, a second layer including an N-doped first semiconductor material disposed on the first layer, a multi-junction micro PV cell stack disposed on a portion of the second layer, a first trench extending downward into the first layer, the first trench disposed to the left of each micro PV cell, and a second trench extending downward into the first layer, the second trench disposed to the right of each micro PV cell. a second trench disposed adjacent the second trench and extending downward into the second layer, a third trench disposed adjacent the second trench and extending downward into the second layer, the third trench disposed to the right of each micro PV cell adjacent to the left of the second trench; a first left shoulder disposed to the left of each micro PV cell at a bottom of the first trench; a second right shoulder disposed to the right of each micro PV cell at a bottom of the third trench; and an integrated monolithic bypass diode including a PN junction disposed between the second layer and the first layer, wherein the common substrate is the first layer.

[0079] [000119] Example 19. The PV device of example 18, wherein the PV device comprises 45 or more micro PV cells all connected in series, and the PV device has an output voltage greater than about 90V.

[0080] [000120] Example 20. The surface area of each individual micro PV cell in the PV device is about 1 cm 2 20. The PV device of Example 18 or 19, wherein:

[0081] [000121] Example 21. 21. The PV device of any one of Examples 18 to 20, further comprising a pair of voltage tabs disposed at opposite corners of the PV device.

[0082] [000122] Example 22. 22. The PV device of any one of Examples 18 to 21, wherein the photocurrent generated by the array of micro PV cells flows in a serial serpentine manner across the PV device when illuminated.

[0083] [000123] Example 23. The PV device of any one of Examples 18 to 22, wherein the PV device has an octagonal shape.

[0084] [000124] Example 24. The PV device is approximately 45 cm 2 The PV device of any one of Examples 18 to 23, having a surface area of at least 1000 nm.

[0085] [000125] Example 25. The PV device of any one of Examples 18 to 14, wherein the common substrate comprises P-doped Ge.

[0086] [000126] Example 26. 1. A photovoltaic (PV) device comprising an array of micro PV cells disposed on a common substrate and electrically connected in series, each micro PV cell having a right and a left side, a first layer comprising a first semiconductor material, a second layer comprising the first semiconductor material disposed on the first layer, a third layer comprising the first semiconductor material disposed on the second layer, a fourth layer comprising the first semiconductor material disposed on the third layer, a fifth layer comprising a second semiconductor material disposed on the fourth layer, a sixth layer comprising the second semiconductor material disposed on the fifth layer, a seventh layer comprising a third semiconductor material disposed on the sixth layer, an eighth layer comprising the third semiconductor material disposed on the seventh layer, and an eighth layer comprising the third semiconductor material extending downward into the first layer and disposed to the left of the micro PV cell. a first trench disposed on the first layer, a second trench extending downward into the first layer and disposed to the right of the micro PV cell, a third trench extending downward into the second layer and disposed to the left of the micro PV cell adjacent the first trench, a fourth trench extending downward into the fourth layer and disposed to the right of the micro PV cell adjacent the second trench, a first left shoulder disposed to the left of the micro PV cell at a bottom of the second trench, a second right shoulder disposed to the right of the micro PV cell at a bottom of the fourth trench, and an integrated monolithic bypass diode including a buried PN junction disposed between the fourth layer and the third layer, wherein the common material is the first layer.

[0087] [000127] Example 27. 27. The PV device of example 26, wherein the common substrate comprises semi-insulating GaAs.

[0088] [000128] Example 28. 1. A photovoltaic (PV) panel comprising: an array of a plurality of PV devices, each PV device comprising an array of a plurality of PV micro PV cells disposed on a common substrate and electrically connected in series, each micro PV cell having a right and a left side; a first layer including a P-doped first semiconductor material; a second layer including an N-doped first semiconductor material disposed on the first layer; a multi-junction micro PV cell stack disposed on a portion of the second layer; a first trench extending downward into the first layer, the first trench disposed to the left of the micro PV cell; a second trench extending downward into the first layer; a second trench disposed to the right of the micro PV cell; a third trench disposed adjacent to the second trench and extending downward into the second layer, the third trench disposed to the right of the micro PV cell adjacent to the left side of the second trench; a first left shoulder disposed to the left of the micro PV cell at a bottom of the first trench; a second right shoulder disposed to the right of the micro PV cell at a bottom of the third trench; and the second layer disposed on the first layer, wherein the common substrate is the first layer.

[0089] [000129] Example 29. 29. The PV panel of Example 28, wherein the positive polarity electrical bus comprises an interdigitated pattern of positive voltage conductors and the negative polarity electrical bus comprises an interdigitated pattern of negative voltage conductors, the positive polarity electrical bus and the negative polarity electrical bus being electrically connected to the array of the plurality of PV devices.

[0090] [000130] Example 30. 30. The PV panel of example 28 or 29, comprising one or more rows of PV devices, each row comprising a plurality of PV devices electrically connected in parallel.

[0091] [000131] Example 31. 30. The PV panel of Example 30, wherein each PV device includes a negative voltage tab and a positive voltage tab located on opposite sides of the PV device, and wherein a first positive voltage tab of a first PV device located in a first row of the PV panel is located directly across from a second positive voltage tab of an adjacent second PV device located in an adjacent second row of the PV panel.

[0092] [000132] Example 32. 31. The PV panel of Example 31, wherein each PV device includes a negative voltage tab and a positive voltage tab located on opposite sides of the PV device, and wherein a first negative voltage tab of a first PV device located in a first row of the PV panel is located directly across from a second negative voltage tab of an adjacent second PV device located in an adjacent second row of the PV panel.

[0093] [000133] Example 33. 33. The PV panel of any one of Examples 30 to 32, further comprising a respective blocking diode disposed between the PV device and the positive polarity electrical bus.

[0094] [000134] Example 34. 1. A photovoltaic (PV) panel comprising: an array of a plurality of PV devices, each PV device comprising an array of a plurality of PV micro PV cells disposed on a common substrate and electrically connected in series, each micro PV cell having a right and a left side; a first layer comprising a first semiconductor material; a second layer comprising a first semiconductor material disposed on the first layer; a third layer comprising the first semiconductor material disposed on the second layer; a fourth layer comprising the first semiconductor material disposed on the third layer; a fifth layer comprising a second semiconductor material disposed on the fourth layer; a sixth layer comprising the second semiconductor material disposed on the fifth layer; a seventh layer comprising a third semiconductor material disposed on the sixth layer; an eighth layer comprising the third semiconductor material disposed on the seventh layer; a first trench extending downward into the first layer, the first trench being a first trench extending downward into the first layer; a first trench disposed to the left of the micro PV cell; a second trench extending downward into the first layer, the second trench disposed to the right of the micro PV cell; a third trench extending downward into the second layer, the third trench disposed to the left of the micro PV cell adjacent to the first trench; a fourth trench extending downward into the fourth layer, the fourth trench disposed to the right of the micro PV cell adjacent to the second trench; a first left shoulder disposed to the left of the micro PV cell at a bottom of the second trench; a second right shoulder disposed to the right of the micro PV cell at a bottom of the fourth trench; and the fourth layer disposed on the third layer, wherein the common material is the first layer.

[0095] [000135] In the present disclosure, reference is made to various embodiments. However, it should be understood that the disclosure is not limited to the particular described embodiments. Instead, any combination of features and elements, whether associated with various embodiments, is contemplated for implementing and practicing the teachings provided herein. Furthermore, when elements of an embodiment are described in the form of "at least one of A and B," it should be understood that embodiments including element A only, element B only, and elements A and B are each contemplated. Furthermore, while some embodiments may realize other potential solutions and / or advantages over the prior art, whether or not a particular advantage is realized by a given embodiment does not limit the disclosure. Accordingly, the embodiments, features, and advantages disclosed herein are merely exemplary and should not be considered elements of or limit the scope of the appended claim(s) unless expressly recited in the claim(s). Similarly, references to "the present invention" should not be construed as generalizing all inventive subject matter disclosed herein, and should not be considered an element of or limiting the scope of any accompanying claim(s) unless expressly recited in the claim(s).

[0096] [000136] Unless otherwise indicated, the terms "first," "second," etc. are used herein merely as designators and are not intended to impose any sequential, positional, or hierarchical requirements on the items they represent. Furthermore, a reference to, for example, a "second" item does not require or preclude the presence of, for example, a "first" or lower-numbered item, or, for example, a "third" or higher-numbered item.

[0097] [000137] Spatial terms (e.g., "beneath," "below," "lower," "above," "upper," etc.) may be used herein to facilitate description of the relationship of one component and / or feature to another component and / or feature or other component(s) and / or feature(s) illustrated in the figures. It will be understood that these spatial terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figure(s).

[0098] [000138] As used herein, the terms "comprising," "comprise," and "comprises" are intended to be optionally interchangeable in all instances with the terms "consist essentially of," "consist essentially of," "consisting of," "consist of," and "consists of," respectively. To the extent that the words "includes / including," "has," and "contains," and variations thereof, are used herein, these words, like the word "comprises," are intended to be inclusive as open transition words that do not exclude any additional or other elements.

Claims

1. A photovoltaic (PV) micro PV cell (100), comprising: a first layer (12) comprising a P-doped first semiconductor material; a second layer (14) comprising an N-doped first semiconductor material disposed on the first layer (12); a multi-junction PV micro PV cell stack (16) disposed on a portion of the second layer (14); a first trench (22) extending downward into the first layer (12), the first trench (22) being located to the left of the PV micro PV cell (100); a second trench (22') extending downward into the first layer (12), the second trench (22') being located to the right of the PV micro PV cell (100); a third trench (52) disposed adjacent to the second trench (22') and extending downward into the second layer (14), the third trench (52) being disposed to the right of the PV micro PV cell (100) adjacent to the left side of the second trench (22'); a left first shoulder (26) disposed on the left side of the PV micro PV cell (100) at the bottom of the first trench (22); a right second shoulder (24) located on the right side of the PV micro PV cell (100) at the bottom of the third trench (52); and A PV micro PV cell (100) including an integrated monolithic bypass diode including a buried PN junction (15) disposed between the second layer (14) and the first layer (12).

2. 2. The PV micro PV cell (100) of claim 1, wherein the multi-junction PV micro PV cell stack (16) comprises one, two or three PN junctions (15, 17, 19).

3. The PV micro PV cell (100) of claim 1, wherein the first layer (12) has no metal disposed on a backside thereof.

4. a third layer (42) comprising a P-doped second semiconductor material disposed on the second layer (14); a fourth layer (44) comprising an N-doped second semiconductor material disposed on the third layer (42); a fifth layer (46) disposed on the fourth layer (44) and including a P-doped third semiconductor material; and The PV micro PV cell (100) of claim 1, further comprising a sixth layer (48) comprising an N-doped third semiconductor material disposed on the fifth layer (46).

5. the first layer (12) comprises P-doped Ge; the second layer (14) comprises N-doped Ge; the third layer (42) comprises P-doped GaAs; the fourth layer (44) comprises N-doped GaAs; the fifth layer (46) comprises P-doped InGaP; The PV micro PV cell (100) of claim 4, wherein the sixth layer (48) comprises N-doped InGaP.

6. the first layer (12) comprises P-doped Ge; the second layer (14) comprises N-doped GaAs on P-doped GaAs; the third layer (42) comprises P-doped GaAs; the fourth layer (44) comprises N-doped GaAs; the fifth layer (46) comprises P-doped InGaP; The PV micro PV cell (100) of claim 4, wherein the sixth layer (48) comprises N-doped InGaP.

7. A photovoltaic (PV) device (64) comprising an array of a plurality of PV micro-PV cells (100, 102, 104) disposed on a common substrate (600) and electrically connected in series; Each PV micro PV cell (100, 102, 104) a first layer (12) comprising a P-doped first semiconductor material; a second layer (14) comprising an N-doped first semiconductor material disposed on the first layer (12); a multi-junction PV micro PV cell stack (16) disposed on a portion of the second layer (14); a first trench (22) extending downward into the first layer (12), the first trench (22) being located to the left of each PV micro PV cell (100, 102, 104); a second trench (22') extending downward into the first layer (12), the second trench (22') being located to the right of each PV micro PV cell (100, 102, 104); a third trench disposed adjacent to the second trench (22') and extending downward into the second layer (14), the third trench being disposed to the right of each PV micro PV cell (100, 102, 104) adjacent to the left side of the second trench (22'); a left first shoulder (26) disposed to the left of each PV micro PV cell (100, 102, 104) at the bottom of the first trench (22); a right second shoulder (24) located to the right of each PV micro PV cell (100, 102, 104) at the bottom of the third trench; and an integrated monolithic bypass diode including the second layer (14) disposed on the first layer (12); The common substrate (600) is the first layer (12), of the PV device (64).

8. 8. The PV device (64) of claim 7, wherein the PV device (64) comprises 45 or more PV micro cells (100, 102, 104) all connected in series, and the PV device (64) has an output voltage greater than about 90V.

9. The surface area of each individual PV microcell (100, 102, 104) within said PV device (64) is about 1 cm 2 8. The PV device (64) of claim 7, wherein:

10. The PV device (64) of claim 7, further comprising a pair of voltage tabs (90, 90') located at opposite corners of the PV device (64).

11. 10. The PV device (64) of claim 7, wherein photocurrent generated by the array of the plurality of PV micro PV cells (100, 102, 104) flows in a serial serpentine manner across the PV device (64) when illuminated.

12. The PV device (64) of claim 7, wherein the PV device (64) has an octagonal shape.

13. The PV device (64) is approximately 45 cm 2 8. The PV device (64) of claim 7 having a surface area of at least 1000 nm.

14. The PV device (64) of claim 7, wherein the common substrate (600) comprises P-doped Ge.

15. A photovoltaic (PV) panel (58) comprising an array of a plurality of PV devices (64, 64'), each PV device (64, 64') comprising an array of a plurality of PV micro cells (100, 102, 104) disposed on a common substrate (600) and electrically connected in series; Each PV micro PV cell (100, 102, 104) a first layer (12) comprising a first semiconductor material; a second layer (14) disposed on the first layer (12); a multi-junction PV micro PV cell stack (16) disposed on a portion of the second layer (14); a first trench (22) extending downward into the first layer (12), the first trench (22) being located to the left of the PV micro PV cell (100); a second trench (22') extending downward into the first layer (12), the second trench (22') being located to the right of the PV micro PV cell (100); a third trench (52) disposed adjacent to the second trench (22') and extending downward into the second layer (14), the third trench (52) being disposed to the right of the PV micro PV cell (100) adjacent to the left side of the second trench (22'); a left first shoulder (26) disposed on the left side of the PV micro PV cell (100) at the bottom of the first trench (22); a right second shoulder (26') located on the right side of the PV micro PV cell (100) at the bottom of the second trench (22'); a right third shoulder (24) located on the right side of the PV micro PV cell (100) at the bottom of the third trench (52); and an integrated monolithic bypass diode (15) including the second layer (14) disposed on the first layer (12); The common substrate (600) is the first layer (12), of the PV panel (58).

16. 16. The PV panel (58) of claim 15, further comprising an interdigitated pattern of positive and negative polarity conductive buses (72 and 74) disposed beneath and electrically connected to the array of PV devices (64, 64').

17. 16. The PV panel (58) of claim 15, comprising one or more rows of the plurality of PV devices (64, 64'), each row comprising the plurality of PV devices (64, 64') electrically connected in parallel.

18. Each PV device (64) includes a negative voltage tab (90) and a positive voltage tab (90') located on opposite sides of the PV device (64); 18. The PV panel (58) of claim 17, wherein a first positive voltage tab (90′) of a first PV device (64) disposed in a first row (A) of the PV panel (58) is disposed directly across from a second positive voltage tab (92′) of an adjacent second PV device (66′) disposed in an adjacent second row (B) of the PV panel.

19. 20. The PV panel (58) of claim 18, wherein a first negative voltage tab (93) of a third PV device (66") disposed in a second row (B) of the PV panel (58) is disposed directly across from a second negative voltage tab (94) of an adjacent fourth PV device (69') disposed in an adjacent third row (C) of the PV panel (58).

20. 20. The PV panel (58) of claim 17, further comprising individual blocking diodes (218) disposed between adjacent pairs (64, 64') of parallel-connected PV devices along a single row (A).

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