Display device and manufacturing method thereof

Abstract

To provide a technique that can suppress manufacturing processing time and irregularities in brightness uniformity.SOLUTION: A display device includes a substrate; a plurality of common voltage lines on the substrate; a plurality of connection electrodes disposed on the plurality of common voltage lines, at least one of which is electrically connected to a corresponding line of the plurality of common voltage lines; a plurality of pixel electrode sets spaced from the plurality of connection electrodes, each of the pixel electrode sets comprising a first pixel electrode, a second pixel electrode, and a third pixel electrode to realize a full color pixel; an emission layer disposed on the plurality of connection electrodes and the plurality of pixel electrode sets, the emission layer having a plurality of openings, each of the plurality of openings corresponding to a different respective one of the plurality of connection electrodes, a total number of the openings being 25% or less of a total number of the pixel electrode sets; and a common electrode disposed on the emission layer, and electrically connected to the connection electrodes through the plurality of openings.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. patent application Ser. No. 18 / 428,136, filed Jan. 31, 2024, the contents of which are incorporated herein by reference in their entirety. The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] The display device includes a display area including a plurality of pixels. Each pixel includes a pixel electrode (e.g., an anode), a plurality of transistors (e.g., switching transistors and driving transistors), a capacitor for storing a voltage corresponding to a data signal, and a common electrode (e.g., a cathode) facing the pixel electrode. At least one layer (e.g., a light-emitting layer) is disposed between the pixel electrode and the common electrode.

[0003] The common electrode may be formed as one electrode (e.g., a single continuous electrode) over a plurality of pixels and coupled to a voltage source (e.g., a common voltage source having a constant voltage). When a pixel is current-driven, a pixel voltage output from a driving transistor is provided from the pixel electrode to the common electrode of the pixel through the pixel, thereby causing the light corresponding to the data signal to be emitted by the light-emitting layer of the pixel.

[0004] The above information disclosed in this Background is merely intended to aid in understanding the background of the present invention and may therefore include information that does not form part of prior art already known to those skilled in the art. Summary of the Invention [Problem to be solved by the invention]

[0005] A common electrode formed on the plurality of pixels may be electrically connected to an underlying auxiliary electrode through an opening formed in an emission layer located between the common electrode and the auxiliary electrode.

[0006] Embodiments of the present invention reduce manufacturing processing time (e.g., takt time) and reduce IR-drop associated with the common electrode while improving the brightness uniformity of the display area to the point where irregularities (e.g., mura) are less visible or even invisible. [Means for solving the problem]

[0007] According to one or more embodiments of the present invention, a display device includes: a substrate; a plurality of common voltage lines on the substrate; a plurality of connecting electrodes disposed on the plurality of common voltage lines, at least one of which is electrically connected to a corresponding one of the plurality of common voltage lines; a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each of which includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, to implement full-color pixels; a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel electrode sets, the light-emitting layer having a plurality of openings, each of which corresponds to a respective one of the plurality of connecting electrodes, the total number of the openings being 25% or less of the total number of the pixel electrode sets; and a common electrode disposed on the light-emitting layer, the common electrode being electrically connected to the connecting electrodes through the plurality of openings.

[0008] According to one or more embodiments, the plurality of apertures may include laser drilled holes (ie, laser drilled holes, LD holes, or LD apertures).

[0009] According to one or more embodiments, the total number of apertures can range from 700 to 3,700,000.

[0010] According to one or more embodiments, the total number of apertures can range from 57,000 to 920,000.

[0011] According to one or more embodiments, the distance between the closest ones of the apertures may range from about 1.1 mm to about 20 mm.

[0012] According to one or more embodiments, the plurality of pixel electrode sets may include a plurality of pixel electrode set groups, each of which may include a plurality of pixel electrode set subgroups, and only one of a plurality of subgroups in one of the plurality of groups may have a corresponding one of the apertures.

[0013] According to one or more embodiments, the subgroups within the plurality of pixel electrode set groups having corresponding openings among the openings define hole formation regions, and the width of one of the hole formation regions may be equal to the distance between two of the hole formation regions that are closest to each other.

[0014] According to one or more embodiments, the number of subgroups in one of the pixel electrode set groups may range from 4 to 64.

[0015] According to one or more embodiments, a ratio between the total number of pixel electrode sets and the total number of apertures in one of the plurality of subgroups may range from 1 to 64.

[0016] According to one or more embodiments, the plurality of pixel electrode set groups may be arranged in a matrix.

[0017] According to one or more embodiments, the plurality of subgroups of the pixel electrode sets in each of the plurality of groups may be arranged in a matrix.

[0018] According to one or more embodiments, the display device includes a 65-inch display panel, and the total number of apertures may range from 57,000 to 920,000.

[0019] According to one or more embodiments, the ratio between the total number of pixel electrode sets and the total number of apertures may be in the range of 4 to 5,184.

[0020] According to one or more embodiments, the ratio between the total number of the apertures and the total number of the pixel electrode sets may be in the range of 1 / 144 to 1 / 9.

[0021] According to one or more embodiments, the maximum width of one of the openings may range from about 1 μm to about 30 μm. The maximum width of one of the openings may be at least about 3 μm. The maximum width of one of the openings may range from about 4 μm to about 7 μm. The maximum width of one of the openings may range from about 4 μm to about 5 μm. The maximum width of one of the openings may range from about 3 μm to about 20 μm.

[0022] According to one or more embodiments, the contact resistance of one of the openings may range from about 1 ohm to about 1,000 ohms.

[0023] According to one or more embodiments, the thickness of the common electrode may range from about 40 Å to about 200 Å. The thickness of the common electrode may range from about 50 Å to about 140 Å.

[0024] According to one or more embodiments, the common electrode may include YbAg:Mg.

[0025] According to one or more embodiments, the common electrode may have a sheet resistance of about 9.7 Ω / □ to about 50 Ω / □, and a thickness ranging from about 40 Å to about 140 Å.

[0026] According to one or more embodiments, the common electrode may have a sheet resistance of less than about 32 Ω / □.

[0027] According to one or more embodiments, the resistance of one of the common voltage lines from one end to the opposite end may range from about 0.03 ohms to about 0.4 ohms.

[0028] According to one or more embodiments, one of the common voltage lines may include multiple metal layers.

[0029] According to one or more embodiments of the present invention, a display device includes a substrate, a plurality of common voltage lines on the substrate, a plurality of connecting electrodes disposed on the plurality of common voltage lines, at least one of which is electrically connected to a corresponding one of the plurality of common voltage lines, a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each of which includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and which implements full-color pixels, a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel electrode sets, the light-emitting layer having a plurality of openings, and a common electrode disposed on the light-emitting layer and electrically connected to the connecting electrodes through the plurality of openings, wherein the IR-drop is about 0.80V or less.

[0030] According to one or more embodiments, the IR-drop of the display device may be in a range of about 0.40V to about 0.80V. The IR-drop of the display device may be in a range of about 0.4567V to about 0.7920V. The IR-drop of the display device may be in a range of about 0.50V to about 0.75V. The IR-drop of the display device may be in a range of about 0.6V to about 0.7V.

[0031] According to one or more embodiments, the IR-drop is the result of a mathematical formula: IR-drop=((2.083*x4)-(7.1e -03 *x3)-(4.94e -05 *x2)+(1.758e -05 *x2*x3)+(4.3e -03 *x1*x4)+0.266+(3.544e -04 *x3 2 )-(0.18*x4 2 ))*I / (1μ*horizontal resolution*vertical resolution), where I is the panel current, x1 is the resistance through one of the plurality of apertures, x2 is the sheet resistance of the common electrode, x3 is the spacing between the closest apertures of the plurality of apertures, and x4 is the resistance of one of the plurality of apertures.

[0032] According to one or more embodiments, a display device includes a substrate, a plurality of common voltage lines on the substrate, a plurality of connecting electrodes disposed on the plurality of common voltage lines, at least one of which is electrically connected to a corresponding line of the plurality of common voltage lines, a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each of which includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and which implements full-color pixels, a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel voltage sets, the light-emitting layer having a plurality of openings, one of which has a maximum width in the range of about 1 μm to about 30 μm, and a common electrode disposed on the light-emitting layer and electrically connected to the connecting electrodes through the plurality of openings.

[0033] According to one or more embodiments, the plurality of apertures may include laser drilled holes (ie, laser drilled holes, LD holes, or LD apertures).

[0034] According to one or more embodiments, the maximum width of one of the openings may be about 3 μm. The maximum width of one of the openings may range from about 4 μm to about 7 μm. The maximum width of one of the openings may range from about 4 μm to about 5 μm. The maximum width of one of the openings may range from about 3 μm to about 20 μm.

[0035] According to one or more embodiments of the present invention, a display device includes: a substrate; a plurality of common voltage lines on the substrate; a plurality of connecting electrodes disposed on the plurality of common voltage lines, at least one of which is electrically connected to a corresponding one of the plurality of common voltage lines; a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each of which includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and which implement full-color pixels; a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel voltage sets, the light-emitting layer having a plurality of openings; and a common electrode disposed on the light-emitting layer, the common electrode being electrically connected to the connecting electrodes through the plurality of openings, the common electrode having a thickness ranging from about 60 Å to about 140 Å.

[0036] According to one or more embodiments, the thickness of the common electrode can range from about 70 Å to about 140 Å.

[0037] According to one or more embodiments, the common electrode may have a sheet resistance of about 9.7 ohms / square to about 50 ohms / square.

[0038] According to one or more embodiments, the common electrode may have a sheet resistance of less than about 32 Ω / □.

[0039] According to one or more embodiments of the present invention, a display device includes a substrate, a plurality of auxiliary voltage lines disposed on the substrate from one end to the opposite end of the display device, a plurality of connecting electrodes disposed on the plurality of auxiliary voltage lines, at least one of which is electrically connected to a corresponding one of the plurality of auxiliary voltage lines, a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each pixel electrode set including a first pixel electrode, a second pixel electrode, and a third pixel electrode, realizing full-color pixels, a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel voltage sets, the light-emitting layer having a plurality of openings, and a common electrode disposed on the light-emitting layer and electrically connected to the connecting electrodes through the plurality of openings, wherein a resistance of one of the auxiliary voltage lines is in the range of about 0.003 Ω to about 0.4 Ω.

[0040] According to one or more embodiments, the resistance of one of the auxiliary voltage lines may range from about 0.03 ohms to about 0.4 ohms.

[0041] According to one or more embodiments, the plurality of auxiliary electrode lines may include a plurality of first common voltage lines and a plurality of backplane metal lines extending in the same direction as the plurality of first common voltage lines, and one of the plurality of backplane metal lines may be electrically connected to a corresponding one of the plurality of first common voltage lines through an opening in a first insulating layer located between the corresponding line and the plurality of first common voltage lines.

[0042] According to one or more embodiments, the plurality of auxiliary electrode lines may further include a plurality of second common voltage lines positioned between the plurality of first common voltage lines and the plurality of backplane metal lines in the thickness direction of the substrate, and one of the plurality of second common voltage lines may be electrically connected to a corresponding one of the plurality of first common voltage lines through an opening in the second insulating layer positioned between the corresponding line and the second common voltage line.

[0043] According to one or more embodiments, one of the plurality of auxiliary electrode lines includes a plurality of overlapping common voltage lines spaced apart from each other in the thickness direction of the substrate, and the display device further includes an insulating layer between two adjacent lines of the plurality of overlapping common voltage lines in the thickness direction, and the two adjacent lines of the plurality of overlapping common voltage lines may be electrically connected to each other through an opening in the insulating layer.

[0044] According to one or more embodiments, the plurality of overlapping common voltage lines may include at least three overlapping common voltage lines that overlap and are electrically connected to each other in a thickness direction of the substrate. [Brief explanation of the drawings]

[0045] [Figure 1A] 1 is a schematic plan view illustrating a pixel including one set of pixel electrodes (each including three pixel electrodes) and a common voltage line, according to one or more embodiments of the present invention. [Figure 1B] 1 is a schematic plan view illustrating a plurality of pixels, each including a corresponding one of a plurality of pixel electrode sets (each including three electrodes), according to one or more embodiments of the present invention. [Figure 2] 1B is a schematic cross-sectional view of a pixel PX of the display panel shown in FIG. 1A taken along line II', in accordance with one or more embodiments of the present invention. [Figures 3A-3D] 3A-3D are graphs illustrating how different parameters affect IR-drop characteristics based on simulations performed in accordance with one or more embodiments of the present invention. [Figures 4A-4D]4A-4D are graphs showing normalized versions of the graphs 3A-3D in FIGS. 3A-3D, respectively. [Figure 5A] 1 is a graph showing the change in sheet resistance of common electrode materials including ytterbium (Yb) and silver-magnesium (Ag:Mg) based on a range of common electrode thicknesses from 40 Å to 140 Å, in accordance with one or more embodiments of the present invention. [Figure 5B] 10 is a chart showing the difference in efficiency associated with red, green, blue, and white based on different common electrode thicknesses. [Figure 5C] FIG. 10 shows the luminance of a display with a common electrode thickness of about 60 Å. [Figure 5D] FIG. 10 shows the luminance of a display with a common electrode thickness of about 80 Å. [Figure 6A] 10 is a graph illustrating common electrode sheet resistance for different materials and thicknesses, according to some embodiments of the present invention. [Figure 6B] 10 is a graph illustrating common electrode sheet resistance for different materials and thicknesses, according to some embodiments of the present invention. [Figure 7A] 3A-3C are schematic plan views of light-emitting layer openings formed in a light-emitting layer, according to some embodiments of the present invention; [Figure 7B] 7B is a schematic cross-sectional view of a light-emitting layer opening formed in the light-emitting layer shown in FIG. 7A, in accordance with one or more embodiments of the present invention. [Figure 7C] 10A-10C are three focused ion beam (FIB) images of three different outer widths and inner widths associated with three different light-emitting layer holes of an example experiment, according to one or more embodiments of the present invention. [Figure 8A-8B] 8A and 8B are schematic diagrams illustrating a display having drilled (e.g., laser-drilled) holes at substantially regular intervals across the display area of the display, in accordance with one or more embodiments of the present invention. [Figure 8C-8D]8C and 8D are each schematic diagrams illustrating a display having holes drilled in a pattern (eg, a chess pattern) associated with subgroups of pixel electrode sets, according to one or more embodiments of the present invention. [Figure 8E] 10A-10C are diagrams illustrating variations in patterns (e.g., chess patterns) associated with subgroups of pixel electrode sets, in accordance with one or more embodiments of the present invention. [Figure 8F] 10A-10C are diagrams illustrating variations in patterns (e.g., chess patterns) associated with subgroups of pixel electrode sets, in accordance with one or more embodiments of the present invention. [Figure 8G] 10A-10C are diagrams illustrating variations in patterns (e.g., chess patterns) associated with subgroups of pixel electrode sets, in accordance with one or more embodiments of the present invention. [Figure 8H] 1 is a chart of pixel and hole parameters corresponding to a 65-inch display in accordance with one or more embodiments of the present invention. [Figure 9] 1 is a chart of pixel and hole parameters corresponding to different display sizes and types, in accordance with one or more embodiments of the present invention. [Figure 10A] 1 is a schematic plan view of layers of a display device in accordance with one or more embodiments of the present invention. [Figure 10B] 1 is a schematic plan view of layers of a display device in accordance with one or more embodiments of the present invention. [Figure 10C] 1 is a schematic plan view of layers of a display device in accordance with one or more embodiments of the present invention. [Figure 10D] 1 is a schematic plan view of layers of a display device in accordance with one or more embodiments of the present invention. [Figure 10E] 1 is a schematic plan view of layers of a display device in accordance with one or more embodiments of the present invention. [Figure 11A] 1 is a schematic cross-sectional view of a display device including a common voltage line in one layer according to some embodiments of the present invention; [Figure 11B]1 is a schematic cross-sectional view of a display device including common voltage lines on two layers according to some embodiments of the present invention. [Figure 11C] 1 is a schematic cross-sectional view of a display device including common voltage lines in three layers, the first common voltage line being coupled to a backplane-metal layer, according to some embodiments of the present invention; [Figure 11D] 1 is a schematic cross-sectional view of a display device including common voltage lines on three layers, the first common voltage line not being coupled to a backplane-metal layer, according to some embodiments of the present invention; [Figure 12A] 1 is a schematic plan view of some layers of a display device in accordance with one or more embodiments of the present invention. [Figure 12B] 12B is a schematic cross-sectional view of some layers of the display device shown in FIG. 12A taken along line A-A', according to one or more embodiments of the present invention. [Figure 13A] 1 is a schematic plan view of layers of a display device in accordance with one or more embodiments of the present invention. [Figure 13B] 13B is a schematic cross-sectional view of some layers of the display device shown in FIG. 13A taken along line BB', in accordance with one or more embodiments of the present invention. [Figure 14] FIG. 2 is a schematic diagram illustrating components of a display panel associated with measuring backplane wiring resistance in accordance with one or more embodiments of the present invention. [Figure 15] 1 is a graph showing an IR-drop scatter plot in accordance with one or more embodiments of the present invention. [Figure 16] 1 is a table illustrating the relationship between four parameters and IR-drop in accordance with one or more embodiments of the present invention. [Figure 17] 1A-1D illustrate exemplary steps in a method for manufacturing a display panel in accordance with one or more embodiments of the present invention. [Figures 18A-18B]18A and 18B each illustrate a display panel configured to determine IR_drop that measures luminance and / or color coordinates, according to one or more embodiments of the present invention. [Figure 19A] 10 is a graph of luminance and color coordinates versus ELVDD in accordance with one or more embodiments of the present invention. [Figure 19B] 10 is a graph of luminance and color coordinates versus ELVDD in accordance with one or more embodiments of the present invention. [Figure 19C] 10 is a graph of luminance and color coordinates versus ELVDD in accordance with one or more embodiments of the present invention. [Figure 19D] 10 is a graph of luminance and color coordinates versus ELVDD in accordance with one or more embodiments of the present invention. [Figure 20] 1 is a table showing the results of measuring luminance for nine points on a display panel to determine Long Range Uniformity (LRU), in accordance with one or more embodiments of the present invention. [Figure 21] 21 is a schematic diagram of a display panel showing nine points at which the luminance of FIG. 20 was measured, in accordance with one or more embodiments of the present invention. [Figure 22] 1 is a contour map for luminance measurements in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0046] One or more embodiments of the present invention and aspects of how to achieve the same will become more readily understood with reference to the detailed description of the embodiments and the accompanying drawings. The embodiments are described in more detail below with reference to the accompanying drawings. However, the described embodiments may be modified in various ways and implemented in various different forms, and should not be construed as being limited to only the embodiments described herein. Rather, the present embodiments are provided to complete the disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art. It should be understood that the present invention encompasses all modifications, equivalents, and alternatives within the spirit and technical scope of the present invention. Therefore, steps, elements, and techniques unnecessary for those skilled in the art to fully understand aspects of the present invention may not be described.

[0047] Unless otherwise specified, the same reference numerals, letters, or combinations thereof refer to the same components throughout the accompanying drawings and detailed description of the invention, and therefore, descriptions thereof will not be repeated. Also, parts that are not relevant to the description of the embodiments may not be illustrated in order to clarify the specification.

[0048] In the drawings, the relative sizes of components, layers, and regions may be exaggerated for clarity. Also, in the accompanying drawings, cross-hatching and / or shading are generally provided to clarify boundaries between adjacent components. The presence or absence of such cross-hatching and / or shading may or may not indicate preferences or requirements for particular materials, properties of materials, dimensions, proportions, commonalities between the illustrated components, and / or certain other features, attributes, properties, etc. of the components, unless otherwise specifically described.

[0049] Various embodiments are described herein with reference to schematic illustrations of examples and / or intermediate structures. Therefore, it is expected that shapes may differ from those shown in the drawings as a result of, for example, manufacturing techniques and / or tolerances. Furthermore, the description of specific structures or functions disclosed herein is merely for the purpose of technically explaining embodiments according to the concepts of the present invention. Therefore, the embodiments disclosed herein should not be limited to the shapes of specifically illustrated regions. For example, the shapes shown in the embodiments disclosed herein may include deviations in shape that depend on manufacturing results, such as manufacturing errors.

[0050] For example, a region of one shape illustrated as a square may not transition to a typical rounded or curved shape, and / or may have a gradient at the corners of the shape rather than a binary transition from one shape to another. Similarly, a transition region formed by a shape change may result in a change in part of the area between the surface of the transition region and the surface of the region used to transition to the transition region. That is, in this embodiment, one shape (e.g., a square) and another shape (e.g., a circle) may coexist, for example, a region may have a portion having one shape (e.g., a square) and a portion having another shape (e.g., a circle). The transition between one shape and another shape may be gradual.

[0051] Therefore, the regions shown in the drawings are essentially schematic, and the shapes are not intended to represent or limit the actual shapes of device regions. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in many different ways without departing from the spirit or scope of the present invention.

[0052] In the detailed description, for purposes of explanation, numerous specific details are presented to provide a thorough understanding of various embodiments. However, various embodiments may be implemented in similar forms that include such specific details, in which case the specific details will not be repeatedly described. In other instances, well-known structures and devices are shown in simplified block diagram form to avoid unnecessarily obscuring the present disclosure.

[0053] Spatial terms such as "below," "below," "below," "above," "above," and the like may be used to describe the relationship of one component or feature shown in the figures to another component(s) or feature(s) for ease of description. Spatial terms are intended to encompass different orientations of the device in use or operation other than the orientation shown in the figures. For example, even if a component or feature is described as being "below," "below," or "below" another component or feature, if the device is inverted in the figures, the component or feature may be "above" the other component or feature. Thus, the exemplary terms "below" and "below" can both encompass an above and below orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at another orientation), and the spatial descriptions used herein should be interpreted accordingly. Similarly, even if a first part is described as being positioned "above" a second part, if there is no restriction on the upper side based on the direction of gravity, this indicates that the first part can be positioned above or below the second part.

[0054] Also, as used herein, "on a plane" or "plan view" means viewing the target portion from above, and "on a cross section" means viewing a cross section formed by cutting the target portion vertically from the side.

[0055] When a component, layer, region, or component is referred to as being "formed on," "on," "coupled to," or "bonded to" another component, layer, region, or component, this may mean that the component, layer, region, or component is directly formed on, directly coupled to, or directly bonded to the other component, layer, region, or component, or that the component is indirectly formed on, indirectly coupled to, or indirectly bonded to the other component, layer, region, or component through one or more intervening components, layers, regions, or components. This may also refer collectively to direct or indirect coupling, or coupling, and integral or non-integral coupling, or connection. For example, when a layer, region, or component is referred to as being "electrically coupled" or "electrically coupled" to another layer, region, or component, this may mean that the component is directly electrically coupled or bonded to the other layer, region, and / or component, or there may be intervening layers, regions, or components between the regions. However, when the term "directly coupled / directly bonded" or "directly on" is used, this refers to one component being directly coupled or bonded to another component, or being on top of another component without any intervening components. However, other expressions describing the relationship between components, such as "between," "immediately between," or "adjacent to" and "directly adjacent to," may also be interpreted in a similar manner. Also, when a component or layer is referred to as being "between" two components or layers, it should be understood that this means that there may be only one component or layer between the two components or layers, or that there may also be one or more intervening components or layers.

[0056] For purposes of the present invention, a phrase such as "at least one" preceding a list of elements modifies the entire list of elements, not the individual elements of the list. For example, "at least one of X, Y, and Z," "at least one of X, Y, or Z," and "at least one selected from the group consisting of X, Y, and Z" can also be interpreted as X alone, Y alone, or Z alone, e.g., XYZ, XYY, YZ, and ZZ, or as any combination of two or more of X, Y, and Z, with modifications thereto. Similarly, "at least one of A and B" can include A, B, or A and B. As used herein, "or" can generally mean "and / or," and the term "and / or" includes any and all combinations of one or more of the associated list items (X, Y, Z, A, B, C, etc.). For example, a phrase such as "A and / or B" can include A, B, or A and B.

[0057] The terms “first,” “second,” “third,” and the like may be used herein to describe various elements, components, regions, layers, and / or sections, but these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, region, layer, or section from another element, region, layer, or section. Thus, a first element, first component, first region, first layer, or first section described below does not depart from the spirit and scope of the present invention. A component that can be used as a second element, second component, second region, second layer, or second section may also be described as a “first” element, and this does not necessarily imply the presence of a second or other component in addition to the first component. The terms “first,” “second,” and the like may also be used herein to distinguish other categories or sets of elements. For clarity, the terms “first,” “second,” and the like may be expressed as “first category” (or first set) or “second category” (or second set), respectively.

[0058] In the examples, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may intersect perpendicularly with each other, or may not intersect perpendicularly with each other and may indicate other directions. The same applies to the first, second, and / or third directions.

[0059] It should be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used herein, the singular form "a," "an," or "an" is intended to include the plural unless the context clearly dictates otherwise. It should be understood that the terms "comprise," "include," "including," "have," and "having," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0060] If one or more embodiments may be implemented differently, certain operations may be performed differently than described. For example, two operations described as successive may be performed substantially simultaneously or may be performed in the reverse order of the operations described.

[0061] As used herein, the terms "substantially," "about," "approximately," and similar terms may be used as terms of approximation, not as terms of degree, and are intended to account for inherent variations in measurements or calculations that would be recognized by one of ordinary skill in the art. As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of variation relative to the specified value, taking into account the measurement and error associated with measuring the particular quantity (i.e., the limits of what a measurement system can measure). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, 20%, 10%, or 5%. Furthermore, the term "may" when describing an embodiment of the present invention may also refer to "one or more embodiments of the present invention."

[0062] Furthermore, any numerical range disclosed and / or cited herein is intended to include all subranges of the same numerical precision contained within the cited range. For example, a range of "1.0 to 10.0" includes all subranges between the recited value of 1.0 and the recited maximum value of 10.0 (and corresponding values), with a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. It is intended that the minimum numerical limitation (critical value) cited herein includes all lower numerical limitations contained therein, and the maximum numerical limitation cited herein includes all higher numerical limitations contained therein. Accordingly, applicants reserve the right to amend this specification, including the claims, and expressly recite subranges contained within the ranges expressly recited herein. In other words, any amendment to any numerical range within the numerical ranges disclosed and / or cited herein is an amendment within the scope of this specification. All such ranges and amendments expressly reciting such subranges are intended to be essentially as written herein to comply with the requirements of 35 U.S.C. § 112(a) and 35 U.S.C. § 132(a).

[0063] Unless otherwise defined, each of the terms (including technical and scientific terms) used herein has the same meaning as commonly recognized by one skilled in the art to which the present invention belongs. Furthermore, the same terms as those commonly used and defined in advance should be intended to have a meaning consistent with the meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this specification.

[0064] Because all conductors have non-zero resistance at room temperature, a voltage drop (i.e., IR-drop) occurs when a current I passes through a conductor. In a display device, a driving voltage (or driving voltages) is typically supplied from one or more edges (ends, terminals, etc.). Therefore, pixels located far from the edges (e.g., pixels near the central region) experience a higher voltage drop (i.e., IR-drop) than pixels near the edges (or the source or drain of the driving current). Such brightness non-uniformity may be due to different IR-drops experienced by different pixels at different locations on the display device. In manufacturing conventional display devices (e.g., top-emission organic light-emitting (OLED) display devices), it can be difficult to increase the size of the display device due to issues with IR-drop across the display area (e.g., IR-drop associated with the cathode electrode (also referred to as the "common electrode")), which is generally formed throughout the entire display area of the display device and shared by the pixels of the display device. IR-drop issues can result in visible irregularities (e.g., "mura") and reduced long-range uniformity (LRU). The common electrode may be formed on a thin cathode electrode that acts as a conductive electrode for an area corresponding to a pixel of the display device (e.g., a very large area or the entire display area). The cathode electrode may have a light transmittance suitable for transmitting light through the cathode electrode for top-side emission applications. The cathode electrode may have transparent or semi-transparent properties depending on its dimensions and forming material.

[0065] To solve the IR drop problem, the cathode electrode may be made to contact auxiliary wiring (e.g., a common voltage line) to which a power supply voltage (e.g., an ELVSS voltage) is applied at multiple locations within the display area of the display device. The auxiliary wiring (e.g., a common voltage line) may be connected to the backplane wiring (e.g., a backplane-metal layer (BML)) of the display device with one or more insulating layers between them. To allow contact between the cathode electrode and the auxiliary wiring, an opening may be formed in an emissive layer (e.g., an emissive layer, a luminous evaporation layer, or an organic emissive layer) formed between the auxiliary electrode and the cathode electrode. The opening in the emissive layer may be formed by removing a portion of the emissive layer using a laser (e.g., laser drilling (LD) technology).

[0066] Although the light-emitting layer is described herein as essentially a single layer, the light-emitting layer may also be referred to as an interlayer (e.g., one or more layers between the cathode and anode), including, but not limited to, one or more of a hole injection layer (HIL), a hole transport layer (HTL), an organic light-emitting layer, an electron transport layer (ETL), and / or an electron injection layer (EIL). In one or more embodiments, the light-emitting layer may have a tandem structure, in which multiple light-emitting and / or other layers may be stacked between the cathode and anode.

[0067] Aspects of one or more embodiments of the present invention provide improvements to LD hole drilling, improving takt time (e.g., the time it takes for a product to be assembled to meet product requirements). For example, in the manufacture of display devices, reducing the number of LD holes can reduce product assembly time, which in turn can improve takt time.

[0068] An aspect of one or more embodiments of the present invention provides conditions or values (e.g., optimal conditions or values) suited to each of four parameters (e.g., cathode electrode sheet resistance, LD hole contact resistance, LD hole distance, and backplane wiring resistance) that affect IR-drop, which affects the display characteristics of a display device. One or more embodiments of the present invention also provide mathematical formulas that define the relationship between the four parameters and IR-drop.

[0069] FIG. 1A is a schematic plan view illustrating a pixel including one set of pixel electrodes (each including three pixel electrodes) and a common voltage line according to one or more embodiments of the present invention.

[0070] FIG. 1B is a schematic plan view illustrating a plurality of pixels, each including a corresponding one of a set of pixel electrodes (each including three electrodes), according to one or more embodiments of the present invention.

[0071] 1A and 1B, a display device (e.g., a display panel) may include a plurality of pixels PX that can display (i.e., are configured to display) an image. As used herein, the terms display device and display may be used interchangeably and may include a television, a personal computer, a personal computer monitor, a mobile phone, a handheld device, a tablet, a game console, and / or a navigation device. According to one or more embodiments, the display panel may be a component of a display device and may include memory, input / output devices, one or more processors, one or more communication modules, and other suitable components recognized by those skilled in the art. Alternatively, the terms "display device" and "display panel" may be used interchangeably.

[0072] The pixels PX may be arranged roughly in a matrix (e.g., arranged in rows and columns), but are not limited to this, and may be repeatedly arranged according to a certain rule (e.g., according to a corresponding appropriate layout scheme). A display device may include any suitable electronic device capable of displaying images. For example, a television, a personal computer, a personal computer monitor, a mobile phone, a mobile device, a tablet, a game console, and / or a navigation device may include a display panel for displaying images.

[0073] In one or more embodiments, each pixel PX may include multiple sub-pixels PX1, PX2, and PX3. The sub-pixels PX1, PX2, and PX3 included in each pixel PX may display light of different colors. For example, the sub-pixels PX1, PX2, and PX3 may display primary colors such as red R, green G, and blue B. The sub-pixels PX1, PX2, and PX3 may combine different intensities of the different primary colors to display (or represent) various colors. In one or more embodiments, each pixel PX may include four or more sub-pixels, which may correspond to red R, green G, blue B, and white W sub-pixels, respectively, or any other suitable combination of red R, green G, blue B, and white W sub-pixels, and each pixel PX may include two or more sub-pixels of the same color.

[0074] Each of the subpixels PX1, PX2, and PX3 may include a pixel electrode PE (e.g., an anode) to which a driving current from each driving transistor is applied. When a desired signal corresponding to a desired gray level is applied to the subpixels PX1, PX2, and PX3, the capacitor within the subpixel stores a voltage corresponding to the desired data signal, and the driving transistor supplies a corresponding driving current from the pixel electrode PE to a common electrode (e.g., a cathode electrode) through the subpixel according to the stored voltage. Light is then generated and emitted by an emissive layer located between the pixel electrode PE and the common electrode. A full-color display may be realized by emitting light of each color from the three subpixels PX1, PX2, and PX3. The pixel electrodes PE may be located in the same layer. The pixel electrodes PE may include the same material. The pixel electrodes PE located in the same pixel PX may be collectively referred to as a pixel electrode set PES. For example, each pixel PX may include one pixel electrode set PES including three pixel electrodes PE corresponding to three sub-pixels configured to emit red R, green G, and blue B, respectively, a common electrode, and a light-emitting layer located (or formed) between the one pixel electrode set PES and the common electrode. A display device may include multiple pixel electrode sets PES. While the term "light-emitting layer" is generally used to refer collectively to the light-emitting layers located in each sub-pixel according to one or more embodiments, the light-emitting layers located in different sub-pixels of each pixel may be configured to emit light of each color (e.g., red R, green G, blue B, and / or white W light) to implement a full-color display.

[0075] A display device according to one or more embodiments includes a plurality of common voltage lines CVL, which may be referred to as auxiliary lines or ELVSS lines, and a plurality of connecting electrodes AE (which may also be referred to as a plurality of auxiliary electrodes AE) for transmitting a common voltage (e.g., ELVSS voltage).

[0076] The common voltage line CVL may extend in a length direction (e.g., in the Y direction). At least one common voltage line CVL may be arranged for each pixel PX (e.g., along the X direction). FIG. 1A shows an example in which one common voltage line CVL is arranged spaced apart along the X direction and extends in the Y direction, located for each pixel PX (e.g., there may be one common voltage line CVL for multiple pixels PX arranged in the Y direction). According to one or more embodiments, a display device may include multiple common voltage lines located on different layers, with one or more insulating layers between the different layers. The common voltage lines located on different layers may extend in the same direction, at least overlap each other (e.g., at least partially overlap each other in the thickness direction of the display device or its substrate), and may be electrically connected to each other via one or more openings formed in one or more insulating layers.

[0077] In one or more embodiments, there may be at least one connecting electrode AE for each pixel PX in the X or Y direction. Figures 1A and 1B show an example in which one connecting electrode AE is formed for each pixel PX in each of the X and Y directions. However, the present invention is not limited thereto. For example, one connecting electrode AE may be formed for multiple pixels PX.

[0078] The connecting electrodes AE are located on a conductive layer different from the conductive layer of the common voltage lines CVL. At least a portion of each connecting electrode AE may overlap with the corresponding common voltage line CVL in a Z direction (e.g., in the thickness direction of the display device) substantially perpendicular to the X and Y directions. The portion of the connecting electrode AE overlapping with the common voltage line CVL may be electrically connected to the common voltage line CVL through an opening in at least one insulating layer (e.g., a via layer VIA in FIG. 2) located between the common voltage line CVL and the connecting electrode AE. As will be discussed in detail below, the connecting electrode AE may overlap with an emitting layer opening ELOP of an emitting layer associated with each pixel PX.

[0079] The light-emitting layer openings ELOP may be located on or overlap portions of the connecting electrodes AE. According to one embodiment, one light-emitting layer opening ELOP (e.g., a laser-drilled hole) is provided for each pixel, and a row of light-emitting layer openings ELOP including a plurality of light-emitting layer openings ELOP is provided corresponding to each common voltage line CVL. This allows the connecting electrodes AE to electrically connect each common voltage line CVL to the common electrode. That is, the common voltage line CVL is electrically connected to the connecting electrode AE through an opening in at least one insulating layer (e.g., via layer VIA in FIG. 2) located between the common voltage line CVL and the connecting electrode AE. The connecting electrode AE is electrically connected to the common electrode (the common electrode CME in the example of FIG. 2) through the light-emitting layer openings ELOP, allowing the connecting electrode AE to electrically connect each common voltage line CVL to the common electrode. However, the present invention is not limited to an embodiment in which one light-emitting layer opening ELOP is provided for each pixel. As will be discussed in more detail below, the pitch of the emissive layer openings ELOP in the X and Y directions (e.g., the distance between each emissive layer opening in the X and Y directions) is greater than the pitch of the pixels PX in the X and Y directions, respectively. The pitch of the emissive layer openings ELOP in the X direction (e.g., the number of pixels between the nearest emissive layer openings ELOP) can be the same as or different from the pitch of the emissive layer openings ELOP in the Y direction (e.g., the number of pixels between the nearest emissive layer openings ELOP). And, for example, one emissive layer opening ELOP can be provided for multiple pixels PX.

[0080] In one or more embodiments, the pitch (e.g., in millimeters (mm)) of the light emitting layer openings ELOP in the X direction may be greater than, for example, an integer multiple of, the pitch of the plurality of common voltage lines CVL in the X direction. Also, the pitch (e.g., in mm) of the light emitting layer openings ELOP in the X direction may be greater than, for example, an integer multiple of, the pitch of the plurality of connecting electrodes AE in the X direction.

[0081] In one or more embodiments, some of the connecting electrodes AE among the connecting electrode AE column (including a plurality of connecting electrodes AE) may not correspond to (e.g., may not overlap) any of the light emitting layer openings ELOP. In one or more embodiments, the common voltage lines CVL may not be formed corresponding to one or more connecting electrode AE columns that are not aligned with (e.g., do not overlap) the light emitting layer openings ELOP. Furthermore, the common voltage lines CVL may be formed to have the same pitch as the light emitting layer openings ELOP in the X direction.

[0082] In one or more embodiments, at least a portion of the connecting electrode AE that is not electrically connected to the common voltage line CVL or that does not overlap the light-emitting layer opening ELOP may be omitted. The planar shape of the light-emitting layer opening ELOP may vary. For example, the planar shape of the light-emitting layer opening ELOP may be, but is not limited to, circular, elliptical, polygonal, etc. Also, as can be seen from FIGS. 1A and 1B, the shapes of the connecting electrode AE and the subpixel (e.g., pixel electrode PE) may vary in different embodiments. In FIG. 1A, the connecting electrode AE may include, for example, a polygonal body portion and an extension portion extending from the body portion (extending in the Y direction in the example of FIG. 1A), which may be used for electrical connection to the common voltage line CVL located below. In FIG. 1B, the connecting electrode may not include the extension portion as in FIG. 1A but may include, for example, a polygonal body portion, and the body portion may be electrically connected to the common voltage line CVL below the light-emitting layer opening ELOP. In various embodiments, the arrangement, size, and shape of the pixels, sub-pixels, pixel electrodes, etc. may vary in any suitable manner as recognized by those skilled in the art.

[0083] 2 is a schematic cross-sectional view of the display panel pixel PX shown in FIG. 1A taken along line II' in accordance with one or more embodiments of the present invention. Note that the example of FIG. 2 illustrates an example in which an opening is not formed in the via layer VIA so as to overlap the emissive layer opening ELOP below the emissive layer opening ELOP, in keeping with the embodiment of FIG. 1A. However, an opening may be formed in the via layer VIA so as to overlap the emissive layer opening ELOP. In FIG. 1B, the emissive layer opening ELOP and the opening in the via layer VIA may be formed to overlap in the Z direction.

[0084] 2, in one or more embodiments, the display panel DP may include a base substrate BS, a circuit layer DP-CL, and a display component layer DP-EDL. The circuit layer DP-CL may be formed on the base substrate BS.

[0085] The circuit layer DP-CL may include a buffer layer BL, a transistor T1 (e.g., a driving transistor), a first connecting electrode CNE1, a common voltage line CVL (e.g., an auxiliary wiring or a power supply voltage wiring), and multiple insulating layers (e.g., a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, and a fourth insulating layer 40). In one or more embodiments, the fourth insulating layer 40 may include a via layer VIA. The transistor T1 may include a gate electrode G1, a drain D1, and a source S1.

[0086] The display component layer DP-EDL may include a pixel electrode PE and a connecting electrode AE (e.g., a second connecting electrode). The pixel electrode PE and the connecting electrode AE may be in the same layer and may correspond to the anode layer AN of the display panel DP. The display component layer DP-EDL may also include a pixel definition film PDL and a common electrode CME (e.g., a cathode layer shared by multiple pixels). The pixel electrode PE may be located in a pixel opening POP of the pixel definition film PDL along with a portion of the emissive layer EL and the common electrode CME. The pixel electrode PE, the emissive layer EL, and the common electrode CME may operate together to emit light from the pixel PX.

[0087] The connecting electrode AE may be located in the auxiliary opening AOP of the pixel definition layer PDL (e.g., overlapping and located below the auxiliary opening AOP in the thickness direction of the substrate). The connecting electrode AE may operate, together with the common voltage line CVL, to provide a power supply voltage ELVSS to the common electrode CME. The light-emitting layer opening ELOP may be formed in the light-emitting layer EL. The light-emitting layer opening ELOP may be formed with a laser (e.g., a Gaussian laser) using laser-drilled-hole LD technology and may be referred to as a laser-drilled hole, laser-drilled hole, or LD hole. In one or more embodiments, the light-emitting layer EL may be completely removed from a central region (e.g., the third region R3). The laser may have a Gaussian beam shape, and the laser intensity (or strength) at the edge or peripheral region of the beam may be less than that at the central region of the beam. Thus, the light-emitting layer opening ELOP may be surrounded by a first region R1 and a second region R2, and the two regions may be tilted due to the change in beam intensity. As can be seen from FIG. 2, the first region R1 has a bump shape (e.g., a sloped shoulder shape) and is therefore higher than the region directly surrounding the first region R1. This difference in bump height occurs because the light-emitting layer material (e.g., the light-emitting layer material in the second region R2) is not removed but is pushed toward the edge or periphery of the light-emitting layer opening ELOP by the laser output. Specifically, referring to FIG. 2, the first to third regions R1 to R3 are formed by applying a laser to the light-emitting layer EL corresponding to the light-emitting layer opening ELOP as described above. The remaining light-emitting layer EL in the third region R3 has the thinnest thickness among the first to third regions R1 to R3. The second region R2 is formed to surround the third region R3, and the remaining light-emitting layer EL has a thickness thicker than that in the third region R3 but thinner than that in the first region R1. In the second region R2, the beam intensity weakens outward, so the remaining light-emitting layer EL is formed in a gradient manner, with the thickness increasing outward. The first region R1 is formed to surround the second region R2, and the remaining light-emitting layer EL is thicker than the second region R2. In the first region R1, the beam intensity weakens further from the second region R2 side and strengthens toward the outer periphery of the first region R1, so that the first region R1 is formed in a convex shape (the aforementioned bump shape).Since the beam intensity weakens further outward from the first region R1, the light-emitting layer EL remains in a sloped shape toward the periphery of the first region R1. However, the shape of the light-emitting layer opening ELOP can be formed as desired by adjusting the beam intensity. Although not shown in the cross-sectional view of FIG. 2, the connection electrode AE may be connected to the common voltage line CVL, for example, through a contact hole (CH) of FIG. 1A. In the example of FIG. 2, the contact hole CH is formed in the via layer VIA. A common electrode CME may be formed on the light-emitting layer EL. A single laser beam having a Gaussian beam shape may be provided to portions of the light-emitting layer EL corresponding to each of the plurality of light-emitting layer openings ELOP while being dispersed in various ways, and multiple holes may be simultaneously drilled in the light-emitting layer EL.

[0088] A UV laser may be used to form the light-emitting layer aperture ELOP. For example, the laser may be a Q-switched DPSS neodymium-doped yttrium aluminum garnet (Nd:YAG) laser. However, the invention is not limited thereto, and any other suitable laser or lasers may be used, as will be appreciated by those skilled in the art.

[0089] The common electrode CME may contact the connecting electrode AE through the emissive layer opening ELOP. Contact between the common electrode CME and the connecting electrode AE at multiple locations may reduce IR-drop (e.g., IR-drop across the common electrode CME). Reducing the IR-drop may improve brightness uniformity across the display area. As discussed in detail below, parameters associated with the emissive layer opening ELOP and the contact between the common electrode CME and the connecting electrode AE may be selected to improve (e.g., optimize) the display characteristics of the display panel DP.

[0090] In one or more embodiments, the pixel electrode PE may be connected to the transistor T1 through a first contact hole CH1 (e.g., a contact hole in the third insulating layer 30), a second contact hole CH2 (e.g., a contact hole in the fourth insulating layer 40), and a first connecting electrode CNE1. That is, the source S1 of the transistor T1 and the first connecting electrode CNE1 (a connecting electrode formed on the third insulating layer 30) are connected through the first contact hole CH1, and the first connecting electrode CNE1 may be further connected to the pixel electrode PE through the second contact hole CH2. In one or more embodiments, the connecting electrode AE may be connected to the common voltage line CVL through a third contact hole (e.g., through another contact hole in the fourth insulating layer 40). For example, according to one or more embodiments of the present invention, the third contact hole may be formed to be offset from the light emitting layer opening ELOP in the Y direction such that the second hole H2 is offset from the first hole H1, as shown in FIG. 13B. Alternatively, in one or more other embodiments, the third contact hole may be aligned with the third region 3 where the light-emitting layer EL is completely removed in the thickness direction (Z direction) of the base substrate.

[0091] 3A-3D are graphs illustrating how different parameters affect IR-drop characteristics based on simulations performed in accordance with one or more embodiments of the present invention, respectively.

[0092] By way of example, a low (or relatively low) backplane (eg, common voltage line) resistance was used to obtain the simulation results provided in 3A through 3C in FIGS. 3A-3D.

[0093] Referring to Figures 3A-3D, it can be seen that IR-drop can be reduced by reducing the cathode electrode sheet resistance (also referred to as "common electrode sheet resistance"). As used herein, cathode electrode sheet resistance is the resistance measured across the surface of the cathode electrode between the electrodes (or probes). By way of example, as those skilled in the art will recognize, sheet resistance can be measured using a four-point probe system, in which, for example, four probes define the four corners of a square on a sheet of material (e.g., the cathode electrode), and the resistance between two diagonal corners of the square is measured. Thus, sheet resistance is typically given in units of ohms per square (Ω / □). For example, the x-axis of Figures 3A-3D shows the range of common electrode sheet resistance from 0 Ω / □ to approximately 1,000 Ω / □. The y-axis of FIG. 3A in FIG. 3A-3D represents the IR-drop in volts (V) when the corresponding common electrode sheet resistance is applied to the common electrode (cathode electrode), and ranges from approximately 0.467V to 0.476V.

[0094] Referring to Figures 3A-3D, 3B shows that the IR-drop can be reduced by reducing the LD (e.g., laser drilled hole, LD hole, or emissive layer opening ELOP) contact resistance (corresponding to the resistance of the contact between the common electrode CME and the connecting electrode AE through the emissive layer opening ELOP). For example, the x-axis of Figures 3A-3D 3B shows the LD contact resistance value range from about 0 Ω to about 1,000 Ω. The y-axis of Figures 3A-3D 3B shows the IR-drop in volts (V) for the corresponding LD contact resistance, ranging from about 0.471 V to 0.48 V.

[0095] Referring to Figures 3A-3D, 3C, the IR-drop can be reduced by varying the laser drill (LD) spacing per pixel (corresponding to the number of ELOPs per given pixel). For example, the x-axis of Figures 3A-3D shows the LD spacing ratio range from approximately one ELOP per pixel to approximately one ELOP per 70 pixels. The y-axis of Figures 3A-3D shows the IR-drop in volts (V) at the corresponding LD spacing, ranging from approximately 0.47V to 0.55V.

[0096] Referring to Figures 3A-3D, backplane (BP) wire resistance (which can also be referred to as backplane wiring resistance) corresponds to the resistance measured across the common voltage line CVL across the display panel. It can be seen that reducing the backplane wire resistance (which can also be referred to as the resistance from a pad connected to one end of the common voltage line CVL on one side of the display panel to the opposite end of the common voltage line CVL on the opposite side of the display panel) can reduce the IR-drop. For example, the x-axis of Figures 3A-3D represents a range of BP wire resistance values from about 0 Ω to about 0.4 Ω per pixel. The y-axis of Figures 3A-3D represents the IR-drop in volts (V) at the corresponding BP wire resistance values, ranging from about 0.2 V to 1.1 V.

[0097] 4A-4D are graphs showing normalized versions of the graphs in FIGS. 3A-3D.

[0098] Referring to 4A and 4D in Figures 4A-4D, the IR-drop values on the y-axis are adjusted to range from approximately 0 V to 1.2 V. That is, the ranges of 4A, 4B, 4C, and 4D in Figures 4A-4D are adjusted or normalized to match the range of 3D in Figures 3A-3D. As can be seen, by comparing the degree of change between 4A to 4D in Figures 4A-4D, it can be seen that changes in BP wire resistance (4D in Figures 4A-4D) and LD spacing (4C in Figures 4A-4D) can have a greater impact on IR-drop than changes in cathode sheet resistance (4A in Figures 4A-4D) or LD contact resistance (4B in Figures 4A-4D).

[0099] Parameter 1 (corresponding to x2 in the following formula 1): common electrode sheet resistance 5A is a graph showing the change in sheet resistance of common electrode materials including ytterbium (Yb) and silver-magnesium (Ag:Mg) based on a range of common electrode thicknesses from about 40 Å to 140 Å, in accordance with one or more embodiments of the present invention. As one skilled in the art will recognize, sheet resistance can be measured using the four-point probe system described above.

[0100] The common electrode sheet resistance (also referred to as the "cathode sheet resistance" or "cathode electrode sheet resistance") affects the IR drop of a display device. The common electrode sheet resistance can be determined (e.g., approximated) and / or varied based on the thickness and type of material used to form the common electrode CME (see, for example, FIG. 2). For example, a thin common electrode CME may have a higher resistance than a thick common electrode CME. A thick common electrode is more suitable for low resistance and may also result in a low IR drop. However, the thickness of the common electrode may affect light transmittance. Therefore, a thin common electrode may be more suitable when considering light output efficiency. According to one or more embodiments, when a common electrode includes ytterbium (Yb) and silver-magnesium (Ag:Mg) and has a thickness of about 60 Å, the sheet resistance may be greater than about 32 Ω / □. Therefore, when ytterbium (Yb) and silver-magnesium (Ag:Mg) are used as the common electrode material, a thickness of about 70 Å to about 140 Å may be an appropriate thickness range. If the common electrode has a thickness of about 70 Å or more, its sheet resistance may be less than about 32 Ω / □, which is the sheet resistance when the common electrode has a thickness of about 60 Å, and thus the thickness may have little or no effect on IR-drop. On the other hand, if the thickness is about 140 Å or more, light transmittance may be reduced. Furthermore, according to one or more embodiments, the thickness of the cathode electrode in a display device may not be uniform across the entire display panel and may vary, as will be appreciated by those skilled in the art. As described above, the common electrode may be formed to have a low sheet resistance (e.g., low surface resistance). If the sheet resistance is too high, the IR-drop problem may not be sufficiently reduced. In one or more embodiments, the common electrode may be formed of a material and thickness that provides a sheet resistance in the range of about 1 Ω / □ to about 50 Ω / □. In one or more embodiments, the common electrode may be formed of a material and thickness that provides a sheet resistance in the range of about 32 Ω / □ or less.

[0101] Referring to FIG. 5A, a common electrode having a thickness of about 40 Å may have a sheet resistance of about 50 Ω / □, a common electrode having a thickness of about 60 Å may have a sheet resistance of about 32 Ω / □, a common electrode having a thickness of about 80 Å may have a sheet resistance of about 22 Ω / □, a common electrode having a thickness of about 100 Å may have a sheet resistance of about 14 Ω / □, a common electrode having a thickness of about 120 Å may have a sheet resistance of about 10 Ω / □, and a common electrode having a thickness of about 140 Å may have a sheet resistance of about 9.5 Ω / □.

[0102] FIG. 5B is a chart showing the difference in efficiency associated with red, green, blue, and white based on different common electrode thicknesses.

[0103] 5B, the efficiency of each color can also vary depending on the thickness of the common electrode. For example, a common electrode having a thickness of approximately 60 Å may have a red efficiency of approximately 6.9 candelas / ampere, a green efficiency of approximately 27.6 candelas / ampere, a blue efficiency of approximately 84.7 candelas / ampere, and a white efficiency (also referred to as "W efficiency") of approximately 12.9 candelas / ampere. Also, a common electrode having a thickness of approximately 100 Å may have a red efficiency of approximately 10.1 candelas / ampere, a green efficiency of approximately 32.9 candelas / ampere, a blue efficiency of approximately 95.0 candelas / ampere, and a white efficiency of approximately 16.2 candelas / ampere.

[0104] In addition, when a very thin common electrode is used in a display panel, the light output efficiency may decrease. For example, a common electrode having a thickness of about 60 Å may have a relatively high IR drop and a very large current flow per unit area (e.g., per unit area), which may increase the risk of part of the common electrode burning. On the other hand, a common electrode having a thickness of about 80 Å or about 100 Å may have a relatively low IR drop and may reduce the risk of part of the common electrode burning.

[0105] FIG. 5C shows the luminance of a display including a common electrode having a thickness of about 60 Å.

[0106] FIG. 5D shows the luminance of a display including a common electrode having a thickness of about 80 Å.

[0107] As can be seen by comparing Figure 5C with Figure 5D, the brightness of a display with a common electrode having a thickness of approximately 60 Å may be of relatively lower quality (e.g., less uniform) than a display with a common electrode having a thickness of approximately 80 Å. For example, a display including a common electrode having a thickness of approximately 60 Å may exhibit irregularities and unevenness in brightness within the display area (e.g., irregularities in brightness in, for example, the upper and lower portions of the area shown in Figure 5C). Conversely, a display including a common electrode having a thickness of approximately 80 Å may exhibit improved irregularities and unevenness in brightness within the display area (e.g., improved irregularities in brightness across the entire area shown in Figure 5D compared to Figure 5C), thereby relatively reducing (e.g., appearing less or being eliminated) the unevenness.

[0108] The upper limit of the range of common electrode thicknesses that can be accommodated in a display panel can be determined (e.g., selected) based on how much increasing the common electrode thickness reduces the light transmittance of the front (or top) of the display panel.

[0109] As discussed below with respect to Figures 15 and 16, changes to one or more other parameters may affect the results discussed above with respect to Figures 5A-5D, i.e., the effects of the parameters discussed herein are interdependent.

[0110] The common electrode may be formed of different materials and with different thicknesses (e.g., by appropriately selecting various materials and thicknesses) to reduce (e.g., eliminate) the associated IR drop. The common electrode may be formed of different materials and with different thicknesses (e.g., by appropriately selecting various materials and thicknesses) to increase light transmittance and thereby increase the light output efficiency of the corresponding light-emitting component. The common electrode may be deposited thinly to improve light transmittance. However, if the common electrode is too thin, it may be ineffective or less effective in reducing (e.g., preventing) IR drop issues at the contact between the common electrode CME and the connecting electrode AE (see FIG. 2). On the other hand, if the common electrode is too thick, transmittance may be reduced, and the corresponding light output efficiency of the light-emitting component may also be reduced. In one or more embodiments, the common electrode may be formed to have a thickness in the range of approximately 40 to 200 Å. In one or more embodiments, the common electrode may be formed to have a thickness in the range of approximately 50 to 140 Å. In one or more embodiments, the common electrode may be formed to have a thickness in the range of approximately 70 to 140 Å.

[0111] The common electrode may be made of a material suitable for a given transmissive configuration (e.g., transflective, transflective, or reflective) associated with the display. For example, in a transmissive display embodiment, the common electrode may include one or more transparent metal oxides. Some exemplary metal oxides for transmissive common electrodes include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. In a transmissive display embodiment or a reflective display embodiment, the common electrode may include one or more of silver (Ag), magnesium (Mg), copper (Cu), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), molybdenum (Mo), titanium (Ti), ytterbium (Yb), tungsten (W), indium (In), zinc (Zn), tin (Sn), and the like, as well as compounds or mixtures thereof (e.g., AgMg, AgYb, MgAg, etc.). However, the present invention is not limited thereto. For example, the common electrode may include other components known to those skilled in the art. Alternatively, in one or more embodiments, the common electrode may include a multi-layer structure including one or more layers including components associated with a transmissive mode and / or one or more layers including components associated with a semi-transmissive and / or reflective mode.

[0112] FIG. 6A is a graph illustrating common electrode sheet resistance for different materials and thicknesses, according to some embodiments of the present invention.

[0113] Referring to FIG. 6A , measurement results for nine different common electrode embodiments show how the material and thickness affect the resulting sheet resistance of the common electrode. Each common electrode described below with reference to FIG. 6A is located adjacent to (or formed with) an electron injection layer EIL containing ytterbium (Yb). In this case, the material constituting the common electrode may include, for example, silver, magnesium, and ytterbium (Yb) constituting the electron injection layer EIL. However, the present invention is not limited thereto. Also, the last three common electrodes described below with reference to FIG. 6A are located adjacent to (or formed with) an electron injection layer EIL containing 1512C:Yb (10 Å, 5%). In this case, the material constituting the common electrode may include, for example, silver, magnesium, and 1512C:Yb (10 Å, 5%) constituting the electron injection layer EIL.

[0114] For example, when the electron injection layer EIL contains ytterbium (Yb), according to the three bar graphs on the left side of Figure 6A, a common electrode containing AgMg and having a thickness of about 60 Å may have a sheet resistance of about 11.8 Ω / □, a common electrode containing AgMg and having a thickness of about 80 Å may have a sheet resistance of about 9.8 Ω / □, and a common electrode containing AgMg and having a thickness of about 100 Å may have a sheet resistance of about 7.8 Ω / □.

[0115] 6A , when the electron injection layer EIL includes ytterbium (Yb), the common electrode including a first AgMg layer having a thickness of about 10 Å, a second Ag layer having a thickness of about 40 Å, and a third AgMg layer having a thickness of about 10 Å may have a sheet resistance of about 7.0 Ω / □, the common electrode including a first AgMg layer having a thickness of about 10 Å, a second Ag layer having a thickness of about 60 Å, and a third AgMg layer having a thickness of about 10 Å may have a sheet resistance of about 5.4 Ω / □, and the common electrode including a first AgMg layer having a thickness of about 10 Å, a second Ag layer having a thickness of about 80 Å, and a third AgMg layer having a thickness of about 10 Å may have a sheet resistance of about 4.4 Ω / □.

[0116] When the electron injection layer EIL includes 1512C:Yb (10 Å, 5%), the three bar graphs on the right side of FIG. 6A show that a common electrode including a first AgMg layer having a thickness of about 10 Å, a second Ag layer having a thickness of about 40 Å, and a third AgMg layer having a thickness of about 10 Å may have a sheet resistance of about 6.5 Ω / □, a common electrode including a first AgMg layer having a thickness of about 10 Å, a second Ag layer having a thickness of about 60 Å, and a third AgMg layer having a thickness of about 10 Å may have a sheet resistance of about 6.1 Ω / □, and a common electrode including a first AgMg layer having a thickness of about 10 Å, a second Ag layer having a thickness of about 80 Å, and a third AgMg layer having a thickness of about 10 Å may have a sheet resistance of about 4.6 Ω / □.

[0117] FIG. 6B is a graph illustrating common electrode sheet resistance for different materials and thicknesses, according to some embodiments of the present invention.

[0118] Referring to FIG. 6B , three different examples of common electrodes containing AgMg of different thicknesses are used as a reference ("Ref") for how different materials affect the common electrode sheet resistance. For example, the sheet resistance of a common electrode containing AgMg and having a thickness of approximately 60 Å may be approximately 15.4 Ω / □, the sheet resistance of a common electrode containing AgMg and having a thickness of approximately 80 Å may be approximately 12.8 Ω / □, and the sheet resistance of a common electrode containing AgMg and having a thickness of approximately 100 Å may be approximately 10.1 Ω / □. These sheet resistance values differ from the sheet resistance values for common electrodes containing AgMg and having the same thickness in the graph of FIG. 6A . This is because the common electrode sheet resistance also depends on other factors, such as the material and composition of the layer on which the common electrode is formed (e.g., the material and composition of the electron injection layer EIL when the common electrode is formed adjacent to the electron injection layer EIL). Similarly, the other sheet resistances shown in FIG. 6B can be achieved by changing the material and / or composition of the underlying layer in contact with the common electrode.

[0119] According to some embodiments, the sheet resistance of a common electrode containing pure Ag and having a thickness of approximately 60 Å may be approximately 20.7 Ω / □, the sheet resistance of a common electrode containing pure Ag and having a thickness of approximately 80 Å may be approximately 12.0 Ω / □, and the sheet resistance of a common electrode containing pure Ag and having a thickness of approximately 100 Å may be approximately 6.1 Ω / □.

[0120] According to some embodiments, a common electrode including a first AgMg layer having a thickness of about 10 Å and a second Ag layer having a thickness of about 50 Å may have a sheet resistance of about 12.9 Ω / □, a common electrode including a first AgMg layer having a thickness of about 10 Å and a second Ag layer having a thickness of about 60 Å may have a sheet resistance of about 11.7 Ω / □, and a common electrode including a first AgMg layer having a thickness of about 10 Å and a second Ag layer having a thickness of about 70 Å may have a sheet resistance of about 10.0 Ω / □. A common electrode including a first AgMg layer having a thickness of about 10 Å and a second Ag layer having a thickness of about 80 Å may have a sheet resistance of about 8.2 Ω / □, a common electrode including a first AgMg layer having a thickness of about 10 Å and a second Ag layer having a thickness of about 90 Å may have a sheet resistance of about 7.0 Ω / □, and a common electrode including a first AgMg layer having a thickness of about 10 Å and a second Ag layer having a thickness of about 100 Å may have a sheet resistance of about 5.8 Ω / □.

[0121] According to some embodiments, a common electrode including a first AgMg layer having a thickness of about 10 Å, a second Ag layer having a thickness of about 60 Å, and a third AgMg layer having a thickness of about 10 Å may have a sheet resistance of about 6.1 Ω / □; a common electrode including a first AgMg layer having a thickness of about 10 Å, a second Ag layer having a thickness of about 80 Å, and a third AgMg layer having a thickness of about 10 Å may have a sheet resistance of about 5.8 Ω / □; and a common electrode including a first AgMg layer having a thickness of about 10 Å, a second Ag layer having a thickness of about 100 Å, and a third AgMg layer having a thickness of about 10 Å may have a sheet resistance of about 4.7 Ω / □.

[0122] According to one or more embodiments, the thickness of the common electrode CME (e.g., cathode electrode) ranges from about 40 Å to about 200 Å. According to one or more embodiments, the cathode electrode has a thickness ranging from about 40 Å to about 140 Å. According to one or more embodiments, the thickness of the common electrode may range from about 50 Å to about 140 Å. According to one or more embodiments, the thickness of the common electrode CME ranges from about 60 Å to about 140 Å. According to one or more embodiments, the thickness of the common electrode CME ranges from about 70 Å to about 140 Å. According to one or more embodiments, the common electrode CME includes (e.g., is formed of) a metal or a combination of metals. According to one or more embodiments, the common electrode includes one or more layers (e.g., consists of one or more layers) including at least one of ITO, IZO, ZnO, ITZO, Yb, Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Lr, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, Sn, W, In, Zn, or a combination thereof. According to one or more embodiments, the common electrode includes YbAg:Mg. According to one or more embodiments, the common electrode CME has a sheet resistance of about 9.7 Ω / □ to about 50 Ω / □. According to one or more embodiments, the common electrode CME has a sheet resistance of less than about 32 Ω / □.

[0123] Parameter 2 (corresponding to x1 in the following formula 1): Contact resistance FIG. 7A is a schematic plan view of a light-emitting layer opening formed in a light-emitting layer in accordance with one or more embodiments of the present invention.

[0124] 7B is a schematic cross-sectional view of a light-emitting layer opening formed in the light-emitting layer shown in FIG. 7A in accordance with one or more embodiments of the present invention.

[0125] The contact resistance condition affects the IR-drop. The contact resistance can be determined (e.g., approximated) and / or modified based on the area of the contact hole (e.g., the area corresponding to the light-emitting layer opening ELOP). Such contact resistance (also referred to as "LD resistance") is represented by the resistance corresponding to the contact area (e.g., the amount of contact) between a portion of the common electrode CME and a portion of the connecting electrode AE at the light-emitting layer opening ELOP. In one or more embodiments, the extent of removal of the light-emitting layer can be monitored to improve or optimize the LD contact resistance condition to reduce the IR-drop. For example, a smaller light-emitting layer opening ELOP can result in a higher resistance than a larger light-emitting layer opening ELOP. Here, a smaller light-emitting layer opening ELOP allows for a smaller contact area between the common electrode CME and the connecting electrode AE. On the other hand, a larger light-emitting layer opening ELOP allows for a larger contact area between the common electrode CME and the connecting electrode AE. A larger contact area allows for a larger contact area than a smaller contact area. That is, the LD contact resistance is generally inversely proportional to the size of the light-emitting layer opening ELOP. The IR-drop increases with increasing resistance.

[0126] As those skilled in the art will recognize, there are numerous alternative systems and methods that can be used to measure LD contact resistance. Furthermore, those skilled in the art should be able to devise systems and / or methods for measuring and / or determining LD contact resistance in a display device (or display panel) without undue experimentation. Therefore, embodiments of the present invention are not related to the need for any particular method or system for measuring LD contact resistance.

[0127] 7A and 7B , the emissive layer EL region is completely removed at the emissive layer opening ELOP, so that the common electrode CME on one side (upper side) of the emissive layer EL may contact the connecting electrode AE on the other side (lower side) of the emissive layer EL. As described above, a laser may be used on the emissive layer EL to form the emissive layer opening ELOP. In one or more embodiments, a Gaussian beam laser may be used to drill a laser drill hole to form the emissive layer opening ELOP. The Gaussian beam may have the highest intensity in the center and gradually decrease in intensity from the center to the periphery. Thus, the emissive layer opening ELOP may be surrounded by a sloped region in a cross-sectional view, and some, but not all, of the emissive layer may be removed.

[0128] For example, the first region R1 may include a sloped shoulder-like portion of the light-emitting layer EL, where the shoulder-like portion corresponds to a portion of the sloped region having a thickness of the light-emitting layer EL that is greater (higher) than the normal thickness (e.g., average thickness) of the light-emitting layer EL. The thick shoulder-like portion of the light-emitting layer in the first region R1 may be formed as a bar (e.g., a bump or region where the light-emitting layer EL has a height higher than adjacent regions) in which the light-emitting layer EL is pushed outward by laser drilling holes to form the third region R3, the second region R2, etc., in the light-emitting layer EL, and may have a shape based on a portion of the light-emitting layer EL. The outer edge of the first region R1 may have an outer width (OW) (e.g., outer diameter) associated with the light-emitting layer opening ELOP. The outer width OW may correspond to a portion of the light-emitting layer EL that is directly or indirectly affected by laser processing. The first region R1 may surround a second region (e.g., the first region R1 may be adjacent to and immediately surround the second region R2). The second region R2 may include a portion of the light-emitting layer that is thinner than the normal thickness of the light-emitting layer EL. The second region R2 may surround the third region R3 (e.g., the second region R2 may be adjacent to and immediately surround the third region R3). The third region R3 may correspond to the light-emitting layer opening ELOP. The third region R3 may be a hole formed through (e.g., completely through) the light-emitting layer EL, where the light-emitting layer EL is completely removed (e.g., completely deleted). The third region R3 (and the light-emitting layer opening ELOP) may have an inner width (IW, e.g., inner diameter). The inner diameter IW may be inferred based on the outer diameter W1 of the first region R1 if measuring the outer diameter OW is easier (e.g., faster or more convenient) than measuring the inner diameter IW. For example, in one or more embodiments, if the outer diameter OW is considered to be 100, the inner diameter IW can be inferred to be 60 + / - 20 (40 (= 60 - 20) or more, 80 (= 60 + 20) or less). The third region R3 can correspond to a position where the intensity of the Gaussian beam is greatest during laser processing. The fourth region R4 can surround the first region R1 (e.g., the fourth region R4 can be adjacent to and immediately surround the first region R1). The fourth region R4 can include a thickness of the light-emitting layer that is closer to the normal thickness of the light-emitting layer EL than the thickness of the light-emitting layer in the first region R1 and / or the second region R2.

[0129] Although Figure 7A illustrates circular regions R1-R3, the present invention is not limited thereto. For example, regions R1-R3 may have a polygonal shape (e.g., an octagonal shape), in which case the inner width IW and outer width OW may correspond to the maximum distance between the diagonals of the polygonal shape, respectively. The shape of regions R1-R3 may be any suitable shape known to those skilled in the art. This maximum distance may be referred to as the greatest width, which may also refer to the largest dimension of a non-angular closed curve (a closed curve form without corners) such as a circle. For example, the greatest width of a circle is its diameter.

[0130] According to one or more embodiments, the inner width IW can be in a range from about 1 μm to about 30 μm. According to one or more embodiments, the inner width IW can be determined based on a corresponding (e.g., resulting) LRU percentage. For example, the emissive layer opening ELOP can be formed to have an inner width IW in a range that does not include an LRU of less than 70%. For example, a display with an LRU of less than 70% can exhibit irregularities (e.g., mura) such as spots (e.g., discoloration). In some cases, an inner width IW of about 3 μm can result in a white efficiency of about 12 candelas / amp, an LRU of about 60.1%, and mura that renders (appears to be) a display defect. Alternatively, an inner width IW of about 5 μm can result in a white efficiency of about 13.2 candelas / amp, an LRU of about 93.8%, and no mura (e.g., that renders) a display defect. In one or more embodiments, the inner width IW may be at least about 4 μm and the LRU may be at least 70%. According to one or more embodiments, the inner width IW may range from about 4 μm to about 7 μm. If the inner width IW is about 7 μm, the white efficiency may be 13.2 candela / amp. In one or more embodiments of the present invention, the display device may have a white efficiency of about 13.8 candela / amp and an LRU of about 80%, with no visible mura.

[0131] According to one or more embodiments, the outer width OW can range from about 1 μm to about 30 μm. According to one or more embodiments, the outer width OW can be about 10 μm. Based on the ratio (inner width IW / outer width OW = 0.4-0.8) of 100 to 60 + / - 20 (e.g., if the outer width OW is 100, the inner width IW is 60 + / - 20 (40 (= 60 - 20) or more, 80 (= 60 + 20) or less)) discussed above, an outer diameter OW in the range of about 1 μm to about 30 μm can be used to estimate an inner diameter IW of about 0.4 μm to about 24 μm (e.g., 0.6 μm + / - 0.2 μm to 18 μm + / - 6 μm). Alternatively, an outer diameter OW of about 10 μm can be used to estimate an inner diameter IW of about 4 μm to 8 μm.

[0132] FIG. 7C shows three focused ion beam FIB images of outer and inner widths associated with three different light-emitting layer apertures of an example experiment, according to one or more embodiments of the present invention.

[0133] 7C, in a first example, an outer diameter OW of about 11 μm corresponds to an inner diameter IW of about 7.1 μm. In a second example, an outer diameter OW of about 6 μm corresponds to an inner diameter IW of about 3.2 μm; and in a third example, an outer diameter OW of about 7 μm corresponds to an inner diameter IW of about 5.3 μm.

[0134] Based on measurements and / or calculations (e.g., based on simulations), it has been found that the contact resistance is inversely proportional to the size of the light-emitting layer opening. For example, an outer diameter OW of about 0.8 μm may result in a contact resistance of about 1,500 Ω. An outer diameter OW of about 1 μm may result in a contact resistance of about 980 Ω. An outer diameter OW of about 5 μm may result in a contact resistance of about 39.2 Ω. An outer diameter OW of about 10 μm may result in a contact resistance of about 9.8 Ω. An outer diameter OW of about 30 μm may result in a contact resistance of about 1.1 Ω. The contact resistance may be determined (e.g., calculated) based on an assumed square region having the same length and width as the outer diameter OW. In one or more embodiments, the contact resistance may range between about 1 Ω and about 1,000 Ω per light-emitting layer opening.

[0135] Parameter 3 (corresponding to x3 in Equation 1 below): hole-forming interval and hole count 8A and 8B are schematic diagrams illustrating a display (e.g., a display device or display panel) having holes drilled (e.g., laser drilled) at substantially regular (or uniform) intervals across the display area of the display, in accordance with one or more embodiments of the present invention.

[0136] 8C and 8D are schematic diagrams illustrating a display (e.g., a display device or display panel) having holes drilled (e.g., laser drilled) in a pattern (e.g., a chess pattern) associated with subgroups of pixel electrode sets, according to one or more embodiments of the present invention.

[0137] The hole formation-spacing (e.g., pitch) conditions (e.g., LD hole spacing conditions) and hole count affect IR-drop. Focusing on a given spacing (e.g., maximum distance) between adjacent light-emitting layer openings ELOP can reduce or minimize the occurrence of IR-drop while reducing or minimizing the fabrication time in forming the light-emitting layer openings ELOP. However, as the spacing between nearest neighboring light-emitting layer openings ELOP increases, it becomes more difficult to reduce IR-drop across the display panel and the risk of burning of the common electrode CME at the light-emitting layer openings ELOP increases.

[0138] 8A-8B, 8A and 8B show that the emissive layer openings ELOP can be formed across the entire display panel DP (e.g., across the entire display panel DP). In one or more embodiments, the emissive layer openings ELOP can be formed in a first pattern P1 (e.g., a constant pitch pattern or a uniform pitch pattern) that defines a constant interval (e.g., defines a constant pitch or a uniform pitch) across the entire display panel DP. For example, in the first pattern P1, each emissive layer opening ELOP can be spaced a substantially constant distance d (e.g., spacing) from an adjacent (e.g., neighboring) emissive layer opening ELOP (e.g., the nearest emissive layer opening ELOP) across the entire display panel DP (e.g., across the entire display panel DP). The distance d can also be referred to as the hole formation spacing (also referred to as the "pitch" in mm or the "LD spacing" in mm). The LD spacing can also be referred to in terms of apertures per pixel. For example, in one or more embodiments, the LD spacing of the first pattern P1 can range from one emitting layer opening ELOP per (1×1) pixel (i.e., one emitting layer opening ELOP per pixel in each horizontal and vertical direction) to one emitting layer opening ELOP per (72×72) pixel (i.e., one emitting layer opening ELOP per 72 pixels in each horizontal and vertical direction). In other embodiments, there can be a different number of emitting layer openings in the horizontal and vertical directions. For example, there can be one emitting layer opening per (2×2) pixel, per (3×3) pixel, per (4×4) pixel, per (5×5) pixel, per (6×6) pixel, per (7×7) pixel, per (8×6) pixel, per (9×9) pixel, per (10×12) pixel, or any other suitable number of pixels as will be appreciated by those skilled in the art. Additionally, the number of pixels between the emitting layer openings in the horizontal and vertical directions can be different from each other. By reducing the number of light emitting layer openings ELOP relative to the number of pixels, the production time for each display panel DP can be reduced, thereby improving the tact time.As an example, in a 65-inch television, the distance d (e.g., spacing) between nearest emissive layer openings ELOP may range from about 1.1 mm (or 1.116 mm) to about 20 mm, and the number of emissive layer openings ELOP may be in the range of about 57,000 to about 920,000 (or about 57,600 to about 921,600).

[0139] Referring to FIGS. 8C and 8D, in one or more embodiments, the emissive layer openings ELOP may be formed in (or based on) a chess pattern CP throughout the display panel DP. For example, the display panel DP may be divided into hole-forming regions HFA and skip regions SKA. The hole-forming regions HFA and skip regions SKA may be formed in groups G. The groups G may be formed in an alternating pattern similar to the visual pattern on a chessboard. That is, the hole-forming regions HFA and skip regions SKA are formed adjacent to each other. According to the example of FIG. 8C in FIGS. 8C-8D, the hole-forming regions HFA and skip regions SKA are alternately arranged along the X direction, and the hole-forming regions HFA and skip regions SKA are alternately arranged along the Y direction. The hole-forming regions HFA may include emissive layer openings ELOP formed at a substantially constant pitch, as discussed above with respect to the distance d between adjacent emissive layer openings ELOP. The skip regions SKA do not have emissive layer openings ELOP formed therethrough. One hole formation region HFA may correspond to one subgroup SG of the pixel electrode sets (or pixels). One skip region SKA may correspond to another subgroup SG of the pixel electrode sets (or pixels). The subgroups SG of the pixel electrode sets in each group G may be arranged in a matrix (e.g., arranged in rows and columns of pixel electrode sets). Throughout each hole formation region HFA, each light-emitting layer opening ELOP may be spaced a substantially constant (e.g., substantially uniform) distance d from an adjacent (e.g., adjacent) light-emitting layer opening ELOP (e.g., the nearest light-emitting layer opening ELOP). Each hole formation region HFA may have a hole formation region width W along a horizontal line (e.g., in the X direction) from the leftmost light-emitting layer opening ELOP of the hole formation region HFA to the rightmost light-emitting layer opening ELOP of the hole formation region HFA. In one hole formation region HFA, the light-emitting layer openings may be referred to as a subset of light-emitting layer openings. Each hole formation region HFA may have a hole formation region height H along the vertical direction (eg, the Y direction) from the uppermost light-emitting layer opening ELOP of the hole formation region HFA to the lowermost light-emitting layer opening ELOP of the hole formation region HFA.Each hole formation region HFA may be separated from its nearest neighbor (e.g., adjacent) hole formation region HFA by a horizontal separation distance (HSd), which is the distance from the rightmost light-emitting layer opening ELOP of one hole formation region HFA to the nearest leftmost light-emitting layer opening ELOP of the nearest hole formation region HFA. Each hole formation region HFA may be separated from its nearest neighbor hole formation region HFA by a vertical separation distance (VSd), which is the distance from the bottommost light-emitting layer opening ELOP of one hole formation region HFA to the nearest topmost light-emitting layer opening ELOP of the nearest hole formation region HFA. According to one or more embodiments, the width W is approximately 5.58 mm, and the horizontal separation distance HSD is approximately 5.58 mm. However, the present invention is not limited thereto. In other embodiments, W and HSD may be different from 5.58 mm or may be different from each other.

[0140] According to one or more embodiments, the width W of the hole formation region may be the same as or different from the height H of the hole formation region. The distance d between adjacent (e.g., adjacent) emissive layer openings ELOP in the horizontal and vertical directions may be the same as or different from the height H of the hole formation region. Not all pixel electrode sets in a hole formation region have corresponding emissive layer openings ELOP. For example, in each hole formation region, the distance between two emissive layer openings in the horizontal and vertical directions may be greater than the distance between two adjacent pixels (e.g., pixel electrode sets). For example, the distance between two emissive layer openings in the horizontal and vertical directions may be expressed as the distance between two adjacent pixels (e.g., pixel electrode sets) multiplied by a predetermined factor, such as, but not limited to, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, etc. Furthermore, the horizontal and vertical dimensions of the hole-forming regions HFA may differ from each other, and the distances between adjacent (eg, neighboring) light-emitting layer openings ELOP in the horizontal and vertical directions may differ from each other.

[0141] 8E, 8F, and 8G are diagrams illustrating variations in patterns (eg, chess patterns) associated with subgroups of pixel electrode sets, in accordance with one or more embodiments of the present invention.

[0142] 8E, in one or more embodiments, the chess pattern may be a first chess pattern CP1 that is a 1 / 4 chess pattern, where each group G includes four subgroups SG, with only one of the subgroups SG corresponding to a hole formation region HFA. That is, each group G includes four subgroups SG, one subgroup SG being a hole formation region HFA and three subgroups SG being skip regions SKA. Based on the first chess pattern CP1, the total number of emissive layer openings ELOP may be 25% or less of the total number of pixels (or pixel electrode sets) of the display panel DP.

[0143] Referring to FIG. 8F, in one or more embodiments, the chess pattern may be a second chess pattern CP2 that is a 1 / 9 chess pattern, but each group G includes nine subgroups SG, with only one of the subgroups SG corresponding to a hole formation region HFA. That is, each group G includes nine subgroups SG, one subgroup SG being a hole formation region HFA, and eight subgroups SG being skip regions SKA. In the second chess pattern CP2, the total number of emissive layer openings ELOP may be smaller than the total number of emissive layer openings ELOP in the first chess pattern CP1. Also, not all pixels in a subgroup SG within a hole formation region may have an emissive layer opening ELOP. For example, in the second chess pattern CP2, the total number of emissive layer openings ELOP may be 11.1% or less of the total number of pixels (or pixel electrode sets) of the display panel DP.

[0144] Referring to FIG. 8G , in one or more embodiments, the chess pattern may be a third chess pattern CP3, which is a 1 / 16 chess pattern, but each group G includes 16 subgroups SG, with only one of the subgroups SG corresponding to a hole formation region HFA. That is, each group G includes 16 subgroups SG, one subgroup SG corresponding to a hole formation region HFA, and 15 subgroups SG corresponding to skip regions SKA. In the third chess pattern CP3, the total number of emissive layer openings ELOP may be less than the total number of emissive layer openings in the first chess pattern CP1. In the third chess pattern CP3, the total number of emissive layer openings ELOP may be less than the total number of emissive layer openings in the second chess pattern CP2. Also, not all pixels in a subgroup SG within a hole formation region may have an emissive layer opening ELOP. For example, in the third chess pattern CP3, the total number of emissive layer openings ELOP may be less than 6.25% of the total number of pixels (or pixel electrode sets) in the display panel DP.

[0145] Those skilled in the art should understand that the present invention is not limited to the examples shown with 4, 9, and 16 subgroups SG per group G. For example, the number of subgroups SG per group G may be 25, 32, 64, or any other suitable number of subgroups per group G as recognized by those skilled in the art. Also, the pitch of the light-emitting layer openings ELOP in each subgroup SG may be the same as or greater than the pitch of the pixels in each subgroup SG.

[0146] FIG. 8H is a chart of pixel and hole parameters for a 65-inch display in accordance with one or more embodiments of the present invention.

[0147] Referring to FIG. 8H, a display panel (e.g., included in a 65-inch television) may have a resolution of 3840 x 2160 (e.g., 8,294,400 pixels (or pixel electrode sets)). Implementing the first pattern P1 on a 65-inch display with such a constant pitch (k) may result in a hole count (e.g., emissive layer openings ELOP) of approximately 921,600. That is, the display panel may have one emissive layer opening per 3 x 3 or 9 pixels (e.g., pixel electrode sets). In this particular embodiment, the number of holes (e.g., emissive layer openings) is 921,600, although the present invention is not limited thereto. For example, the process distance during manufacturing may be between approximately 0.8 mm and approximately 1.2 mm.

[0148] Implementing the first chess pattern CP1 on a 65-inch display panel results in a hole count (e.g., emissive layer openings) of approximately 230,400 (e.g., one emissive layer opening per 3x3 or 9 pixels in each subgroup of a group of pixels (or pixel electrode sets), with the group containing four subgroups implementing a 1 / 4 chess pattern. In this particular embodiment, the number of holes (e.g., emissive layer openings) is 230,400, although the invention is not so limited. By way of example, the process distance during manufacturing may be between approximately 4.8 mm and approximately 7.2 mm.

[0149] Implementing the second chess pattern CP2 on a 65-inch display panel results in a hole count (e.g., emissive layer openings) of approximately 102,400 (e.g., one emissive layer opening per 3x3 or 9 pixels in each subgroup of a group of pixels (or pixel electrode sets)), with the group containing 9 subgroups implementing a 1 / 9 chess pattern. In this particular example, the number of holes (e.g., emissive layer openings) is 102,400, although the invention is not so limited. By way of example, the process distance during manufacturing may be between approximately 9.6 mm and approximately 14.2 mm.

[0150] Implementing the third chess pattern CP3 on a 65-inch display panel results in a hole count (e.g., emissive layer openings) of approximately 57,600 (e.g., one emissive layer opening per 4x4 or 16 pixels in each subgroup of a group of pixels (or pixel electrode sets)), with the group containing 16 subgroups implementing a 1 / 16 chess pattern. In this particular embodiment, the number of holes (e.g., emissive layer openings) is 57,600, although the invention is not so limited. By way of example, the process distance during manufacturing may be between approximately 14.4 mm and approximately 21.6 mm.

[0151] In one or more embodiments, a plurality of pixel electrode sets PES, each including a plurality of pixel electrodes and embodying a full-color pixel, are configured into a plurality of groups G, each of which includes three pixel electrodes PE corresponding to three sub-pixels. Each of the plurality of groups G of the pixel electrode set PES includes a plurality of sub-groups SG included in one pixel electrode set, and only one of the sub-groups SG in one group G has a corresponding one of the light-emitting layer openings ELOP. For example, each pixel electrode set PES includes pixel electrodes PE corresponding to red (R), green (G), and blue (B) sub-pixels, respectively, although the present invention is not limited thereto.

[0152] In one or more embodiments, subgroups SG in a plurality of pixel electrode set groups G having corresponding emissive layer apertures define aperture regions HFA, and the width W of one aperture region HFA is equal to the distance HSd between two adjacent aperture regions HFA. According to one or more embodiments, the number of subgroups constituting one of the pixel electrode set groups ranges from 4 to 64 (e.g., 4, 9, 16, 25, 36, 49, or 64), although the invention is not limited thereto. In other embodiments, the number of subgroups constituting one of the pixel electrode set groups may be any suitable number greater than 64 (e.g., in the range of 64 to 1.00). According to one or more embodiments, the pixel electrode set groups G may be arranged in a matrix. According to one or more embodiments, the ratio between the total number of pixel electrode sets and the total number of emissive layer apertures ELOP in one of the subgroups ranges from 1 to 64 (e.g., 1, 4, 9, 16, 25, 36, 49, or 64), although the invention is not limited thereto. In other embodiments, the ratio between the total number of pixel electrode sets and the total number of light emitting layer openings ELOP in one of the subgroups may be any suitable number greater than or equal to 64 (e.g., in the range of 65 to 1.00). According to one or more embodiments, the subgroups of pixel electrode sets in each of a plurality of groups are arranged in a matrix.

[0153] FIG. 9 is a chart of pixel and hole parameters for different display sizes and types in accordance with one or more embodiments of the present invention.

[0154] Referring to Figure 9, rows RW1 through RW9 contain data for a display size of 77 inches versus 26.5 inches (e.g., standard display size) associated with a pitch where one light emitting layer aperture is arranged per pixel (see column CL4, which shows one LD spacing for rows RW1 through RW9). Rows RW10 through RW18 contain data for a display size of 77 inches versus 26.5 inches associated with a pitch where one light emitting layer aperture is arranged per 72 pixels (see column CL4, which shows 72 LD spacing for rows RW10 through RW18).

[0155] Referring to rows RW1 through RW10, a 77-inch display having a pixel pitch of approximately 0.443 mm (see column CL1), a resolution of 3840 x 2160 (e.g., a total of 8,294,400 pixels) (see column CL2), and approximately 57.3 pixels per inch (ppi) (see column CL3) may have: (i) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 0.443 mm and an emissive layer aperture count of approximately 8,294,400 (see column CL6), based on a pitch of one emissive layer aperture per pixel (see column CL4); and (ii) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 31.896 mm and an emissive layer aperture count of approximately 1,600 (see column CL6), based on a pitch of one emissive layer aperture per 72 pixels (see column CL4).

[0156] Referring to rows RW2 through RW11, a 65-inch display having a pixel pitch (see column CL1) of approximately 0.372 mm, a resolution (see column CL2) of 3840 x 2160 (e.g., a total of 8,294,400 pixels), and approximately 67.8 pixels per inch (ppi) (see column CL3) may have: (i) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 0.372 mm and an emissive layer aperture count (see column CL6) of approximately 8,294,400, based on a pitch of one emissive layer aperture per pixel (see column CL4); and (ii) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 26.784 mm and an emissive layer aperture count (see column CL6), based on a pitch of one emissive layer aperture per 72 pixels (see column CL4).

[0157] Referring to rows RW3 through RW12, a 55-inch display having a pixel pitch (see column CL1) of approximately 0.315 mm, a resolution (see column CL2) of 3840 x 2160 (e.g., a total of 8,294,400 pixels), and approximately 80.6 pixels per inch (see column CL3): (i) in one or more embodiments, based on a pitch of one emissive layer aperture per pixel (see column CL4), an emissive layer aperture spacing (see column CL5) of approximately 0.315 mm and an emissive layer aperture count (see column CL6) of approximately 8,294,400; and (ii) in one or more embodiments, based on a pitch of one emissive layer aperture per 72 pixels (see column CL4), an emissive layer aperture spacing (see column CL5) of approximately 22.68 mm and an emissive layer aperture count (see column CL6).

[0158] Referring to rows RW4 through RW13, a 49-inch display having a pixel pitch (see column CL1) of approximately 0.233 mm, a resolution (see column CL2) of 5136 x 1456 (e.g., a total of 7,478,016 pixels), and approximately 109 pixels per inch (ppi) (see column CL3) may have: (i) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 0.233 mm and an emissive layer aperture count (see column CL6) based on a pitch of one emissive layer aperture per pixel (see column CL4); and (ii) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 16.776 mm and an emissive layer aperture count (see column CL6) based on a pitch of one emissive layer aperture per 72 pixels (see column CL4).

[0159] Referring to rows RW5 through RW14, a 34-inch display having a pixel pitch (see column CL1) of approximately 0.2315 mm, a resolution (see column CL2) of 3456 x 1456 (e.g., a total of 5,031,936 pixels), and approximately 109.6 pixels per inch (see column CL3): (i) in one or more embodiments, based on a pitch of one emissive layer aperture per pixel (see column CL4), an emissive layer aperture spacing (see column CL5) of approximately 0.2315 mm and an emissive layer aperture count (see column CL6) of approximately 5,031,936; and (ii) in one or more embodiments, based on a pitch of one emissive layer aperture per 72 pixels (see column CL4), an emissive layer aperture spacing (see column CL5) of approximately 16.668 mm and an emissive layer aperture count (see column CL6).

[0160] Referring to rows RW6 through RW15, a 31.5-inch display having a pixel pitch (see column CL1) of approximately 0.1814 mm, a resolution (see column CL2) of 3840 x 2160 (e.g., a total of 8,294,400 pixels), and approximately 140 pixels per inch (ppi) (see column CL3) may have: (i) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 0.1814 mm and an emissive layer aperture count of approximately 8,294,400 (see column CL6), based on a pitch of one emissive layer aperture per pixel (see column CL4); and (ii) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 13.0608 mm and an emissive layer aperture count of approximately 1,600 (see column CL6), based on a pitch of one emissive layer aperture per 72 pixels (see column CL4).

[0161] Referring to rows RW7 through RW16, a 26.5-inch display having a pixel pitch (see column CL1) of approximately 0.2292 mm, a resolution (see column CL2) of 2560 x 1440 (e.g., a total of 3,686,400 pixels), and approximately 110.8 pixels per inch (ppi) (see column CL3) may have: (i) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 0.2292 mm and an emissive layer aperture count (see column CL6) of approximately 3,686,400, based on a pitch of one emissive layer aperture per pixel (see column CL4); and (ii) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 16.5024 mm and an emissive layer aperture count (see column CL6), based on a pitch of one emissive layer aperture per 72 pixels (see column CL4).

[0162] Referring to rows RW8 through RW17, a 26.5-inch display having a pixel pitch (see column CL1) of approximately 0.153 mm, a resolution (see column CL2) of 3840 x 2160 (e.g., a total of 8,294,400 pixels), and approximately 166 pixels per inch (ppi) (see column CL3) may have: (i) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 0.153 mm and an emissive layer aperture count (see column CL6) based on a pitch of one emissive layer aperture per pixel (see column CL4); and (ii) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 11.016 mm and an emissive layer aperture count (see column CL6) based on a pitch of one emissive layer aperture per 72 pixels (see column CL4).

[0163] Referring to rows RW9 through RW18, a 26.5-inch display having a pixel pitch (see column CL1) of approximately 0.1148 mm, a resolution (see column CL2) of 5120 x 2880 (e.g., a total of 14,745,600 pixels), and approximately 220 pixels per inch (ppi) (see column CL3) may have: (i) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 0.1148 mm and an emissive layer aperture count (see column CL6) based on a pitch of one emissive layer aperture per pixel (see column CL4); and (ii) in one or more embodiments, an emissive layer aperture spacing (see column CL5) of approximately 8.2656 mm and an emissive layer aperture count (see column CL6) based on a pitch of one emissive layer aperture per 72 pixels (see column CL4).

[0164] For example, in a 2560x1440 television, the total number of emissive layer apertures may range from about 700 (or about 711, at 72 pixel intervals) to about 3,700,000 (or about 3,686,400, at 1 pixel intervals). As another example, in a 5120x2880 television, the total number of emissive layer apertures may range from about 2,800 (or about 2,844, at 72 pixel intervals) to about 14,750,000 (or about 14,745,600, at 1 pixel intervals). Thus, in various embodiments of the present invention, the total number of apertures may be in the range of about 700 to 14,750,000, or any suitable sub-range therein. Also, in a 5120 x 2880 television, if the spacing between adjacent emissive layer apertures is two pixels (i.e., one emissive layer aperture per two pixels in both the horizontal and vertical directions), there will be approximately 25% of the number of pixels, and therefore the number of emissive layer apertures will be 3,686,400, which is 25% of the total number of pixels (14,745,600). Of course, in various embodiments, the number of emissive layer apertures can vary based on the size of the television (i.e., horizontal and vertical resolution) and the spacing between pixels. Furthermore, if the emissive layer apertures are arranged in a chess pattern, the number of emissive layer apertures can also vary depending on the number of subgroups in each group and the ratio between the number of emissive layer apertures and the number of pixels (or pixel electrode sets) in each group.

[0165] In one or more embodiments, the display device is a 65-inch television (including a 65-inch display panel), and the total number of light-emitting layer apertures is in the range of 57,000 to 920,000 (e.g., in the range of 57,600 to 921,600). In one or more embodiments, the total number of pixels (or pixel electrode sets) is in the range of 4 to 5,184 (i.e., 2x2 to 72x72). In one or more embodiments, the ratio between the total number of light-emitting layer apertures and the total number of pixels (or pixel electrode sets) is in the range of 1 / 144 to 1 / 9 (e.g., in the range of 57,600 to 921,600 light-emitting layer apertures for a display having a resolution of 3840x2160).

[0166] According to one or more embodiments, the maximum width of one of the light-emitting layer openings is in the range of about 1 μm to about 30 μm. According to one or more embodiments, the maximum width of one of the light-emitting layer openings is at least about 3 μm. According to one or more embodiments, the maximum width of one of the light-emitting layer openings is in the range of about 4 μm to about 7 μm. According to one or more embodiments, the maximum width of one of the light-emitting layer openings is in the range of about 4 μm to about 6 μm. According to one or more embodiments, the maximum width of one of the light-emitting layer openings is in the range of about 3 μm to about 20 μm. Here, the maximum width refers to the maximum dimension of the light-emitting layer opening where the light-emitting layer is completely removed (or eliminated). For example, if the shape of the light-emitting layer opening is circular, the maximum width is the diameter.

[0167] Parameter 4 (corresponding to x4 in Equation 1 below): Backplane wire (or wiring) resistance 10A-10E are schematic plan views of layers of a display device according to one or more embodiments of the present invention.

[0168] The backplane wire resistance (e.g., power supply voltage ELVSS wiring resistance) condition affects the IR-drop. For example, focusing on the resistance range for the common voltage line CVL connected to the common electrode CME can reduce or minimize the occurrence of IR-drop. The BP wire resistance can be determined (e.g., approximated) and / or modified based on the wire material and wire thickness as well as the number of wire layers used.

[0169] Referring to Figures 10A to 10E, the backplane BP wire resistance can be determined (e.g., approximated) and / or modified based on the configuration and conductive material, which provides a conductive path from the backplane metal layer BML (e.g., see Figure 10A) to the connecting electrode AE (e.g., see Figure 10E).

[0170] Referring to FIG. 10A , the display panel may include a backplane metal layer BML. In one or more embodiments, the backplane metal layer BML may pass a voltage from a power supply voltage ELVSS to a common voltage line CVL for connection to a common electrode CME (see FIG. 2 ). Thus, a driving current flows within a pixel (or subpixel) from the pixel electrode to the common electrode and then to the common voltage line CVL and / or the backplane metal layer BML. In one or more embodiments, the backplane metal layer BML may include Ti and / or Cu. As such, the present invention is not limited in this respect, and the backplane metal layer BML may include any suitable metal and / or material known to those skilled in the art.

[0171] Referring to FIG. 10B , the gate electrode layer GT may be located on top of (e.g., overlap) the backplane metal layer. According to one or more embodiments, the gate electrode layer GT may be located in the same layer as the gate electrode of a transistor (e.g., a thin film transistor (TFT)) of a display device. The gate electrode layer GT may be electrically isolated from (e.g., not electrically connected to) the gate electrode of the transistor. The backplane metal layer BML may include contacts (e.g., electrical contacts) at one or more locations that do not overlap with the gate electrode layer GT to connect (e.g., electrically connect) the backplane metal layer BML to one or more other layers. For example, a contact CNT may be used to electrically connect the backplane metal layer BML to a common voltage line CVL (e.g., as shown in FIGS. 10C and 10D ). In one or more embodiments, the gate electrode layer GT may include Ti and / or Cu. However, the present invention is not limited thereto, and the gate electrode layer GT may include any suitable metal and / or material known to those skilled in the art.

[0172] Referring to FIG. 10C , the gate electrode layer GT may be electrically coupled to the common voltage line CVL (e.g., at the source-drain layer S / D). For example, the gate electrode layer GT may be electrically coupled to the common voltage line CVL via the contact CNT shown in FIG. 10B. In one or more embodiments, the common voltage line CVL may be located in the same layer as the source and / or drain electrodes of the transistors. The common voltage line CVL may be electrically isolated from (e.g., not electrically coupled to) the source and / or drain electrodes of the transistors. In one or more embodiments, the common voltage line CVL may receive the power supply voltage ELVSS from the backplane metal layer BML. In one or more embodiments, the common voltage line CVL may receive the power supply voltage ELVSS from the gate electrode layer GT. However, the present invention is not limited thereto, and the common voltage line CVL may receive the power supply voltage ELVSS via another suitable interface, for example, one or more pads directly coupled (e.g., electrically coupled) to the common voltage line CVL. In one or more embodiments, the driving current flowing from the pixel electrode to the common electrode through the light-emitting layer may pass through the common voltage line CVL to the pad and / or backplane metal layer BML. In one or more embodiments, the common voltage line CVL may include Ti, Cu, and / or ITO. However, the present invention is not limited thereto, and the common voltage line CVL may include any suitable metal and / or material known to those skilled in the art.

[0173] Referring to FIG. 10D , the common voltage line CVL may be covered by a via layer (VIA). The via layer VIA may include an insulating layer to insulate the common voltage line CVL from conductive components above the common voltage line CVL. The via layer VIA may also act as a planarizing layer to provide a substantially flat surface above the components it covers. According to one or more embodiments, the via layer VIA may have a thickness of approximately 3.0 μm. However, the present invention is not limited thereto, and the via layer VIA may include any suitable thickness known to those skilled in the art.

[0174] Referring to FIG. 10E, an anode layer AN may be formed on the via layer VIA. The anode layer AN may include a pixel electrode PE and a connecting electrode AE. While FIG. 10E illustrates one set of three subpixels in each pixel (i.e., three sets of pixel electrodes PE (or pixel electrode sets PES) in each pixel), the present invention is not limited thereto. The pixel electrode PE may be formed under a portion of the light-emitting layer within a pixel opening for one or more pixels (e.g., an opening for one or more subpixels PX1 to PX3). The connecting electrode AE may be formed adjacent to, spaced apart from, or in the same layer as the pixel electrode PE. The connecting electrode AE may be electrically insulated from (e.g., not electrically connected to) the pixel electrode PE. In one or more embodiments, the anode layer AN may include ITO and / or Ag. However, the present invention is not limited thereto, and the anode layer AN may include any suitable metal and / or material known to those skilled in the art. A pixel defining layer PDL may be formed on the via layer VIA. The pixel defining layer PDL may define the shapes of the subpixels PX1 to PX3.

[0175] FIG. 11A is a schematic cross-sectional view of a display device including a common voltage line in one layer according to some embodiments of the present invention.

[0176] Referring to FIG. 11A , in one or more embodiments, the laser drill region LDR may include a substrate layer SUB, a backplane metal layer BML, a buffer layer BL, a gate insulating layer GI, a gate electrode layer GT, an interlayer-insulation layer (ILD), a common voltage line CVL, a passivation layer (PVX), a via layer VIA, a connecting electrode AE, and a pixel definition layer PDL. The backplane metal layer BML may include a backplane metal line extending in the same direction as the common voltage line CVL and may partially or completely overlap the common voltage line CVL. The backplane metal line and the common voltage line CVL are electrically connected to each other through one or more openings in the interlayer insulating layer and may be collectively referred to as an auxiliary line or auxiliary voltage line. Also, in the example of FIG. 11A , the gate electrode layer GT is connected to the common voltage line CVL through a through-hole in the interlayer insulating layer ILD.

[0177] Although a common electrode or a light-emitting layer is not shown in FIG. 11A , a display device according to one or more embodiments may include both a common electrode and a light-emitting layer, as well as other appropriate layers recognized by one skilled in the art. The substrate layer SUB may include a pad (e.g., a pad may be formed on or within the substrate layer SUB). The pad may be formed at the interface between the source of the power supply voltage ELVSS and the backplane metal layer BML, although the present invention is not limited thereto. By way of example, the pad may be directly coupled to the common voltage line CVL according to one or more embodiments. A buffer layer BL and a gate insulating layer GI may cover the backplane metal layer BML. The buffer layer BL and the gate insulating layer GI may provide planarization and / or insulation functions (e.g., for components of the backplane metal layer BML and / or components of the gate electrode layer GT). In one or more embodiments, the buffer layer BL may include silicon nitride (SiNz) and / or silicon oxide (SiOx). However, the present invention is not limited thereto, and the buffer layer BL may include any appropriate material (e.g., any appropriate insulating material) known to one skilled in the art. In one or more embodiments, the gate insulating layer GI may include SiOx. However, the present invention is not limited thereto, and the gate insulating layer GI may include any suitable material (e.g., any suitable insulating material) known to those skilled in the art. The interlayer insulating layer ILD may cover the gate electrode layer GT. The interlayer insulating layer ILD may provide a planarization and / or insulating function (e.g., for components of the gate electrode layer GT). In one or more embodiments, the interlayer insulating layer ILD may include silicon oxynitride (SiON). However, the present invention is not limited thereto, and the interlayer insulating layer ILD may include any suitable material known to those skilled in the art. The passivation layer PVX may cover the common voltage line CVL and may provide a planarization and / or insulating function (e.g., for components of the source-drain layer S / D). In one or more embodiments, the passivation layer PVX may include SiNx. However, the present invention is not limited thereto, and the passivation layer PVX may include any suitable material (e.g., any suitable insulating material) known to those skilled in the art.

[0178] FIG. 11B is a schematic cross-sectional view of a display device including a common voltage line having two layers according to some embodiments of the present invention.

[0179] Referring to FIG. 11B, in one or more embodiments, the laser drill region LDR includes the same layers and components as FIG. 11A and may include one or more additional layers. For example, the common voltage line CVL in FIG. 11A corresponds to the first common voltage line CVL1 in FIG. 11B and is electrically connected to the backplane metal layer BML. In addition to the first common voltage line CVL1, one or more additional layers may include a second common voltage line CVL2 and a second insulating layer IL2. In one or more embodiments, the second common voltage line CVL2 may be located on top of the substrate SUB (e.g., may at least partially or completely overlap the thickness of the substrate) and may extend in the same direction as the first common voltage line CVL1. In one or more embodiments, the second common voltage line CVL2 may be connected to the first common voltage line CVL1 through one or more openings in the passivation layer PVX. In one or more embodiments, the second insulating layer IL2 may cover the second common voltage line CVL2. The second insulating layer IL2 may provide planarization and / or insulation functions (e.g., for the second common voltage line CVL2). In one or more embodiments, the connecting electrode AE is connected to the second common voltage line CVL2 through an opening (e.g., a contact hole) in the via layer VIA. According to one or more embodiments, the backplane metal line BML partially or completely overlaps and is electrically connected to the first and second common voltage lines CVL1 and CVL2. The backplane metal line BML and the first and second common voltage lines CVL1 and CVL2 may collectively be referred to as auxiliary lines or auxiliary voltage lines. Also, in the example of FIG. 11B, the gate electrode layer GT is connected to the first common voltage line CVL1 through a through-hole in the interlayer insulating layer ILD.

[0180] FIG. 11C is a schematic cross-sectional view of a display device including a common voltage line having three layers, where a first common voltage line is coupled to a backplane metal layer BML, according to some embodiments of the present invention.

[0181] Referring to FIG. 11C, in one or more embodiments, the laser drilled region LDR includes the same layers and components as FIG. 11B, but may also include one or more additional layers. For example, in addition to the first common voltage line CVL1 and the second common voltage line CVL2, the laser drilled region LDR may also include one or more additional layers, such as a third common voltage line CVL3 and a third insulating layer IL3. For example, a display device in such an embodiment may have triple layer lines (e.g., triple wiring) that at least partially (or completely) overlap each other in the thickness direction of the substrate SUB and extend in the same direction. In one or more embodiments, the third common voltage line CVL3 may be located on top of (e.g., overlap) the second common voltage line CVL2. In one or more embodiments, the third common voltage line CVL3 may be connected to the second common voltage line CVL2 through an opening (e.g., a contact hole) in the second insulating layer IL2. In one or more embodiments, the third common voltage line CVL3 may be covered by the third insulating layer IL3. The third insulating layer IL3 may provide planarization and / or insulation functions (e.g., for the third common voltage line CVL3). In one or more embodiments, the connecting electrode AE is connected to the third common voltage line CVL3 through an opening (e.g., a contact hole) in the via layer VIA. According to one or more embodiments, the backplane metal line BML partially or completely overlaps and is electrically connected to the first, second, and third common voltage lines CVL1, CVL2, and CVL3. The backplane metal line BML and the first, second, and third common voltage lines CVL1, CVL2, and CVL3 may collectively be referred to as auxiliary lines or auxiliary voltage lines. Also, in the example of FIG. 11C , the gate electrode layer GT is connected to the first common voltage line CVL1 through a through-hole in the interlayer insulating layer ILD.

[0182] 11D is a schematic cross-sectional view of a display device including a common voltage line having three layers according to some embodiments of the present invention. In the embodiment of FIG. 11D, one or more of the common voltage lines CVL1, CVL2, and CVL3 selected from the first, second, and third common voltage lines CVL1, CVL2, and CVL3 may be directly coupled to a voltage source for the ELVSS voltage via one or more pads at one or both ends of the common voltage line. The common voltage lines CVL1, CVL2, and CVL3 may at least partially or completely overlap each other in the thickness direction of the substrate SUB and extend in the same direction. According to one or more embodiments, the first, second, and third common voltage lines CVL1, CVL2, and CVL3, which are electrically connected to each other via one or more insulating layers, may be collectively referred to as auxiliary lines or auxiliary voltage lines.

[0183] Referring to FIG. 11D , in one or more embodiments, the laser drill region LDR includes the same layers and components as FIG. 11B and may include one or more additional layers (e.g., a display device may have triple-layered lines); however, according to embodiments associated with FIG. 11D , the first common voltage line CVL1 may not be connected to (e.g., may be disconnected from) the backplane metal layer BML. For example, in one or more embodiments, the first common voltage layer CVL may receive a common voltage from a path (e.g., a different interface) different from the backplane metal layer BML. For example, one or more of the common voltage lines CVL1, CVL2, and / or CVL3 may be electrically connected to one or more pads at one or both ends and configured to receive a voltage (e.g., an ELVSS voltage) from an external power source. However, the present invention is not limited thereto. The common voltage lines CVL1, CVL2, and CVL3 may be electrically connected to one or more pads so that a driving current can pass through the pad and / or flow to the backplane metal layer. In the example of FIG. 11D, the gate electrode layer GT is connected to the first common voltage line CVL1 via a through-hole in the interlayer insulating layer ILD.

[0184] According to one or more embodiments, a display device (or display panel) includes a substrate SUB and a plurality of auxiliary voltage lines on the substrate SUB, wherein a resistance of one of the auxiliary voltage lines extending from one end of the display panel to an opposite end thereof ranges from about 0.003 Ω to about 0.4 Ω. The display device includes a plurality of connecting electrodes AE for the plurality of auxiliary voltage lines, wherein at least one of the plurality of connecting electrodes AE is electrically connected to a corresponding one of a plurality of auxiliary electrode lines. The display device includes a plurality of pixel electrode sets PES spaced apart from the plurality of connecting electrodes AE, each pixel electrode set including a first pixel electrode PE, a second pixel electrode PE, and a third pixel electrode PE to realize full-color pixels. The display device includes a plurality of connecting electrodes AE and a plurality of pixel electrode sets PES, each pixel electrode set PES including an emitting layer EL, the emitting layer EL including a plurality of emitting layer openings ELOP. The emitting layer EL includes a common electrode CME, and the connecting electrode AE is electrically connected to the plurality of common electrodes CME via a plurality of emitting layer openings ELOP. The resistance of one of the auxiliary voltage lines (common voltage line CVL, backplane metal line, etc.) is in the range of approximately 0.003 Ω to 0.4 Ω.

[0185] According to one or more embodiments, the plurality of auxiliary electrode lines include a plurality of first common voltage lines CVL1 and a plurality of backplane metal lines BML extending in the same direction as the plurality of first common voltage lines CVL1, and one of the plurality of backplane metal lines BML is electrically connected to a corresponding line of the plurality of first common voltage lines CVL1 through an opening in the first insulating layer ILD located between the corresponding line and the plurality of first common voltage lines CVL1.

[0186] According to one or more embodiments, the plurality of auxiliary electrode lines further includes a plurality of second common voltage lines CVL2 located between the plurality of first common voltage lines CVL1 and the plurality of backplane metal lines BML in the thickness direction of the substrate SUB, and one of the plurality of second common voltage lines CVL2 is electrically connected to a corresponding line of the plurality of first common voltage lines CVL1 through an opening in the second insulating layer located between the corresponding line and the second common voltage line CVL2.

[0187] According to one or more embodiments, one of the plurality of auxiliary electrode lines includes a plurality of overlapping common voltage lines CVL1, CVL2, and CVL3 spaced apart from one another in a thickness direction of the substrate, and the display device further includes an insulating layer between two adjacent lines (two adjacent overlapping common voltage lines among the plurality of overlapping common voltage lines) among the plurality of common voltage lines overlapping in the thickness direction, and the two adjacent lines among the plurality of overlapping common voltage lines are electrically connected to one another through openings in the insulating layer. According to one or more embodiments, the plurality of overlapping common voltage lines includes at least three overlapping common voltage lines overlapping and electrically connected to one another in a thickness direction of the substrate SUB. 11B, 11C, and 11D show an embodiment in which the pixel electrode PE is located in the same layer as the connecting electrode AE, and the connecting electrode AE is directly connected to the common voltage line CVL, or the connecting electrode AE is connected to the first common voltage line CVL1 (connected to the first common voltage line CVL1 via the second common voltage line CVL2, or connected to the first common voltage line CVL1 via the second and third common voltage lines CVL2 and CVL3), but the present invention is not limited thereto. In other embodiments, several connecting electrode layers may be formed in a manner similar to the common voltage lines CVL1, CVL2, and CVL3 and may be used to connect (i.e., electrically connect) the pixel electrode PE to a lowest connecting electrode that is connected to the source or drain of a transistor (e.g., a driving transistor) via a number of contact holes.

[0188] FIG. 12A is a schematic plan view of some layers of a display panel in accordance with one or more embodiments of the present invention.

[0189] FIG. 12B is a schematic cross-sectional view of some layers of the display device shown in FIG. 12A taken along line AA', according to one or more embodiments of the present invention.

[0190] 12A and 12B, in one or more embodiments, the first hole H1 and the second hole H2 may be formed in the pixel defining layer PDL and / or the via layer VIA, and a power supply voltage ELVSS from a common voltage line CVL may be provided to the connecting electrode AE. In one or more embodiments, the common voltage line CVL may be formed below the pixel defining layer PDL, below the via layer VIA, and below the connecting electrode AE.

[0191] FIG. 13A is a schematic plan view of the layers of a display panel in accordance with one or more embodiments of the present invention.

[0192] FIG. 13B is a schematic cross-sectional view of some layers of the display device shown in FIG. 13A taken along line BB', according to one or more embodiments of the present invention.

[0193] 13A and 13B, the second hole H2 may extend deeper than the first hole H1 in the thickness direction Th of the display device. For example, in one or more embodiments, the second hole H2 may be formed through the passivation layer PVX (in the example of FIG. 13B, the second hole H2 may be formed through the pixel definition layer PDL, the via layer VIA, and the passivation layer PVX), so that the common voltage line CVL (the line of the ELVSS voltage) below the passivation layer PVX is exposed through the second hole H2.

[0194] As mentioned above, the material and thickness of the layer materials can significantly affect the IR drop of the display panel. In one or more embodiments, the anode layer AN can be formed (e.g., formed into a layer structure) of a combination of ITO / Ag / ITO having thicknesses of 100 Å / 850 Å / 100 Å, respectively, and can have a sheet resistance of approximately 0.4 Ω / □. In one or more embodiments, the anode layer AN can be formed (e.g., formed into a layer structure) of a combination of ITO / Ag / ITO having thicknesses of 150 Å / 1,000 Å / 150 Å, respectively, and can have a sheet resistance of approximately 0.4 Ω / □.

[0195] In one or more embodiments, the common voltage line CVL (e.g., SD layer) is formed (e.g., formed in a layer structure) of a combination of Ti / Cu / Ti having thicknesses of 200 Å / 6000 Å / 550 Å, respectively, and may have a sheet resistance of approximately 0.038 Ω / □. In one or more embodiments, the common voltage line CVL (e.g., SD layer) is formed (e.g., formed in a layer structure) of a combination of Ti / Cu / ITO having thicknesses of 200 Å / 6000 Å / 550 Å, respectively, and may have a sheet resistance of approximately 0.038 Ω / □.

[0196] In one or more embodiments, the backplane metal layer BML may be formed (eg, formed into a layer structure) of a combination of Ti / Cu having thicknesses of 200 Å / 6000 Å, respectively, and may have a sheet resistance of approximately 0.038 Ω / □.

[0197] FIG. 14 is a schematic diagram illustrating components of a display panel DP associated with measuring backplane wiring resistance in accordance with one or more embodiments of the present invention.

[0198] Referring to FIG. 14 , the backplane wiring resistance (e.g., the BP resistance of the BP wiring resistance) of a display panel DP according to one or more embodiments may range from about 0.03 Ω to about 0.40 Ω. For example, the backplane wiring resistance may range from about 0.03 Ω to about 0.40 Ω. As those skilled in the art will recognize, there are numerous alternative systems and methods that can be used to measure the backplane wiring resistance. Furthermore, those skilled in the art should be able to devise systems and / or methods for measuring and / or determining the backplane wiring resistance in a display device (or display panel) without undue experimentation. Thus, embodiments of the present invention are not associated with requiring any particular method or system for measuring the backplane wiring resistance.

[0199] The display panel DP may include a plurality of substrates SUB. Pads PAD may be located on the substrate SUB, and the display panel DP receives a power supply voltage ELVSS. The pads PAD may be located at a first end E1 of the display panel DP. The pads PAD may be connected to one or more common voltage lines CVL at the first end E1. The common voltage line CVL may be connected to one or more connecting electrodes AE. The connecting electrodes AE may be associated with one or more pixel electrode sets PES. According to one or more embodiments of the present invention, the backplane wiring resistance may be measured along a line from a first end E1, where the common voltage line CVL is connected to the pad PAD, to an opposite end of the common voltage line CVL at a second end E2 (e.g., an opposite end of the display panel DP opposite the first end E1). For example, the first end E1 and the second end E2 correspond to opposite ends of the display panel DP.

[0200] In one or more embodiments, an 83-inch display (e.g., an 83-inch 4K display) may have a backplane wiring resistance of approximately 0.1 Ω. In one or more embodiments, a 26.5-inch display (e.g., a 26.5-inch 5K display) may have a backplane wiring resistance of approximately 0.37 Ω. In one or more embodiments, the common voltage line CVL may include a double-layer line and a triple-layer line (e.g., triple wiring). In one or more embodiments, the backplane wiring resistance may be approximately 0.03 Ω when the common voltage line CVL includes three layers.

[0201] According to one or more embodiments, the resistance of one of the common voltage lines CVL is in the range of approximately 0.003 Ω to 0.4 Ω. Those skilled in the art will understand how to measure the resistance of the common voltage lines. For example, the range of approximately 0.003 Ω to approximately 0.4 Ω may be measured from one end of the common voltage line (e.g., coupled to a pad) to the opposite end of the common voltage line (e.g., coupled to another pad). According to one or more embodiments, the common voltage line (e.g., one of CVL, CVL1, CVL2, and / or CVL3 in FIGS. 11A through 11D) includes at least one of Ag, Mg, Ti, Al, Cu, ITO, and / or combinations thereof.

[0202] According to one or more embodiments, a display device (or display panel DP) includes a substrate SUB (e.g., a base substrate SUB), a plurality of auxiliary voltage lines CVL on the substrate SUB, and a plurality of connecting electrodes AE (e.g., a plurality of auxiliary electrodes AE) on the plurality of common voltage lines CVL. At least one of the plurality of connecting electrodes AE is electrically connected to a corresponding one of the plurality of common voltage lines CVL. The display device includes a plurality of pixel electrode sets PES spaced apart from the plurality of connecting electrodes AE. Each pixel electrode set PES includes a first pixel electrode PE, a second pixel electrode PE, and a third pixel electrode PE to implement a full-color pixel. The display device includes a plurality of connecting electrodes AE, a plurality of pixel electrode sets PES, and an emitting layer EL on the plurality of pixel electrode sets PES, the emitting layer EL including a plurality of emitting layer openings ELOP. Each of the plurality of emitting layer openings corresponds to a different one of the plurality of connecting electrodes AE, and the total number of the emitting layer openings ELOP is 25% or less of the total number of pixel electrode sets PES. A common electrode CME is disposed on the light-emitting layer EL, and the plurality of connecting electrodes AE are electrically connected to each other by the common electrode through the plurality of light-emitting layer openings.

[0203] According to one or more embodiments, a display device (or display panel DP) includes a substrate SUB (e.g., a base substrate SUB), a plurality of auxiliary voltage lines CVL on the substrate SUB, and a plurality of connecting electrodes AE (e.g., a plurality of auxiliary electrodes AE) on the plurality of common voltage lines CVL. At least one of the plurality of connecting electrodes AE is electrically connected to a corresponding one of the plurality of common voltage lines CVL. The display device includes a plurality of pixel electrode sets PES spaced apart from the plurality of connecting electrodes AE, each pixel electrode set PES including a first pixel electrode PE, a second pixel electrode PE, and a third pixel electrode PE to implement full-color pixels. The display device includes a plurality of connecting electrodes AE, a plurality of pixel electrode sets PES, and an emitting layer EL on the plurality of pixel electrode sets PES, the emitting layer EL including a plurality of emitting layer openings ELOP. One of the plurality of emitting layer openings has a maximum width ranging from about 1 μm to about 30 μm. The display device includes a common electrode CME on the emitting layer EL, and the plurality of connecting electrodes AE are electrically connected to each other by the common electrode through the plurality of emitting layer openings.

[0204] According to one or more embodiments, a display device (or display panel DP) includes a substrate SUB (e.g., a base substrate SUB), a plurality of auxiliary voltage lines CVL on the substrate SUB, and a plurality of connecting electrodes AE on the plurality of common voltage lines CVL. At least one of the plurality of connecting electrodes AE is electrically connected to a corresponding one of the plurality of common voltage lines CVL. The display device includes a plurality of pixel electrode sets PES spaced apart from the plurality of connecting electrodes AE, each pixel electrode set PES including a first pixel electrode PE, a second pixel electrode PE, and a third pixel electrode PE to implement full-color pixels. The display device includes a plurality of connecting electrodes AE, a plurality of pixel electrode sets PES, and an emitting layer EL on the plurality of pixel electrode sets PES, the emitting layer EL including a plurality of emitting layer openings ELOP. The display device also includes a common electrode CME (e.g., a cathode electrode) on the emitting layer EL, and the plurality of connecting electrodes AE are electrically connected to the common electrode CME via a plurality of emitting layer openings ELOP. The common electrode CME has a thickness of about 60 Å to about 140 Å.

[0205] Relationship between the four parameters and IR-drop FIG. 15 is a graph illustrating an IR-drop scatter plot in accordance with one or more embodiments of the present invention.

[0206] FIG. 16 is a table for determining the relationship between four parameters and IR-drop in a display panel in accordance with one or more embodiments of the present invention.

[0207] The IR-drop associated with a given display panel may be determined (e.g., approximated) and / or modified based on one or more mathematical formulas that indicate the relationship between the four parameters. For example, the one or more mathematical formulas may be derived by fitting simulation results to a polynomial having multiple constants and four parameters. The one or more formulas may be used to determine whether a combination of the multiple constants and four parameters can result in an acceptable IR-drop for a given application. For example, a given combination of parameters may be selected to be implemented based on a determination that the combination results in less IR-drop than a particular voltage at which luminosity irregularities are unlikely to occur (i.e., a lower IR-drop than a particular voltage at which luminosity irregularities can be suppressed).

[0208] Referring to FIG. 15 , an IR-drop scatter plot illustrates a distribution of IR-drop (e.g., voltage drop) values in volts (V) based on IR-drop values generated by one or more simulations and IR-drop values calculated using a formula (e.g., a polynomial, Equation 1, shown below) derived from the generated IR-drop values. In the IR-drop scatter plot of FIG. 15 , the x-axis (i.e., horizontal axis or y) illustrates the IR-drop values generated by the simulations, and the y-axis (i.e., vertical axis or y fit) illustrates the IR-drop values calculated from the formula derived from the generated IR-drop values. The formula illustrates the generated IR-drop values, where the calculated IR-drop values are fitted or substantially fitted to the generated IR-drop values. As can be seen from the IR-drop value scatter plot of FIG. 15 , the R2 =0.9996, which means that the calculated IR-drop values were almost perfectly fitted to the generated IR-drop values.

[0209] FIG. 16 illustrates a table of IR-drop values generated by simulation, in accordance with one or more embodiments of the present invention. The generated IR-drop values were used to derive Equation 1 below. In Equation 1, "1μ" is replaced by "1*10 -6 " is the same as "

[0210] IR-drop[V]=((2.083*x4)-(7.1e -03 *x3)-(4.94e -05 *x2)+(1.758e -05 *x2*x3)+(4.3e -03 *x1*x4)+0.266+(3.544e -04 *x3 2 )-(0.18*x4 2 ))*I / (1μ*horizontal resolution*vertical resolution) (Formula 1) While generating the IR-drop values in one or more simulations, the current per pixel (e.g., a pixel including a red (R), green (G), and blue (B) subpixel) was set to 1 μA. Thus, in Equation 1, 1 μ*horizontal resolution*vertical resolution is used as the denominator to normalize the IR-drop values. For example, the horizontal resolution, which is the number of pixels in each row (i.e., horizontal direction), may be 3840, and the vertical resolution, which is the number of pixels in each column (i.e., vertical direction), may be 2160. Of course, the values shown in the denominator are the amount of current per pixel used and may be different in other embodiments or simulations where the number of pixels in each row and / or the number of pixels in each column may be different. Also, Equation 1 may be calculated using several constants (e.g., 2.083, 7.1e -3 , 4.94e -05 , 1.758e -05 , 4.3e -03 , 0.266, 3.544e -04, 0.18) and four parameters, x1, x2, x3, and x4. However, the present invention is not limited thereto, and other constants and / or other combinations of the parameters, x1, x2, x3, and x4, may be used to derive a polynomial that can calculate (and output) a calculated IR-drop value that is similar, identical, or better fitted to the IR-drop value generated by simulation.

[0211] As can be seen from Equation 1 above, the IR-drop values generated by simulation for the entire display panel were used to generate Equation 1 based on four parameters, x1, x2, x3, and x4. Here, x1 corresponds to the resistance of the LD CNT contact with the laser-drilled hole (i.e., laser-drilled opening) in ohms (Ω), x2 corresponds to the resistance (Cathode Rs) of the common electrode (i.e., cathode electrode) in ohms / □ (Ω / □), x3 corresponds to the spacing (LD spacing) between the laser-drilled holes (i.e., laser-drilled openings) in pixels corresponding to adjacent laser-drilled holes; and x4 corresponds to the backplane resistance (BP Res) in ohms (Ω). Here, the backplane resistance is defined as the resistance (e.g., measured resistance) from a pad connected to one end of a common voltage line on one side of the display panel to the opposite end of the common voltage line on the other side of the display panel (the side opposite the one side).

[0212] In the above equation (1), I is the ELVSS panel current in amperes (A). Because the IR-drop simulation was performed on a panel having horizontal and vertical resolution with the terminal pixel current set to 1 μA, the IR-drop value was calculated by multiplying the measured ELVSS panel current I, as well as the horizontal resolution (e.g., number of horizontal pixels) and vertical resolution (e.g., number of vertical pixels) of the display panel, and dividing by 1 μA. The parameter combinations and constants in equation (1) were derived through experimentation, calculation, and / or simulation. Although the parameter combinations and constants are used in equation (1), the present invention is not limited thereto. In other embodiments of the present invention, different constants may be applied, and different parameter combinations may be applied to control the IR-drop of the common electrode to achieve a top-emitting display panel having at least about 70% long-range uniformity (LRU), while maintaining appropriate emission transmittance of the light-emitting elements while reducing or preventing unevenness. In one or more embodiments, approximately 60% LRUs may be accommodated, while in other embodiments, greater than approximately 70% (eg, 80% or more) LRUs may be intended or desired.

[0213] 16, a table of IR-drop values (generated by one or more simulations, i.e., experimental design) can be divided into two regions: Region 1 and Region 2. As can be seen from Fig. 16, Region 1 is where the generated IR-drop values can be accommodated (may be of desired (or appropriate) quality), and Region 2 is where the generated IR-drop values cannot be accommodated (may not be of desired (or appropriate) quality).

[0214] Simulations can be performed with different coupling values for x1, x2, x3, and x4. For example, as can be seen from the table in FIG. 16, values of 5, 100, 200, 500, and 1000 Ω were used for parameter x1 as LD CNT Res. (i.e., the contact resistance of the laser drilled opening). Values of 5, 30, and 50 Ω / □ were used for parameter x2 as Cathode Rs. (i.e., the sheet resistance of the common electrode (i.e., the cathode electrode)). Values of 1, 3, 6, 12, and 18 were used for parameter x3 as LD spacing (i.e., the number of pixels corresponding to the spacing between two adjacent laser drilled openings). Values of 0.1, 0.2, 0.3, and 0.4 Ω were used for parameter x4, BP Res (i.e., the backplane resistance or the resistance of the common electrode line from one end connected to a pad at one end of the display panel to the opposite end of the common voltage line located at the opposite end of the display panel).

[0215] As can be seen from the table of FIG. 16, when the BP Res., which is the parameter x4, is 0.3Ω or 0.04Ω, the IR-drop value falls in Region 2. Region 2 is a region where the IR-drop cannot be accommodated and a display panel of desired (or adequate) quality (i.e., having at least 70% LRU) cannot be implemented. On the other hand, if the BP Res., which is the parameter x4, is 0.1Ω, all generated IR-drop values fall within Region 1 regardless of the values of other parameters, and if the BP Res., which is the parameter x4, is 0.2Ω, most generated IR-drop values fall within Region 1. Therefore, if more than one simulation is used to generate the IR-drop value, the BP Res., which is the parameter x4, will appear as most of the major parameters. However, the present invention is not limited thereto, and other parameters may have more weight (i.e., may be more important) in generating the IR-drop value depending on the combination of constants and parameters used.

[0216] For example, if x1 is 5Ω, x2 is 5Ω / □, and x4 is 0.1Ω, the generated IR-drop value varies based on the value applied to parameter x3. Here, if the LD spacing values of parameter x3 are 3, 6, and 12, respectively, the generated IR-drop values are 0.4568V, 0.4570V, and 0.4579V. As another example, if x1 is 5Ω, x3 is 12, and x4 is 0.1Ω, the generated IR-drop value varies based on the value applied to parameter x2. Here, if the values of parameter x2 are 5, 30, and 50Ω / □, respectively, the generated IR-drop values are 0.4579V, 0.4633V, and 0.4646V.

[0217] According to one or more embodiments of the present invention, a method for manufacturing a display is provided, where the values of parameters x1 (LD CNT Res.), x2 (Cathode Rs.), x3 (LD Spacing), and x4 (BP Res.) in Equation 1 are adjusted to realize an acceptable (i.e., desired or appropriate) IR-drop value (that falls within Region 1) and achieve an LRU of at least 70% (or any other desired or appropriate LRU%). As shown in the table of FIG. 16, the IR-drop value ranges from approximately 0.4567 V (when x1 is 5 Ω, x2 is 5 Ω / □, x3 is 1, and x4 is 0.1 Ω) to approximately 0.7920 V (when x1 is 1,000 Ω, x2 is 5 Ω / □, x3 is 12, and x4 is 0.2 Ω), which is within the range of approximately 0.45 V to approximately 0.8 V. According to one or more embodiments, the display panel is fabricated using a method that produces a calculated range of IR-drop values between about 0.4567V and 0.7920V (or between about 0.45V and 0.80V). According to one or more embodiments, the IR-drop values may be between about 0.50V and about 0.75V, between about 0.60V and about 0.70V, or between about 0.40V and about 0.8V (or between about 0.45V and about 0.80V). Those skilled in the art can measure the IR-drop associated with (or across) the display panel using any suitable method known to those skilled in the art, or devise a suitable method for measuring the IR-drop without undue experimentation.

[0218] The display device includes a substrate SUB (e.g., a base substrate BS), a plurality of common voltage lines CVL on the substrate, and a plurality of connecting electrodes AE on the common voltage lines CVL. At least one of the connecting electrodes AE is electrically connected to a corresponding one of the common voltage lines. The display device includes a plurality of pixel electrode sets PES spaced apart from the connecting electrodes AE. Each pixel electrode set PES includes a first pixel electrode PE, a second pixel electrode PE, and a third pixel electrode PE to implement a full-color pixel. The display device includes a plurality of connecting electrodes AE and an emitting layer EL on the plurality of pixel electrode sets PES. The emitting layer EL includes a plurality of emitting layer openings ELOP. The display device includes a common electrode CME on the emitting layer EL. The connecting electrodes AE are electrically connected to the common electrode CME via a plurality of emitting layer openings ELOP. The IR-drop of the display device is approximately 0.80 or less.

[0219] According to one or more embodiments, the IR-drop of the display device may be in the range of about 0.45V to about 0.8V; may be in the range of about 0.50V to about 0.75V; may be in the range of about 0.55V to about 0.70V; may be in the range of about 0.45V to about 0.55V; may be in the range of about 0.50V to about 0.60V; or may be in the range of about 0.4567V to about 0.7920V.

[0220] According to one or more embodiments, the IR-drop is the result of the mathematical formula: IR-drop=((2.083*x4)-(7.1e -03 *x3)-(4.94e -05 *x2)+(1.758e -05 *x2*x3)+(4.3e -03 *x1*x4)+0.266+(3.544e -04 *x3 2 )-(0.18*x4 2))*I / (1μ*horizontal resolution*vertical resolution), where: I is the panel current; x1 is the resistance through one of the plurality of light-emitting layer openings ELOP; x2 is the sheet resistance of the common electrode CME; x3 is the spacing between the closest openings of the plurality of light-emitting layer openings ELOP; and x4 is the resistance of one of the common voltage lines CVL.

[0221] FIG. 17 is a diagram illustrating exemplary operations of a method for manufacturing a display panel in accordance with one or more embodiments of the present invention.

[0222] According to one or more embodiments of the present invention, method 17000 may include one or more of the following steps: An emissive layer EL may be formed on top of connecting electrodes AE of a display device (or display panel DP). The emissive layer may include one or more layers and may be deposited using, for example, vapor deposition. The display panel (or display panel DP) may include a plurality of pixel electrode sets PES (S17001). A plurality of emissive layer openings ELOP may be formed in the emissive layer EL using a laser (S17002). In one or more embodiments, the plurality of emissive layer openings ELOP may be separated by a spacing (e.g., one emissive layer opening ELOP per four or more pixel electrode sets). However, the present invention is not limited thereto. In one or more embodiments, for example, there may be one emissive layer opening ELOP per pixel (e.g., per pixel electrode set). A common electrode CME may be formed on top of the emissive layer EL (S17003). The common electrode CME may contact (e.g., be electrically connected to) the connecting electrodes AE (S17003).

[0223] In other embodiments, the spacing between the emissive layer openings may vary as shown and described herein, and / or one or more checkerboard patterns may be applied to the formation of the emissive layer openings as shown and described herein.

[0224] As described above with reference to Figures 15 and 16, a display device (or display panel) having an accommodating IR-drop may be implemented in accordance with one or more embodiments of the present invention. As those skilled in the art will recognize, there are numerous alternative systems and methods that may be used to measure IR-drop. Furthermore, those skilled in the art should be able to devise systems and / or methods for measuring and / or determining IR-drop in a display device (or display panel) without undue experimentation. Thus, embodiments of the present invention are not associated with requiring any particular method or system for measuring IR-drop.

[0225] For example, IR-drop can be measured by measuring the saturated ELVDD and confirming the Max Load voltage and the Min Load voltage. For example, the Min Load voltage can be the saturated operating voltage (e.g., saturated ELVDD) under the Max Load condition, and the Min Load voltage can be the saturated operating voltage (e.g., saturated ELVDD) under the Min Load condition, but is not limited thereto. For example, IR-drop can be defined by the following Equation 2. The load (voltage) can be expressed as the differential voltage between the pixel electrode and the common electrode.

[0226] IR-drop = Max Load voltage - Min Load voltage (Equation 2) The steps / procedures summarized below are one example and may be modified or improved, and settings and / or parameters such as the interval between measurements of the operating voltage (e.g., ELVDD) may be different or updated in other examples. Therefore, the following steps / procedures are merely one example and the present invention is not limited thereto.

[0227] For example, a saturated operating voltage (e.g., saturated ELVDD) can be measured by sweeping the operating voltage (e.g., ELVDD) and determining an operating voltage value (e.g., ELVDD) with a color coordinate (e.g., CIEx) of 0.002 or a 1% change in luminance. Under measurement conditions, the color coordinate and / or luminance can be measured with a measurement pattern at the center of the display panel. The size of the measurement pattern can be 80x80 (80 pixels x 80 pixels), and measurements can be performed while changing the gray level of the measurement pattern in four gray level intervals from 0 to 255.

[0228] 18A-18B are diagrams illustrating a display panel configured to measure luminance and / or color coordinates to determine IR-drop, according to one or more embodiments of the present invention.

[0229] 18A-18B, to measure luminance under the Max Load condition, a load box 1800 may be positioned in the center region of the display panel DP, and a central pattern (e.g., only the central pattern) may be varied in four gray level intervals to measure luminance. For example, the load box 1800 may have a 10% load and a fixed pattern of 255 gray levels. Under this Max Load condition, a saturation operating voltage (e.g., saturation ELVDD) may be identified, and by sweeping the saturation operating voltage, a color coordinate (e.g., CIEx) of 0.002 or an operating voltage value (e.g., ELVDD) with a luminance change of 1% may be determined and measured (or determined).

[0230] 18A-18B, to measure luminance under the Min Load condition, a load box 1802 may be positioned in the center region of the display panel DP, and the central pattern (e.g., only the central pattern) may be varied in four gray level intervals to measure luminance. For example, the load box 1802 may have a 0.25% load and be fixed to black (e.g., 0 gray level). Under this Min Load condition, a saturation operating voltage (e.g., saturation ELVDD) may be identified, and by sweeping the saturation operating voltage, a color coordinate (e.g., CIEx) of 0.002 or an operating voltage value (e.g., ELVDD) with a luminance change of 1% may be determined and measured (or determined).

[0231] As an example, the saturated operating voltage (eg, saturated ELVDD) can be determined from a delta() brightness / delta() gray graph.

[0232] 19A-19D are graphs of luminance and color coordinates versus ELVDD in accordance with one or more embodiments of the present invention. As can be seen from FIGS. 19A and 19B, at 2,000 nits (nits, cd / m 2 ) brightness (eg, target brightness) may correspond to a saturated operating voltage (eg, saturated ELVDD) in the range of approximately 23V to 24V.

[0233] 19C-19D are graphs of color coordinate values (e.g., CIEx) versus ELVDD, according to one or more embodiments of the present invention. As can be seen from Figures 19C and 19D, the color coordinate values are just below 0.3 when the operating voltage (e.g., ELVDD) is in the range of approximately 23V to 24V.

[0234] As discussed above, a display panel with an LRU of less than 70% may exhibit irregularities (e.g., unevenness) such as spots (e.g., discoloration). As one skilled in the art will recognize, there are numerous alternative systems and methods that can be used to measure the LRU. Furthermore, one skilled in the art should be able to devise a system and / or method for measuring and / or determining the LRU in a display device (or display panel) without undue experimentation. Thus, embodiments of the present invention are not associated with requiring any particular method or system for measuring the LRU.

[0235] FIG. 20 illustrates a table of results obtained by measuring the luminance of nine points on a display panel to determine the LRU, according to one or more embodiments of the present invention. For example, in the table of FIG. 20, the display panel used for the measurement may have a 3x3 laser drill hole (i.e., LD hole) spacing, although the present invention is not limited thereto. The values observed from the table are 90.00%, 91.80%, 90.30%, 97.10%, 93.80%, 96.10%, 95.30%, 100.00%, and 95.00%. The luminance LRU is calculated using Equation 3 below. For example, if the luminance of nine points on a display panel is measured as shown in the table of FIG. 20, the largest of the nine measured luminances is MAX, and the smallest of the nine measured luminances is MIN.

[0236] LRU=MIN / MAX*100 (Formula 3) 21 is a schematic diagram of a display panel showing nine points at which the luminance of FIG. 20 is measured, in accordance with one or more embodiments of the present invention. The display panel DP is shown in FIG. 21 as having nine measurement points. However, exemplary LRU measurement methods are not limited to this. Other examples include, but are not limited to, 4x4 (=16), 5x5 (=25), 6x6 (=36), or 7x7 (=49) measurement points that may be used to measure the LRU.

[0237] 22 is a contour plot for luminance measurements in accordance with one or more embodiments of the present invention. The contour plot of FIG. 22 shows a relatively low luminance region 2200 and a relatively high luminance region 2202.

[0238] While the embodiments of the present invention have been described as being presently considered to be working examples, the invention is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalents included within the spirit and scope of the appended claims. [Explanation of symbols]

[0239] 10: First insulating layer 20: Second insulating layer 30: Third insulating layer 40: Fourth insulating layer AE: Connecting electrode AN: Anode layer BL: Buffer layer BML: Backplane metal layer, backplane metal line BS: Base substrate CH: Contact hole (CH1: 1st contact hole, CH2: 2nd contact hole) CME: Common electrode CP: Chess pattern (CP1~CP3: 1st~3rd chess pattern) CVL: Common voltage line (CVL1 to CVL3: 1st to 3rd common voltage lines) DP: Display Panel DP-CL:Circuit layer EIL: Electron injection layer EL: Light-emitting layer ELOP: Light-emitting layer opening GI: Gate insulating layer GT: gate electrode layer ILD: Interlayer insulating layer LD: Laser drilled hole LDR: Laser drilling area PDL: Pixel Defined Layer PE: pixel electrode PES: Pixel electrode set POP: Pixel Aperture PVX: Passivation layer PX: Pixels

Claims

1. A substrate; a plurality of common voltage lines on the substrate; a plurality of connection electrodes disposed on the plurality of common voltage lines, at least one of which is electrically connected to a corresponding one of the plurality of common voltage lines; a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each set including a first pixel electrode, a second pixel electrode, and a third pixel electrode, for realizing full-color pixels; a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel electrode sets, the light-emitting layer having a plurality of openings, each of the plurality of openings corresponding to the plurality of connecting electrodes, and the total number of the openings being 25% or less of the total number of the pixel electrode sets; a common electrode disposed on the light-emitting layer and electrically connected to the connecting electrode through the plurality of openings.

2. The display device of claim 1 , wherein the plurality of openings comprise laser-drilled holes.

3. 2. The display device of claim 1, wherein the total number of apertures is in the range of 700 to 3,700,000.

4. 2. The display device of claim 1, wherein the total number of apertures is in the range of 57,000 to 920,000.

5. 10. The display device of claim 1, wherein the distance between the closest ones of the apertures is in the range of about 1.1 mm to about 20 mm.

6. the plurality of pixel electrode sets include a plurality of pixel electrode set groups, each of the plurality of pixel electrode set groups including a plurality of pixel electrode set sub-groups; The display device of claim 1 , wherein only one of a plurality of subgroups in one of the plurality of groups has a corresponding one of the apertures.

7. 7. The display device of claim 6, wherein the subgroups within the plurality of pixel electrode set groups having corresponding openings among the openings define hole formation regions, and the width of one of the hole formation regions is the same as the distance between two of the hole formation regions that are closest to each other.

8. The display device of claim 6, wherein the number of the plurality of subgroups in one of the pixel electrode set groups is in the range of 4 to 64.

9. 7. The display device of claim 6, wherein a ratio between the total number of pixel electrode sets and the total number of apertures in one of the plurality of subgroups is in the range of 1 to 64.

10. 7. The display device of claim 6, wherein the plurality of pixel electrode sets are arranged in a matrix.

11. 11. The display device of claim 10, wherein the plurality of subgroups of the pixel electrode sets of each of the plurality of groups are arranged in a matrix.

12. the display device includes a 65-inch display panel; 2. The display device of claim 1, wherein the total number of apertures is in the range of 57,000 to 920,000.

13. 2. The display device of claim 1, wherein a ratio between the total number of pixel electrode sets and the total number of apertures is in the range of 4 to 5,184.

14. 2. The display device of claim 1, wherein a ratio between the total number of the apertures and the total number of the pixel electrode sets is in the range of 1 / 144 to 1 / 9.

15. 10. The display device of claim 1, wherein the maximum width of one of the openings is in the range of about 1 [mu]m to about 30 [mu]m.

16. 16. The display device of claim 15, wherein one of the openings has a maximum width of at least about 3 [mu]m.

17. 17. The display device of claim 16, wherein the maximum width of one of the openings is in the range of about 4 [mu]m to about 7 [mu]m.

18. 18. The display device of claim 17, wherein the maximum width of one of the openings is in the range of about 4 [mu]m to about 5 [mu]m.

19. 17. The display device of claim 16, wherein the maximum width of one of the openings is in the range of about 3 [mu]m to about 20 [mu]m.

20. 10. The display device of claim 1, wherein the contact resistance of one of the openings ranges from about 1 ohm to about 1,000 ohms.

21. 10. The display device of claim 1, wherein the thickness of the common electrode ranges from about 40 Å to about 200 Å.

22. 22. The display device of claim 21, wherein the thickness of the common electrode ranges from about 50 Å to about 140 Å.

23. 23. The display device of claim 22, wherein the common electrode comprises Yb Ag:Mg.

24. 24. The display device of claim 23, wherein the common electrode has a sheet resistance of about 9.7 ohms / square to about 50 ohms / square.

25. 25. The display device of claim 24, wherein the common electrode has a thickness in the range of about 40 Å to about 140 Å.

26. 10. The display device of claim 1, wherein the common electrode has a sheet resistance of less than about 32 ohms / square.

27. 10. The display device of claim 1, wherein the resistance of one of the common voltage lines from one end to the opposite end ranges from about 0.03 ohms to about 0.4 ohms.

28. The display device of claim 1 , wherein one of the common voltage lines comprises a plurality of metal layers.

29. A substrate; a plurality of common voltage lines on the substrate; a plurality of connection electrodes disposed on the plurality of common voltage lines, at least one of which is electrically connected to a corresponding one of the plurality of common voltage lines; a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each of which includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and which implement full-color pixels; a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel electrode sets, the light-emitting layer having a plurality of openings; a common electrode disposed on the light emitting layer and electrically connected to the connecting electrode through the plurality of openings; A display device having an IR-drop of about 0.80V or less.

30. 30. The display device of claim 29, wherein the IR-drop of the display device is in the range of about 0.40V to about 0.80V.

31. 30. The display device of claim 29, wherein the IR-drop of the display device is in the range of about 0.4567V to about 0.7920V.

32. 30. The display device of claim 29, wherein the IR-drop of the display device is in the range of about 0.50V to about 0.75V.

33. 30. The display device of claim 29, wherein the IR-drop of the display device is in the range of about 0.6V to about 0.7V.

34. The IR-drop is a result of the formula: IR-lower = ((2.083*x4)-(7.1e －０３ *x3)-(4.94e －０５ *x2)+(1.758e －０５ *x2*x3)+(4.3e －０３ *x1*x4)+0.266+(3.544e －０４ *x3 ２ )-(0.18*x4 ２ ))*I / (1μ*Horizontal resolution*Vertical resolution)であり、 where: I is the panel current, x1 is a resistance through one of the plurality of openings; x2 is the sheet resistance of the common electrode, x3 is the spacing between the closest openings of the plurality of openings, 30. The display device of claim 29, wherein x4 is a resistor in one of the plurality of apertures.

35. A substrate; a plurality of common voltage lines on the substrate; a plurality of connection electrodes disposed on the plurality of common voltage lines, at least one of which is electrically connected to a corresponding one of the plurality of common voltage lines; a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each of which includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and which implement full-color pixels; a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel voltage sets, the light-emitting layer having a plurality of openings, one of the openings having a maximum width ranging from about 1 μm to about 30 μm; a common electrode disposed on the light-emitting layer and electrically connected to the connecting electrode through the plurality of openings.

36. 36. The display device of claim 35, wherein the plurality of openings comprise laser-drilled holes.

37. 36. The display device of claim 35, wherein one of the openings has a maximum width of about 3 μm.

38. 38. The display device of claim 37, wherein the maximum width of one of the openings is in the range of about 4 [mu]m to about 7 [mu]m.

39. 39. The display device of claim 38, wherein the maximum width of one of the openings is in the range of about 4 [mu]m to about 5 [mu]m.

40. 38. The display device of claim 37, wherein the maximum width of one of the openings is in the range of about 3 [mu]m to about 20 [mu]m.

41. A substrate; a plurality of common voltage lines on the substrate; a plurality of connection electrodes disposed on the plurality of common voltage lines, at least one of which is electrically connected to a corresponding one of the plurality of common voltage lines; a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each of which includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and which implement full-color pixels; a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel voltage sets, the light-emitting layer having a plurality of openings; a common electrode disposed on the light-emitting layer, electrically connected to the connecting electrode through the plurality of openings, and having a thickness ranging from about 60 Å to about 140 Å.

42. 42. The display device of claim 41, wherein the thickness of the common electrode is in the range of about 70 Å to about 140 Å.

43. 42. The display device of claim 41, wherein the common electrode has a sheet resistance of about 9.7 ohms / square to about 50 ohms / square.

44. 42. The display device of claim 41, wherein the common electrode has a sheet resistance of less than about 32 ohms / square.

45. In a display device, A substrate; a plurality of auxiliary voltage lines disposed on the substrate and extending from one end of the display device to the opposite end; a plurality of connection electrodes disposed on the plurality of auxiliary voltage lines, at least one of which is electrically connected to a corresponding one of the plurality of auxiliary voltage lines; a plurality of pixel electrode sets spaced apart from the plurality of connecting electrodes, each of which includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and which implement full-color pixels; a light-emitting layer disposed on the plurality of connecting electrodes and the plurality of pixel voltage sets, the light-emitting layer having a plurality of openings; a common electrode disposed on the light emitting layer and electrically connected to the connecting electrode through the plurality of openings; A display device, wherein the resistance of one of the auxiliary voltage lines is in the range of about 0.003 Ω to about 0.4 Ω.

46. 46. The display device of claim 45, wherein the resistance of one of the auxiliary voltage lines is in the range of about 0.03 ohms to about 0.4 ohms.

47. 46. The display device of claim 45, wherein the plurality of auxiliary electrode lines include a plurality of first common voltage lines and a plurality of backplane metal lines extending in the same direction as the plurality of first common voltage lines, and one of the plurality of backplane metal lines is electrically connected to a corresponding one of the plurality of first common voltage lines through an opening in a first insulating layer located between the corresponding line and the first common voltage line.

48. 48. The display device of claim 47, wherein the plurality of auxiliary electrode lines further include a plurality of second common voltage lines positioned between the plurality of first common voltage lines and the plurality of backplane metal lines in a thickness direction of the substrate, and one of the plurality of second common voltage lines is electrically connected to a corresponding one of the plurality of first common voltage lines through an opening in a second insulating layer positioned between the corresponding line and the second common voltage line.

49. 46. The display device of claim 45, wherein one of the plurality of auxiliary electrode lines includes a plurality of overlapping common voltage lines spaced apart from each other in a thickness direction of the substrate, the display device further includes an insulating layer between two adjacent lines of the plurality of overlapping common voltage lines in the thickness direction, and the two adjacent lines of the plurality of overlapping common voltage lines are electrically connected to each other through an opening in the insulating layer.

50. 50. The display device of claim 49, wherein the plurality of overlapping common voltage lines includes at least three overlapping common voltage lines overlapping and electrically connected to each other in a thickness direction of the substrate.

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