Configuration of variable gain amplifier, front-end module, and radio device

Abstract

To provide a variable gain amplifier for achieving a targeted or improved linearity.SOLUTION: A variable gain signal amplifier 310a includes: a variable gain stage for receiving an input signal and generating an amplified output signal; and a degeneration switching block coupled to the variable gain stage, for providing a plurality of gain levels of the variable gain stage. The variable gain signal amplifier 310a selectively provides a bypass path for bypassing the variable gain stage and an amplification path for passing through the variable gain stage.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present disclosure relates to amplifiers for wireless communication applications.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application is filed on August 31, 2016, entitled "Degeneration Switching Block U.S. Provisional Application No. 62 / 3 entitled "Multiple Input Amplifier with Low-Loss Bypass Capability and Circuit Breaker" Priority is claimed to US Pat. No. 81,851, the entire contents of which are expressly incorporated by reference for all purposes. can be incorporated into the [Background technology]

[0003] Wireless communication devices are typically configured to amplify received radio frequency (RF) signals. The front-end module contains the components. It may include multiple gain modes that provide different levels of amplification. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2010 / 0321113(A1) [Patent Document 2] US Patent Application Publication No. 2014 / 0203872(A1) Summary of the Invention

[0005] According to a number of implementations, the present disclosure provides a method for receiving an input signal and generating an amplified output signal. a variable gain stage configured to adjust a plurality of gains of the variable gain stage; and a degeneration switching block configured to provide a variable gain level. Regarding the gain signal amplifier.

[0006] In some embodiments, the signal comprises a radio frequency signal. The amplifier has a bypass path that bypasses the variable gain stage and an amplification path that passes through the variable gain stage. The optical fiber is configured to selectively provide a path.

[0007] In some embodiments, the degeneration switching block further comprises: The variable gain stage is configured to provide a variable impedance. In the above, the customized impedance is Compared to a variable gain stage that is not coupled to a degeneration switching block, In a further embodiment, the amplifier is configured to provide improved linearity in the output signal. The degeneration switching block selects a first gain level of the plurality of gain levels. providing a first tailored impedance to the filter and a second gain of multiple gain levels; The second impedance is configured to provide a second tailored impedance to the level. In a further embodiment, the first tailored impedance is The impedance is greater than the impedance obtained, and the first gain level is less than the second gain level.

[0008] In some embodiments, the amplifier also includes a variable gain stage and a degeneration switch. Also included is a control circuit configured to generate an amplified control signal that controls the switching circuit. In one embodiment, the control circuit generates a plurality of amplification control signals corresponding to a plurality of gain levels. It is configured to give.

[0009] In some embodiments, the amplifier further comprises an intermediate gain stage coupled to the input of the variable gain stage. Gain mode feedback block. Intermediate gain mode is a part of multiple gain levels. The variable gain stage is configured to provide feedback for aggregation. In the intermediate gain mode feedback block and degeneration switching The blocks are an intermediate gain feedback block and a degeneration switching block. This provides improved linearity to the amplified output signal compared to amplifiers without a clock.

[0010] In some embodiments, the amplifier further comprises a bias coupled to the input of the variable gain stage. A pass block is included. The bypass block provides a bypass path that does not include a variable gain stage. The gain level is configured to be activated at a low gain level of the plurality of gain levels. In a further embodiment, the bypass path is a degeneration switching block Does not include.

[0011] In some embodiments, the amplifier further comprises a cascade coupled to the output of the variable gain stage. In some embodiments, the amplifier further comprises a variable gain stage. In a further embodiment, the amplifier includes a plurality of input nodes. The input signal is configured to receive a plurality of input signals at a plurality of input terminals, each of the received signals being a different In yet a further embodiment, the amplifiers have frequencies within the signal frequency band. the signal received at the input port is amplified independently of the amplification of other received signals. It is configured as follows.

[0012] According to a number of implementations, the present disclosure provides a method for controlling a power supply having various gain levels. coupled to a signal amplifier configured to provide the various associated impedance values. a variable impedance stage operatively associated with said variable impedance stage; a switch implemented to selectively isolate the variable impedance stage from the reference potential node; The present invention relates to a degeneration switching circuit including:

[0013] In some embodiments, the signal amplifier is configured to amplify the radio frequency signal. In some embodiments, the bypass path provided in the circuit is a variable impedance Bypass the amplifier stage.

[0014] In some embodiments, different impedance values are associated with the different gain levels. connected to a degeneration switching circuit with various impedance values configured to provide improved linearity of the signal amplifier compared to an uncoupled signal amplifier. In a further embodiment, the variable impedance stage has a first gain of various gain levels. A first custom impedance value is given for each level, and a second custom impedance value is given for various gain levels. configured to provide a second customized impedance value for a gain level of .

[0015] In some embodiments, the circuitry further controls the variable impedance stage and the switch. In a further embodiment, the amplifier further comprises a control circuit configured to generate an amplification control signal that controls the amplifier. The control circuit is configured to provide a plurality of amplification control signals corresponding to different gain levels. will be done.

[0016] According to a number of implementations, the present disclosure provides a front-end architecture that includes a variable gain signal amplifier. A variable gain signal amplifier receives an input signal and generates an amplified output signal. a variable gain stage configured to: and a degeneration switching block configured to provide a gain level. The front-end architecture also includes a variable gain signal amplifier coupled to the variable gain signal amplifier. Also included is a filter assembly for directing a frequency band to a selected input of the signal amplifier. The architecture also includes a variable gain signal amplifier to control the variable gain signal amplifier to provide multiple gain modes. In the low gain mode, the variable gain signal amplifier includes a variable gain stage. Direct the signal along the bypass route.

[0017] In some embodiments, the degeneration switching block further comprises: The variable gain stage is configured to provide a variable impedance. In the above, the customized impedance is Compared to a variable gain stage that is not coupled to a degeneration switching block, In a further embodiment, the amplifier is configured to provide improved linearity in the output signal. The degeneration switching block selects a first gain level of the plurality of gain levels. providing a first tailored impedance to the filter and a second gain of multiple gain levels; The level is configured to provide a second tailored impedance.

[0018] According to a number of implementations, the present disclosure provides a diversity antenna and a method for receiving and selecting signals. a filter coupled to the diversity antenna to direct a frequency band along the path; The wireless device also includes a filter assembly for receiving an input signal. a variable gain stage configured to generate an amplified output signal; a degeneration switch configured to provide a plurality of gain levels for the variable gain stage; The wireless device also includes a variable gain signal amplifier including a switching block. A controller is also included which is implemented to control the variable gain signal amplifier to provide the mode. In gain mode, the variable gain signal amplifier directs the signal along a path that bypasses the variable gain stage. Point towards.

[0019] In some embodiments, the degeneration switching block further comprises: The amplifier is configured to direct the impedance to a variable gain stage. In the above, the customized impedance is Compared to a variable gain stage that is not coupled to a degeneration switching block, In a further embodiment, the amplifier is configured to provide improved linearity in the output signal. The degeneration switching block selects a first gain level of the plurality of gain levels. providing a first tailored impedance to the filter and a second gain of multiple gain levels; The level is configured to provide a second tailored impedance.

[0020] For purposes of summarizing the disclosure, certain aspects, advantages and novel features have been described herein. Not necessarily all such advantages will be achieved in any particular embodiment. Thus, embodiments of the present disclosure may be implemented to achieve one or more of the advantages or groups of advantages taught herein. achieve or optimize the above without necessarily achieving any of the other advantages taught or suggested herein. It can be implemented in such a manner. [Brief explanation of the drawings]

[0021] [Figure 1] 1 illustrates a wireless device having a primary antenna and a diversity antenna. [Figure 2] 1 illustrates a diversity receiver (DRx) configuration including a DRx front-end module (FEM). [Figure 3A] 1 illustrates an example variable gain amplifier configuration that includes a multi-input gain stage configured to receive multiple inputs and selectively amplify the received signals through the gain stages or provide a bypass path through a bypass block. [Figure 3B] 3B illustrates another example variable gain amplifier that includes the same components as the variable gain amplifier of FIG. 3A with the addition of certain elements. [Figure 3C] 3B illustrates another example variable gain amplifier similar to that of FIG. 3A, but omitting the bypass switch. [Figure 3D] 3C illustrates another example variable gain amplifier that includes the same components as the variable gain amplifier of FIG. 3C, with the addition of certain elements. [Figure 4] 1 illustrates a variable gain signal amplifier that includes a variable gain stage configured to receive an input signal and generate an amplified output signal. [Figure 5] 1 illustrates a degeneration switching circuit that includes a variable impedance stage coupled to a signal amplifier having various gain levels. [Figure 6] 3B illustrates an example of a variable gain amplifier configuration similar to that of the variable gain amplifier of FIG. 3B. [Figure 7A] 7 illustrates an example of an operating mode of the variable gain signal amplifier configuration of FIG. 6. [Figure 7B] 7 illustrates an example of an operating mode of the variable gain signal amplifier configuration of FIG. 6. [Figure 7C] 7 illustrates an example of an operating mode of the variable gain signal amplifier configuration of FIG. 6. [Figure 8] 7 illustrates a variable gain signal amplifier similar to the variable gain signal amplifier configuration of FIG. 6, but excluding the bypass switch. [Figure 9] 7 illustrates a variable gain signal amplifier similar to the variable gain signal amplifier configuration of FIG. 6, but with a shutdown switch block instead of a mid-gain mode feedback module. [Figure 10] 10 illustrates a variable gain signal amplifier 1010 similar to the variable gain signal amplifier configuration of FIG. 9, but omitting the bypass switch. [Figure 11] It is noted that in some embodiments, some or all of the diversity receiver configurations may be implemented in whole or in part within a module. [Figure 12] It will be noted that in some embodiments, some or all of the diversity receiver configurations may be implemented in whole or in part within the architecture. [Figure 13] 1 illustrates an example wireless device having one or more advantageous features described herein. DETAILED DESCRIPTION OF THE INVENTION

[0022] The headings provided herein, if any, are for convenience only and do not affect the scope of the claims. It does not necessarily affect the scope or meaning of such inventions.

[0023] overview

[0024] FIG. 1 illustrates a wireless device having a primary antenna 160 and a diversity antenna 170. 1 illustrates an example wireless device 100. The wireless device 100 includes an RF module that can be controlled by a controller 102. The transceiver 104 receives an analog signal (e.g., a radio frequency It is configured to convert between a radio frequency (RF) signal and a digital data signal. For this purpose, the transceiver 104 may include a digital-to-analog converter, an analog-to-digital converter, a local oscillator for modulating or demodulating a baseband analog signal to or from a carrier frequency; oscillator, between digital samples and data bits (e.g., voice or other types of data) It may include a baseband processor or other components that perform the conversion.

[0025] The RF module 106 is coupled between the primary antenna 160 and the transceiver 104 . The RF module 106 provides a physical connection to the primary antenna 160 to reduce attenuation due to cable losses. The RF module 106 is a front-end module (FEM) because it can be logically close to The RF module 106 provides the primary antenna for the transceiver 104. 160 or from the transceiver 104 for transmission via the primary antenna 160 The received analog signal can be processed. For this purpose, the RF module 1 06 includes filters, power amplifiers, low noise amplifiers, band select switches, attenuators, matching circuits, and other components.

[0026] When a signal is transmitted to the wireless device 100, the signal is transmitted through the primary antenna 160 and the diverse antennas. The signal can be received by both the primary antenna 160 and the diversity antenna 170. The city antenna 170 is physically separated so that the primary antenna 160 and the diver The signals at the city antenna 170 are received with different characteristics. In an embodiment, the primary antenna 160 and the diversity antenna 170 have different attenuation The transceiver 1 can receive signals with attenuation, noise, frequency response and / or phase shift. 04 uses both signals of different characteristics to determine the data bits corresponding to the signals. In some implementations, the transceiver 104 may include a primary antenna 160 and a die. The antenna can be selected from among the various antennas 170 based on the characteristics. An antenna with a high signal-to-noise ratio can be selected. The receiver 104 combines the signals from the primary antenna 160 and the diversity antenna 170. In some implementations, the transmitter and receiver The receiver 104 processes the signals to provide multiple input / multiple output (MiMo) communication.

[0027] In some embodiments, diversity antenna 170 may be configured to receive multiple cellular frequencies. Signals in several bands and / or Wireless Local Area Network (WLAN) frequency bands In such an embodiment, the wireless device 100 is configured to receive a diversity antenna 170 configured to split the city signal into different frequency ranges; a multiplexer, switching network and / or filter assembly coupled to For example, the multiplexer may pass a frequency range that includes low-band cellular frequencies. and a low-pass filter for filtering low-band WLAN signals and mid-band and high-band cellular signals. a bandpass filter that passes a frequency range including the wideband WLAN signal; This example can be configured to include a high-pass filter that passes a range of frequencies. For illustrative purposes only. As another example, a multiplexer may be used to provide a high pass filter and a low pass filter. It may have a variety of different configurations, such as a diplexer that provides the function of a filter.

[0028] Because the diversity antenna 170 is physically separated from the primary antenna 160, The diversity antenna 170 may be attached to a cable or a printed circuit board (PCB) trace. In some implementations, the transmission line is lossy and the signal received at the diversity antenna 170 is 4. Therefore, in some implementations, the diversity antenna A gain is applied to the signal received at the filter 170. Other analog processing (e.g., analog processing) may be applied by the diversity receiver module 108. Such a diversity receiver module 108 can receive signals from a diversity antenna 1. 70 are physically located close to the diversity receiver front-end module An example of this is now described in detail.

[0029] The RF module 106 and the diversity receiver module 108 are connected to the primary antenna 1. Multiple gain modes for amplifying signals from the antenna 60 and the diversity antenna 170, respectively. The variable gain amplifiers 110a, 110b are configured to provide 10a, 110b are each a gain stage 120 and a variable gain amplifier 110a, 110b. a degenerator that varies the inductance based at least in part on one gain mode; and a signal switching block 130. The signal received at the amplifier 120 may be amplified using a gain stage 120, or the signal may be As detailed in

[0034] , it may be permissible to bypass the gain stage 120. The selected inductance, bypass path, and / or The gain modes of the variable gain amplifiers 110a and 110b are controlled by the controller 102. The degeneration switching block 130 changes the inductance. The performance of the variable gain amplifiers 110a, 110b can be fixed by configuring The inductance of the amplifier can be increased relative to the and / or can increase performance by reducing noise introduced during amplification The variable gain amplifiers 110a and 110b receive multiple input signals and output a single signal or multiple signals. In certain implementations, each input can be an input port. To improve the input isolation between the corresponding individual degeneration switching blocks, It may have a

[0030] Advantageously, the architecture of the variable gain amplifiers 110a, 110b does not use switches. Multi-input processing can be provided without using variable gain amplifiers 110a, 110b. b is advantageously a switchable degenerator with tailored inductance. Achieving targeted or improved linearity by using a rectification block The variable gain amplifiers 110a and 110b can be provided with a shunt switch in the bypass path. can be used to provide targeted or improved input-to-output isolation. The variable gain amplifiers 110a and 110b are configured to operate in a specific gain mode, such as a low gain mode. This allows for a low loss direct bypass mode.

[0031] The controller 102 may be configured to generate control signals and / or to control other components of the wireless device 100. In some embodiments, the method may be configured to send the The controller 102 is compliant with the Mobile Industry Processor Interface Alliance (MIPI) The controller 1 provides a signal based at least in part on specifications provided by the Alliance. 02 receives signals from other components of the wireless device 100 and transmits the signals to the other components. The control signals received by the device can be processed to determine In this embodiment, the controller 102 analyzes the signal or data and determines whether the wireless device 100 It can be configured to determine the control signals sent to other components. The gain control unit 102 is configured to generate a control signal based on the gain mode provided by the wireless device 100. For example, the controller 102 can be configured to generate a control signal to control the gain mode. The controller 102 can also transmit the signal to the variable gain amplifiers 110a and 110b. Generates a control signal to select the inductance of the generation switching block 130. The controller may be configured to generate a variable gain amplifier to provide a bypass path. The control signals can be configured to generate control signals that control the transducers 110a, 110b.

[0032] In some implementations, the controller 102 may be configured to service an input signal received at an input. In some implementations, the control circuit generates an amplifier control signal based on the signal quality metric. The device 102 receives a signal from the communication controller and then processes the received signal. Generates amplifier control signals based on the Quality of Service (QoS) metrics of the received signal. The QoS metrics are received, at least in part, at the diversity antenna 170. The received signal may be based on a diversity signal (e.g., an input signal received at the input). The QoS metric of the received signal is further based on the signal received at the primary antenna 160. In some implementations, the controller 102 may receive a signal from a communication controller. Instead, the amplifier control signal is generated based on the QoS metric of the diversity signal. In some implementations, the QoS metric includes signal strength. The block can be configured to measure bit error rate, data throughput, transmission delay or any other QoS metric. In some implementations, the controller 102 may include variable gain amplifiers 110a, 110b, 110c, 11c, 11d, 11e, 11f, 11g, 11h, 11m, 11m. 0b) to control the gain (and / or current) of the amplifier. The control unit 102 adjusts the gain of other components of the wireless device based on the amplifier control signal. Control.

[0033] In some implementations, the variable gain amplifiers 110a, 110b amplify the received signal. a stage configured to amplify the gain by one of a plurality of set amounts indicated by the amplifier control signal; In some implementations, the variable gain amplifier 110a, 10b amplifies the received signal by a gain proportional to or indicated by the amplifier control signal. In some implementations, the variable gain amplifier may include a continuously variable gain amplifier configured to Amplifiers 110a, 110b draw one of a number of preset amounts of current as indicated by the amplifier control signal. a step variable current amplifier configured to amplify the received signal by In some implementations, the variable gain amplifiers 110a, 110b receive an amplifier control signal. A continuous variable resistor configured to amplify a received signal by drawing a current proportional to the It may include a variable current amplifier.

[0034] FIG. 2 shows a diversity receiver including a DRx front-end module (FEM) 208. 2 illustrates a receiver (DRx) configuration 200. The DRx configuration 200 receives a diversity signal. , and transmits the diversity signal to the DRx FEM 150 via the filter assembly 272. The filter assembly 27 includes a diversity antenna 170 configured to provide 2, for example, by transmitting signals within the target frequency range through a degeneration switching circuit. 230 to selectively direct the signals along each path to the multi-input amplifier 220. The signal may include a multiplexer configured to receive, for example, a cellular signal (e.g., low, medium, high and / or ultra-high band cellular frequencies), WLAN signals, BLUETOOTH (registered trademark The signals may be radio frequency (RF) signals, including but not limited to GPS signals, GPS signals, etc. .

[0035] The DRx FEM 208 receives the diversity signal from the filter assembly 272. For example, the DRx FEM 208 may be configured to process a diversity signal. one or more active frequency bands, which may include cellular and / or WLAN frequency bands The controller 102 can be configured to filter to a target filter. The DRx FEM208 is controlled to selectively direct signals to the filter to achieve filtering. As another example, the DRx FEM 208 may be configured to control the amplifier 22. 0 may be configured to amplify one or more of the filtered signals. For this purpose, the DRx FEM208 includes a filter, a low-noise amplifier, and a band-select switch. , matching circuits, and other components. DRx FEM to intelligently select the path for the diversity signal through The components at 208 may be configured to interact with each other.

[0036] The DRx FEM208 transmits and receives at least a portion of the processed diversity signal. The transceiver 104 can be controlled by the controller 102. In some implementations, the controller 102 may be implemented within the transceiver 104 .

[0037] The DRx FEM 208 can be configured to provide multiple gain modes. For several gain modes, the variable impedance of the degeneration switching circuit 230 The gain stage 232 allows different inductances to be provided. , the switch 234 of the variable impedance stage 232 is connected to the The impedance (e.g., inductance) can be configured to be selected. Such selection can be done, for example, to improve the linearity of the amplification process. The variable impedance can be embedded in a multiple input amplifier architecture.

[0038] In some embodiments, a selectable impedance, e.g., L, coupled to the amplifier stage. The use of NA can improve linearity and / or IIP3. 4, the variable impedance stage 232 advantageously allows for specific gain modes and / or or coupling amplifier 220 to a desired or target impedance for signal amplitude. In some embodiments, the DRx configuration 200 may be configured to It bypasses the amplification when operating in one gain mode and amplifier 220 when operating in other gain modes. This advantageously enables the DRx configuration 200 to The linearity in a particular gain mode can be improved.

[0039] In some embodiments, amplifier 220 receives multiple input signals and outputs a single output. In certain embodiments, the amplifier 220 is configured to provide a plurality of input The filter may be configured to receive a signal and provide a corresponding number of output signals. Assembly 272 routes signals corresponding to specific frequency bands to designated paths to amplifier 220. In certain implementations, the amplifier 220 may be configured to direct the light along the receiving The variable impedance stage 232 can provide different gain modes for the received signal. uses a switch 234 coupled to the amplifier 220 to select different impedances. The selected impedance may be determined, at least in part, by the In certain implementations, amplifier 220 is in a bypass configuration. In an amplifier configuration, the signal is amplified. The selected impedance can be a variable impedance. This advantageously provides the DRx FEM 208 negative impact on linearity (e.g., IIP3) and / or noise figure (NF) The reduction is compared with a configuration in which the path route and / or variable impedance are not selectively provided. While the amplifier 220 is in operation, it may provide variable gain and / or multiple gain modes. may include any suitable amplifier circuit configured to provide a desired or targeted amplification. In some embodiments, amplifier 220 includes a low noise amplifier (LNA) circuit. This is because multiple frequency bands ( configured to amplify signals from a frequency band (e.g., a cellular frequency band and / or a WLAN frequency band). However, the embodiments described herein may be implemented using low noise amplifiers. It should be understood that this includes, but is not limited to, implementations using any of a variety of amplifiers.

[0040] The amplifier 220 is configured to amplify the signal based at least in part on a plurality of gain modes. For example, amplifier 220 can be configured for a first gain mode with a first amplification factor of or gain, and for a second gain mode, a second amplification or gain, etc. The amplifier 220 may be controlled by the controller 102, which controls the gain provided to the amplifier 220. For example, the controller 102 may be configured to control the desired or target gain can be provided to amplifier 220, which provides a target gain. The controller 102 may, for example, receive information from other components in the wireless device. , receive an indication of the target gain, and adjust the amplifier 220 based at least in part on the indication. Similarly, the degeneration switching circuit 230 can control the amplification based at least in part on the gain mode and / or target gain of the amplifier 220. It is possible.

[0041] The controller 102 controls the DRx FEM to selectively provide a tailored impedance. For example, the controller 102 and the DRx FE The M208 provides a target impedance based at least in part on the gain mode. To achieve this, variable impedance stage 232 can be controlled to configure switch 234. As another example, the controller 102 and the DRx FEM 208 may be configured, at least in part, to The amplifier can be controlled to provide a bypass path based on the mode. The controller 102 and DRx FEM 208 use the amplifier 220 to provide multiple gain modes. can be given.

[0042] Variable Gain Amplifier Architecture Example

[0043] The front-end module generally includes a low-noise amplifier (LNA) to amplify the received signal. In wireless devices that offer various gain modes, performance is improved. Selectively providing variable or tailored impedance to gain stages to improve Similarly, for at least one gain mode, improving performance (e.g. It may be advantageous to bypass the gain stage (e.g., to improve linearity).

[0044] Thus, what is provided herein is a method for at least partially controlling the gain mode of a variable gain amplifier. Depending on the degeneration block and / or feedback block, It is a variable gain amplifier that selectively provides a tailored impedance. Advantageously, the performance penalty is reduced or eliminated in one or more gain modes. In addition, the variable impedance improves the linearity of the amplification process in the target gain mode. Similarly, a variable gain amplifier can be configured to increase or decrease the gain to improve signal quality. , can be configured to provide a low loss bypass mode in low gain mode.

[0045] FIG. 3A illustrates an example variable gain amplifier configuration 310 a that includes a multiple-input gain stage 312 . The multi-input gain stage 312 receives multiple inputs and filters the received signals through the gain stage 320. to selectively amplify or provide a bypass path through bypass block 340. The gain stage 320 is coupled to a degeneration switching block 330. The degeneration switching block 330 is connected to the variable gain amplifier configuration 310a. selectively providing a tailored impedance based at least in part on the gain mode of the In certain implementations, the multi-input gain stage 312 is configured to receive the separate input ports. Each separate input port is configured to receive multiple signals at the input port. configured to receive signals in one or more specific cellular frequency bands, e.g. A signal in the first band is received at the first input port, and a signal in the second band is received at the second input port. and a signal in a third band is received at a third input port.

[0046] The variable gain amplifier 310a can be configured to receive multiple inputs without using a switching network. The variable gain amplifier 310a can be configured to provide degeneration. It is designed to achieve relatively high linearity through the use of a phase switching block 330. In certain implementations, the bypass block 340 may be a shunt switch. The shunt switch provides higher input-to-output isolation compared to configurations with such switches. The variable gain amplifier 310a can convert the signal from the input to a bypass block. low loss direct current by directing it through the clock 340 but not through the gain stage 320 It can be configured to provide a low loss direct bypass mode. The mode can be implemented in a low gain mode, for example.

[0047] The variable gain amplifier 310a includes a multi-input gain stage 312 that provides a voltage to a current gain stage 320. The multi-input gain stage 312 can be configured to provide isolation between the inputs. In some embodiments, the variable gain amplifier 310a provides a differential gain for each input. A decoupling switching block 330 may be included to further isolate the inputs. do.

[0048] The degeneration switching block 330 changes the impedance into the gain stage 320. In this way, it is possible to match the previous stage in the processing chain. By adding power and / or noise, performance can be improved. The motion switching block 330 provides a feedback mechanism to The gain stage 320 may be configured to improve linearity. Thus, the degeneration switching block 330 selects a first inductor for the first gain mode. and configured to provide a second impedance for a second gain mode. The selected impedance provided by the degeneration switching block 330 The gain stage 320 may also be configured to improve the linearity of the gain stage 320. In bypass mode, the degeneration switching block 330 In this way, the gain stage 320 can be configured to bypass the Reducing or minimizing leakage current can improve linearity performance.

[0049] Bypass block 340 is configured to receive signals from multiple inputs and to provide a bypass to gain stage 32. 0 or provides a path to the output that does not pass through the degeneration switching block 330. The bypass block 340 is configured to take advantage of the benefits provided by the variable gain amplifier 310a. A component that serves to separate the input and output sections in one or more of the acquisition modes. It may include.

[0050] The intermediate gain mode feedback block 350a is configured to The intermediate gain modes are configured to be activated for a subset of the gain modes. The feedback block 350a is configured to provide a target impedance to the input signal. This can help improve the linearity of the amplification process. Feedback block 350a controls the feedback within variable gain amplifier 310a. The intermediate gain mode feedback block 350a can also be configured as follows: The degeneration block can be configured to provide the same functionality as the circuit This can be done.

[0051] The bypass switch 360 is connected to the bypass block 340 via the input to the output. 320. The gain stage 320 is configured to selectively provide a path from the input to the output. The bypass switch 360 controls at least part of the gain mode of the variable gain amplifier 310a. one or more switching elements that isolate and / or select a desired path based on the It may include.

[0052] In certain embodiments, the variable gain amplifier 310a can have multiple gain modes, e.g., It can be configured to give modes G0, G1, ..., GN, where G0 is the highest gain. When operating in gain mode GN, the variable gain amplifier 31 0a can be configured to direct signals from the input to the bypass block 340. When operating in gain modes G0 to GN-1, the variable gain amplifier 310a includes gain stages 32 Activate the degeneration switching block 330 by directing the signal through 0. The degeneration switching block 330 can be configured to may be different impedance levels for individual gain modes or for groups of gain modes. Even in these gain modes, the bypass block The bypass block 340 provides isolation between the input and output sections. By activating the switch, it can be at least partially activated. The variable gain amplifier 310a can select one or more of the gain modes G0 to GN-1 as an intermediate gain. The gain mode feedback block 350a can be configured to activate do.

[0053] The variable gain signal amplifier 310a is the intermediate gain mode feedback block 35 of the present disclosure. 0a, bypass block 340, and degeneration switching block 330. Achieves relatively low noise and high linearity (e.g., higher IIP3) compared to amplifiers without The variable gain signal amplifier 310a can be configured to receive the cellular signal, WL Radio frequencies (R) such as AN signals, BLUETOOTH (registered trademark) signals, GPS signals, etc. F) The variable gain signal amplifier 310a can be configured to amplify a number of signals. By receiving signals across multiple frequency bands at the input and processing the signals, The variable gain signal amplifier 310a can be configured to provide wideband performance. It can be configured to process the signal at each input independently. The gain signal amplifier 310a is connected to a controller (e.g., the control circuit described herein with reference to FIGS. 1 and 2). The control circuit assembly, such as the control circuit 102, can be configured to control the The path assembly intelligently and selectively switches the path between the amplification path and the bypass path. can be selectively switched by the degeneration switching block 330 Impedance can be provided.

[0054] Although three inputs are illustrated, the variable gain amplifier 310a may have any number of suitable inputs. It should be understood that the input section may include, for example, without limitation, a variable gain amplifier 310a has at least two inputs, at least four inputs, at least eight inputs, At least 16 inputs, at least 32 inputs, at least 64 inputs, or The input may include at least any number of inputs in the ranges listed. The gain amplifier 310a may have 64 or fewer inputs, 32 or fewer inputs, 16 or fewer inputs, It may include eight or fewer inputs, four or fewer inputs, or any number within the stated range.

[0055] FIG. 3B shows a variable gain amplifier 310a having the same components as FIG. 3A with the addition of certain elements. 3 illustrates another example variable gain amplifier 310b including a variable gain amplifier component. b includes matching networks 313, 318, and 345. The input matching network 313 is , configured to provide an impedance match to the signal received at the input. Similarly, the output matching network 318 is connected to the output load 316, the gain stage 320, and the cascode bridge. The amplifier including the buffer 314 is configured to provide impedance matching. The bypass matching network 345 also provides an impedance matching to the bypass block 340. The matching networks 313, 318, and 345 are given the target impedance. Any suitable combination of inductors and capacitors may be used to provide the This can be done.

[0056] The variable gain amplifier 310b also includes an output load 316 and a cascade amplifier as part of the amplification chain. The cascode buffer 314 acts as a current buffer. The cascode buffer 314 can be configured to provide a gain stage 320 and an output stage 322. The cascode buffer 314 is also configured to provide isolation from the variable gain amplifier. The output load 316 may be configured to improve the gain of the output voltage. The output load 316 is configured to provide a load to the current to generate the amplitude. tuned or tunable to each band received in The output load 316 can be adjusted by customizing the resistance of the output load 316. It can be configured to improve return loss and / or increase bandwidth. Voltage VD D can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD may be such that a lower current flows through the output load 316, which may result in a variable gain amplifier. The amplifier 310b can be configured to accommodate the lower gain.

[0057] FIG. 3C is similar to the variable gain amplifier 310a of FIG. 3A, but includes a bypass switch 360. 3 illustrates another example variable gain amplifier 310c in which the bypass switch 360 is omitted. Therefore, the output of the bypass block 340 is coupled to the output of the output of the gain stage 320. In addition, the intermediate gain mode feedback block is connected to the shutdown switch block. 3A. However, the shutdown switch block 350c is replaced by the It is not coupled to the output as in variable gain amplifier 310a. Therefore, the shutdown switch block 350c reduces leakage in the amplifier 310c. In some embodiments, the input node is configured to selectively isolate the input node. This is the switch between the input node and the reference potential node when the input is not in use. It can be activated by activating the switch. The switch can couple the input node to the reference potential node via the capacitive element. .

[0058] FIG. 3D shows the same components as variable gain amplifier 310c of FIG. 3C, with the addition of certain elements. 3 illustrates another example variable gain amplifier 310d that includes the variable gain amplifier 310b. 0d includes matching networks 313, 318 and 345. 3 is configured to provide impedance matching to the signal received at the input. Similarly, the output matching network 318 is connected to the output load 316, the gain stage 320, and the cascode. and an amplifier including a buffer 314. The bypass matching network 345 also provides an impedance matching to the bypass block 340. The matching networks 313, 318, and 345 are given the target impedance. Any suitable combination of inductors and capacitors may be used to provide the impedance. It is possible.

[0059] The variable gain amplifier 310d also includes an output load 316 and a cascade amplifier as part of the amplification chain. The cascode buffer 314 acts as a current buffer. The cascode buffer 314 can be configured to provide a gain stage 320 and an output stage 322. The cascode buffer 314 is also configured to provide isolation from the variable gain amplifier. The output load 316 may be configured to improve the gain of the output voltage. The output load 316 is configured to provide a load to the current to generate the amplitude. tuned or tunable to each band received in The output load 316 can be adjusted by customizing the resistance of the output load 316. It can be configured to improve return loss and / or increase bandwidth. Voltage VD D can be configured to set the gain mode of the variable gain amplifier 310d. For example, the voltage VDD may be such that a lower current flows through the output load 316, which may result in a variable gain amplifier. The amplifier 310d can be configured to accommodate the lower gain.

[0060] FIG. 4 illustrates a variable gain amplifier configured to receive an input signal and generate an amplified output signal. Illustrated is a variable gain signal amplifier 410 including a stage 420. The variable gain signal amplifier 410 also , also includes a degeneration switching block 430 coupled to the variable gain stage 420. The degeneration switching block 430 controls the different gains of the variable gain stage 420. It can be configured to provide a gain level.

[0061] FIG. 5 illustrates a variable impedance amplifier 520 coupled to a signal amplifier 520 with various gain levels. Illustrated is a degeneration switching circuit 530 including a variable impedance stage 532. The impedance stage 532 is configured to provide different impedance values associated with different gain levels. The degeneration switching circuit 530 can be configured as follows: The switch 534 is operatively associated with the dance stage 532. The switch 534 , implemented to selectively isolate the variable impedance stage 532 from the reference potential node. .

[0062] FIG. 6 illustrates a variable gain amplifier 310b configured similarly to the variable gain amplifier 310b described herein with reference to FIG. 3B. 6 illustrates an example of a variable gain amplifier configuration 610. The variable gain amplifier 610 is an example of an amplifier implementation. It includes example electrical components to demonstrate, however, this is merely an example of an implementation. , the scope of this disclosure extends to additional implementations encompassing similar architectures. You should understand.

[0063] The variable gain amplifier arrangement 610 receives inputs A, B, and C and converts the received signals into A cascode buffer 614 having a transistor Q10 in conjunction with corresponding transistors Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q30, Q31, Q32, Q33, Q34, Q35, Q36, Q37, Q38, Q49, Q41, Q42, Q43, Q44, Q45, Q46, Q47, Q48, Q49, Q50, Q51, Q52, Q53, Q54, Q55, Q56, Q57, Q58, Q59, Q60, Q61, Q62, Q63, Q64, Q 6. The amplifier 600 includes a multi-input gain stage 612 configured to selectively amplify the gains by Q4 and Q5. The multi-input gain stage 612 also includes a switching transformer for each of the inputs A, B, and C. To provide a bypass path through bypass block 340 including resistors Q6, Q7 and Q8. It is configured as follows.

[0064] The multi-input gain stage 612 is coupled to a degeneration switching block 630. The degeneration switching block 630 is Selectively providing a tailored impedance based at least in part on the gain mode. In certain implementations, the multi-input gain stage 612 is configured to have separate input ports. Each separate input port is configured to receive a number of signals at a single configured to receive signals in one or more specific cellular frequency bands. Input A receives signals in the first band, input B receives signals in the second band, and input C receives signals in the third band. In some embodiments, transistors Q3, Q4, and Q5 receive a signal in the band. Each has a dedicated degeneration switch to increase isolation between input ports. Each of these inputs can be coupled to a switching block 630. The FETs are coupled to inductors L4, L5 and L6 to provide phase matching.

[0065] The variable gain amplifier configuration 610 provides multi-input signals without the use of a switching network. The variable gain amplifier arrangement 610 can be configured to provide power processing. To achieve relatively high linearity through the use of a phase switching block 630 In certain implementations, the bypass block 640 can be configured to The shunt switch Q can provide higher input-to-output isolation compared to a configuration with a 9. The variable gain amplifier arrangement 610 includes a bypass block 640 from the input. It can be configured to provide a low-loss direct bypass mode by directing the signal to The low loss direct bypass mode can be implemented in low gain mode, for example. can.

[0066] The variable gain amplifier configuration 610 provides a voltage to a current gain stage including transistors Q3-Q5. The multi-input gain stage 312 provides a voltage to the current gain stage. Furthermore, the multi-input gain stage 312 is configured to convert each input signal into a 10. The amplifier 610 is configured to amplify the input signal in conjunction with a cascode buffer 614 including a transistor Q10. The code buffer 614 lowers the input impedance and increases the output impedance. The inverter is configured to act as a current buffer to increase the current.

[0067] The degeneration switching block 630 controls the gain stages of the multi-input gain stage 612. In this way, the front end of the processing chain is By providing power and / or noise matching to the stages, performance can be improved. The generation switching block 630 provides a feedback mechanism. This improves the linearity of the gain stage (for example, transistors Q3 to Q5). The degeneration switching block 630 includes transistors Q2 and and transistor Q1 are activated, respectively, to set the first impedance L1. a first gain mode and a second impedance provided by L1 and L2 in a second gain mode. The degeneration switching block 63 can be configured to provide The selected impedance provided by the zero is also configured to improve the linearity of the gain stage. The variable gain amplifier configuration 610 can also be used in bypass mode for degeneration. The on-switching block 630 can be configured to be bypassed. to improve linearity performance by reducing or minimizing leakage current through the gain stage. In certain implementations, the degeneration switching block 630 may , can be configured to provide low inductance in high gain modes. The amount of inductance provided by the ration switching block 630 is This can be changed by changing the gain mode of the configuration 610.

[0068] The bypass block 640 is configured to receive signals from multiple inputs and to provide a gain stage (e.g. For example, through transistors Q3 to Q5) or degeneration switching block 630 Bypass block 640 is configured to provide a path to the output that does not exceed the The output is configured to provide a single path through transistor Q11 and capacitor C1. Capacitor C1 can be configured to block direct current (DC) voltage from the output supply. Bypass block 640 also helps isolate the input from the output. 6. The bypass block 640 is selectively coupled to the reference potential node via transistor Q9. The bypass matching network 645 includes a shunt switch. This allows for flexibility in performance matching.

[0069] The intermediate gain mode feedback block 650 is configured to provide the The intermediate gain modes are configured to be activated for a subset of the gain modes. The feedback block 650 is configured to provide a target impedance to the input signal. This can help improve the linearity of the amplification process. An RC matching network 651 can be used to control the amount of feedback. Additionally, the RC matching network 651 is configured to act as a block for the DC voltage. The RC matching network 651 can be configured as an amplitude and phase feedback The RC matching network 651 can be configured to control the capacitance. capacitor, resistor, capacitor and resistor in series, or capacitor, resistor and other components The medium gain mode feedback block 65 may include any suitable combination of the following: 0 can also be configured to control feedback within the variable gain amplifier 610. The medium gain mode feedback block 650 is a second degeneration block. The blocks can be configured to provide similar functionality as included in the circuit.

[0070] When activated, the signals from inputs A, B and C are A , B and C At point D In the Exit the lock. This point D output matching network 618 and bypass switch 6 60. In other words, the intermediate gain mode feedback block The circuit 650 connects the inputs A, B, and C to the transistors Q14 to Q16 and Q18. An additional transistor Q17 acts as a bypass block. Similar to block 640, a shunt switch can be configured to provide a reference potential node. Key Points D is connected to the output matching network 618 so as to be ahead of the output matching network 618. It can be positioned within the output matching network 618 or after the output matching network 618. The medium gain mode feedback block 650 can be used to cancel the input and output. can be configured to generate a point D has variable gain to improve performance It may be positioned within the amplifier arrangement 610 .

[0071] The bypass switch 660 is connected to the inputs A, B, and C via the bypass block 640. The path to the output, or from inputs A, B and C to gain stage elements and amplifier elements (e.g. cascoders) 614 and output matching network 618 to the output. The bypass switch 660 controls the connection between the amplification path and the output. The transistor Q12 controls the connection between the bypass path and the output. 13. The bypass switch 660 controls the gain mode of the variable gain amplifier 610 at least The control can be based in part on both.

[0072] Matching networks 618 and 645 are used to provide the desired impedance. The output may include any suitable combination of inductors and capacitors that can The combining network 618 connects the output load 616 to the gain stage (e.g., transistors Q3-Q5) and and an amplifier including a cascode buffer 614. The bypass matching network 645 is also configured to gives the impedance matching of

[0073] The variable gain amplifier 610 includes an output load 616 and a cascode backplane as part of the amplification path. The cascode buffer 614 is configured to act as a current buffer. The cascode buffer 614 includes a transistor Q10 formed between the gain stage and the output. The cascode buffer 614 is also configured to provide isolation. The output load 616 can also be configured to improve the gain of 10. The output load 616 is configured to provide a load to the current to generate a It is configured to be tuned or tunable for each band received. For example, the output load can be tuned for a specific cellular frequency band. The output load 616 also includes a variable capacitor C2. to improve return loss and / or increase bandwidth by incorporating It is also possible.

[0074] The voltage VDD can be configured to set the gain mode of the variable gain amplifier 310b. For example, the voltage VDD may be lower so that the current flowing through the output load 316 is lower. The gain of the variable gain amplifier 310b can be configured to accommodate this.

[0075] 7A-7C illustrate several example modes of operation of the variable gain signal amplifier configuration 610 of FIG. FIG. 7A illustrates operation in one or more high-gain modes. In this mode, the bypass block 640 is deactivated except for the shunt switch Q9. The signals received at inputs A, B and C are fed to a receiving circuit including transistors Q3 to Q5. 614 and through the cascode buffer 614, and the output matching network The output is reached through a work 618 and a bypass switch 660. In these high gain modes, Q12 is activated and Q13 is deactivated. Additionally, in these high gain modes, transistor Q2 is turned on and transistor Q1 is turned off, so that the gain is The inductance applied to the stage is L1. In these high gain modes, the intermediate gain The mode feedback block 650 is also deactivated.

[0076] FIG. 7B illustrates operation in one or more intermediate gain modes. These modes also These intermediate gain modes can be referred to as low gain, high linearity modes. There are several significant differences in the operation of the high gain modes. In block 630, transistor Q2 is turned off and transistor Q1 is turned on. , which is then fed to the gain stage via the degeneration switching block 630. The inductance applied is given by both L1 and L2. A higher gain mode results in an increased impedance, or a higher gain mode results in a decreased impedance. Second, the medium gain mode feedback block 650 is active. This reduces the circuit load, just like adding a second degeneration block. This provides additional feedback to the

[0077] FIG. 7C illustrates operation in one or more low-gain modes. In this case, the bypass block 640 is activated and the gain stage transistors Q3 to Q5 are activated. The signals received at inputs A, B and C are deactivated in bypass block 64. 0, through a bypass matching network 645 and a bypass switch 660, and In these low-gain modes, the bypass switch activates Q13. and deactivate Q12. In addition, the degeneration switching block To deactivate 630, transistors Q1 and Q2 are turned off, and the gain stage transistor Reducing or minimizing the leakage current through transistors Q3-Q5 improves linearity performance. The medium gain mode feedback block 650 also controls the gain in these low gain modes. It is deactivated.

[0078] FIG. 8 shows a variable gain signal amplifier configuration 610 similar to that of FIG. 6, but without bypass switch 66. 8 illustrates a variable gain signal amplifier 810 with the zero removed. , the output of the bypass matching network 645 is instead connected to the output matching network 618. In this configuration, the selection of the amplification path or the bypass path is controlled. There is no bypass switch controlling the gain stage. Rather, the selected transistor (e.g. transistors Q3-Q5), and selected transistors of the bypass block (e.g. Transistors Q6-Q8 are selectively active to provide a bypass path or an amplification path. are activated and deactivated.

[0079] FIG. 9 illustrates a variable gain signal amplifier configuration 610 similar to that of FIG. 6, but with an intermediate gain mode feedback. Variable gain with shutdown switch block 950 instead of feedback module 9 illustrates a signal amplifier 910. In this configuration, the output node of the output matching network 618 Since the shutdown switch block 950 is not coupled to the amplification path in Instead, the shutdown switch block 950 is Transistors Q14-Q16 and capacitors configured to selectively isolate A, B, and C In some embodiments, the shutdown switch block 950 does not include capacitors C3 to C5. The shutdown switch block 950 is Switches on when the corresponding input is not in use (e.g., transistors) This reduces leakage in the amplifier configuration. To reduce or eliminate this, the input can be shut off to ground. can.

[0080] FIG. 10 is similar to the variable gain signal amplifier configuration 910 of FIG. 9, but with bypass switch 6 8 illustrates the variable gain signal amplifier 1010 with the variable gain signal amplifier 8 of FIG. 10, the bypass matching network 6 is eliminated by eliminating the bypass switch. This results in the output of 45 being coupled to the input node of output matching network 618. In this configuration, there is no bypass switch to control the selection of the amplification path or the bypass path. In addition, selected transistors in the gain stage (e.g., transistors Q3-Q5) and the bypass Selected transistors (e.g., transistors Q6 to Q8) in the sub-block are bypassed. The amplifiers are selectively activated and deactivated to provide either a passive or an amplifying path.

[0081] Example Products and Architectures

[0082] FIG. 11 illustrates, in some embodiments, a combination of features (e.g., FIGS. 1-10). Diversity receiver configurations including some or all of the diversity receiver configurations having Some or all of the above may be implemented in whole or in part in modules. The module may be, for example, a front-end module (FEM). The module may be, for example, a diversity receiver (DRx) FEM. The module may be, for example, a multiple input, multiple output (MiMo) module.

[0083] In the example of FIG. 11, module 1108 includes a package substrate 1101. A certain number of components are mounted on the package board 1101. For example, controller 1102 (which may include an end-end power management integrated circuit [FE-PIMC]), Assembly 1106, a gain stage 1120 having one or more features described herein, and a delay a variable gain amplifier assembly 1110 including a transmission switching block 1130; and a filter bank 1108 (which may include one or more bandpass filters) in a package. Mounted and / or mounted on and / or within the package substrate 1101 Other components, such as a certain number of SMT devices 1105, can be packaged. All of the various components can be mounted on a package board 1101. Although depicted as laid out on a printed circuit board 1101, certain components It is understood that components may also be implemented on top of other components.

[0084] FIG. 12 illustrates, in some embodiments, a combination of features (e.g., FIGS. 1-10). Diversity receiver configurations including some or all of the diversity receiver configurations having may be implemented in whole or in part in the architecture. Such an architecture includes one or more modules, a diversity receiver (DRx) It can be configured to provide front-end functionality such as front-end functionality.

[0085] In the example of FIG. 12, the architecture 1208 includes a front-end power management integrated circuit ( [FE-PIMC]) controller 1202, combination assembly 1206, A gain stage 1220 and degeneration switching element having one or more of the features described in a variable gain amplifier assembly 1210 including a gain block 1230; a filter bank 1208 (which may include a pass filter) on the package substrate 1201 and and / or may be attached and / or mounted within a package substrate 1201. Other components, such as SMT devices 1205, may also be included in the architecture 1208. It can be implemented.

[0086] In some implementations, a device and / or The circuitry may be included in an RF electronic device such as a radio frequency device. The service and / or circuitry may be integrated directly into the wireless device, in a modular form as described herein, or in a In some embodiments, such The wireless device may be, for example, a mobile phone, a smartphone, a handheld device with or without a telephone function, or This may include handheld wireless devices, wireless tablets, and the like.

[0087] FIG. 13 illustrates an example wireless device 1300 having one or more advantageous features described herein. In the context of one or more modules having one or more features described herein, Such modules are generally designated by dashed lines (which may be implemented as front-end modules, for example). enclosure 1306, and a diversity The receiver (DRx) module 1308 is depicted.

[0088] Referring to FIG. 13, a plurality of power amplifiers (PAs) 1382 are provided in the transceiver 130. The transceiver 1304 can receive RF signals from the configured and operable to generate a signal and to process a received signal. The transceiver 1304 transmits data and / or voice signals appropriate for the user to the transceiver 1304. a baseband subsystem 130 configured to provide conversion between an RF signal suitable for 5. The transceiver 1304 also interacts with the wireless device 1300. communicating with a power management component 1307 configured to manage power for operation purposes; Such power management may also be performed on the baseband subsystem 1305 as well as the modules. The operation of modules 1306 and 1308 can also be controlled.

[0089] The baseband subsystem 1305 processes the audio and video signals provided to and received from the user. and / or a user interface 1301 to facilitate various inputs and outputs of data. The baseband subsystem 1305 is also shown connected to the wireless device. Memory 1 configured to facilitate operation and / or provide information storage for the user. 303. The memory 1303 is configured to store data and / or instructions. will be done.

[0090] In the example wireless device 1300, the output of the PA 1382 is The amplified and filtered signals are then matched and routed to each duplexer 1386. The filtered signals are routed through a switching network 1309 for transmission. The duplexer 1360 may be routed to the next antenna 1360. The antenna 1386 allows a common antenna (e.g., primary antenna 1360) to be used for transmitting. In FIG. 13, the received signal is 13. The variable gain amplifier assembly 1310a provides the features and benefits of the variable gain amplifier shown. The DRx module 1308 is also shown as being driven by a similar variable gain amplifier assembly. Includes Bri 1310b.

[0091] In the example wireless device 1300, a signal received at a primary antenna 1360 is The signal may be transmitted to a variable gain amplifier 1310a in the front end module 1306. The amplifier 1310a includes a gain stage 1320 and a degeneration switching block 1330. 30. The variable gain amplifier 1310a receives a plurality of signals at an input 1311. and configured to receive the processed signals at output 1319. The gain amplifier 1310a amplifies the signal based at least in part on the gain mode. and a degeneration switching block based at least in part on the gain mode. 330 to provide the target impedance. It is designed to improve signal linearity compared to variable gain amplifiers that do not incorporate one or more of the features. In at least one low gain mode, the gain stage 1320 and the degenerator The allocation switching block 1330 may be bypassed. In the gain mode, the gain is controlled via the intermediate gain mode feedback module described herein. As shown, additional gain is added in the variable gain amplifier 1310a to improve the linearity of the amplification process. Can give feedback.

[0092] The wireless device also includes a diversity antenna 1370 and a diversity antenna It also includes a diversity receiver module 1308 that receives signals from 1370. The city receiver module 1308 is a variable gain receiver in the front-end module 1306. The diversity receiver module includes a variable gain amplifier 1310b similar to the amplifier 1310a. The module 1308 and the variable gain amplifier 1310b process the received signal and output the processed signal. 13. In some embodiments, a diplexer, a triplicate, a plexer, or other multiplexer or filter assembly, as described herein. Between the diversity antenna 1370 and the diversity receiver module 1370 can be included in

[0093] One or more features of the present disclosure may be implemented in conjunction with the various cellular frequency bands described herein. Examples of such bands are listed in Table 1. It will be appreciated that At least some of the bands may be divided into sub-bands. It is understood that implementations may also be carried out with frequency ranges that do not have the designation as in the example of 1. The terms RF and radio frequency signals include at least the frequencies listed in Table 1. It is understood that reference is made to a signal. [Table 1]

[0094] Throughout this specification and claims, unless the context clearly indicates otherwise, The words "include," "comprise," and the like are used in an inclusive sense as opposed to an exclusive or exhaustive sense. In other words, it should be interpreted as meaning "including but not limited to." The word "coupled" as used herein means connected directly or through one or more intermediate elements. In addition, the words "here," "on," " "below" and words of similar import when used in this Application shall mean "under" and "below" "Application" refers to the entire application and not to any particular portion of the application. Where the context permits, words in the above description of certain embodiments using the singular or plural Each of the terms "or" and "or" refer to a list of two or more items. "Or" covers all of the following interpretations of the word: Any item, all items in the list, and any combination of items in the list do.

[0095] The above detailed description of embodiments of the present invention is not intended to be exhaustive, i.e., to limit the invention to the above disclosure. It is not intended to be limited to the precise form, and specific embodiments of the invention and examples thereof are illustrative. While the above description is for illustrative purposes, those skilled in the art will recognize that various equivalents are within the scope of the present invention. Modifications are possible. For example, although processes or blocks are presented in a given order, alternative implementations may be used. Embodiments may involve performing routines having steps in a different order or systems having blocks. The system can be used, and some processes or blocks can be deleted, moved, added, or subdivided. Each of these processes or blocks may be The processes or blocks may be implemented in various different ways. Although these processes or blocks may be shown as They can be done in parallel or at different times.

[0096] The teachings of the present invention provided herein are not necessarily limited to the systems described above, but may also be used in other The various embodiment elements and acts described above may also be applied to systems They can be combined to give embodiments.

[0097] While several embodiments of the present invention have been described, these embodiments are presented by way of example only. and are not intended to limit the scope of the present disclosure. The novel methods and systems disclosed herein may be embodied in a variety of other forms. Various omissions, substitutions and changes in the form of the methods and systems described herein are within the scope of this disclosure. The appended claims and their equivalents are intended to encompass within the scope of this disclosure. It is intended to cover such forms or modifications as come within the scope and spirit of the present invention.

Claims

1. 1. A variable gain signal amplifier, comprising: a variable gain stage configured to receive an input signal and generate an amplified output signal; coupled to the variable gain stage and configured to provide a plurality of gain levels for the variable gain stage; Degeneration switching block and an amplifier including

2. 2. The amplifier of claim 1, wherein the signal comprises a radio frequency signal.

3. The amplifier a bypass path that bypasses the variable gain stage; an amplification path passing through the variable gain stage; 2. The amplifier of claim 1 configured to selectively provide:

4. The degeneration switching block further comprises a tailored impedance 2. The amplifier of claim 1 configured to provide said variable gain stage.

5. The customized impedance is a digital signal having the customized impedance. Compared to a variable gain stage that is not coupled to a generation switching block, the amplified 5. The amplifier of claim 4 configured to provide improved linearity in the output signal.

6. The degeneration switching block selects a first gain level of the plurality of gain levels. providing a first tailored impedance to the bell and a second tailored impedance to the bell; a second custom impedance for a gain level of The amplifier of claim 4.

7. The first customized impedance is greater than the second customized impedance. It is also larger, 7. The amplifier of claim 6, wherein said first gain level is lower than said second gain level.

8. an amplification control circuit for controlling the variable gain stage and the degeneration switching circuit; The amplifier of claim 1 further comprising a control circuit configured to generate the signal.

9. The control circuit is configured to provide a plurality of amplification control signals corresponding to the plurality of gain levels.

9. The amplifier of claim 8, wherein

10. further comprising an intermediate gain mode feedback block coupled to the input of the variable gain stage. fruit, The intermediate gain mode provides feedback for a subset of the plurality of gain levels.

10. The amplifier of claim 1 configured to provide a variable gain stage.

11. the intermediate gain mode feedback block and the degeneration switching block The lock is connected to the intermediate gain feedback block and the degeneration switch. imparting improved linearity to the amplified output signal compared to an amplifier without a block.

11. The amplifier of claim 10.

12. further comprising a bypass block coupled to an input of the variable gain stage; The bypass block may be configured to bypass the multiple gain stages to provide a bypass path that does not include the variable gain stage.

2. The gain control system of claim 1, wherein the gain control system is configured to be activated at a low gain level of the plurality of gain levels. amplifier.

13. 13. The bypass path does not include the degeneration switching block. amplifier.

14. 2. The amplifier of claim 1, further comprising a cascode buffer coupled to the output of said variable gain stage. 。

15. 2. The amplifier of claim 1, further comprising a plurality of input nodes coupled to said variable gain stage.

16. The amplifier is configured to receive a plurality of input signals at the plurality of input nodes. 、 16. The amplifier of claim 15, wherein the individual received signals have frequencies within different signal frequency bands.

17. The amplifiers separate the signals received at each input port from the amplification of other received signals.

17. The amplifier of claim 16 configured for independent amplification.

18. 1. A degeneration switching circuit comprising: coupled to signal amplifiers having different gain levels and associated with said different gain levels; a variable impedance stage configured to provide a variety of impedance values; operatively associated with the variable impedance stage to select the variable impedance stage A switch mounted to effectively isolate the reference potential node A circuit including:

19. 20. The circuit of claim 18, wherein the signal amplifier is configured to amplify a radio frequency signal.

20. 2. The circuit of claim 1, wherein a bypass path is provided in the circuit that bypasses the variable impedance stage. Circuit 8.

21. The different impedance values are associated with the different gain levels. The impedance value of the signal amplifier is not coupled to the degeneration switching circuit.

10. The method of claim 1, wherein the signal amplifier is configured to provide improved linearity in the signal amplifier compared to a conventional amplifier. Circuit 8.

22. The variable impedance stage provides a first gain level for a first one of the various gain levels. Given a custom impedance value, a second customized impedance for a second gain level of the various gain levels; 22. The circuit of claim 21 configured to provide a value.

23. configured to generate an amplified control signal to control the variable impedance stage and the switch 20. The circuit of claim 18, further comprising a control circuit.

24. The control circuit is configured to provide a plurality of amplification control signals corresponding to the various gain levels.

24. The circuit of claim 23 comprising:

25. A front-end architecture, comprising: a variable gain signal amplifier including a variable gain stage and a degeneration switching block; a filter assembly; Controller and Including, the variable gain stage configured to receive an input signal and generate an amplified output signal; The degeneration switching block is coupled to the variable gain stage to configured to provide a plurality of gain levels of the gain stage; The filter assembly directs a frequency band to a selected input of the variable gain signal amplifier. coupled to the variable gain signal amplifier so that The controller is adapted to control the variable gain signal amplifier to provide a plurality of gain modes. Implemented, In a low gain mode, the variable gain signal amplifier directs the signal to a low gain stage that bypasses the variable gain stage. Architecture that directs the path along which

26. The degeneration switching block further comprises a tailored impedance 26. The architecture of claim 25 configured to provide a gain to the variable gain stage.

27. The customized impedance is Compared to a variable gain stage that is not coupled to a degeneration switching block, the amplified 27. The architecture of claim 26 configured to provide improved linearity in a received output signal. Slurp.

28. The degeneration switching block selects a first gain level of the plurality of gain levels. providing a first tailored impedance to the bell and a second tailored impedance to the bell; a second custom impedance for a gain level of The architecture of claim 26.

29. 1. A wireless device, comprising: A diversity antenna, a filter assembly; a variable gain signal amplifier; Controller and Including, The filter assembly is coupled to the diversity antenna to receive signals and filter out circumferential directing a wavenumber band along a selected path; The variable gain signal amplifier a variable gain stage configured to receive an input signal and generate an amplified output signal; coupled to the variable gain stage and configured to provide a plurality of gain levels for the variable gain stage; Degeneration switching block and Including, The controller is adapted to control the variable gain signal amplifier to provide a plurality of gain modes. Implemented, In a low gain mode, the variable gain signal amplifier directs the signal to a low gain stage that bypasses the variable gain stage. A device that is oriented along a path.

30. The degeneration switching block further comprises a tailored impedance 30. The device of claim 29 configured to provide a gain to the variable gain stage.

31. The customized impedance is Compared to a variable gain stage that is not coupled to a degeneration switching block, the amplified 31. The device of claim 30, configured to provide improved linearity in an output signal. 。

32. The degeneration switching block selects a first gain level of the plurality of gain levels. providing a first tailored impedance to the bell and a second tailored impedance to the bell; a second custom impedance for a gain level of The device of claim 30.

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