Light-emitting device

Abstract

To provide a semiconductor device the parasitic capacitance of which is small, or provide a semiconductor device the power consumption of which is small.SOLUTION: Provided is a semiconductor device having a transistor and a capacitive element. The transistor includes a first electrical conductor, a first insulator on the first electrical conductor, a semiconductor having a region that overlaps the first electrical conductor via the first insulator, a second insulator on the semiconductor, a second electrical conductor having a region that overlaps the semiconductor via the second insulator, and a third and a fourth electrical conductor having a region that adjoins the upper surface of the semiconductor. The capacitive element includes the same layer as the first electrical conductor and the same layer as the third and fourth electrical conductors.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, , manufacture, or composition of matter. In particular, The present invention relates to, for example, a semiconductor, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a or a semiconductor, a semiconductor device, a display device, a light-emitting device, The present invention relates to a method for manufacturing a lighting device, a power storage device, a memory device, or a processor. device, display device, light-emitting device, lighting device, power storage device, storage device or processor driving method Regarding.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of devices, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. may have semiconductor devices. [Background technology]

[0003] The technology of constructing transistors using semiconductors on substrates with insulating surfaces is attracting attention. Such transistors are widely used in semiconductor devices such as integrated circuits and display devices. Silicon is known as a semiconductor that can be used in transistors.

[0004] The silicon used in transistor semiconductors is either amorphous silicon or polycrystalline silicon depending on the application. For example, silicon dioxide, silicon dioxide, and monocrystalline silicon are used to make large display devices. When applied to transistors, amorphous silicon is used, for which film formation technology for large-area substrates has been established. On the other hand, it is preferable to use a high-performance LCD such as forming a driver circuit and a pixel circuit on the same substrate. When applied to a transistor constituting a display device of a high performance, a transistor having a high field effect mobility It is preferable to use polycrystalline silicon, which can be used to fabricate transistors. When applied to transistors using silicon dioxide, it is possible to create transistors with even higher field-effect mobility. It is preferable to use monocrystalline silicon, which can be easily produced. Polycrystalline silicon has a high Known methods for forming the insulating film include heat treatment at high temperature or laser light treatment.

[0005] In recent years, oxide semiconductors have been attracting attention. Oxide semiconductors can be produced by a method such as sputtering. Since film formation can be performed using Furthermore, a transistor using an oxide semiconductor has high field-effect mobility. Therefore, it is possible to realize a highly functional display device in which the drive circuit and pixel circuit are formed on the same substrate. In addition, some of the production facilities for amorphous silicon transistors can be improved and used. This also has the advantage of reducing capital investment.

[0006] Incidentally, a transistor including an oxide semiconductor has a very low leakage current in a non-conducting state. For example, it is known that transistors using oxide semiconductors have low leakage current. A low-power CPU that uses current has been disclosed (see Patent Document 1). When a transistor using an oxide semiconductor is applied to an integrated circuit such as a CPU, It is desirable to reduce the size of the transistor and increase its integration density.

[0007] As semiconductor devices become more highly integrated, the wiring and electrodes are overlapped, resulting in the formation of The influence of the parasitic capacitance generated by the oxide semiconductor may become unnegligible. A transistor with a gate structure is disclosed in Patent Document 2. By injecting electrons from the conductor electrode into the semiconductor, the offset region is effectively eliminated. It is disclosed that a transistor having excellent electrical characteristics can be obtained. By using the technology disclosed in Patent Document 3, the problem of overlapping wiring, electrodes, etc. can be solved. This can reduce the parasitic capacitance formed by the resistor.

[0008] In addition, by forming a well-type potential in the active layer made of semiconductor, a high electric field effect It has been disclosed that a transistor having high mobility can be obtained (see Patent Document 4). [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-278115 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-22507 [Patent Document 4] Japanese Patent Application Laid-Open No. 2012-59860 Summary of the Invention [Problem to be solved by the invention]

[0010] It is an object of the present invention to provide a semiconductor device with low parasitic capacitance. Another object of the present invention is to provide a semiconductor device having excellent frequency characteristics. Another object of the present invention is to provide a semiconductor device with a high degree of integration. Another object is to provide a robust semiconductor device. An object of the present invention is to provide a novel semiconductor device.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] (1) One aspect of the present invention is a semiconductor device including a first conductor, a second conductor, a third conductor, and a fourth conductor. , a fifth conductor, a sixth conductor, a first insulator, a second insulator, and a third insulator. a semiconductor device including a fourth insulator, a fifth insulator, and an oxide semiconductor, The first insulator has a region in contact with the upper surface of the first conductor and a region in contact with the upper surface of the second conductor. , the second insulator has a region in contact with the top surface of the first insulator, and the oxide semiconductor has The third insulator has a region in contact with the top surface of the oxide semiconductor. the third conductor has a region in contact with the top surface of the third insulator, and the fourth insulator a region in contact with the top surface of the third conductor, a region in contact with the side surface of the third insulator, and an oxide semiconductor a region in contact with the upper surface of the first insulator, and a region in contact with the upper surface of the second insulator; The fourth conductor has a region in contact with the top surface of the oxide semiconductor. the fifth conductor has a region in contact with the top surface of the oxide semiconductor; has a region in contact with the top surface of the fourth insulator, and the first conductor is in contact with the first insulator and the second a region where the first conductor and the oxide semiconductor overlap with each other with the insulator therebetween; The third conductor and the oxide semiconductor are overlapped with each other through the third insulator. a second conductor is connected to the second conductor through the first insulator and the fourth insulator; and the sixth conductor overlap each other.

[0013] (2) Alternatively, in one embodiment of the present invention, the oxide semiconductor has a first region in contact with the third insulator and a fourth region in contact with the third insulator. a second region and a third region in contact with the insulator, The region has a region having a lower resistance than the first region, and the fourth conductor has a region adjacent to the second region. The semiconductor device according to (1), wherein the fifth conductor has a region in contact with the third region. is.

[0014] (3) Alternatively, in one embodiment of the present invention, the oxide semiconductor may include a first oxide semiconductor and a second oxide semiconductor. the second oxide semiconductor has a region in contact with a top surface of the first oxide semiconductor; In a region where the fourth conductor and the oxide semiconductor overlap each other, the first oxide semiconductor is The semiconductor device according to (1) or (2) has a higher conductivity than the oxide semiconductor. .

[0015] (4) Alternatively, in one embodiment of the present invention, the oxide semiconductor may include a first oxide semiconductor and a second oxide semiconductor. the second oxide semiconductor has a region in contact with a top surface of the first oxide semiconductor; In a region where the fourth conductor and the oxide semiconductor overlap each other, the second oxide semiconductor is The semiconductor device according to (1) or (2) has a higher conductivity than the oxide semiconductor. .

[0016] (5) Alternatively, in one embodiment of the present invention, the oxide semiconductor may include a first oxide semiconductor and a second oxide semiconductor. and a third oxide semiconductor, the second oxide semiconductor being disposed on the first oxide semiconductor. the third oxide semiconductor has a region in contact with the top surface of the second oxide semiconductor; and a second oxide semiconductor is formed in a region where the fourth conductor and the oxide semiconductor overlap each other. has a higher electrical conductivity than the first oxide semiconductor and the third oxide semiconductor (1); is the semiconductor device described in (2).

[0017] (6) Alternatively, in one embodiment of the present invention, the third insulator has a shape that protrudes further than the third conductor. The semiconductor device according to any one of (1) to (5) above.

[0018] (7) Alternatively, in one aspect of the present invention, the third insulator has a region whose end section has an arc-shaped cross section. The semiconductor device according to (6) above.

[0019] (8) Alternatively, in one embodiment of the present invention, the third conductor has a first conductive layer and a second conductive layer. The second conductive layer has a region in contact with the top surface of the first conductive layer, and the first conductive layer has a region in contact with the top surface of the second conductive layer. The semiconductor device according to any one of (1) to (7), wherein the conductive layer has a shape that protrudes from the conductive layer. be.

[0020] (9) Alternatively, in one embodiment of the present invention, the oxide semiconductor includes indium and zinc (1) to (3). The semiconductor device according to (8) is a semiconductor device.

[0021] (10) Another embodiment of the present invention is a semiconductor device comprising: a semiconductor device according to any one of (1) to (9); and a main board.

[0022] (11) Another embodiment of the present invention is the semiconductor device according to any one of (1) to (9). , (10) The module according to (10), and a speaker, an operation key, or a battery. It is an electronic device.

[0023] In the semiconductor device according to one embodiment of the present invention, the oxide semiconductor may be replaced with another semiconductor. It's okay. [Effects of the Invention]

[0024] It is possible to provide a transistor with small parasitic capacitance or excellent switching characteristics. Alternatively, a transistor with a small current when non-conducting can be provided. Alternatively, a transistor with a large current when conducting can be provided. Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a semiconductor device with low parasitic capacitance can be provided. It is possible to provide a semiconductor device having excellent frequency characteristics. Alternatively, a highly integrated semiconductor device can be provided. Alternatively, a robust semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided. It is possible.

[0025] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 17]FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A and 1B are a cross-sectional view and a band diagram of a transistor according to one embodiment of the present invention. [Figure 19] 1A and 1B are a top view and a circuit diagram of a display device according to one embodiment of the present invention. [Figure 20] FIG. 1 is a circuit diagram of a display device according to one embodiment of the present invention. [Figure 21] FIG. 1 is a circuit diagram of a display device according to one embodiment of the present invention. [Figure 22] FIG. 1 is a circuit diagram of a display device according to one embodiment of the present invention. [Figure 23] FIG. 1 is a circuit diagram of a display device according to one embodiment of the present invention. [Figure 24] FIG. 1 is a cross-sectional view of a display device according to one embodiment of the present invention. [Figure 25] 1A and 1B illustrate a display module according to one embodiment of the present invention. [Figure 26] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a circuit diagram of a memory device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a block diagram of an RF tag according to an embodiment of the present invention. [Figure 29] 1A and 1B are diagrams illustrating examples of use of an RF tag according to one embodiment of the present invention. [Figure 30] FIG. 2 is a block diagram illustrating a CPU according to an embodiment of the present invention. [Figure 31] FIG. 10 is a circuit diagram of a memory element according to one embodiment of the present invention. [Figure 32] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 33] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 34] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 35] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 36] 10A and 10B illustrate structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 37]Cross-sectional TEM image of the sample and flowchart. [Figure 38] FIG. 10 is a diagram illustrating the temperature dependence of resistivity. [Figure 39] Schematic diagram illustrating a film formation model of CAAC-OS, and cross-sectional views of a pellet and CAAC-OS. [Figure 40] Schematic diagram explaining the film formation model of nc-OS and a diagram showing the pellet. [Figure 41] FIG. [Figure 42] 10A and 10B are diagrams illustrating the force applied to a pellet on a surface to be formed. [Figure 43] 10A and 10B are diagrams illustrating the movement of pellets on a surface to be formed. [Figure 44] A diagram explaining the InGaZnO4 crystal. [Figure 45] A diagram explaining the structure of InGaZnO4 before the atoms collide. [Figure 46] A diagram explaining the structure of InGaZnO4 after the atoms collide. [Figure 47] A diagram explaining the trajectories of atoms after they collide. [Figure 48] Cross-sectional HAADF-STEM images of the CAAC-OS and target. [Figure 49] Electron diffraction pattern of CAAC-OS. [Figure 50] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. DETAILED DESCRIPTION OF THE INVENTION

[0027] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and details can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the structure of the invention using the drawings, the same symbols are used in different The hatch pattern is used in common between drawings. However, there are cases where no particular symbol is attached.

[0028] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where this is the case.

[0029] Also, voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. .

[0030] The ordinal numbers such as 1st and 2nd are used for convenience and do not represent the order of processes or stacking. Therefore, for example, "the first" should not be replaced with "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. , the ordinal numbers used to identify an aspect of the present invention may not match.

[0031] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be written as "insulator." In addition, the boundary between "semiconductor" and "insulator" is vague, and Therefore, the term "semiconductor" as used herein may be used interchangeably with "insulator." Similarly, the term "insulator" used herein can be interpreted as "semiconductor." " can sometimes be rephrased as ".

[0032] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is vague, and Therefore, the term "semiconductor" as used herein may be used interchangeably with "conductor." Similarly, the term "conductor" used in this specification can be used to refer to a "semiconductor." " can sometimes be rephrased as ".

[0033] The impurities in a semiconductor refer to, for example, substances other than the main components that make up the semiconductor. For example, the concentration Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the body and carrier mobility The semiconductor may become an oxide semiconductor, and the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1 and Group 2. These include elements, group 14 elements, group 15 elements, and transition metals other than the main component, in particular, for example, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies are formed due to the inclusion of impurities such as hydrogen. Also, if the semiconductor is silicon, impurities that change the properties of the semiconductor may be generated. Examples of the elements include oxygen, elements of Group 1 except for hydrogen, elements of Group 2, elements of Group 13, elements of Group 15, Group elements, etc.

[0034] In the following embodiments, the semiconductor is an oxide semiconductor. However, the present invention is not limited to this. For example, semiconductors may have a polycrystalline structure, a single crystalline structure, etc. Alternatively, a material having strain such as strained silicon may be used. Alternatively, a semiconductor such as a high electron mobility transistor (HEMT) may be used as the semiconductor. : Applicable to High Electron Mobility Transistor Gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, Indium phosphide, silicon germanium, etc. may also be used. This makes it possible to provide a transistor suitable for high-speed operation.

[0035] In this specification, when it is stated that A has a region of concentration B, for example, If the concentration in the entire depth direction in the region where A is present is B, then the concentration in the depth direction in the region where A is present is If the average concentration is B, and the median concentration in the depth direction in a region of A is B, In this case, if the maximum concentration in the depth direction in a region where A is present is B, If the minimum concentration in the depth direction is B, the concentration in the depth direction in a region of A is When the value is B, the concentration in the area where the most likely value of A itself can be obtained by measurement is B. Including cases where

[0036] In this specification, A has an area of size B, length B, thickness B, width B or distance B. When describing "to be" in a certain area of A, for example, the overall size, length, thickness, width, or the size, length, thickness, width, or distance of an area of A if the distance is B If the average value of is B, then the size, length, thickness, width, or distance of a certain area of A If the median is B, then the maximum size, length, thickness, width, or distance in a region of A The minimum size, length, thickness, width, or distance in a region of A when the maximum value is B If the value is B, then the convergence value of size, length, thickness, width, or distance in a region of A When B is the size, length, and thickness of the area where the value of A itself can be obtained by measurement This includes cases where the length, width, or distance is B.

[0037] In this specification, the deposition of an insulator, semiconductor, conductor, etc. is referred to as "film deposition" unless otherwise specified. Except for sputtering and chemical vapor deposition (CVD), position method, molecular beam epitaxy (MBE) Epitaxy or Pulsed Laser Deposition (PLD) position) method, Atomic Layer Deposition method (ALD) This can be done using the ion method or the like.

[0038] The CVD method is a plasma CVD (PECVD) method that uses plasma. enhanced CVD method, thermal CVD (TCVD) Furthermore, depending on the source gas used, it can be classified into metal CVD (MCVD:Met) and other methods. al CVD) method, Metal Organic CVD (MOCVD) method ) can be divided into

[0039] The plasma CVD method produces high-quality films at relatively low temperatures. The thermal CVD method uses plasma. Therefore, no plasma damage occurs and a film with few defects can be obtained.

[0040] The CVD method allows the composition of the resulting film to be controlled by adjusting the flow rate ratio of the source gases. For example, in the MCVD and MOCVD methods, a film of any composition can be produced by adjusting the flow rate ratio of the source gases. Furthermore, for example, in the MCVD method and the MOCVD method, By changing the flow rate ratio of the source gases, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to film deposition, the time required for deposition is shortened by the time required for transportation and pressure adjustment. Therefore, the productivity of the transistor can be improved.

[0041] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source voltage) in the region where the The distance between the source and drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is any one value, maximum value, The minimum or average value.

[0042] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the current flows and the gate electrode overlap, or the region where the channel is formed. The length of the part where the source and drain face each other in the region. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of each transistor may not be determined to be a single value. In the document, the channel width is defined as any one value, maximum value, or The minimum or average value.

[0043] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in a transistor with a fine, three-dimensional structure, The ratio of the channel region formed on the side of the semiconductor to the channel region formed In this case, the apparent channel width shown in the top view may be larger. The effective channel width where the channel is actually formed is larger than the actual channel width.

[0044] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0045] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length of the overlapping area where the source and drain face each other The channel width of the In this specification, it is sometimes referred to as "channel width." In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referred to as a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and enclosure The width of the embedded channel can be determined by taking a cross-sectional TEM image and analyzing the image. The value can be determined by

[0046] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0047] In this specification, when it is stated that A has a shape that protrudes more than B, it is not limited to a top view. In the cross-sectional view, at least one end of A is located outside at least one end of B. Therefore, it may be stated that A has a shape that protrudes more than B. For example, in the top view, one end of A is outside one end of B. It can be read as having.

[0048] <Semiconductor device> A semiconductor device according to one embodiment of the present invention will be described below with reference to drawings.

[0049] FIG. 1 is a cross-sectional view of a semiconductor device including a transistor 150 and a capacitor 160. .

[0050] The semiconductor device shown in FIG. 1 includes an insulator 101 on a substrate 100 and a conductor 10 4a1, the conductor 104a2 on the conductor 104a1, and the conductor 104b on the insulator 101. 1, the conductor 104b2 on the conductor 104b1, on the insulator 101, on the conductor 104a1 , the insulator 102a on the conductor 104a2, the conductor 104b1, and the conductor 104b2 , an insulator 102b on the insulator 102a, a semiconductor 106a on the insulator 102b, and a semiconductor A semiconductor 106b on the body 106a, an insulator 112 on the semiconductor 106b, and an insulator 112 on the The conductor 114a, the conductor 114b on the conductor 114a, the insulator 102a, the insulator 102b, on the semiconductor 106a, on the semiconductor 106b, on the insulator 112, and on the conductor 114a and the insulator 108 on the conductor 114b, the insulator 118 on the insulator 108, and the semiconductor 1 106b, on the insulator 108, on the conductor 116a1 on the insulator 118, and on the semiconductor 106b, Conductor 116b1 on insulator 108 and insulator 118, and conductor 116a1 on conductor 116b1. 16a2, conductor 116b2 on conductor 116b1, and conductor 116 on insulator 118. a1, conductor 116a2, conductor 116b1, and conductor 116b2. 28 and has.

[0051] The insulator 101 prevents impurities from being mixed into the channel formation region of the transistor 150. For example, the conductor 104a2 and the conductor 104b2 may have a function of suppressing the When the semiconductor 106a or the semiconductor 106b has impurities such as copper, the insulating The body 101 may have a function of blocking copper and the like.

[0052] The stack of the conductor 104a1 and the conductor 104a2 is collectively referred to as the conductor 104a. The region 104 a may have a region that functions as the gate electrode of the transistor 150 . The conductor 104a has a function of blocking light from a channel formation region of the transistor 150 and the like. There may be cases where this is the case.

[0053] The stack of the conductor 104b1 and the conductor 104b2 is collectively referred to as the conductor 104b. The region 104b may have a region that functions as one of the electrodes of the capacitor 160. The conductor 104b may have a function of shielding the semiconductor device from light.

[0054] The conductor 104a1 and the conductor 104b1 may be in the same layer. In this case, the process can be shortened compared to when the conductor 104a1 and the conductor 104b1 are not in the same layer. In addition, the conductor 104a2 and the conductor 104b2 can be formed in the same layer. In this case, the conductor 104a2 and the conductor 104b2 may be formed in the same layer. The process can be shortened compared to when no such process is used.

[0055] The conductor 104a1 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Smoke, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sm, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductors containing one or more types of tungsten may be used in a single layer or a multilayer structure. Conductors that may be gold or compounds, aluminum-containing conductors, copper- and titanium-containing conductors, Conductors containing copper and manganese, conductors containing indium, tin and oxygen, titanium and The conductor 104a1 may be a conductor containing titanium or nitrogen. It is preferable to use

[0056] The conductor 104b1 may be selected from the conductors shown as the conductor 104a1. It is particularly preferable to use the same type of conductor as the conductor 104a1. .

[0057] The conductor 104a2 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Smoke, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sm, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductors containing one or more types of tungsten may be used in a single layer or a multilayer structure. Conductors that may be gold or compounds, aluminum-containing conductors, copper- and titanium-containing conductors, Conductors containing copper and manganese, conductors containing indium, tin and oxygen, titanium and Conductors containing copper and nitrogen may also be used. It is preferable to have one.

[0058] The conductor 104b2 may be selected from the conductors shown as the conductor 104a2. It is particularly preferable to use the same type of conductor as the conductor 104a2. .

[0059] The insulator 102a and the insulator 102b are collectively referred to as the insulator 102. It may have a region that acts as a gate insulator for the transistor 150. The insulating layer 102a prevents impurities from entering the channel forming region of the transistor 150. For example, the conductor 104a2 may have a function of forming a semiconductor 106a such as copper. Or, when the semiconductor 106b has impurities, the insulator 102a blocks copper or the like. The insulator 102a may have a function of blocking the capacitance element 160. They may have regions that function in conjunction with one another.

[0060] The insulator 102b may have an opening in the area where it overlaps with the conductor 104b. By providing the opening in 02b, the capacitance of the capacitor 160 can be increased.

[0061] The insulator 102a may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Nitride, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, di a single layer of an insulator containing zinc, lanthanum, neodymium, hafnium or tantalum; The insulator 102a may be made of silicon nitride or silicon oxynitride. It is preferable to use a

[0062] The insulator 102b may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Nitride, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, di a single layer of an insulator containing zinc, lanthanum, neodymium, hafnium or tantalum; Alternatively, a laminated layer may be used. The insulator 102b is preferably silicon oxide or silicon oxynitride. It is preferable to use a

[0063] The semiconductor 106a and the semiconductor 106b are collectively referred to as the semiconductor 106. It may have a region that functions as a channel forming region of the transistor 150 .

[0064] The semiconductor 106a is made of silicon, germanium, or the like, having a polycrystalline or single-crystalline structure. Alternatively, a semiconductor having strain such as strained silicon may be used. Conductor 106a may be gallium arsenide, aluminum gallium arsenide, or gallium arsenide, which are applicable to HEMTs. Indium gallium nitride, gallium nitride, indium phosphide, silicon germanium, etc. Alternatively, an oxide semiconductor may be used as the semiconductor 106a. It is particularly preferable to use an oxide semiconductor for 6a.

[0065] The semiconductor 106b is made of silicon, germanium, or the like, having a polycrystalline or single-crystalline structure. Alternatively, a semiconductor having strain such as strained silicon may be used. Conductor 106b may be gallium arsenide, aluminum gallium arsenide, or gallium arsenide, which are applicable to HEMTs. Indium gallium nitride, gallium nitride, indium phosphide, silicon germanium, etc. Alternatively, an oxide semiconductor may be used as the semiconductor 106b. It is particularly preferable to use an oxide semiconductor for 6b.

[0066] For details of oxide semiconductors that can be used for the semiconductors 106a and 106b, see This will be discussed later.

[0067] The semiconductor 106a is formed in a region that does not overlap with the insulator 112, the conductor 114a, the conductor 114b, etc. The semiconductor 106b has an insulator 112 and an insulator 113. The region 107a2 and the region 107b2 that do not overlap with the conductor 114a, the conductor 114b, etc. The region 107a1 and the region 107b1 are formed by the insulator 112 of the semiconductor 106a, the conductor 112 of the semiconductor 106a, and the This region has a lower resistance than the region overlapping with the conductor 114a, the conductor 114b, etc. The region 107a2 and the region 107b2 are formed by the insulator 112 and the conductor 114a of the semiconductor 106b. The area has a lower resistance than the area overlapping with the conductor 114b. can also be called a region of high carrier density.

[0068] When the semiconductor 106a and the semiconductor 106b are oxide semiconductors, the carrier generation source is water. For details on the carrier generation source of oxide semiconductors, will be discussed later.

[0069] The area 107a1 and the area 107a2 are collectively referred to as the area 107a. Area 107b1 and area 107b2 are collectively referred to as area 107b. 07b has regions that function as the source and drain regions of transistor 150. This may occur.

[0070] Insulator 112 may have a region that serves as the gate insulator for transistor 150. The insulator 112 may have a shape that protrudes beyond the conductor 114a. In addition, the insulator 112 may have a region where the cross section of the end portion is an arc. By having such a shape, the insulators, conductors, etc. arranged above the insulator 112 can be easily removed. In some cases, it may be possible to suppress the shape defects.

[0071] The insulator 112 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. The insulator 112 may be made of silicon oxide or silicon oxynitride. It is preferable to use it.

[0072] When the semiconductor 106 is an oxide semiconductor, an insulating layer having a region in contact with the semiconductor 106 The body 102b and / or the insulator 112 have an energy level above the top of the valence band of the oxide semiconductor. An insulator with a low level density between the energy (Evos) and the energy (Ecos) of the lower edge of the conduction band For example, when the level traps electrons, the threshold voltage of the transistor This causes the voltage to fluctuate in the positive direction.

[0073] For example, nitrogen oxide (NO X ), among which nitric oxide (NO ) and nitrogen dioxide (NO2) may form a level between Evos and Ecos. Therefore, in order to obtain a transistor with stable electrical characteristics, the insulator 102 b) or / and when the insulator 112 is preferably made of silicon oxide with low nitrogen oxide content, Although silicon oxide will be described below, silicon oxynitride The same applies to silicon oxide with a low nitrogen oxide content. In Thermal Desorption Spectroscopy (TDS), nitrogen In some cases, the amount of ammonia released may be greater than the amount of oxide released. Output is 1 x 10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The following may occur: The amount of ammonia released is higher when the surface temperature of the membrane is between 50°C and 650°C, or between 50°C and 5 The amount released is determined by heating at 50°C or below.

[0074] The insulator 102b and / or the insulator 112 are made of an insulator that releases oxygen when heated. It is preferable to do so.

[0075] Here, the insulators that release oxygen when heated are those that, according to TDS analysis, are those that are heated to 100°C or higher and 70°C or lower. 1 x 10 in the range of surface temperatures below 0°C or between 100°C and 500°C18 atoms / cm 3 That's it, 1×10 19 atoms / cm 3 or more than 1×10 20 atoms / cm 3 It may release more than this amount of oxygen (calculated as the number of oxygen atoms).

[0076] Here, a method for measuring the amount of released oxygen using TDS analysis will be described below.

[0077] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated based on the integral value of the ion intensity of the released gas. Then, by comparison with a standard sample, the total amount of gas released can be calculated.

[0078] For example, the TDS analysis results of a silicon substrate containing a predetermined density of hydrogen as a standard sample, and From the TDS analysis results of the measurement sample, the amount of released oxygen molecules (N O2 ) is expressed as Here, the gas detected with a mass-to-charge ratio of 32 obtained by TDS analysis is We assume that all of the carbon atoms are derived from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but The possibility is low and is not considered here. The abundance ratio of oxygen atoms and oxygen molecules containing oxygen atoms with mass number 18 in nature is The rate is so small that it is not taken into consideration.

[0079] N O2 =N H2 / S H2 ×S O2 ×α

[0080] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Laid-Open Publication No. 6-275697. Using a thermal desorption analyzer EMD-WA1000S / W manufactured by Gakushugaku Co., Ltd., For example, 1×10 16 atoms / cm 2 Measurements are performed using a silicon substrate containing hydrogen atoms. .

[0081] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0082] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount released.

[0083] Alternatively, an insulator that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 Insulators containing peroxide radicals are sensitive to electron spin resonance (ESR) Electron Spin Resonance (G-value) is inconsistent with the g value of 2.01. It may also have a signal of the same name.

[0084] Alternatively, an insulator containing excess oxygen can be formed by using silicon oxide (SiO X (X>2) Silicon oxide (SiO X (X>2)) is the number of silicon atoms It contains more than twice as many oxygen atoms per unit volume as silicon atoms per unit volume. The number of electrons and oxygen atoms was measured by Rutherford backscattering (RBS). The values were measured by backscattering spectrometry.

[0085] When silicon oxide contains NO2, the g value is 2.03 at ESR below 100K. The first absorption line has a g value between 7 and 2.039, and the second absorption line has a g value between 2.001 and 2.003. A signal with a third absorption line and a g value between 1.964 and 1.966 was observed. The distance between the first absorption line and the second absorption line, and the The spacing between the first and third absorption lines is about 5 mT in X-band ESR measurements. Therefore, silicon oxide with a low nitrogen oxide content has a spin density of 1×10 18 spins / cm 3 Less than or equal to 1 x 10 17 spins / cm 3 More than 1×10 18 spins / cm 3 is less than.

[0086] In addition, silicon oxide with low nitrogen oxide content can be analyzed by secondary ion mass spectrometry (SIMS). The nitrogen concentration measured by Nitrogen Ion Mass Spectrometry (NIM) is 6 x10 20 atoms / cm 3 The following is the result.

[0087] The conductor 114a and the conductor 114b are collectively referred to as the conductor 114. It may have a region that functions as the gate electrode of the transistor 150. The light emitting element 114 may have a function of blocking light from a channel forming region of the transistor 150. do.

[0088] The conductor 114a may have a shape that protrudes further than the conductor 114b. The conductor 114b may have a steeper shape than the conductor 114a. The conductor 114a and the conductor 14b may have a region where the cross section of the end portion is an arc. By having such a shape, the conductor 114b is more resistant to the electric current than the conductor 114a and the conductor 114b. This may prevent defects in the shape of insulators, conductors, etc. that are placed on top of the substrate.

[0089] The conductor 114a may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Aluminum, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and titanium A conductor containing one or more kinds of tungsten may be used in a single layer or a multilayer. Conductors containing aluminum, conductors containing copper and titanium, and copper and manganese-containing conductors, indium, tin and oxygen-containing conductors, titanium and A conductor containing nitrogen may also be used. The conductor 114a is particularly a conductor containing tantalum nitride. It is preferable to use the body.

[0090] The conductor 114b may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Aluminum, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and titanium A conductor containing one or more kinds of tungsten may be used in a single layer or a multilayer. Conductors containing aluminum, conductors containing copper and titanium, and copper and manganese-containing conductors, indium, tin and oxygen-containing conductors, titanium and Conductors containing nitrogen may also be used. The conductor 114b is particularly a conductor containing tungsten. It is preferable to use the body.

[0091] The insulator 108 prevents impurities from being mixed into the channel formation region of the transistor 150. For example, the conductor 116a2 and the conductor 116b2 may have a function of suppressing the When the semiconductor 106a or the semiconductor 106b has impurities such as copper, the insulating The insulator 108 may have a function of blocking copper or the like. It may have a region that acts as a dielectric for the element 160 .

[0092] The insulator 108 has an opening that reaches the semiconductor 106. The opening is disposed so as to overlap with the region 107a of the semiconductor 106. It may also be arranged to overlap with the area 107b.

[0093] The insulator 108 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. The insulator 108 may be made of silicon nitride or silicon nitride oxide. It is preferable to use it.

[0094] As the insulator 108, an insulator having a low level density between Evos and Ecos is used. It's okay.

[0095] Insulator 118 may have regions that function as interlayer insulators for transistor 150. For example, by providing the insulator 118, the transistor 150 can be electrically connected to the wirings (conductors). ) can reduce the parasitic capacitance.

[0096] The insulator 118 has an opening at a position that overlaps with the opening of the insulator 108. The opening is disposed so as to overlap the region 107a of the semiconductor 106. The opening may also be arranged to overlap the region 107b of the semiconductor 106. The insulator 118 may have an opening in the area where it overlaps with the conductor 104b. The capacitance of the capacitor 160 is increased by providing an opening in the region overlapping with the capacitor 104b. It is possible.

[0097] The insulator 118 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. The insulator 118 may be made of silicon oxide or silicon oxynitride. It is preferable to use it.

[0098] The conductor 116a1 and the conductor 116a2 are collectively referred to as the conductor 116a. The conductor 116b1 and the conductor 116b2 are collectively referred to as the conductor 116b. The conductor 116a and the conductor 116c2 are collectively referred to as the conductor 116c. Body 116b is a region that functions as the source and drain electrodes of transistor 150. The conductor 116a and the conductor 116b may have a The conductor 116c may have a function of blocking light from a channel forming region of the capacitor 116. The conductor 116c may have a region that functions as the other electrode of the element 160. The light emitting element may have a function of shading the semiconductor device from light.

[0099] The conductor 116a1, the conductor 116b1, and the conductor 116c1 are in the same layer. In this case, the conductor 116a1, the conductor 116b1, and the conductor 116c1 The process can be shortened compared to when the conductive layer 1 and the conductive layer 2 are not the same layer. The conductor 16a2, the conductor 116b2, and the conductor 116c2 may be in the same layer. In this case, the conductor 116a2, the conductor 116b2, and the conductor 116c2 are in the same layer. The process can be shortened compared to when no such process is used.

[0100] The conductor 116a1 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Smoke, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sm, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductors containing one or more types of tungsten may be used in a single layer or a multilayer structure. Conductors that may be gold or compounds, aluminum-containing conductors, copper- and titanium-containing conductors, Conductors containing copper and manganese, conductors containing indium, tin and oxygen, titanium and The conductor 116a1 may be, for example, a conductor containing titanium nitride or titanium nitride. It is preferable to use a conductor containing tantalum or tungsten.

[0101] The conductor 116b1 may be selected from the conductors shown as the conductor 116a1. It is particularly preferable to use the same type of conductor as the conductor 116a1 for the conductor 116b1. The conductor 116c1 is selected from the conductors shown as the conductor 116a1. The conductor 116c1 may have the same structure as the conductor 116a1 or the conductor 116b1. It is preferable to use a type of conductor.

[0102] The conductor 116a2 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Smoke, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sm, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductors containing one or more types of tungsten may be used in a single layer or a multilayer structure. Conductors that may be gold or compounds, aluminum-containing conductors, copper- and titanium-containing conductors, Conductors containing copper and manganese, conductors containing indium, tin and oxygen, titanium and Conductors containing copper and nitrogen may also be used. It is preferable to have one.

[0103] The conductor 116b2 may be selected from the conductors shown as the conductor 116a2. It is particularly preferable to use the same type of conductor as the conductor 116a2 for the conductor 116b2. The conductor 116c2 is selected from the conductors shown as the conductor 116a2. The conductor 116c2 may have the same structure as the conductor 116a2 or the conductor 116b2. It is preferable to use two kinds of conductors. When a conductor containing copper is used as the conductor 116c2, the conductor 116a1 and the conductor 11 In some cases, the semiconductor 106 may not be provided. The conductors 116a2 and 116b2, which are conductors containing copper, may be in direct contact with each other. No.

[0104] The insulator 128 prevents impurities from being mixed into the channel forming region of the transistor 150. It may have an inhibitory function.

[0105] The insulator 128 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. The insulator 128 may be made of silicon nitride or silicon oxynitride. It is preferable to use it.

[0106] The substrate 100 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates. There are various substrates, such as zirconia substrates (yttria-stabilized zirconia substrates), and resin substrates. The substrate may be, for example, a single semiconductor substrate such as silicon or germanium, or a silicon carbide substrate. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates such as silicon. A semiconductor substrate having such a structure, for example, an SOI (Silicon On Insulator) substrate Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. The substrates include a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, and There are substrates provided with an edge, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, a substrate having an element provided thereon may be used. Examples of the elements include capacitance elements, resistance elements, switch elements, light-emitting elements, and memory elements.

[0107] A flexible substrate may also be used as the substrate 100. Alternatively, a sheet, film, or foil woven with the material may be used. In addition, the substrate 100 may return to its original shape when the bending or pulling is stopped. Alternatively, the substrate 100 may have a property of not returning to its original shape. The thickness is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less. More preferably, the thickness is 15 μm or more and 300 μm or less. The device can be made lighter. In addition, by making the substrate 100 thinner, it is possible to use glass or the like. It may have elasticity even after bending or pulling, or it may return to its original shape when bending or pulling is stopped. Therefore, if the semiconductor device on the substrate 100 is dropped or otherwise damaged, This makes it possible to absorb shocks and the like, and thus to provide a robust semiconductor device.

[0108] The substrate 100, which is a flexible substrate, may be made of, for example, metal, alloy, resin, glass, or The substrate 100, which is a flexible substrate, has a linear expansion coefficient of 1.5. The lower the coefficient of thermal expansion, the more preferable it is because deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×1 0 -5 The resin may be, for example, polyester, poly Olefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, Acrylic, etc. In particular, aramid has a low linear expansion coefficient, making it suitable for flexible substrates. 100 is preferable.

[0109] As a method for providing a transistor on a flexible substrate, a method for providing a transistor on a non-flexible substrate is also available. There is also a method in which after the transistor is fabricated, the transistor is peeled off and transferred to a flexible substrate. In this case, a release layer may be provided on the substrate 100, which is a non-flexible substrate.

[0110] 2A and 2B are a top view and a cross-sectional view of the transistor 150. 2(B) shows a top view of the transistor 150. Also, FIG. 2(B) shows the area between the dashed dotted line A1- A2 is a cross-sectional view of the transistor 150. 1 is a cross-sectional view of the transistor 150 taken along the dashed dotted line A3-A4.

[0111] 1 and the like, a cross section A1-A1 corresponds to a cross section of the transistor 150 in the channel length direction. 2(B). Therefore, regarding FIG. 2(B), For details, please refer to the description of Figure 1.

[0112] In the top view of FIG. 2A, the transistor 150 has a conductor 116a and a conductor 11 6b and the conductor 114 do not overlap with each other, the parasitic capacitance is small. However, when the transistor 150 is connected to the conductors 116a and 116b, 2A, the transistor 114 may have an overlapping region. The conductor 150 is a structure in which the conductors 116a and 116b overlap with the conductor 104. However, the parasitic capacitance is reduced by having multiple insulators between them. However, the area where the conductors 116a and 116b overlap with the conductor 104 is It doesn't matter if you don't have one.

[0113] 2C, which corresponds to a cross-sectional view in the channel width direction, the gate electrode of the transistor 150 and The conductor 114 having the region that functions as a Therefore, the electric field of the conductor 114 is applied to the top and side surfaces of the semiconductor 106. It can be seen that the gate electrode of the transistor 150 The conductor 104 having a region facing the bottom surface of the semiconductor 106 through the insulator 102 is Therefore, the electric field of the conductor 104 does not affect the bottom surface of the semiconductor 106. You can see that this is possible.

[0114] Thus, the transistor 150 has a conductor 114 that functions as a gate electrode and a conductor The body 104 provides a structure in which the top, side and bottom surfaces of the semiconductor 106 are surrounded by an electric field. Such a structure is referred to as a surrounding channel (s-channel) in this specification. This is called a rounded channel structure.

[0115] A transistor with an s-channel structure has a channel in the entire semiconductor (bulk). Therefore, a transistor having an s-channel structure may be formed as follows: A large current can be passed between the source and drain, and the current (on-current) when conducting can be increased. In addition, a transistor having an s-channel structure can be formed by the electric field of the gate electrode. Since the influence of the Therefore, a transistor with an s-channel structure has a subthreshold The swing value (also called the S value) can be reduced. Also, a small S value reduces the off-state current. The flow can also be reduced.

[0116] <Method for manufacturing semiconductor device> Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described.

[0117] First, a substrate 100 is prepared.

[0118] Next, the insulator 101 is deposited.

[0119] Next, a conductor that will become the conductor 104a1 and the conductor 104b1 is formed.

[0120] Next, a conductor that will become the conductor 104a2 and the conductor 104b2 is formed.

[0121] Next, the laminated conductors are processed by a lithography process or the like to form the conductors 104a. Conductor 104a having conductors 104b1 and 104b2, and conductors 104b1 and 104b3. The conductor 104b is formed by the conductor 104b2 (see FIG. 3). The process is shortened by forming the conductive material 104a and the conductive material 104b through the same process. That is, the productivity of the semiconductor device can be increased.

[0122] Next, the insulator 102a is deposited.

[0123] Next, an insulator 132 is formed (see FIG. 4). The insulator 132 will be formed as an insulator through a subsequent process. Since this is the insulator that becomes 102b, the description of the insulator 102b is referred to.

[0124] Silicon oxide with a low content of nitrogen oxide can be obtained by, for example, using the PECVD method at a substrate temperature of The temperature is set to 220°C or higher, 280°C or higher, or 350°C or higher, and silane and dioxide are added to the raw material gas. The film can be formed by using nitrogen.

[0125] Next, a protective film 113 is formed. The protective film 113 may be made of, for example, the above-mentioned conductor or the above-mentioned insulator. The protective film 113 may be made of an insulator or the aforementioned semiconductor. The protective film 113 is made of, for example, silicon oxide or silicon oxynitride. The protective film 113 preferably has a columnar crystal structure. The protective film 113 is preferably a film having a lower oxygen permeability than tungsten. , tantalum nitride is used.

[0126] Next, a process of adding oxygen is carried out from the upper surface side of the protective film 113 (see FIG. 5). The treatment to be performed includes, for example, plasma treatment in an atmosphere containing an oxidizing gas. The oxidizing gas may be, for example, a gas containing oxygen atoms, specifically oxygen gas, nitrous oxide gas, etc. For example, oxygen can be added by using oxygen source gas. Doping is a process in which molecules containing oxygen atoms are ionized. There are two types of doping: doping with mass-separated ions and doping with ions without mass separation. Either method can be used.

[0127] The protective film 113 has the function of blocking oxygen, thereby suppressing the release of added oxygen. While doing so, oxygen can be added to the insulator 132 and / or the insulator 102a. Therefore, the amount of oxygen added is greater when the protective film 113 is provided than when oxygen is added without the protective film 113. When oxygen is added in the insulator 132 or / and the insulator 102a, The amount of oxygen added to the protective film 113 can be increased by the treatment of adding oxygen. It is okay if it is oxidized.

[0128] The protective film 113 has a function of blocking oxygen and is thin enough to prevent oxygen from reaching the lower layer. For example, the protective film 113 may have a thickness of 1 nm or more and 150 nm or less, or 5 The thickness may be set to 100 nm or more.

[0129] By adding oxygen, the insulator 132 and / or the insulator 102a contains excess oxygen. It becomes an insulator.

[0130] Next, the protective film 113 is removed. However, if the protective film 113 is made of an insulator or a semiconductor, In this case, there may be cases where the protective film 113 does not need to be removed.

[0131] Next, the insulator 132 is processed by a lithography process or the like to form the insulator 102b. (See FIG. 6.) The insulator 102b is formed so as to overlap the conductor 104b of the insulator 102a. This is done so that the desired area is exposed.

[0132] Next, a semiconductor film that will become the semiconductor 106a is formed.

[0133] Next, a semiconductor film that will become the semiconductor 106b is formed.

[0134] Next, first heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower. The first heat treatment is preferably performed at a temperature of 300° C. or higher and 500° C. or lower. or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed under an inert gas atmosphere. After heat treatment in the atmosphere, oxidizing gas is added at 10 ppm or more, 1 The heat treatment may be performed in an atmosphere containing 10% or more of ZnO. In order to improve the crystallinity of the semiconductor that will become the semiconductor 106a and the semiconductor that will become the semiconductor 106b, It is also possible to remove impurities such as hydrogen and water.

[0135] Next, the semiconductor layer is processed by a lithography process or the like to form a semiconductor 106a and semiconductor 106b are formed (see FIG. 7).

[0136] Next, an insulator that will become the insulator 112 is formed.

[0137] Next, a conductor that will become the conductor 114a is formed.

[0138] Next, a conductor that will become the conductor 114b is formed.

[0139] Next, the stack of conductors is processed by a lithography process or the like. This is done by etching under conditions where etching of the conductor occurs faster than etching of the underlying conductor. The conductor 114b and the conductor 114a have a shape that protrudes more than the conductor 114b. Complete.

[0140] Next, the insulator that will become the insulator 112 is processed using the conductor 114a or the like as a mask. The insulator 112 is formed so as to protrude beyond the conductor 114a. The upper surface of the body 106 may be etched by 0.1 nm to 5 nm.

[0141] Next, the insulator 112, the conductor 114a, and the conductor 114b are used as a mask to form a semiconductor 106 (See Figure 8.)

[0142] This treatment may involve, for example, doping with an impurity that has the function of increasing the carrier density of the semiconductor 106. When the semiconductor 106 is an oxide semiconductor, the impurities can be For example, boron, carbon, nitrogen, neon, aluminum, phosphorus, argon, manganese, and arsenic The impurities may be one or more selected from the group consisting of fluorine, krypton, xenon, etc. In particular, argon is preferably used. The impurity may be added by a doping method or the like. The treatment may be carried out in an atmosphere containing the above-mentioned elements (e.g., argon). The plasma treatment may be performed by, for example, applying a plasma to the substrate 100 side. It is preferable to apply a self-bias.

[0143] When the oxide semiconductor is subjected to the above-described treatment, oxygen in the oxide semiconductor is released, and oxygen deficiency is formed. Loss (V O It is also called a hydrogen atom.) can be formed. Status (V O H) forms a donor level in the oxide semiconductor, The carrier density of the region can be increased, and the resistance can be reduced. O H is Donna The formation of the -level will be described in detail later.

[0144] In this way, the regions 107a1 and 107b, which are the regions to be processed of the semiconductor 106a, are 1, and the region 107a2 and the region 107b2 which are the regions to be processed of the semiconductor 106b. It is possible to form the region 107a1 and the region 107a2 together (see FIG. 9). The area 107b1 and the area 107b2 are collectively referred to as area 107a. It's called 7b.

[0145] Next, an insulator 138 is formed. The insulator 138 is an insulating material that will become the insulator 108 in a later process. Since it is an insulator, please refer to the description of the insulator 108.

[0146] The insulator 138 is preferably formed by PECVD. The insulator containing hydrogen, particularly silicon nitride containing hydrogen (also referred to as SiNH), is used. By doing so, hydrogen can be added to the regions 107a and 107b. As a result, the hydrogen is contained in the V in the region 107a and the region 107b. O By filling in the donor level Forming a V O H can be efficiently formed. If the element is included, V in the region 107a and the region 107b O Hydrogen is released from H to form V O Even if it becomes V O It can be converted back to H. The formed regions 107a and 107b can stably maintain a low resistance state. That is, the region 107a and the region 107b are used as the source region and the drain region. In this case, the on-state current of the transistor 150 can be increased.

[0147] An oxide semiconductor that has been made conductive in this way can be called an oxide conductor. Oxide semiconductors have a wide energy gap and therefore transmit visible light. On the other hand, an oxide conductor is an oxide semiconductor having a donor level near the conduction band. The influence of absorption due to the donor level is small, and the transparency of the semiconductor to visible light is as high as that of an oxide semiconductor. It has sexuality.

[0148] Here, the temperature dependence of resistivity in an oxide conductor will be explained with reference to FIG. .

[0149] The oxide conductor contained in the sample for which resistivity was measured was a nitride silicon dioxide containing hydrogen. The oxide conductor (OC_SiNH) formed by contacting the silicon, In this case, argon is added to the oxide semiconductor and the oxide semiconductor is brought into contact with silicon nitride containing hydrogen. The oxide conductor (OC_Ar doped + SiNH) or the plasma treatment equipment In the method, argon ions are irradiated using argon plasma, and silicon nitride containing hydrogen is formed. The oxide conductor (OC_Ar plasma + SiNH) was formed by contacting the did.

[0150] The method for preparing a sample containing oxide conductor (OC_SiNH) is as follows. First, a glass substrate After forming a silicon oxynitride layer with a thickness of 400 nm on the substrate by PECVD, oxygen plasma By adding oxygen ions to silicon oxynitride using a silicon dioxide film, oxygen is released by heating. Silicon oxynitride was formed. Next, on the silicon oxynitride that releases oxygen by heating, Sputtering using a sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2 A 100 nm thick In-Ga-Zn oxide was formed by the annealing method, and then heated at 450°C in a nitrogen atmosphere. After heat treatment in a nitrogen atmosphere, it was heat treated in a nitrogen and oxygen mixed gas atmosphere at 450°C. Next, silicon nitride was formed to a thickness of 100 nm by PECVD. The heat treatment was carried out in a mixed gas atmosphere of nitrogen and oxygen.

[0151] The method for preparing a sample containing an oxide conductor (OC_Ar doped+SiNH) is described below. First, a silicon oxynitride film with a thickness of 400 nm was formed on a glass substrate by the PECVD method. Then, oxygen ions are added to the silicon oxynitride using oxygen plasma, and the silicon oxynitride is heated. Next, silicon oxynitride that releases oxygen by heating was formed. A sputtering target with an atomic ratio of In:Ga:Zn=5:5:6 on silicon nitride A 100 nm thick In-Ga-Zn oxide was formed by sputtering using After heat treatment in a nitrogen atmosphere at 450°C, the specimen was heated in a nitrogen and oxygen mixed gas atmosphere at 450°C. Next, the In-Ga-Zn oxide was doped with a doping device at an accelerating voltage. The voltage was 10 kV and the dose was 5 × 10 14 / cm 2 Add argon to In-Ga-Z Oxygen vacancies were formed in the n-oxide. Next, a 100 nm thick silicon nitride film was deposited by PECVD. Next, the substrate was heat-treated at 350° C. in a mixed gas atmosphere of nitrogen and oxygen.

[0152] The preparation method of the sample containing oxide conductor (OC_Ar plasma + SiNH) is shown below. First, a 400 nm thick silicon oxynitride film is formed on a glass substrate by the PECVD method. After that, oxygen plasma is used to form silicon oxynitride, which releases oxygen when heated. Next, a silicon oxynitride film with an atomic ratio of In:G was formed on the silicon oxynitride film, which releases oxygen when heated. By sputtering method using a sputtering target of a:Zn=1:1:1.2 Then, a 100 nm thick In-Ga-Zn oxide was formed and heat-treated in a nitrogen atmosphere at 450°C. After that, the substrate was heat-treated at 450°C in a mixed gas atmosphere of nitrogen and oxygen. In the processing equipment, argon plasma is generated and accelerated argon ions are injected into the In-Ga Oxygen vacancies were created by colliding with ZnO. Next, a 10 mm thick film was formed by PECVD. Next, a silicon nitride film with a thickness of 0 nm was formed in a nitrogen and oxygen mixed gas atmosphere at 350°C. Heat treated.

[0153] Next, the resistivity of each sample was measured and the results are shown in Figure 38. Here, the resistivity was measured using a four-terminal The measurement was performed using the van der Pauw method. In Figure 38, the horizontal axis represents the measurement temperature, and the vertical axis represents the The resistivity is shown. The measurement results for oxide conductor (OC_SiNH) are shown with squares, and the oxide The measurement results for the solid conductor (OC_Ar doped + SiNH) are shown by circles, and the measurement results for the oxide conductor ( The measurement results of OC_Ar plasma+SiNH) are shown by triangles.

[0154] Although not shown, an oxide semiconductor that is not in contact with silicon nitride containing hydrogen has high resistivity. Therefore, it is difficult to measure the resistivity of oxide conductors. It is clear that it is low.

[0155] From Figure 38, the oxide conductor (OC_Ar doped + SiNH) and the oxide conductor (O C_Ar plasma+SiNH) contains oxygen vacancies and hydrogen, resulting in a resistivity It can be seen that the variation of is small. Typically, the resistivity is The fluctuation rate is less than ±20%. Or, at temperatures between 150K and 250K, the resistivity is , the fluctuation rate is less than ±10%. That is, oxide conductors are degenerate semiconductors, and the conduction band minimum It is estimated that the Fermi level is equal to or approximately equal to the oxide conductor. By using it as the source and drain regions of a transistor, the oxide conductor and the source The conductors that function as the source electrode and drain electrode form an ohmic contact, In addition, the contact resistance between the conductor functioning as the drain electrode and the oxide conductor can be reduced. In addition, the resistivity of oxide conductors has low temperature dependence, so the source and drain electrodes The contact resistance between the conductor functioning as a conductive material and the oxide conductor has a small variation and is highly reliable. It is possible to fabricate high-quality transistors.

[0156] Next, an insulator that will become the insulator 148 is formed. Since this is an insulator that becomes the insulator 118 through a process, the description of the insulator 118 is referred to.

[0157] Next, a second heat treatment may be performed. By performing the second heat treatment, the semiconductor 106 Excess oxygen contained in the insulator 102 moves to the semiconductor 106b via the semiconductor 106a. The body 106b is covered with either the semiconductor 106c, the insulator 112, or the insulator 108. Therefore, the outward diffusion of excess oxygen is unlikely to occur. By performing this process, defects (oxygen vacancies) in the semiconductor 106b can be efficiently reduced. The second heat treatment diffuses excess oxygen (oxygen) in the insulator 102 to the semiconductor 106b. For example, the description of the first heat treatment may be referred to. In this case, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference in the heat treatment of 2 is 20°C or more and 150°C or less, preferably 40°C or more and 100°C or less. This prevents excess oxygen (oxygen) from being released from the insulator 102. It is possible.

[0158] Next, the insulator is processed by a lithography process or the like to form the insulator 148. (See FIG. 10.) The insulator 148 is formed so as to overlap the conductor 104b of the insulator 138. This is done so that the desired area is exposed.

[0159] Next, the stack of the insulators 138 and 148 is processed by a lithography process or the like. Thus, a laminate of the insulator 108 and the insulator 118 is formed (see FIG. 11). The formation of the insulating layer 108 and the insulating layer 118 is performed so that the regions 107a and 107b are exposed. conduct.

[0160] Next, conductors to be the conductors 116a1, 116b1, and 116c1 are formed. do.

[0161] Next, conductors to be the conductors 116a2, 116b2, and 116c2 are formed. do.

[0162] Next, the laminated conductors are processed by a lithography process or the like to form the conductors 116a. Conductor 116a having conductor 116b1 and conductor 116a2, conductor 116b1 and conductor 11 conductor 116b having conductor 116c1 and conductor 116c2; In this way, the conductor 116a, the conductor 116b, and the conductor 116c are formed. 116c through the same process, the process can be shortened. That is, the productivity of the semiconductor device can be increased.

[0163] Next, an insulator 128 is deposited (see FIG. 12).

[0164] In the above manner, a semiconductor device including the transistor 150 and the capacitor 160 is fabricated. It can be manufactured.

[0165] <Modification of Semiconductor Device> In FIG. 1 and other figures, the semiconductor 106 of the transistor 150 functions as a channel formation region. and a region 107a having a region that functions as a source region and a drain region. and region 107b. The semiconductor device is not limited to this structure. For example, as shown in FIG. 106, there are further regions 107a and 107b inside the region 107c and the region 10 Alternatively, the structure may include regions 7d, 107e, and 107f.

[0166] The region 107c has a region adjacent to the region 107a. The region 10 overlaps with the insulator 112 but does not overlap with the conductor 114a. The region 107d has a region adjacent to the region 107b. The region 107d is also adjacent to the insulator 112. The region 107e has a region that overlaps with the conductor 114a and does not overlap with the conductor 114b. The region 107e overlaps with the conductor 114a and is adjacent to the conductor 114c. The region 107f has a region that does not overlap with the conductor 114b. The region 107f is adjacent to the region 107d. The region 107f overlaps with the conductor 114a and has a region It has an area that does not overlap with b.

[0167] The region 107c is, for example, an LDD (Lightly Doped Drain) region. The LDD region may have a region that functions as a gate electrode rather than a source or drain region. A region with a low carrier density or / and impurity concentration, and with a higher carrier density than the channel forming region. The region 107c has a high carrier density and / or a high impurity concentration. For example, the offset region may have a region that functions as an offset region. It has a region with the same carrier density and / or impurity concentration as the formation region.

[0168] The region 107d may also include a region that functions as an LDD region. The region 107d may have a region that functions as an offset region, for example. The region 107e may have a region that functions as an LDD region, for example. 7e may have an area that functions as an offset area. For example, region 107f may have a region that functions as an LDD region. For example, the semiconductor 106 may have a region that functions as an offset region. The area where the region 107e and / or the region 107f overlaps with the conductor 114a is The area is called the overlap area.

[0169] At least one of the regions 107c, 107d, 107e, and 107f is an LDD region. having an area that functions as a center area and / or an offset area; Therefore, it is possible to reduce the deterioration caused by the concentration of the drain electric field of the transistor. A highly reliable semiconductor device can be obtained.

[0170] For example, the region 107c and the region 107d function as LDD regions, and the region When the region 107e and the region 107f have regions that function as offset regions, the This is preferable in some cases because it can reduce degradation caused by concentration of the drain electric field of the transistor. do.

[0171] The length of each region functioning as an LDD region in the channel length direction is less than 20%, less than 10%, less than 5%, or less than 2% of the distance between the drain region and the drain region Alternatively, the length of each overlap region in the channel length direction is preferably The length is less than 20%, less than 10%, or less than 5% of the distance between the source region and the drain region. Or, it is preferable that the offset region is less than 2%. The length in the channel length direction is 20% of the distance between the source region and the drain region. Preferably, it is less than 10%, less than 5% or less than 2%.

[0172] 1 and the like, a region that functions as a channel formation region of the transistor 150 is The semiconductor 106 has two layers, a semiconductor 106a and a semiconductor 106b. However, the semiconductor device according to one embodiment of the present invention is not limited to this structure. For example, as shown in FIG. 14, the semiconductor 106 may include a semiconductor 106a, a semiconductor 106b, and a semiconductor 106c. The region 107a may have a three-layer structure of the conductor 106c. The structure has a region 107a1, a region 107a2, and a region 107a3. 7b has a structure including a region 107b1, a region 107b2, and a region 107b3. 15, the semiconductor 106 may have a single layer structure. The region 107a has a single layer structure, and the region 107b has a single layer structure.

[0173] Also, in FIG. 1 and elsewhere, an insulator having a region that functions as a gate insulator for transistor 150 is shown. The structure in which the cross section of the edge of the edge body 112 has a region that is an arc has been described. The semiconductor device according to one aspect of the present invention is not limited to this structure. For example, the semiconductor device shown in FIG. As shown in FIG. 1, the cross section of the end of the insulator 112 does not have a region that is an arc. It's okay.

[0174] Note that the insulator 112, the conductor 114a, and the conductor 114b of the transistor 150 according to one embodiment of the present invention are At least one of the insulators 114b preferably has a tapered angle. The angle θ1 between the top surface of the semiconductor 106 and the side surface of the insulator 112 is less than 90°, 30° It is preferable that the cross section has an angle of 45° to 70° or 85° to 85°. The angle θ2 between the top surface of the insulator 112 and the side surface of the conductor 114a is 90°. Less than 10°, 15° or more and 85° or less, 30° or more and 85° or less, or 4° or more and 85° or less, It is preferable that the conductor 114b has a cross section with an angle of 5° or more and 70° or less. Angle θ between a line approximately parallel to the top surface of the conductor 114a and a line approximately parallel to the side surface of the conductor 114b 3 is less than 90°, or 30° to 85°, or 45° to 70° In addition, if the angle θ1 is smaller than the angle θ2, the coating of the layer to be formed later may be In addition, if the angle θ3 is smaller than the angle θ2, the layer to be formed later may be This is preferable because it increases the coverage of the film.

[0175] <Wiring position> Connections of wirings and the like in a semiconductor device according to one embodiment of the present invention will be described below.

[0176] FIG. 17(A) is a cross-sectional view showing an example of a connection between wirings of a semiconductor device. The conductor 104c is in the same layer as the conductor 104a and / or the conductor 104b. , conductor 116a, conductor 116b and / or conductor 116c, etc. Specifically, the conductor 104c is electrically connected to the conductor 116d. The insulator 102 and the insulator 112 are connected to the conductor 114 through openings formed therein. The conductor 116d has a region in contact with the conductor 115a, which is a single layer, and the conductor 116d has a region in contact with the insulator 108 and It is only necessary that the insulator 118 has a region in contact with the conductor 115a through an opening provided in the insulator 118.

[0177] The openings provided in the insulator 102 and the insulator 112 are formed through the same process. Alternatively, the insulator 108 and the insulator 11 may be formed through different processes. The openings provided in the substrate 8 may be formed through the same process or through different processes. These steps may be performed together with the fabrication of the transistor 150 and the capacitor 160. By performing this process, the productivity of semiconductor devices can be increased in some cases.

[0178] FIG. 17(B) is a cross-sectional view showing an example of a connection between wirings of a semiconductor device. and conductor 104d, which is in the same layer as conductor 104a and / or conductor 104b. , conductor 116a, conductor 116b and / or conductor 116c, etc. Specifically, the conductor 104d is electrically connected to the conductor 116e. The conductor 116e is in contact with the insulator 108 and the conductor 116e through the openings provided in the insulator 118. It is sufficient to have an area where

[0179] The openings provided in the insulators 108 and 118 are formed through the same process. These steps may be performed to form the transistor 150. By performing this process together with the manufacturing of the capacitor element 160, productivity of the semiconductor device can be increased. It may be possible.

[0180] FIG. 17(C) is a cross-sectional view showing an example of a connection between wirings of a semiconductor device. conductor 104a and / or conductor 104b, and conductor 104e, which are in the same layer as conductor 104a and / or conductor 104b. , and the conductor 115b which is in the same layer as the conductor 114, etc. Specifically, the conductor 104e is provided in the insulator 102 and the insulator 112. It is only necessary to have a region that is in contact with the conductor 115b through the opening.

[0181] The openings provided in the insulator 102 and the insulator 112 are formed through the same process. These steps may be performed to form the transistor 150. By performing this process together with the manufacturing of the capacitor element 160, productivity of the semiconductor device can be increased. It may be possible.

[0182] FIG. 17(D) is a cross-sectional view showing an example of an intersection between wirings of a semiconductor device. conductor 104a and / or conductor 104b, and conductor 104f, which are in the same layer as conductor 104a and / or conductor 104b. , conductor 116a, conductor 116b and / or conductor 116c, etc. The area where the insulator 116f overlaps with the insulator 102, the insulator 108, and the insulator 118 are interposed. Shows.

[0183] Incidentally, by providing multiple layers of insulators between the wirings, the parasitic capacitance between the wirings can be reduced. Therefore, it is possible to suppress the deterioration of frequency characteristics (also called frequency response) caused by parasitic capacitance. Therefore, it can be seen that the semiconductor device according to one embodiment of the present invention has a favorable f characteristic.

[0184] <Oxide semiconductor> In the following, the semiconductor 106, the semiconductor 106a, the semiconductor 106b, the semiconductor 106c, etc. Possible oxide semiconductors will be described.

[0185] The oxide semiconductor is, for example, an oxide containing indium. When indium is contained, the carrier mobility (electron mobility) increases. It is preferable to contain the element M. The element M is preferably aluminum, gallium, or yttrium. Other elements that can be used for element M include boron, silicon, and Titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, These include lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, as the element M, a combination of the above elements may be used. For example, it is an element with a high bond energy with oxygen. The element M is an element having a higher energy than indium. Alternatively, the element M may be, for example, an element having an energy It is an element that has the function of widening the gap. In addition, the oxide semiconductor preferably contains zinc. When an oxide semiconductor contains zinc, it may be more likely to crystallize.

[0186] However, the oxide semiconductor is not limited to an oxide semiconductor containing indium. For example, zinc tin oxide, gallium tin oxide, and the like are indium-free and zinc-containing. oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. It's okay.

[0187] For example, an oxide having a large energy gap is used as the oxide semiconductor. The energy gap is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV. The voltage is preferably from 3 eV to 3.8 eV, more preferably from 3 eV to 3.5 eV.

[0188] The on-current of a transistor can be increased by reducing the factors that hinder the movement of electrons. For example, if there are no factors that hinder the movement of electrons, it is assumed that electrons will move efficiently. The movement of electrons is also hindered, for example, when the physical unevenness of the channel formation region is large. will be done.

[0189] In order to increase the on-state current of a transistor, for example, , Root Mean Square (RMS) in the range of 1 μm × 1 μm are) roughness less than 1 nm, preferably less than 0.6 nm, and more preferably less than 0.5 nm It is preferable that the thickness is less than 0.4 nm, and more preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) is less than 1 nm, preferably less than 0.6 nm, and more preferably The thickness is preferably less than 0.5 nm, more preferably less than 0.4 nm. The maximum difference in height (also called PV) in the range of m is less than 10 nm, preferably less than 9 nm. The RMS roughness is preferably less than 8 nm, more preferably less than 7 nm. , Ra, and PV were measured using a scanning probe microscope manufactured by SII NanoTechnology, Inc. Measurements can be made using a mirror system such as SPA-500.

[0190] Note that when copper is mixed into an oxide semiconductor, electron traps may be generated. The flip-flop may shift the threshold voltage of the transistor in the positive direction. The copper concentration on the surface or inside of the oxide semiconductor is preferably as low as possible. The body has a copper concentration of 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 or less, or 1 x 10 18 atoms / cm 3 It is preferable to have the following regions:

[0191] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0192] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0193] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0194] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor Conductor, nc-OS (nanocrystalline oxide semiconductor) ctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous li Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, and amorphous oxide semiconductors.

[0195] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC-O S, polycrystalline oxide semiconductor, nc-OS, etc.

[0196] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond is short-range. It can also be described as a structure that has order but does not have long-range order.

[0197] On the other hand, in the case of an essentially stable oxide semiconductor, it is possible to obtain a completely amorphous structure. It cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor (for example, having a periodic structure in a microscopic region) is converted into a completely amorphous oxide. It cannot be called a semiconductor. However, a-like OS is a device that can achieve periodicity in a microscopic area. Although it has a structure, it has voids and is an unstable structure. Its physical properties are similar to those of an amorphous oxide semiconductor.

[0198] <caac-os> First, let me explain about CAAC-OS.

[0199] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0200] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by a combined analysis image (high resolution) When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly identify the CAAC-OS. It can be said that the decrease in electron mobility caused by this is unlikely to occur.

[0201] The CAAC-OS observed by TEM will be described below. This shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction (SAC) is required. The spherical aberration correction function was used to obtain a high-resolution TEM image. In particular, it is called a Cs-corrected high-resolution TEM image. This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by Nippon Denshi Co., Ltd. This can be done.

[0202] FIG. 34(B) shows an enlarged Cs-corrected high-resolution TEM image of region (1) in FIG. 34(A). From Figure 34(B), it can be seen that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also referred to as the surface on which the film is to be formed). The surface reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0203] As shown in Figure 34(B), CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is shown by auxiliary lines in Figure 34(B) and Figure 34(C). Therefore, the size of each pellet is about 1 nm to 3 nm, and the pellets are It can be seen that the size of the gap caused by the tilt is about 0.8 nm. The CA nanocrystals can also be called nanocrystals (nc). AC-OS, CANC (C-Axis Aligned nanocrystals) The oxide semiconductor may also be referred to as an oxide semiconductor having the above structure.

[0204] Here, based on the Cs-corrected high-resolution TEM image, the pellet of CAAC-OS on the substrate 5120 was The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See Figure 34(D)). The inclination between the pellets observed in Figure 34(C) The location where the crack occurs corresponds to the area 5161 shown in FIG.

[0205] In addition, Fig. 35(A) shows the Cs of the plane of the CAAC-OS observed from a direction approximately perpendicular to the sample surface. Corrected high-resolution TEM images are shown for regions (1), (2), and (3) in Figure 35(A). Enlarged Cs-corrected high-resolution TEM images are shown in Figure 35(B), Figure 35(C), and Figure 35(D), respectively. 35(D). From Fig. 35(B), Fig. 35(C) and Fig. 35(D), the pellet It can be seen that the metal atoms are arranged in a triangular, square, or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different pellets.

[0206] Next, the CA analyzed by X-ray diffraction (XRD) We will explain AC-OS. For example, CAAC-OS with InGaZnO4 crystals When structural analysis is performed using the out-of-plane method, the results are as shown in Figure 36(A). A peak may appear at a diffraction angle (2θ) of around 31°. Since the crystal orientation of CAAC-OS is attributed to the (009) plane of nO4, the crystal orientation of CAAC-OS is considered to be c-axis oriented. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0207] In addition, in the structural analysis of CAAC-OS using the out-of-plane method, 2θ is 31° In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the center of the crystal grains indicate that some of the CAAC-OS grains do not have a c-axis orientation. The more preferable CAAC-OS is the structure solution by the out-of-plane method. In the analysis, a peak is observed at 2θ of approximately 31°, but no peak is observed at 2θ of approximately 36°.

[0208] On the other hand, in-plan X-ray irradiation is performed on the CAAC-OS in a direction approximately perpendicular to the c-axis. When structural analysis is performed using the e method, a peak appears at 2θ around 56°. This peak is due to In It is attributed to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was fixed at approximately 100°, and the analysis was performed while rotating the sample around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears as shown in Figure 36(B). However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ is When scanning is performed, the peaks attributable to the crystal plane equivalent to the (110) plane are as shown in Figure 36(C). Therefore, from the structural analysis using XRD, it is clear that CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0209] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe diameter of 300 nm was placed parallel to the sample surface. When an electron beam is incident, a diffraction pattern (selected area transmission electron diffraction) like that shown in Figure 49(A) is generated. This diffraction pattern may show the InGaZnO4 This includes spots due to the (009) plane of the crystal. Therefore, electron diffraction also reveals The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is approximately on the surface to be formed or on the upper surface. On the other hand, for the same sample, the probe is oriented perpendicular to the sample surface. The diffraction pattern when an electron beam with a diameter of 300 nm is incident is shown in Figure 49(B). (B) shows a ring-shaped diffraction pattern. Therefore, electron diffraction also reveals It is clear that the a-axis and b-axis of the pellets contained in the CAAC-OS do not have any orientation. The first ring in FIG. 49(B) is the (010) plane of the InGaZnO4 crystal. The second ring in Figure 49(B) is thought to be due to the (100) plane. This is thought to be due to the (110) plane.

[0210] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the formation of defects, so we take the opposite view. CAAC-OS can be considered an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0211] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0212] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0213] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, the carrier density is set to 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 Such an oxide semiconductor can be a highly purified intrinsic or substantially highly purified oxide semiconductor. CAAC-OS is called an intrinsic oxide semiconductor. It has a low impurity concentration and a low density of defect states. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0214] <nc-os> Next, we will explain nc-OS.

[0215] In the high-resolution TEM image, nc-OS is divided into two regions: one where crystals can be clearly seen and the other where crystals can be clearly seen. The nc-OS has regions where no crystalline parts can be confirmed. The size is often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor with a crystal size of 10 nm or more and 100 nm or less is called a microcrystalline oxide. For example, in high-resolution TEM images, the grain boundaries of nc-OS are It may not be possible to clearly identify the nanocrystals. Therefore, the crystalline part of nc-OS is referred to as the pellet below. There may be cases where this happens.

[0216] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. For example, for nc-OS, there are cases where it is difficult to distinguish between X particles with a diameter larger than that of the pellet. When using X-rays, peaks indicating crystal planes are not detected in the out-of-plane analysis. In addition, for nc-OS, a probe diameter larger than the pellet (for example, 50n When electron diffraction is performed using an electron beam (over 1000 nm), a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS, the size of the pellet is close to or smaller than the pellet. When nanobeam electron diffraction is performed using an electron beam with a diameter of n, spots are observed. When nanobeam electron diffraction is performed on c-OS, a circular (ring-shaped) bright spot appears. In some cases, a ring-shaped area is observed. In addition, multiple spots are observed within the ring-shaped area. There are cases where this happens.

[0217] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, and therefore, nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0218] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0219] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0220] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen and areas where crystals cannot be seen. and areas where it is not possible to

[0221] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0222] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS ( Prepare CAAC-OS (referred to as sample B) and CAAC-OS (referred to as sample C). The sample is also an In-Ga-Zn oxide.

[0223] First, high-resolution cross-sectional TEM images of each sample are acquired. It can be seen that all of the samples have crystalline parts.

[0224] The determination of which part is to be regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, including six layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The area where the spacing is 0.28 nm or more and 0.30 nm or less is considered to be the crystal part of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0225] Figure 50 shows an example of investigating the average size of the crystal parts (22 to 45 locations) of each sample. However, the length of the lattice fringes mentioned above is the size of the crystal part. It was found that the crystalline part of the OS (sample A) grew larger according to the cumulative electron irradiation dose. Specifically, as shown by (1) in Figure 50, in the early stages of TEM observation, the The crystal part (also called the initial nucleus) which was about 2 nm in size, was irradiated with a cumulative dose of 4.2 × 10 8 e - / nm 2 On the other hand, it can be seen that the size of the crystals grows to about 2.6 nm. The nc-OS (sample B) and CAAC-OS (sample C) were subjected to electron accumulation from the start of electron irradiation. The cumulative exposure dose is 4.2 x 10 8 e - / nm 2 No change in the size of the crystals was observed within the range of Specifically, as shown in (2) and (3) in Figure 50, the accumulation of electrons Regardless of the irradiation dose, the size of the crystalline parts of nc-OS and CAAC-OS was 1.4 mm. It can be seen that the thicknesses are approximately 2.1 nm and 2.1 nm.

[0226] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not as good as nc-OS and CAAC-O. It can be seen that the structure is unstable compared to S.

[0227] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC is 78.6% or more and less than 92.3% of that of the original. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0228] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0229] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, the density equivalent to a single crystal of the desired composition is estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate by combining different types of single crystals.

[0230] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0231] <Film formation model> The following describes the film formation models for CAAC-OS and nc-OS.

[0232] FIG. 39(A) shows how a CAAC-OS film is formed by sputtering. FIG.

[0233] The target 230 is adhered onto a backing plate. A plurality of magnets are arranged under the backing plate. A magnetic field is generated above the target 230. The film deposition rate is controlled by using the magnetic field of the magnet. The preferred sputtering method is called magnetron sputtering.

[0234] The target 230 has a polycrystalline structure, and each crystal grain includes a cleavage plane. The cleavage plane will be described in detail later.

[0235] The substrate 220 is disposed so as to face the target 230, and the distance therebetween is d (target The distance between the slot and the substrate (also called the distance between the slots) is 0.01 m or more and 1 m or less, preferably The thickness should be between 0.02m and 0.5m. Most of the gas in the deposition chamber is deposition gas (e.g., oxygen, Argon or a mixed gas containing 50% or more by volume of oxygen) and 0.01P The pressure is controlled to be a or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a voltage above a certain level to the target 230, discharge begins and plasma is confirmed. A high density plasma region is formed by the magnetic field above the target 230. In the high density plasma region, the deposition gas is ionized to generate ions 201. 201 is, for example, an oxygen cation (O + ) and argon cations (Ar + ) etc. .

[0236] The ions 201 are accelerated toward the target 230 by the electric field, and eventually reach the target 230 At this time, pellets, which are sputtered particles in the shape of plates or pellets, are ejected from the cleavage plane. The pellet 200a and the pellet 200b are separated and knocked out. The pellet 200b may be distorted in structure due to the impact of the ion 201. There is.

[0237] The pellet 200a is a flat or pellet-shaped pellet having a triangular, for example, equilateral triangular, plane. The pellet 200b is a sputtered particle. The pellet 200b has a hexagonal, for example, regular hexagonal, plane. The pellets 200a and 200b are sputtered particles in the form of plates or pellets. The flat or pellet-shaped sputter particles such as Pellet 200b are collectively called Pellet 200. The planar shape of the pellet 200 is not limited to a triangle or a hexagon. For example, There are cases where the shape is made up of 2 or more and 6 or less triangles. For example, two triangles (equilateral triangles) Sometimes they form joined squares (diamonds).

[0238] The thickness of the pellet 200 is determined depending on the type of deposition gas. It is preferable that the thickness of the sheet 200 is uniform. A chevron shape is preferable to a thick cubic shape.

[0239] The pellet 200 receives an electric charge as it passes through the plasma, causing the sides to become negative or positive. The pellet 200 has oxygen atoms on its side, and the oxygen atoms are negatively charged. For example, if pellet 200a has negatively charged oxygen atoms on its side, An example of this is shown in Figure 41. In this way, the sides are charged with the same polarity, and the charges This causes repulsion and allows the CAAC-OS to maintain its flat shape. In the case of In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms are negatively charged. Or, oxygen atoms bonded to indium, gallium, or zinc atoms. The electrons may become negatively charged.

[0240] As shown in FIG. 39(A), for example, a pellet 200 flies like a kite through the plasma. The pellet 200 flutters up onto the substrate 220. Therefore, when an area where other pellets 200 have already accumulated approaches, a repulsive force is generated. On the upper surface of the substrate 220, a magnetic field is generated in a direction parallel to the upper surface of the substrate 220. Since a potential difference is applied between the substrate 220 and the target 230, the target Therefore, the pellet 200 is connected to the substrate 220. The upper surface of the magnet is subjected to a force (Lorentz force) due to the action of the magnetic field and the electric current (Figure 42 See (see below). This can be understood by Fleming's left-hand rule. In order to increase the force applied to the substrate 220, A parallel magnetic field of 10 G or more, preferably 20 G or more, more preferably 30 G or more, More preferably, a region where the voltage is 50 G or more is provided. The magnetic field parallel to the upper surface of the substrate 220 is one of the magnetic fields perpendicular to the upper surface of the substrate 220. 0.5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more It is advisable to set up an area where

[0241] In addition, the substrate 220 is heated, and resistance such as friction between the pellet 200 and the substrate 220 is reduced. As a result, as shown in FIG. 43(A), the pellet 200 The pellet 200 glides over the top surface of the substrate 220. 220. After that, as shown in Figure 43(B), the amount of the particles already deposited increases. When the particles reach the side of the pellet 200, the sides join together. The oxygen atom on the side of 00 is released. The released oxygen atom causes the Since oxygen vacancies may be filled, a CAAC-OS with a low density of defect states is obtained.

[0242] Furthermore, when the pellet 200 is heated on the substrate 220, the atoms are rearranged and the ions are The structural distortion caused by the collision of 201 is relaxed. The relaxed pellet 200 is The pellets 200 become almost single crystals. Even if the pellet 200 is heated after being bonded, it is unlikely that the pellet 200 itself will expand or contract. Therefore, the gaps between the pellets 200 widen, forming defects such as grain boundaries, and cracks occur. In addition, the gaps are filled with elastic metal atoms, It is thought that the sides of the 200 misaligned pellets are connected like a highway.

[0243] According to the above model, it is considered that the pellet 200 accumulates on the substrate 220. Therefore, unlike epitaxial growth, when the surface to be formed does not have a crystalline structure, For example, it is possible to form a CAAC-OS film on the upper surface ( It is possible to form a CAAC-OS film even if the surface on which it is formed is amorphous. .

[0244] In addition, the CAAC-OS is not only applied to a flat surface, but also to the upper surface of the substrate 220, which is the surface on which the CAAC-OS is to be formed. Even if the surface has irregularities, the pellets 200 are arranged along the shape of the surface. For example, if the top surface of the substrate 220 is atomically flat, the pellet 200 will be formed on a plane parallel to the ab plane. The flat surface is placed facing downwards, resulting in a layer with uniform thickness, flatness, and high crystallinity. Then, by stacking these layers n times (n is a natural number), CAAC-O S can be obtained (see Figure 39(B)).

[0245] On the other hand, even if the upper surface of the substrate 220 has irregularities, the CAAC-OS allows the pellet 200 to The structure is made up of n layers (n is a natural number) stacked along the unevenness. Due to the unevenness, gaps may easily occur between the pellets 200 in the CAAC-OS. However, intermolecular forces act between the pellets 200, so even if there are irregularities, there will be no gaps between the pellets. Therefore, CAA with high crystallinity is obtained even if there are irregularities. It can be C-OS (see Figure 39(C)).

[0246] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if there is a problem, uniform film formation is possible.

[0247] Since the CAAC-OS film is formed using this model, the sputtered particles have a small thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 220 may not be uniform, and the thickness and crystal orientation may not be uniform. do.

[0248] The film formation model shown above allows for the formation of highly crystalline films even on a surface with an amorphous structure. A CAAC-OS having the formula:

[0249] In addition, CAAC-OS is a coating model containing zinc oxide particles in addition to pellet 200. This can also be explained as follows.

[0250] The zinc oxide particles have a smaller mass than the pellets 200 and therefore reach the substrate 220 first. On the upper surface of the substrate 220, zinc oxide particles grow preferentially in the horizontal direction to form a thin film. The zinc oxide layer has a c-axis orientation. The c-axis of the crystal is oriented parallel to the normal vector of the substrate 220. It acts as a seed layer for growing C-OS, and improves the crystallinity of CAAC-OS. The zinc oxide layer has a thickness of 0.1 nm to 5 nm, and The zinc oxide layer is thin enough that the grain boundaries are barely visible. It is not possible.

[0251] Therefore, to form a highly crystalline CAAC-OS film, a higher than stoichiometric composition is required. It is preferable to use a target containing a small proportion of zinc.

[0252] Similarly, the nc-OS can be understood by the film formation model shown in Figure 40. The only difference between FIG. 40 and FIG. 39(A) is whether or not the substrate 220 is heated.

[0253] Therefore, the substrate 220 is not heated and there is no friction between the pellet 200 and the substrate 220. As a result, the pellet 200 is in a state of high resistance. Since it cannot glide, it accumulates irregularly and You can get the OS.

[0254] <cleavage plane> Below, we explain the cleavage plane of the target described in the CAAC-OS film formation model. do.

[0255] First, the cleavage plane of the target will be explained using FIG. 44. The crystal structure of O4 is shown in Figure 44(A). The c-axis is oriented upward and parallel to the b-axis. The structure of the InGaZnO4 crystal is shown when observed from the c-axis. The figure shows the structure of an InGaZnO4 crystal when observed from a direction parallel to the plane.

[0256] The energy required for cleavage on each crystal plane of an InGaZnO4 crystal was calculated using first-principles calculations. The calculation is performed using a pseudopotential and a density functional process using a plane wave basis. The pseudopotential used is an ultra-soft pseudopotential (CASTEP). The functional is GGA PBE. The energy is set to 400 eV.

[0257] The energy of the structure in the initial state is derived after structural optimization including the cell size. In addition, the energy of the structure after cleavage on each plane is calculated by the atomic arrangement with the cell size fixed. It is derived after structural optimization of the position.

[0258] Based on the crystal structure of InGaZnO4 shown in Figure 44, the first, second, and third planes A structure cleaved at either of the fourth planes was fabricated, and structural optimization calculations were performed with the cell size fixed. Here, the first plane is a crystal plane between the Ga-Zn-O layer and the In-O layer, and (0 The second plane is a crystal plane parallel to the α-plane (or ab-plane) (see Figure 44(A)). The crystal plane between the Ga-Zn-O layers is the (001) plane (or ab The third plane is a crystal plane parallel to the (110) plane (see Figure 44(A)). The fourth plane is a crystal plane (see Figure 44(B)). It is a straight crystal plane (see Figure 44(B)).

[0259] Under the above conditions, the energy of the structure after cleavage on each plane is calculated. The difference between the energy of the structure and the energy of the initial state is divided by the area of the cleavage plane. The cleavage energy, which is a measure of the ease of cleavage on each plane, is calculated. Energy is the kinetic energy of the electrons and the interatomic and atomic energies of the atoms and electrons contained in the structure. -This is the energy that takes into account the interactions between electrons and electrons themselves.

[0260] As a result of calculations, the cleavage energy of the first facet is 2.60 J / m 2 , the cleavage energy of the second face is 0.68J / m 2 , the cleavage energy of the third face is 2.18 J / m 2 , 4th plane cleavage Energy is 2.12J / m 2 It was found that (see table below).

[0261] [Table 1]

[0262] From this calculation, in the crystal structure of InGaZnO4 shown in Figure 44, The cleavage energy is lowest between the Ga-Zn-O layer and the Ga-Zn-O layer. is the plane (cleavage plane) that is easiest to cleave. When referring to the cleavage plane, it refers to the second plane, which is the plane that is easiest to cleave.

[0263] Since the cleavage plane is on the second plane between the Ga-Zn-O layers, the structure shown in FIG. The InGaZnO4 crystal shown in 4(A) can be separated by a plane equivalent to two second planes. Therefore, when ions or the like are bombarded with the target, the highest cleavage energy is The minimum size is a wafer-like unit (we call it a pellet) cleaved along the lower plane of the In this case, the InGaZnO4 pellets are It consists of three layers: a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer.

[0264] The first plane (a crystal plane between the Ga-Zn-O layer and the In-O layer, which is the (001) plane ( The third plane (a crystal plane parallel to the (110) plane) and the fourth plane (a crystal plane parallel to the (110) plane) are more closely spaced than the ab plane. The cleavage energy of the 4th plane (a crystal plane parallel to the (100) plane (or bc plane)) is low. This suggests that the planar shape of the pellets is often triangular or hexagonal.

[0265] Next, classical molecular dynamics calculations were performed to identify the target InGaZ Assuming a crystal of nO4, the target is spat out with argon (Ar) or oxygen (O). The cleavage plane of the InGaZnO4 crystal (268 8 atoms) is shown in Fig. 45(A) and the top view structure is shown in Fig. 45(B). The fixed layer shown in A) is a layer in which the atomic arrangement is fixed so that the position does not fluctuate. The temperature control layer shown in 5(A) is a layer that is always kept at a constant temperature (300K).

[0266] For classical molecular dynamics calculations, Fujitsu Materials Explorer 5. 0 is used. The initial temperature is 300K, the cell size is constant, and the time step width is 0.01 The calculation assumes that the atom is subjected to 300e V energy is applied, and atoms are introduced into the cell from a direction perpendicular to the ab plane of the InGaZnO4 crystal. Let it enter.

[0267] FIG. 46(A) shows the state where argon is incident on the cell having the InGaZnO4 crystal shown in FIG. Figure 46(B) shows the atomic arrangement 99.9 picoseconds (psec) after the cell The atomic arrangement is shown in Fig. 46 after 99.9 picoseconds from the oxygen incident. A part of the fixed layer shown in A) is omitted.

[0268] From Figure 46(A), within 99.9 picoseconds after argon entered the cell, Therefore, cracks occur from the cleavage plane corresponding to the second plane shown in Fig. 1. When argon collides with the crystal, the top surface is the second surface (0th), and the second surface (2 It can be seen that large cracks occur in the first (second) crack.

[0269] On the other hand, from Figure 46(B), it can be seen that within 99.9 picoseconds after oxygen entered the cell, the ) and the cracks start from the cleavage plane corresponding to the second plane shown in Fig. 1. When the collision occurs, a large crack occurs on the second (first) surface of the InGaZnO4 crystal. It can be seen that...

[0270] Therefore, from the top surface of the target containing InGaZnO4 crystals with a homologous structure When atoms (ions) collide with the InGaZnO4 crystal, the InGaZnO4 crystal cleaves along the second plane, forming a flat surface. It can be seen that plate-shaped particles (pellets) peel off. At this time, the size of the pellets is It was found that the collision with oxygen was smaller than that with argon. do.

[0271] The above calculations suggest that the detached pellet contains a damaged area. The damaged area contained in the nucleus can be repaired by reacting oxygen with the defects caused by the damage. There is a match.

[0272] Therefore, we investigated whether the pellet size differs depending on the atom that is collided. do.

[0273] In FIG. 47(A), argon is incident on the cell having the InGaZnO4 crystal shown in FIG. After this, the trajectories of each atom are shown from 0 picoseconds to 0.3 picoseconds. 7(A) corresponds to the period between FIG. 45 and FIG. 46(A).

[0274] From Figure 47(A), it can be seen that argon collides with gallium (Ga) in the first layer (Ga-Zn-O layer). When the gallium collides with zinc (Zn) in the third layer (Ga-Zn-O layer), the zinc It can be seen that lead reaches the vicinity of the sixth layer (Ga-Zn-O layer). The argon that hits the substrate is repelled outwards. When argon is bombarded onto the target, a crack appears on the second surface (2nd) in Figure 45(A). It is thought that this will be included.

[0275] Also, in FIG. 47(B), oxygen enters the cell having the InGaZnO4 crystal shown in FIG. The trajectory of each atom is shown from 0 picoseconds to 0.3 picoseconds after irradiation. 47(B) corresponds to the period between FIG. 45 and FIG. 46(A).

[0276] On the other hand, as shown in Figure 47(B), oxygen collides with gallium (Ga) in the first layer (Ga-Zn-O layer). Then, after the gallium collides with the zinc (Zn) in the third layer (Ga-Zn-O layer), It can be seen that zinc does not reach the fifth layer (In-O layer). Therefore, the target containing InGaZnO4 crystals is When the element is collided, it is thought that a crack will occur on the second surface (first surface) in Figure 45(A). do.

[0277] From this calculation, it can be seen that when atoms (ions) collide with InGaZnO4 crystals, It is suggested that peeling occurs.

[0278] In addition, we will consider the difference in crack depth from the viewpoint of conservation laws. The existence law can be expressed as equations (1) and (2), where E is the The energy of gon or oxygen (300 eV), m A is the mass of argon or oxygen, v A is the velocity of argon or oxygen before the collision, v' A is the velocity of argon or oxygen after the collision, m Ga is the mass of gallium, v Ga is the velocity of gallium before the collision, v' Ga Galliu after the collision is the speed of the

[0279]

number

[0280]

number

[0281] Assuming that the collisions of argon or oxygen are elastic, v A , v' A , v Ga and v' Ga The relationship can be expressed as equation (3).

[0282]

number

[0283] From equations (1), (2) and (3), v Ga If argon or oxygen is collided with The velocity of the gallium after impact is v' Ga can be expressed as in equation (4).

[0284]

number

[0285] In equation (4), m A Substitute the mass of argon or the mass of oxygen into Compare the velocity of gallium after the collision. The energy of argon and oxygen before the collision When the ratio is the same, the collision with argon is 1.24 times greater than the collision with oxygen. Therefore, the energy of gallium is also higher than that of Argon. When an electron collides with an electron, the velocity is higher by the square of the velocity than when an oxygen collides with an electron.

[0286] When argon is bombarded, the speed of gallium after the bombardment is higher than when oxygen is bombarded. Therefore, when argon is collided with the However, it is believed that cracks occurred at a deeper position than when oxygen was bombarded.

[0287] From the above calculations, the target containing InGaZnO4 crystals with a homologous structure was It can be seen that when sputtered, the cleaved surface peels off and a pellet is formed. Sputtering other structural areas of the target that do not have the pores does not result in pellet formation. The sputtered particles are formed at the atomic level, which is smaller than the particles. Since it is smaller than the nozzle, it can be easily evacuated via a vacuum pump connected to the sputtering system. Therefore, the crystal of InGaZnO4 with homologous structure When a target containing gallium is sputtered, particles of various sizes and shapes fly to the substrate and are deposited. It is difficult to imagine a model in which a film is formed by depositing sputtered pellets. The model shown in Figure 39(A) for forming an -OS film is reasonable.

[0288] The density of the CAAC-OS film formed in this way is comparable to that of single-crystal OS. For example, the density of a single crystal OS with a homologous structure of InGaZnO4 is 6.36 g / cm 3 In contrast, the density of CAAC-OS, which has a similar atomic ratio, is 6.3 g / cm 3 It will be about that amount.

[0289] Figure 48 shows the In-Ga-Zn oxide (CAAC-OS) film formed by sputtering. See Figure 48(A).) and the element in the cross section of its target (see Figure 48(B). The atomic arrangement is shown. High-angle scattering annular dark-field scanning transmission electron microscopy (HAA) was used to observe the atomic arrangement. DF-STEM:High-Angle Annular Dark Field Sc anning Transmission Electron Microscopy) In HAADF-STEM, the image intensity of each atom is proportional to the square of the atomic number. Therefore, Zn (atomic number 30) and Ga (atomic number 31) have similar atomic numbers. The HAADF-STEM uses a Hitachi HD-270 scanning transmission electron microscope. Use 0.

[0290] Comparing Figure 48(A) and Figure 48(B), both CAAC-OS and the target It can be seen that they have homologous structures and the arrangement of their atoms corresponds to each other. Therefore, as shown in the film formation model in Figure 39(A), the crystal structure of the target is transferred. It can be seen that a CAAC-OS film is formed by this.

[0291] <Band diagram> A band diagram of an arbitrary cross section of the above-mentioned transistor will be described below.

[0292] FIG. 18A is a cross-sectional view of a transistor 150 according to one embodiment of the present invention.

[0293] For the transistor 150 shown in FIG. 18A, refer to the description of FIG.

[0294] 18B shows the channel formation region of the transistor 150 shown in FIG. The band diagram of the semiconductor 106a is shown in the A-A' cross section. In addition, the energy gap of the insulator 102a, the insulator 102b, and the The insulator 112 has a larger energy gap than the semiconductor 106a and the semiconductor 106b. Also, the semiconductor 106a, the semiconductor 106b, the insulator 102a, and the insulator 103a are The Fermi levels (denoted as Ef) of the insulator 112 and the insulator 112 are The position of the conductor 104a and the conductor 114 is the position of the Lummi level (denoted as Ei). The work function of is set to be equal to the energy difference between the vacuum level and the Fermi level.

[0295] When the gate voltage is set to be equal to or higher than the threshold voltage of the transistor 150, the semiconductor 106a and the semiconductor Due to the difference in energy between the semiconductor 106a and the body 106b, electrons preferentially pass through the semiconductor 106a. In other words, it can be assumed that electrons are embedded in the semiconductor 106a. The energy at the bottom of the conduction band is denoted as Ec, and the energy at the top of the valence band is denoted as Ev.

[0296] Therefore, the transistor 150 according to one embodiment of the present invention can achieve interface conductivity by implanting electrons. Therefore, the transistor 150 according to one embodiment of the present invention is The channel resistance is low.

[0297] Next, in FIG. 18(C), the source region or drain of the transistor 150 shown in FIG. 18(A) is The band diagram of the B-B' cross section including the in-situ region is shown in FIG. 7b1, area 107a2 and area 107b2 are in a degenerated state. In this case, the Fermi level of the semiconductor 106a is set to be approximately equal to the energy of the bottom of the conduction band. In the region 107b2, the Fermi level of the semiconductor 106b is at the energy level of the bottom of the conduction band. The same applies to the area 107a1 and the area 107a2.

[0298] At this time, the conductor 116b having the function of a source electrode or a drain electrode and the region The energy barrier between 107b2 and 107b2 is small enough to form an ohmic contact. The region 107b2 and the region 107b1 form an ohmic contact. The conductor 116a, which functions as a drain electrode, and the region 107a2 are connected to each other. The barrier is small enough to provide ohmic contact. Therefore, the conductors 116a and 116b are in ohmic contact with each other. Electrons are smoothly exchanged between the semiconductor 106a and the semiconductor 106b. You can see that.

[0299] As described above, the transistor according to one embodiment of the present invention has a source electrode and a drain electrode. The electrons are smoothly exchanged between the electrode and the channel forming region, and the channel resistance is low. In other words, it is a transistor with excellent switching characteristics. It can be seen that...

[0300] Next, the semiconductor 106a and the semiconductor 106b are separated into a band diagram as shown in FIG. This article explains:

[0301] For example, the semiconductor 106a contains at least one element other than oxygen that constitutes the semiconductor 106b. Alternatively, the semiconductor 106b may be an oxide semiconductor composed of two or more kinds of oxides. Since the semiconductor 106a is composed of one or more of the elements, An interface state is unlikely to be formed at the interface between the semiconductor 106a and the semiconductor 106b.

[0302] The semiconductor 106a and the semiconductor 106b preferably contain at least indium. When the semiconductor 106a is an In-M-Zn oxide, the sum of In and M is 100 atoms. When the atomic percentage of In is c%, it is preferable that In is less than 50 atomic % and M is more than 50 atomic %. More preferably, In is less than 25 atomic % and M is more than 75 atomic %. When the semiconductor 106b is an In-M-Zn oxide, the sum of In and M is set to 1. When the atomic percentage of In is 0.00, the atomic percentage of In is preferably higher than 25 and the atomic percentage of M is 7. 5 atomic % or less, more preferably In is higher than 34 atomic % and M is 66 Less than atomic percent.

[0303] The semiconductor 106b is made of an oxide having a higher electron affinity than the semiconductor 106a. The conductor 106b has an electron affinity of 0.07 eV or more and 1.3 eV or less than that of the semiconductor 106a. , preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less. The electron affinity is determined by the energy difference between the vacuum level and the bottom of the conduction band. This is the difference between...

[0304] As shown in FIG. 14, the semiconductor 106 includes a semiconductor 106a, a semiconductor 106b, and In the case where the semiconductor 106c is provided, electrons can be embedded in the same manner. For the semiconductor 106c, refer to the description of the semiconductor 106a.

[0305] The transistor structures shown above are only examples, and combinations of these structures are also within the scope of the present invention. This falls within the scope of the embodiment.

[0306] <Application examples of semiconductor devices> Below, application examples of the semiconductor device according to one embodiment of the present invention will be described.

[0307] <Display device> A configuration example of a display device according to one embodiment of the present invention will be described below.

[0308] [Configuration example] FIG. 19A is a top view of a display device according to one embodiment of the present invention. In the display device according to one embodiment of the present invention, a pixel circuit is provided in which a liquid crystal element is used for a pixel. FIG. 19C shows a display device according to one embodiment of the present invention in which an organic EL element is used in a pixel. 1 shows a pixel circuit when the pixel circuit is used.

[0309] The transistor used in the pixel can be any of the above-described transistors. An example using an n-channel transistor is shown. A transistor manufactured through one process may be used for a driver circuit. The capacitor element used in the pixel and the driver circuit can be the capacitor element described above. By using the above-described transistor and capacitor element, high display quality or / and This results in a highly reliable display device.

[0310] Note that the structure of the transistor used in the pixel is different from that of the transistor used in the driver circuit. In some cases, the performance of the display device can be improved by using s-chan The driver circuit uses a transistor with a nel structure, and the driver circuit does not have an s-channel structure. A transistor having an s-channel structure may be used. Compared with transistors without s-channel structure, it has a high on-current and a low off-current. Therefore, transistors used in pixels that require high on-current and / or low off-current are In some cases, it is preferable as a transistor having an s-channel structure. When you want to obtain an on-current equivalent to that of a transistor without an s-channel structure, The occupied area can be reduced in some cases, and therefore the aperture ratio of the pixel can be increased. Specifically, the aperture ratio of the pixel is set to 40% or more, preferably 50% or more, and more preferably Preferably, it can be made 60% or more. The transistors used in the pixels have high light-shielding properties, so they can block light-induced On the other hand, in the drive circuit, the s-channel In some cases, it is preferable to use a transistor without an EL structure because it can further reduce parasitic capacitance. In addition, in the driver circuit, transistors that do not have an s-channel structure In some cases, using the above method provides greater design freedom.

[0311] For example, a transistor having an s-channel structure is used in the driver circuit, and A transistor that does not have an s-channel structure may be used. A transistor having a nel structure has a high on-current and a low off-current, and therefore The present invention is suitable as a transistor for use in a driver circuit that requires low on-state current and / or low off-state current. In addition, a transistor having an s-channel structure may be When it is desired to obtain an on-current equivalent to that of a transistor without a channel structure, the occupied area is reduced. Therefore, it is possible to reduce the area of the driving circuit and make the frame of the display device smaller. Specifically, the width of the frame should be 3 mm or less, preferably In some cases, it may be possible to make the thickness 1 mm or less, more preferably 0.8 mm or less. In pixels, transistors without s-channel structures have more parasitic capacitance. In particular, in a light-emitting device, the pixel may be subjected to threshold correction. If the function is provided, the effect can be increased by reducing the parasitic capacitance. be.

[0312] In addition, for example, a transistor having an s-channel structure is used in a part of the pixel, In another part of the elements, a transistor not having an s-channel structure may be used. Transistors with s-channel structures have high on-current and low off-current Therefore, transistors used in some pixels that require high on-current and / or low off-current are In some cases, it is preferable as a transistor having an s-channel structure. When you want to obtain an on-current equivalent to that of a transistor without an s-channel structure, The occupied area can be reduced in some cases, and therefore the aperture ratio of the pixel can be increased. Specifically, the aperture ratio of the pixel is set to 40% or more, preferably 50% or more, and more preferably Preferably, it can be made 60% or more. The transistors used in the pixels have high light-shielding properties, so they can block light-induced On the other hand, in another part of the pixel, the s-ch A transistor without a channel structure is preferable because it can reduce parasitic capacitance more. In particular, in a light-emitting device, when pixels have a threshold correction function, parasitic capacitance Reducing the amount may increase the effect.

[0313] Also, for example, a transistor having an s-channel structure is used in part of the driver circuit. However, a transistor not having an s-channel structure may be used in another part of the driver circuit. A transistor with an s-channel structure has a high on-current and a low off-current. Therefore, it can be used as a part of a drive circuit that requires a high on-current and / or a low off-current. In some cases, it is preferable to use a transistor having an s-channel structure. The transistor has an on-current similar to that of a transistor without an s-channel structure. Therefore, it is possible to reduce the area occupied by the driver circuit. This may allow the frame of the display device to be made smaller. Each of these should be 3 mm or less, preferably 1 mm or less, and more preferably 0.8 mm or less. On the other hand, in another part of the driver circuit, an s-channel structure is used. In some cases, a transistor without such a gate is preferable because it can reduce parasitic capacitance.

[0314] An example of a top view of an active matrix display device is shown in Figure 19(A). On the substrate 5000, a pixel portion 5001, a first scanning line driving circuit 5002, a second scanning line driving circuit 5003, and a A signal line driver circuit 5003 and a signal line driver circuit 5004 are arranged in the pixel portion 5001. Therefore, the signal line driver circuit 5004 is electrically connected to the first scanning line 5001. The driver circuit 5002 and the second scanning line driver circuit 5003 are electrically connected. In the areas separated by the scanning lines and the signal lines, pixels each having a display element are arranged. The substrate 5000 of the display device is made of an FPC (Flexible Printed Circuit). d Circuit) and other connections, C).

[0315] The first scanning line driver circuit 5002, the second scanning line driver circuit 5003 and the signal line driver circuit 5 004 is formed on the same substrate 5000 as the pixel portion 5001. The cost of manufacturing the display device can be reduced compared to when the display device is manufactured by using a drive circuit. If a separate operating circuit is created, the number of connections between the wiring will increase. By providing a driver circuit in the and / or yield can be improved.

[0316] <Liquid crystal display device> An example of the circuit configuration of a pixel is shown in FIG. 19(B). 1 shows a pixel circuit that can be applied to a pixel such as a liquid crystal display (LCD).

[0317] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrodes. The electrodes are connected to different transistors, and each transistor can be driven by a different gate signal. This allows the individual pixel electrodes of the multi-domain designed pixels to The signals applied to the electrodes can be controlled independently.

[0318] The gate wiring 5012 of the transistor 5016 and the gate wiring 5017 of the transistor 5017 13 are separated so that different gate signals can be applied. The source electrode or drain electrode 5014 serving as a line is connected to the transistor 5016. Transistor 5016 and transistor 5017 are commonly used. The above-described transistor 150 or the like can be used as the capacitor 50. The capacitance element 160 described above can be used as appropriate for the capacitance element 5023A and the capacitance element 5023B. This makes it possible to provide a liquid crystal display device with high display quality and / or high reliability. This can be done.

[0319] The gate electrode of the transistor 5016 is electrically connected to the gate wiring 5012. The gate electrode of the gate electrode 5017 is electrically connected to the gate wiring 5013. Different gate signals are applied to the gate wiring 5012 and the transistor 5013. The alignment of the liquid crystal can be controlled by varying the operation timing of the transistor 5017.

[0320] Also, a capacitance wiring 5010, a gate insulator acting as a dielectric, and a first pixel electrode or A capacitance element may be formed by a capacitance electrode electrically connected to the second pixel electrode.

[0321] The multi-domain structure has a first liquid crystal element 5018 and a second liquid crystal element 5019 in one pixel. The first liquid crystal element 5018 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 5019 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween. do.

[0322] Note that a display device according to one embodiment of the present invention is not limited to the pixel circuit shown in FIG. For example, if a switch, a resistor, a capacitor, a transistor, etc. are newly added to the pixel circuit shown in FIG. 19(B), Additional components such as sensors, logic circuits, etc. may be added.

[0323] <Light-emitting device> Another example of the circuit configuration of a pixel is shown in Figure 19(C). 1 shows a pixel structure of a display device (also called a light-emitting device) using a light-emitting element.

[0324] When a voltage is applied to the light-emitting element, the organic EL element generates a pair of electrodes. Electrons are injected from one electrode and holes are injected from the other electrode into a layer containing a light-emitting organic compound, An electric current flows, and the electrons and holes recombine to form light-emitting organic compounds. An excited state is formed, and light is emitted when the excited state returns to the ground state. Therefore, such a light-emitting element is called a current-excited light-emitting element.

[0325] FIG. 19C is a diagram showing an example of a pixel circuit. Here, one pixel has an n-channel type An example using two transistors and one capacitor is shown. The above-described transistor 150 or the like can be used for the transistor. The pixel circuit can use the above-mentioned capacitance element 160 or the like. Time gray scale driving can be applied.

[0326] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0327] The pixel 5020 includes a switching transistor 5021, a driving transistor 5022, The switching transistor 502 includes a light-emitting element 5024 and a capacitor element 5023. 1, the gate electrode is connected to the scanning line 5026, and the first electrode (the source electrode, the drain electrode) The first electrode (the other of the source and drain electrodes) is connected to a signal line 5025, and the second electrode (the other of the source and drain electrodes) is connected to a drive The gate electrode of the driving transistor 5022 is connected to the gate electrode of the driving transistor 5022. The gate electrode is connected to a power supply line 5027 via a capacitor element 5023, and the first electrode is connected to a power supply line 5026. The second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 5024. The second electrode of the light emitting element 5024 corresponds to the common electrode 5028. are electrically connected to a common potential line formed on the same substrate.

[0328] The switching transistor 5021 and the driving transistor 5022 are the transistors described above. The capacitor 5023 may be the same as the capacitor 150. 160, etc., can be used. This allows for high display quality and / or reliability. This will result in a highly efficient organic EL display device.

[0329] The potential of the second electrode (common electrode 5028) of the light emitting element 5024 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 5027, for example. GND, 0V, etc. can be set as the low power supply potential. The high and low power supply potentials are set so that the potential difference is equal to or greater than the threshold voltage of the light-emitting element. By applying a voltage to the transistor 5024, a current flows through the light emitting element 5024, causing it to emit light. The forward voltage of the light emitting element 5024 refers to the voltage required to achieve a desired luminance, and is at least Both include forward threshold voltage.

[0330] The capacitor 5023 is substituted for the gate capacitance of the driving transistor 5022. The gate capacitance of the driving transistor 5022 can be omitted. A capacitance may be formed between the capacitor formation region and the gate electrode.

[0331] Next, a description will be given of the signal input to the driving transistor 5022. Voltage input voltage driving In this case, the driving transistor 5022 is in either an on or off state. The video signal is input to the driving transistor 5022. In order to operate the inverter 2 in the linear region, a voltage higher than the voltage of the power supply line 5027 is applied to the driving transformer. The signal line 5025 is connected to the gate electrode of the transistor 5022. A voltage equal to or greater than the threshold voltage Vth of the transistor 5022 is applied.

[0332] When analog gradation driving is performed, the gate electrode of the driving transistor 5022 is connected to the light emitting element 50 24 plus the threshold voltage Vth of the driving transistor 5022. A voltage is applied to the video signal so that the driving transistor 5022 operates in the saturation region. A signal is inputted to cause a current to flow through the light emitting element 5024. Also, the driving transistor 5022 is saturated. In order to operate the driving transistor 5022 in the above-mentioned range, the potential of the power supply line 5027 is set to the gate By making the video signal analog, the video signal is applied to the light emitting element 5024. A current corresponding to the signal flows, and analog gradation driving can be performed.

[0333] Note that the display device according to one embodiment of the present invention is not limited to the pixel configuration shown in FIG. For example, the pixel circuit shown in FIG. 19(C) may include a switch, a resistor, a capacitor, a sensor, a transistor, and a A resistor or a logic circuit may be added.

[0334] <Modification 1 of the Light-Emitting Device> For example, FIG. 20A shows an example of a pixel circuit. Here, one pixel has n channels. An example using three channel-type transistors and one capacitor will be shown.

[0335] FIG. 20A shows an example of a circuit diagram of the pixel 5111. The pixel 5111 includes a transistor 5 155, a transistor 5156, a transistor 5157, a capacitor element 5158, and a and an optical element 5154.

[0336] The pixel electrode of the light emitting element 5154 is turned on in accordance with the image signal Sig input to the pixel 5111. The luminance of the light emitting element 5154 is controlled by the potential difference between the pixel electrode and the common electrode. It is determined by.

[0337] The transistor 5156 is in a conductive state between the wiring SL and the gate of the transistor 5155. The transistor 5155 has a function of controlling the The other of the source and drain is electrically connected to the wiring VL. The transistor 5157 is electrically connected to the wiring ML and the The capacitor element 5158 has a function of controlling the conduction state between one of the source and the drain. One of the pair of electrodes is electrically connected to the gate of the transistor 5155, and the other is It is electrically connected to the anode of the light emitting element 5154 .

[0338] The switching of the transistor 5156 is also performed by electrically connecting the gate of the transistor 5156 to the The switching of the transistor 5157 is performed according to the potential of the wiring GL connected to the transistor 5157. The gate of the transistor 5157 is turned on according to the potential of the wiring GL electrically connected to the gate of the transistor 5157. It will be held.

[0339] In addition, the transistors 5155, 5156, and 5157 The above-described transistor 150 or the like can be used for at least one of the capacitors. The element 5158 can be the above-described capacitor 160 or the like.

[0340] For example, if the source (or first terminal, etc.) of the transistor is connected to the (without an intervening resistor), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through (or without) Z2, or The source (or first terminal, etc.) of Z1 is directly connected to a part of Z1 and is directly connected to X, and the drain (or second terminal, etc.) of the transistor is connected to In the case where a part of Z2 is directly connected to Y and another part of Z2 is directly connected to Y, It can be expressed as follows.

[0341] For example, "X and Y and the source (or first terminal, etc.) and drain (or The second terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or (or first terminal, etc.), the drain (or second terminal, etc.) of the transistor, and then Y. It can be expressed as "electrically connected to the source of the transistor." (or first terminal, etc.) is electrically connected to X, and the drain (or The second terminal, etc.) is electrically connected to Y, and the source (or first terminal) of the transistor is connected to X. The transistor drain (or second terminal, etc.) and Y are electrically connected in this order. "X is connected to the source ( or the first terminal) and the drain (or the second terminal) X is the source (or first terminal, etc.) of the transistor, and the drain The terminal (or second terminal, etc.), Y, can be expressed as "provided in this connection order." Using the same expressions as these examples, the order of connections in a circuit configuration can be regulated. By defining the source (or first terminal, etc.) and drain (or The technical scope can be determined by distinguishing between the first terminal and the second terminal. The expression methods are only examples, and the present invention is not limited to these. Z2 is the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) Let's say there is.

[0342] Next, an example of the operation of the pixel 5111 shown in FIG. 20(A) will be described.

[0343] FIG. 20B shows the potential of the wiring GL electrically connected to the pixel 5111 shown in FIG. 10A and 10B are timing charts illustrating examples of the potential of the image signal Sig supplied to the wiring SL. The timing chart shown in FIG. 20B is for the pixel 5111 shown in FIG. This is an example in which all the transistors are n-channel.

[0344] First, in the period t1, a high-level potential is applied to the wiring GL. The image signal S The potential Vdata of ig is given, and the potential Vdata is and applied to the gate of transistor 5155.

[0345] A potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The potential Vano is the threshold voltage Vthe of the light emitting element 5154 and the potential Vcat of the transistor. It is preferable to set the potential higher than the threshold voltage Vth of the capacitor 5155. By providing the above potential difference between L and the wiring CL, The drain current of the transistor 5155 is determined. By supplying light to the light emitting element 5154, the brightness of the light emitting element 5154 is determined.

[0346] In addition, when the transistor 5155 is an n-channel transistor, the potential of the wiring ML is However, the potential is lower than the potential of the wiring CL plus the threshold voltage Vthe of the light emitting element 5154. The potential of the wiring VL is higher than the potential of the wiring ML by the threshold voltage Vth of the transistor 5155. It is preferable that the potential is higher than the added potential. Even if the drain current of the transistor 5155 is Priority can be given to L.

[0347] Next, in the period t2, a low-level potential is applied to the wiring GL. 5156 and transistor 5157 are turned off. Transistor 5156 is turned off. As a result, the potential Vdata is held at the gate of the transistor 5155. A potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The light emitting element 5154 emits light at the luminance determined in the period t1.

[0348] Next, in a period t3, a high-level potential is applied to the wiring GL. 5156 and transistor 5157 are turned on. A potential is applied such that the gate voltage of 5155 becomes greater than the threshold voltage Vth. A potential Vcat is applied to the wiring CL. The potential of the wiring ML is The potential becomes lower than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5154 to the potential of the wiring V The potential of L is the potential of the wiring ML plus the threshold voltage Vth of the transistor 5155. With the above configuration, the drain current of the transistor 5155 is It is possible to give priority to wiring ML rather than 5154.

[0349] The drain current of the transistor 5155 is supplied to the monitor circuit via the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to measure the value of the drain current. In the light-emitting device according to one aspect of the present invention, a signal including the above value is generated. The value of the potential Vdata of the image signal Sig supplied to the pixel 5111 is corrected using the signal. It is possible.

[0350] In the light-emitting device having the pixel 5111 shown in FIG. 20A, after the operation in the period t2, For example, in the pixel 5111, the operation from the period t1 to the period t After repeating the operation of period t2 several times, the operation of period t3 may be performed. After the operation for the period t3 is performed in the pixel 5111, the image signal corresponding to the minimum gradation value 0 is written to the pixels 5111 in one row where the operation has been performed, and the light emitting element 5154 is made to emit no light. After this state is reached, the operation for the period t3 may be performed for the pixels 5111 in the next row. stomach.

[0351] <Modification 2 of the Light-Emitting Device> Also, for example, FIG. 21(A) is a diagram showing an example of a pixel circuit. An example using four n-channel transistors and one capacitor will be shown.

[0352] FIG. 21A shows an example of a circuit diagram of the pixel 5211. The pixel 5211 includes a transistor 5 215, a transistor 5216, a transistor 5217, a capacitor element 5218, and a It includes a photo element 5214 and a transistor 5219 .

[0353] The pixel electrode of the light emitting element 5214 is turned on in accordance with the image signal Sig input to the pixel 5211. The luminance of the light emitting element 5214 is controlled by the potential difference between the pixel electrode and the common electrode. It is determined by.

[0354] The transistor 5219 is in a conductive state between the wiring SL and the gate of the transistor 5215. The transistor 5215 has a function of controlling one of the source and the drain. The transistor 5216 is connected to the anode of the photoelement 5214. The resistor 5215 has a function of controlling the conduction state between the source and the drain of the other of the resistors 5215. The transistor 5217 is connected to the wiring ML and the source and drain of the transistor 5215. The capacitor 5218 has a function of controlling conduction between the pair of electrodes and the other electrode. One is connected to the gate of the transistor 5215, and the other is connected to the anode of the light emitting element 5214. It continues.

[0355] The switching of the transistor 5219 is performed by connecting the gate of the transistor 5219 to the The transistor 5216 is switched on and off according to the potential of the wiring GLa. This is performed according to the potential of the wiring GLb connected to the gate of the transistor 5216. The switching of the transistor 5217 is performed by the wiring connected to the gate of the transistor 5217. This is done according to the potential of GLc.

[0356] The transistors 5215, 5216, 5217 and The above-described transistor 150 or the like is used for at least one of the transistors 5219. The capacitor 5218 can be the above-described capacitor 160 or the like. Cut.

[0357] Next, an example of the operation of external correction of the pixel 5211 shown in FIG. 21(A) will be described.

[0358] FIG. 21B shows a wiring GLa and a wiring GLb connected to the pixel 5211 shown in FIG. 21A. , the timing chart of the potential of the line GLc and the potential of the image signal Sig supplied to the line SL The timing chart shown in FIG. 21(B) is the same as the timing chart shown in FIG. 21(A). This illustrates a case where all the transistors included in the element 5211 are n-channel type. .

[0359] First, in a period t1, a high-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the transistor GLc is applied to the wiring GLd, and a low-level potential is applied to the wiring GLc. Transistor 5219 and transistor 5216 are turned on, and transistor 5217 is turned off. The wiring SL is supplied with a potential Vdata of the image signal Sig, and the potential V The data is applied to the gate of transistor 5215 via transistor 5219. .

[0360] A potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The potential Vano is a potential obtained by adding the threshold voltage Vthe of the light emitting element 5214 to the potential Vcat. The potential Vano of the wiring VL is preferably set to be higher than the potential Vano of the transistor 5216. The voltage is applied to the other of the source and drain of the transistor 5215 via the The value of the drain current of the transistor 5215 is determined according to the level Vdata. Then, the drain current is supplied to the light emitting element 5214, and the light emitting element 5214 emits light. The degree is determined.

[0361] Next, in a period t2, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the transistor GLc is applied to the wiring GLd, and a low-level potential is applied to the wiring GLc. The transistor 5216 is turned on, and the transistor 5219 and the transistor 5217 are turned off. When transistor 5219 is turned off, a voltage is applied to the gate of transistor 5215. The potential Vdata is maintained. The potential Vano is applied to the wiring VL, and the potential Vdata is maintained at the wiring C. Therefore, in the light emitting element 5214, a constant potential Vcat is applied to L during the period t1. The brightness is maintained.

[0362] Next, in a period t3, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A potential of high level is applied to the wiring GLc. The transistor 5217 is turned on, and the transistor 5219 and the transistor 5216 are turned off. A potential Vcat is applied to the wiring CL. A potential Vano is applied to the wiring ML. is provided and is connected to a monitor circuit.

[0363] By the above operation, the drain current of the transistor 5215 is is supplied to the wiring ML. The drain current is monitored via the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to A signal including the value of the rain current as information is generated. In the device, the potential Vdata of the image signal Sig supplied to the pixel 5211 is set by using the signal. The value of can be corrected.

[0364] In the light-emitting device having the pixel 5211 shown in FIG. 21A, after the operation in the period t2, For example, in a light emitting device, the operation from the period t1 to the period t2 may not be performed. After repeating the operation several times, the operation in the period t3 may be performed. After the operation of the element 5211 during the period t3, the image signal corresponding to the minimum gradation value 0 is By writing to the pixels 5211 in one row where this operation has been performed, the light emitting element 5214 is set to a non-light emitting state. After the pixel 5211 in the next row is set to the dummy state, the operation for the period t3 may be performed.

[0365] <Modification 3 of the Light-Emitting Device> Also, for example, FIG. 22(A) is a diagram showing an example of a pixel circuit. An example using five n-channel transistors and one capacitor will be shown.

[0366] 22A shows an example of a circuit diagram of the pixel 5311. The pixel 5311 shown in FIG. is a transistor 5315, a transistor 5316, a transistor 5317, and a capacitor An element 5318, a light-emitting element 5314, a transistor 5319, and a transistor 5320 and,

[0367] The transistor 5320 controls the conduction state between the wiring RL and the anode of the light-emitting element 5314. The transistor 5319 has a function of connecting the wiring SL and the gate of the transistor 5315. The transistor 5315 has a function of controlling the conduction state between the source and the drain. One of the drains is connected to the anode of the light-emitting element 5314. The transistor 5316 The conduction state between the wiring VL and the other of the source and drain of the transistor 5315 is controlled. The transistor 5317 has a function of controlling the signal line ML and the signal line SS of the transistor 5315. The capacitor element 5318 has a function of controlling the conduction state between the source and the drain. One of the pair of electrodes is connected to the gate of the transistor 5315, and the other is connected to the light-emitting element. It is connected to the anode of 5314.

[0368] The switching of the transistor 5319 is performed by connecting the gate of the transistor 5319 to the The transistor 5316 is switched on and off according to the potential of the wiring GLa. This is performed according to the potential of the wiring GLb connected to the gate of the transistor 5316. The switching of the transistor 5317 is performed by the wiring connected to the gate of the transistor 5317. The switching of the transistor 5320 is performed according to the potential of the transistor GLc. This is done according to the potential of the wiring GLd connected to the gate of the stadium 5320.

[0369] In addition, transistors 5315, 5316, 5317, At least one of the transistors 5319 and 5320 is The capacitor 5318 may be the same as the capacitor 160 described above. 0 etc. can be used.

[0370] Next, an example of the operation of external correction of the pixel 5311 shown in FIG. 22(A) will be described.

[0371] FIG. 22B shows a wiring GLa and a wiring GLb connected to the pixel 5311 shown in FIG. 22A. , the potential of the wiring GLc, the wiring GLd, and the potential of the image signal Sig supplied to the wiring SL. The timing chart shown in FIG. 22(B) is an example of the timing chart shown in FIG. A) shows an example in which all transistors included in the pixel 5311 are n-channel transistors. This is what is done.

[0372] First, in a period t1, a high-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the wiring GLc is applied to the wiring GLd, a low-level potential is applied to the wiring GLc, and a high-level potential is applied to the wiring GLd. Therefore, the transistors 5319, 5316, and The transistor 5320 is turned on and the transistor 5317 is turned off. The potential Vdata of the image signal Sig is applied to L. The potential Vd is applied to the gate of the transistor 5315 through the resistor 5319. The value of the drain current of the transistor 5315 is determined according to the ata. The potential Vano is applied to the wiring VL, and the potential V1 is applied to the wiring RL. The drain current flows through the transistor 5316 and the transistor 5320 to the wiring VL. It flows between the wiring RL.

[0373] The potential Vano is a potential obtained by adding the threshold voltage Vthe of the light emitting element 5314 to the potential Vcat. The potential Vano of the wiring VL is preferably set to be higher than the potential Vano of the transistor 5316. The other of the source and drain of the transistor 5315 is connected to the wiring The potential V1 applied to RL is applied to the solenoid of the transistor 5315 via the transistor 5320. A potential Vcat is applied to the line CL.

[0374] The potential V1 is obtained by subtracting the threshold voltage Vth of the transistor 5315 from the potential V0. During the period t1, the potential V1 is set to be sufficiently lower than the potential Vcat. The potential can be made sufficiently lower than the potential obtained by subtracting the threshold voltage Vthe of the light emitting element 5314. Therefore, the light emitting element 5314 does not emit light.

[0375] Next, in a period t2, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A low-level potential is applied to the wiring GLc, a low-level potential is applied to the wiring GLd, Therefore, the transistor 5316 is turned on, and the transistor 53 19, transistor 5317 and transistor 5320 are turned off. 319 is turned off, the potential Vdata is Retained.

[0376] A potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. Therefore, the drain current of the transistor 5315, whose value is determined in the period t1, When the transistor 5320 is turned off, the light is supplied to the light emitting element 5314. The luminance of the light emitting element 5314 is determined by supplying the drain current to the light emitting element 5314. , and the luminance is maintained for a period t2.

[0377] Next, in a period t3, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A high-level potential is applied to the wiring GLc, a low-level potential is applied to the wiring GLd, and Therefore, the transistor 5317 is turned on, and the transistor 53 19, the transistor 5316 and the transistor 5320 are turned off. A potential Vcat is applied to the wiring ML. A potential Vano is applied to the wiring ML. and connected to a monitor circuit.

[0378] By the above operation, the drain current of the transistor 5315 is is supplied to the wiring ML. The drain current is monitored via the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to A signal including the value of the rain current as information is generated. In the device, the potential Vdata of the image signal Sig supplied to the pixel 5311 is set by using the signal. The value of can be corrected.

[0379] In the light-emitting device having the pixel 5311 shown in FIG. 22A, after the operation in the period t2, For example, in a light emitting device, the operation from the period t1 to the period t2 may not be performed. After repeating the operation several times, the operation in the period t3 may be performed. After the operation of the element 5311 during the period t3, the image signal corresponding to the minimum gradation value 0 is By writing to the pixels 5311 in one row where this operation has been performed, the light emitting element 5314 is set to a non-light emitting state. After the pixel 5311 in the next row is set to the dummy state, the operation for the period t3 may be performed.

[0380] In addition, in the pixel 5311 shown in FIG. 22(A), the light emitting element 5314 is degraded and the light emitting element 5314 is no longer emitting light. Even if the resistance value between the anode and cathode of the element 5314 varies between pixels, the potential Vdata can be transferred to the transistor. When applying a voltage to the gate of transistor 5315, the potential of the source of transistor 5315 is set to a predetermined voltage. Therefore, the luminance of the light emitting element 5314 can be set to V1. This can prevent the occurrence of stains.

[0381] <Modification 4 of the Light-Emitting Device> Also, for example, FIG. 23(A) is a diagram showing an example of a pixel circuit. An example using six n-channel transistors and one capacitor will be shown.

[0382] FIG. 23A shows an example of a circuit diagram of the pixel 5411. The pixel 5411 includes a transistor 5 415, a transistor 5416, a transistor 5417, a capacitor element 5418, and a Photoelement 5414, transistor 5440, transistor 5441, and transistor 5 442 and has.

[0383] The pixel electrode of the light emitting element 5414 is turned on in accordance with the image signal Sig input to the pixel 5411. The luminance of the light emitting element 5414 is controlled by controlling the potential difference between the pixel electrode and the common electrode. It is determined by.

[0384] The transistor 5440 is connected between the wiring SL and one of the pair of electrodes of the capacitor 5418. The other of the pair of electrodes of the capacitor 5418 has a function of controlling conduction between the This is connected to one of the source and drain of the transistor 5415. 6 has a function of controlling the conduction state between the wiring VL1 and the gate of the transistor 5415. The transistor 5441 has one of a pair of electrodes of the capacitor 5418 and a The transistor 54 has a function of controlling the conduction state between the gate of the transistor 54 and the gate of the transistor 54. 42 is a connection between one of the source and drain of the transistor 5415 and the positive electrode of the light emitting element 5414. The transistor 5417 has a function of controlling the conduction state between the transistor 5417 and the The transistor 415 has a function of controlling the conduction state between one of the source and drain of the transistor 415 and the wiring ML. do.

[0385] Furthermore, in FIG. 23A, the other of the source and drain of the transistor 5415 is connected to a wiring. It is connected to VL.

[0386] The selection of whether the transistor 5440 is on or off is determined by the This is done according to the potential of the wiring GLa connected to the gate. The on / off selection is performed by the wiring GLa connected to the gate of the transistor 5416. The selection of whether the transistor 5441 is on or off is performed according to the potential. This is done according to the potential of the wiring GLb connected to the gate of the transistor 5441. The on or off selection of the transistor 5442 is performed by connecting the gate of the transistor 5442. The on / off state of the transistor 5417 is controlled by the potential of the wiring GLb connected to the transistor 5417. The selection of whether or not the transistor 5417 is turned on is determined by the potential of the wiring GLc connected to the gate of the transistor 5417. This is carried out in the following manner.

[0387] FIG. 23B shows the wiring GLa and the wiring GLb connected to the pixel 5411 shown in FIG. 23A. , the timing chart of the potential of the line GLc and the potential of the image signal Sig supplied to the line SL The timing chart shown in FIG. 23(B) is the same as the timing chart shown in FIG. 23(A). This is an example in which all the transistors included in the element 5411 are n-channel type. .

[0388] First, in a period t1, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of high level is applied to the wiring GLc. The transistor 5441, the transistor 5442 and the transistor 5417 are turned on, and the transistor Transistor 5440 and transistor 5416 are turned off. Transistor 5442 and transistor When the transistor 5417 is turned on, the source and drain of the transistor 5415 and the other of the pair of electrodes of the capacitor 5418 (illustrated as node A). The potential V0 of the wiring ML is applied to

[0389] A potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The potential Vano is higher than the potential obtained by adding the threshold voltage Vthe of the light emitting element 5414 to the potential V0. It is preferable that the potential V0 is higher than the potential Vcat. It is preferable that the potential V0 is set to the above value, which is lower than the potential obtained by adding the threshold voltage Vthe. By setting the value, it is possible to prevent current from flowing to the light-emitting element 5414 during the period t1. .

[0390] Next, a low-level potential is applied to the wiring GLb, and the transistors 5441 and Transistor 5442 is turned off and node A is held at potential V0.

[0391] Next, in a period t2, a high-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A potential of the transistor GLc is applied to the wiring GLd, and a low-level potential is applied to the wiring GLc. Transistor 5440 and transistor 5416 are turned on, and transistor 5441 and transistor 5442 and transistor 5417 are turned off.

[0392] When the period t1 is changed to the period t2, the potential applied to the wiring GLa is changed from low level to high level. After switching to the high level, the potential applied to the wiring GLc is switched from high to low. By performing such an operation, the voltage applied to the wiring GLa is This can prevent fluctuations in the potential of node A due to potential switching.

[0393] A potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL. The line SL is supplied with a potential Vdata of the image signal Sig, and the line VL1 is supplied with a potential The potential V1 is the threshold voltage V of the transistor 5415. The potential Vano is higher than the potential obtained by adding th, and the threshold voltage V of the transistor 5415 It is preferable that the potential is lower than the potential obtained by adding th.

[0394] In the pixel configuration shown in FIG. 23A, the potential V1 is set to the threshold voltage of the light-emitting element 5414. Even if Vthe is made higher than the value added to the potential Vcat, the transistor 5442 is turned off. Therefore, the range of values that can be set as the potential V0 is This makes it possible to widen the range of values that can be taken as V1-V0. Therefore, the degree of freedom in setting the value of V1-V0 increases, and the threshold of transistor 5415 When the time required to acquire the threshold voltage is shortened or when there is a limit to the period for acquiring the threshold voltage, Even in this case, the threshold voltage of the transistor 5415 can be accurately obtained. do.

[0395] By the above operation, a node B is applied to the gate of the transistor 5415. A potential V1 higher than the potential obtained by adding the threshold voltage to the potential of node A is input, and the transistor Therefore, the voltage of the capacitor 5418 is turned on through the transistor 5415. The charge is released, and the potential of node A, which was at potential V0, begins to rise. The potential of node A converges to V1-Vth, and the gate voltage of transistor 5415 reaches the threshold voltage Once Vth is reached, transistor 5415 turns off.

[0396] One of the pair of electrodes of the capacitor 5418 (depicted as a node C) has a The potential Vdata of the image signal Sig applied to the wiring SL is input to the transistor 5440. and is given.

[0397] Next, in a period t3, a low-level potential is applied to the wiring GLa, and a high-level potential is applied to the wiring GLb. A potential of the transistor GLc is applied to the wiring GLd, and a low-level potential is applied to the wiring GLc. The transistor 5441 and the transistor 5442 are turned on, and the transistor 5440 and the transistor The transistor 5416 and the transistor 5417 are turned off.

[0398] When the period t2 shifts to the period t3, the potential applied to the wiring GLa changes from high to low. After the potential applied to the wiring GLb is changed from low to high, With the above configuration, it is preferable to switch the potential applied to the wiring GLa. Fluctuations in the potential at node A can be prevented.

[0399] A potential Vano is applied to the wiring VL, and a potential Vcat is applied to the wiring CL.

[0400] By the above operation, the potential Vdata is applied to the node B, and the The gate voltage is Vdata-V1+Vth. The voltage can be set to a value that takes into account the threshold voltage Vth. It is possible to suppress variations in the threshold voltage Vth of the transistor 5415. Therefore, the variation in the current value supplied to the light emitting element 5414 can be suppressed, and the brightness of the light emitting device can be improved. This can reduce noise.

[0401] Note that by increasing the fluctuation of the potential applied to the wiring GLb, Preventing variations in threshold voltage from affecting the current value supplied to the light emitting element 5414 That is, the high-level potential applied to the wiring GLb can be The low-level potential applied to the line GLb is sufficiently higher than the threshold voltage. By making the threshold voltage of the transistor 5442 sufficiently smaller than the threshold voltage of the transistor 5442, It ensures on / off switching and minimizes the variation in the threshold voltage of transistor 5442. This can prevent the current value of the light emitting element 5414 from being affected.

[0402] Next, in a period t4, a low-level potential is applied to the wiring GLa, and a low-level potential is applied to the wiring GLb. A potential of high level is applied to the wiring GLc. The transistor 5417 is turned on, and the transistor 5416, the transistor 5440, and the transistor 5441 and transistor 5442 are turned off.

[0403] A potential Vano is applied to the wiring VL, and the wiring ML is connected to the monitor circuit.

[0404] By the above operation, the drain current Id of the transistor 5415 flows through the light emitting element 5414. The monitor circuit does not flow to the wiring ML but flows to the wiring ML via the transistor 5417. The drain current Id is used to generate a signal containing the value of the drain current Id as information. This drain current Id depends on the mobility of the transistor 5415 and the The size depends on the size (channel length, channel width, etc.). In the light emitting device according to one aspect of the present invention, the image signal S supplied to the pixel 5411 is generated using the signal. The value of the potential Vdata of the ig can be corrected. The influence of variations in mobility can be reduced.

[0405] In the light-emitting device having the pixel 5411 shown in FIG. 23A, the expected For example, in a light emitting device, the operation from the period t1 to the period t3 may be omitted. After repeating the operation several times, the operation in the period t4 may be performed. After the operation of the element 5411 during the period t4, the image signal corresponding to the minimum gradation value 0 is By writing to the pixels 5411 in one row where this operation has been performed, the light emitting element 5414 is set to a non-light emitting state. After the pixel 5411 in the next row is set to the dummy state, the operation for the period t4 may be performed.

[0406] In the light-emitting device having the pixel 5411 shown in FIG. 23A, the source of the transistor 5415 The other of the source and drain is electrically isolated from the gate of transistor 5415. Therefore, during the period t2, the potentials of the transistors 1 and 2 can be controlled individually. The potential of the other of the source and drain of the transistor 5415 is connected to the gate of the transistor 5415. The potential can be set to a value higher than the potential obtained by adding the threshold voltage Vth to the potential. Therefore, when the transistor 5415 is normally on, that is, when the threshold voltage Vt When h has a negative value, the source potential of the transistor 5415 is Charge can be stored in the capacitor 5418 until the potential becomes higher than the gate potential V1. Therefore, in the light-emitting device according to one embodiment of the present invention, the transistor 5415 is normally on. Even if the threshold voltage Vth is not obtained during the period t2, the threshold voltage Vth is obtained during the period t3. Thus, the gate voltage can be set according to the obtained threshold voltage Vth.

[0407] Therefore, in the light-emitting device according to one embodiment of the present invention, the transistor 5415 is normally on. Even if this occurs, display unevenness can be reduced and high-quality display can be achieved.

[0408] In addition to the characteristics of the transistor 5415, the characteristics of the light-emitting element 5414 are also monitored. At this time, by controlling the potential of the potential Vdata of the image signal Sig, It is preferable that no current flows through the transistor 5415. As a result, the current of the light emitting element 5414 can be extracted. It is possible to obtain the state of characteristic degradation and variation.

[0409] For example, in this specification and the like, the term "display element," "display device having a display element," "light emitting element," "light emitting device," "light emitting element ... A light-emitting device, which is a device having a light-emitting element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element or the light-emitting device may include, for example, For example, EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), L ED (white LED, red LED, green LED, blue LED, etc.), transistor (current transistors that emit light in response to light), electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices, Grating light valve (GLV), plasma display panel (PDP), ME Display elements using MS (microelectromechanical systems), digital microphones Chromatic mirror device (DMD), DMS (digital micro shutter), IMOD (Interference modulation) element, shutter-type MEMS display element , optical interference type MEMS display element, electrowetting element, piezoelectric ceramic display The display device has at least one of a display element using a spray, a carbon nanotube, or the like. In addition to these, contrast, brightness, reflectance, and transmittance can also be controlled by electrical or magnetic effects. The display device may have a display medium in which the ratio of light emitted from the light emitting diode (EL) element to light emitted from the light emitting diode (EL element) changes. Examples of display devices using electron-emitting devices include EL displays. Field Emission Display (FED) or Single Emission Display (SED) D:Surface-conduction Electron-emitter Di An example of a display device using liquid crystal elements is a liquid crystal display. (Transmissive LCD, Semi-transmissive LCD, Reflective LCD, Direct View LCDs (e.g., LCDs with projection), electronic ink or electrophoresis An example of a display device using the element is electronic paper. When realizing a reflective LCD or a reflective type LCD, some or all of the pixel electrodes For example, a part or all of the pixel electrode may be formed as a reflective electrode. In this case, the reflective electrode may be made of aluminum, silver, or the like. It is also possible to provide a memory circuit such as an SRAM in the memory. This will further reduce power consumption. can be reduced.

[0410] In addition, if the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is white light (W ) to display full color on the display device, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B) Yellow (Y) and other colors can be used in combination as appropriate. The color reproducibility can be improved compared to when no color layer is used. By arranging a region having a colored layer and a region not having a colored layer, the region not having a colored layer can be The white light in the region may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the light emission by about 30%. When using elements to display full color, R, G, B, Y, and W are each represented by a light emitting element. By using a self-luminous element, it is possible to make the light emitted from an element that is not a colored layer. However, power consumption may be further reduced.

[0411] <Pixel structure of light-emitting device> An example of a pixel structure of a light-emitting device according to one embodiment of the present invention will be described below.

[0412] In FIG. 24A, a plurality of transistors 500 (also referred to as FETs) are formed on a substrate 502. Each transistor 500 is connected to each light emitting element (5 Specifically, each The transistor 500 is electrically connected to a conductor 506 of the light-emitting element. The light-emitting element is composed of a conductor 506, a conductor 507, a light-emitting layer 510, and a conductor 512. It should be noted that among the light emitting elements, the light emitting element 504W may not be included. FIG. 24(B) is an enlarged cross-sectional view of region 520 in FIG. 24(A).

[0413] In addition, colored layers (514R, 514G, 514B, 514W) are provided on each light-emitting element. In FIG. 24(A), the colored layer is disposed on the substrate 516. However, the present invention is not limited to this structure. For example, the colored layer may be provided on the substrate 502. In addition, a sealing film 518 is disposed between the substrate 502 and the substrate 516. The sealing film 518 is made of, for example, glass frit or two-component mixed resin. It is possible to use resins that harden at room temperature, such as photocurable resins, and thermosetting resins. Cut.

[0414] In addition, a separator is provided between adjacent light emitting elements so as to cover the ends of the conductors 506 and 507. A wall 508 is provided. A spacer 509 is provided on the partition wall 508. The conductor 506 is a region that functions as a reflective electrode and as an anode of the light-emitting element. The conductor 507 has a region that contributes to adjusting the optical path length of each light-emitting element. In addition, a light-emitting layer 510 is formed on the conductor 507. A conductor 512 is formed on the surface of the conductive layer 512. The conductor 512 functions as a semi-transmissive and semi-reflective electrode. The spacer 5 has a region that functions as a cathode of the light-emitting element and a region that functions as a cathode of the light-emitting element. 09 is disposed between the light emitting element and the colored layer.

[0415] The light-emitting layer 510 may be common to each light-emitting element. Each light-emitting element may have a different structure. This creates a micro-optical resonator (also called a microcavity) that resonates the light emitted from the light-emitting layer 510. Even if the same light emitting layer 510 is used, light of different wavelengths can be extracted by narrowing the line width. Specifically, each light emitting element can be formed by a conductor 510 provided below the light emitting layer 510. By adjusting the thickness of each of the layers 510, the spectrum obtained from the light-emitting layer 510 can be adjusted as desired. Therefore, the desired emission spectrum can be obtained, and light emission with high color purity can be obtained. By using the configuration shown in A), for example, the process of painting different colors becomes unnecessary, and high definition can be achieved. However, in the light-emitting device according to one embodiment of the present invention, it may be easy to realize each light-emitting element. The light-emitting layer may be coated separately on the element.

[0416] The light emitting device shown in FIG. 24(A) has a microcavity structure that narrows the line width of the different By passing the light of a wavelength different from the wavelength of the light through the colored layer, the line width is further narrowed to obtain the desired emission spectrum. Therefore, the microcavity structure and the colored layer are By combining these elements, it is possible to obtain light emission with even higher color purity. The light path length of the light emitting element 504R is adjusted so that red light can be emitted, and the colored layer 5 Red light is emitted in the direction of the arrow through light emitting element 14R. The optical path length of the light emitting element is adjusted so that light can be obtained. The light emitting element 504B emits green light in the direction of the arrow A. The light emitting element 504B emits blue light in the direction of the arrow B. The optical path length of the optical element is adjusted, and blue light is emitted in the direction of the arrow through the colored layer 514B. In addition, the light-emitting element 504W has an optical path length adjusted so as to obtain white light emission. White light is emitted in the direction of the arrow through the colored layer 514W.

[0417] The method for adjusting the optical path length of each light-emitting element is not limited to this. In the device, the thickness of the light-emitting layer 510 may be adjusted to adjust the optical path length.

[0418] The colored layers (514R, 514G, 514B) are made of a material that transmits light in a specific wavelength range. For example, a red (R) colored layer that transmits light in the red wavelength band may be used. , a green (G) colored layer that transmits light in the green wavelength band, and a blue (B) colored layer that transmits light in the blue wavelength band. The colored layer 514W may be, for example, a colored layer of color (B). An acrylic resin material that does not contain pigments may be used. The colored layer can be formed by using a printing method, an inkjet method, or a photolithography process. The desired shape can be formed by the above method.

[0419] The conductor 506 is, for example, a material with high reflectivity (visible light reflectivity of 40% or more and 100% or more). The conductor 506 can be made of metal (preferably 70% or more and 100% or less). For example, aluminum, silver, or alloys containing these metallic materials (e.g., silver and palladium) A single layer or a laminated layer of a metal-copper alloy can be used.

[0420] The conductor 507 can be formed using, for example, a conductive metal oxide. Conductive metal oxides include indium oxide, tin oxide, zinc oxide, and indium tin oxide. oxide, indium zinc oxide, or these metal oxides with silicon or tungsten By providing the conductor 507, it is possible to form the Therefore, the formation of an insulator between the light-emitting layer 510 and the conductor 506 can be suppressed. In addition, the conductive material 507 is preferably used as the conductive material 506. The metal oxide may be formed.

[0421] The conductor 512 may be a conductive material having reflectivity and a conductive material having light-transmitting properties. and the reflectance of visible light is 20% or more and 80% or less, preferably 40% or more and 70% or less. The conductor 512 is preferably made of, for example, silver, magnesium, or the like. An alloy containing these metal materials is formed thinly (for example, 1 nm to 10 nm), and then A conductive metal oxide that can be used for the conductor 507 may be formed.

[0422] In the configuration described above, the structure in which light is extracted to the substrate 516 side (top emission) The light emitting device has a structure in which light is emitted to the substrate 501 on which the transistor 500 is formed. a bottom emission structure, or both the substrate 501 and the substrate 516 The light emitting device may have a structure in which light is extracted (dual emission structure). In the case of a junction structure, for example, the colored layers (514R, 514G, 514B, 514W) are made conductive. The substrate on the light emitting side may be formed with a light-transmitting The substrate on the side from which light is not emitted may be a light-transmitting substrate or a light-shielding substrate. can be used.

[0423] <module> A display module using a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG. The explanation will be given using

[0424] The display module 8000 shown in FIG. 25 is made up of an upper cover 8001 and a lower cover 8002. In between, touch panel 8004 connected to FPC8003, and touch panel 8005 connected to FPC8005 Cell 8006, backlight unit 8007, frame 8009, printed circuit board 801 0, and a battery 8011. 011, the touch panel 8004 may not be provided.

[0425] The semiconductor device according to one embodiment of the present invention can be used for the cell 8006, for example.

[0426] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the cell 80 The shape and dimensions can be changed as needed to fit the size of 06.

[0427] The touch panel 8004 is a resistive or capacitive touch panel. The cell 8006 can be used by being superimposed on the opposite substrate (sealing substrate). It is also possible to provide a panel function. It is also possible to provide an optical sensor to make it an optical touch panel. It is also possible to provide a touch sensor electrode in each pixel of the 6 to create a capacitive touch panel. It is possible.

[0428] The backlight unit 8007 includes a light source 8008. It may be provided at the end of the unit 8007 and configured to use a light diffusion plate.

[0429] The frame 8009 not only protects the cell 8006 but also operates the printed circuit board 8010. It may also have a function as an electromagnetic shield to block the generated electromagnetic waves. The frame 8009 may also function as a heat sink.

[0430] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. In this case, the battery 8011 may not be required.

[0431] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided in addition.

[0432] <Circuit> An example of a circuit configuration that can be realized using a semiconductor device of one embodiment of the present invention will be described below. Reveal.

[0433] The circuit diagram shown in FIG. 26(A) includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected, so-called CMO The figure shows the configuration of an S inverter. The transistor 150 described above may be used as 00.

[0434] The circuit diagram shown in FIG. 26(B) is that of the transistor 2100 and the transistor 2200. The figure shows a configuration in which the source and drain of each transistor are connected. It can function as a so-called CMOS analog switch.

[0435] A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can be stored and has no limit on the number of times it can be written is shown in FIG. Shown below.

[0436] The semiconductor device shown in FIG. 27A includes a transistor 3200 using a first semiconductor and a second The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 can be the transistor 150 described above.

[0437] The transistor 3300 is, for example, a transistor including an oxide semiconductor. The low off-state current of the STAR 3300 allows for long-term storage of specific nodes in the semiconductor device. It is possible to retain the stored contents, i.e., no refresh operation is required, and This allows for extremely low frequency refresh operations, resulting in low power consumption. It becomes a conductor device.

[0438] In FIG. 27A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400. For 0, the above-mentioned capacitive element 160 can be used.

[0439] The semiconductor device shown in FIG. 27A can hold the potential of the gate of the transistor 3200. This property makes it possible to write, store, and read information, as shown below. do.

[0440] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which it becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the capacitor The signal is applied to a node FG electrically connected to one of the electrodes of the capacitance element 3400. A predetermined charge is applied to the gate of the transistor 3200 (write). The charges that give two different potential levels (hereinafter referred to as low-level charge and high-level charge) ) is given. After that, the potential of the fourth wiring 3004 is The transistor 3300 is set to a potential at which it is turned off, thereby turning the transistor 3300 off. As a result, charges are held (retained) at the node FG.

[0441] Since the off-state current of the transistor 3300 is extremely small, the charge of the node FG is maintained for a long period of time. It is held as such.

[0442] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the second wiring 3002 takes a potential according to the amount of charge held in the node FG. If 3200 is an n-channel type, a high level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 Apparent threshold voltage V when a low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it "conductive." The potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential V0 between For example, in a write operation, the charge applied to node FG can be determined. When a high level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 is in a "conducting state." Meanwhile, the node FG When a low level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. It can be put out.

[0443] When memory cells are arranged in an array, the information of the desired memory cell is read. In order to prevent the information of other memory cells from being read, A potential at which transistor 3200 is in a "non-conducting state" regardless of the charge applied to FG. , that is, V th_H A lower potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 is in a "conducting state" regardless of the charge applied to the FG. , that is, V th_L A higher potential may be applied to the fifth wiring 3005 .

[0444] The semiconductor device shown in FIG. 27B differs from the semiconductor device shown in FIG. 27A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This makes it possible to write and retain information.

[0445] The reading of data from the semiconductor device shown in FIG. When the capacitor 3300 is brought into a conductive state, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is determined by the capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0446] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the third The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 takes two states, V1 and V0 (V1>V0), , the potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+C×V 1) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (= It can be seen that it is higher than (CB×VB0+C×V0) / (CB+C)).

[0447] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0448] In this case, the transistor to which the first semiconductor is applied is used in a drive circuit for driving the memory cell. A transistor to which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the drive circuit.

[0449] The semiconductor device described above is a transistor using an oxide semiconductor and having extremely low off-state current. By applying this, it is possible to retain the memory contents for a long period of time. Refresh operations are no longer necessary, or the frequency of refresh operations can be reduced significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if there is no potential (however, it is preferable that the potential is fixed), It is possible to retain the stored contents.

[0450] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional nonvolatile memory, injection of electrons into the floating gate Since electrons are not introduced or extracted from the floating gate, there is no risk of insulator degradation. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as the conventional nonvolatile memory. There is no limit to the number of times it can be rewritten, which is a problem with semiconductors, and reliability has been dramatically improved. Furthermore, information can be written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0451] <RFタグ> In the following, the RF tag including the above-mentioned transistor or memory device will be explained using FIG. 28. and explain.

[0452] The RF tag according to one embodiment of the present invention has a memory circuit therein, stores information in the memory circuit, and It uses contact means, such as wireless communication, to exchange information with the outside world. RF tags are used for individual authentication to identify items by reading their individual information. It is possible to use it in systems such as these. Sex is required.

[0453] The structure of an RF tag will be described with reference to Fig. 28. Fig. 28 is a block diagram showing an example of the structure of an RF tag. FIG.

[0454] As shown in FIG. 28, an RF tag 800 includes a communicator 801 (also known as an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 808. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that the semiconductor of the transistor exhibiting the rectification action included in the demodulation circuit 807 has a reverse current For example, an oxide semiconductor may be used, which can sufficiently suppress the reverse polarity. This suppresses the degradation of rectification caused by directional current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linearity. The data transmission format is an electromagnetic wave in which a pair of coils are placed opposite each other and communication is carried out by mutual induction. Coupling method, electromagnetic induction method that communicates using an induced electromagnetic field, radio wave method that communicates using radio waves The RF tag 800 can be used in any of these methods.

[0455] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 rectifies an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential. The limiter circuit is a circuit for limiting the amplitude of an input AC signal when the amplitude of the input AC signal is large. When the internally generated voltage is large, the power above a certain level is controlled so as not to be input to the subsequent circuit. This is a circuit for

[0456] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the rising edge of the stable power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0457] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation based on the

[0458] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. It is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for

[0459] The above-mentioned circuits can be selected or omitted as appropriate.

[0460] Here, the above-described memory device can be used for the memory circuit 810. Such a storage device is suitable for RF tags because it can retain information even when the power is cut off. Furthermore, the memory device according to one embodiment of the present invention is suitable for reducing the power required for writing data (power The maximum communication voltage when reading and writing data is lower than that of conventional non-volatile memory. It is also possible to prevent the difference in transmission distance. As a result, malfunctions or erroneous writing can be prevented.

[0461] Furthermore, the memory device according to one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the manufacturer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable to do so. The producer ships the product after writing the unique number before shipment Rather than assigning unique numbers to all the manufactured RF tags, it is possible to assign unique numbers to only the good products to be shipped, so that the unique numbers of the products after shipment are not discontinuous, and customer management corresponding to the products after shipment becomes easy.

[0462] <Examples of use of RF tags> Hereinafter, an example of use of an RF tag according to one aspect of the present invention will be described with reference to FIG. 29. R The uses of RF tags are widespread. For example, banknotes, coins, securities, bearer bonds, certificates (driver's licenses, residence certificates, etc., see FIG. 29(A)), packaging containers (wrapping paper, bottles, etc., see FIG. 29(C)), recording media (DVDs, video tapes, etc., see FIG. 29(B)), vehicles (bicycles, etc., see FIG. 29(D)), personal belongings (bags, glasses, etc.), food products, plants , animals, the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal displays , EL display devices, television devices, or mobile phones), etc., or tags (see FIGS. 29(E) and 29(F)) attached to each article can be provided and used.

[0463] The RF tag 4000 according to one aspect of the present invention is fixed to an article by being pasted on or embedded in the surface. For example, if it is a book, it is embedded in the paper, and if it is a package made of an organic resin , it is embedded inside the organic resin and fixed to each article. The RF tag 4000 according to one aspect of the present invention is small, thin, and lightweight, so that even after being fixed to an article, it does not impair the designability of the article itself. Also, banknotes, coins, securities, bearer bonds, or certificates ​​​​The RF tag 4000 according to one embodiment of the present invention can provide authentication functionality to the items, etc. By utilizing this authentication function, it is possible to prevent counterfeiting. The present invention relates to one aspect of the present invention, which is applied to the body, personal belongings, food, clothing, household goods, electronic devices, etc. By attaching RF tags 4000, the efficiency of systems such as inspection systems can be improved. Furthermore, even in the case of vehicles, the RF tag 4000 according to one aspect of the present invention can be attached. By attaching the device, security against theft and the like can be improved.

[0464] As described above, the RF tag according to one aspect of the present invention can be used for the above-mentioned purposes. can.

[0465] <cpu> The following describes a CPU including semiconductor devices such as the above-mentioned transistors and the above-mentioned memory devices. and explain.

[0466] FIG. 30 is a block diagram showing the configuration of an example of a CPU that uses the above-mentioned transistor in part. be.

[0467] The CPU shown in FIG. 30 includes an ALU 1191 (ALU: Arithmetic) on a board 1190. ic logic unit, arithmetic circuit), ALU controller 1192, instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI substrate, The ROM 1199 and ROM interface 1189 are Of course, the CPU shown in FIG. 30 is shown in a simplified form. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 30 is considered as one core, and a configuration including multiple such cores is considered as one core. It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by a circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, 64 bits, It can be a bit or the like.

[0468] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0469] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0470] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to various circuits.

[0471] In the CPU shown in FIG. 30, a memory cell is provided in the register 1196. The memory cell 1196 uses the above-described transistor 150, capacitor element 160, etc. It is possible.

[0472] In the CPU shown in FIG. 30, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, the power supply voltage is applied to the memory cells in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped. .

[0473] FIG. 31 is a circuit diagram of an example storage element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 that prevents stored data from volatilizing when turned off, a switch 1203, and a switch 1204. , a logic element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. 10. The memory element 1200 may include a diode, a resistor, It may further include other elements such as an inductor.

[0474] Here, the above-described memory device can be used for the circuit 1202. When the supply of power supply voltage to the ND (0V) or a potential that turns off the transistor 1209 is continuously input. For example, the gate of the transistor 1209 is configured to be grounded via a load such as a resistor. .

[0475] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the conducting or non-conducting state of transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the transistor 1214. The switch 1204 is connected to the gate of the transistor 1214. The control signal RD input to the first terminal determines whether or not the first terminal is electrically connected to the second terminal. The conducting or non-conducting state of transistor 1214 is selected.

[0476] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The connection point is electrically connected to one of the gate electrodes of the transistor 1210 and the gate of the transistor 1210. The node M2 is connected to the source or drain of the transistor 1210. The other is electrically connected to a wiring (for example, a GND line) that can supply 1203 (one of the source and drain of the transistor 1213) The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the The other terminal of the switch 1204 (one of the source and drain terminals of the transistor 1214) The second terminal of the switch 1204 (the source of the transistor 1214) is electrically connected to the The other of the source and drain terminals is electrically connected to the wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) and the first terminal of the switch 1204 (one of the source and drain of the transistor 1214) ), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207. are electrically connected. Here, the connection point is referred to as node M1. The other of the electrodes may be configured to have a constant potential input thereto. It can be configured so that a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a line that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a line (for example, a GND line). For example, a low power supply potential (such as GND) can be input. ) or a high power supply potential (such as VDD) can be input to the capacitor element 120. The other of the pair of electrodes 8 is connected to a wiring (e.g., GND) that can supply a low power supply potential. The power supply is electrically connected to the power supply line.

[0477] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0478] A control signal WE is input to the gate of the transistor 1209. The switch 1204 is connected between the first terminal and the second terminal by a control signal RD that is different from the control signal WE. The conduction or non-conduction state between the first and second terminals of one switch is selected. When the terminals of one switch are in a conductive state, the first and second terminals of the other switch are in a non-conductive state. This becomes:

[0479] The other of the source and drain of the transistor 1209 is connected to a data line held in the circuit 1201. In FIG. 31, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0480] In FIG. 31, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0481] In addition, in FIG. 31, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are made of a film or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a silicon or silicon-based transistor can be used. The memory element 1 can be a transistor in which a channel is formed in a silicon substrate. All the transistors used in 200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include other elements in addition to the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor.

[0482] The circuit 1201 in FIG. 31 can be, for example, a flip-flop circuit. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0483] In the semiconductor device according to one embodiment of the present invention, while power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 1208 in the circuit 1202. It can be held by

[0484] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is The off-state current is significantly smaller than that of a transistor whose channel is formed in silicon. Therefore, by using this transistor as the transistor 1209, the memory element 12 Even when power supply voltage is not supplied to 00, the signal held in the capacitor 1208 is retained for a long period of time. In this way, the memory element 1200 can maintain its stored contents (data) even when the supply of power supply voltage is stopped. It is possible to hold the data.

[0485] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0486] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the signal held by the capacitor element 1208 is transferred to the state ( The signal can be converted into a conducting state or a non-conducting state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0487] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0488] Although the storage element 1200 has been described as being used as a CPU, the storage element 1200 may also be used as a DSP ( Digital Signal Processor), custom LSI, PLD (Pr LSIs such as programmable logic devices, RF-IDs (Radio Frequency Identification It can also be applied to RF Frequency Identification.

[0489] <Electronic equipment> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices (typically DVD: Digital Versatile Disc) (Devices having a display that can play back recording media such as DVDs and display the images) In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used are Mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0490] FIG. 32A shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908 The portable game machine shown in FIG. 32A has two display units 903 and a display However, the number of display units that the portable game machine has is not limited to this. .

[0491] FIG. 32(B) shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit 9 13, a second display unit 914, a connection unit 915, operation keys 916, etc. The first display unit 911 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. 12. Also, the first display unit 913 and a display having a function as a position input device added to at least one of the first display unit 914 and the second display unit 915. The function as a position input device can be achieved by touching the display device. Alternatively, the function as a position input device can be added by providing a touch panel. By providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device, It is possible.

[0492] FIG. 32C shows a notebook personal computer, which includes a housing 921, a display unit 922, a keyboard, and a keyboard. The computer has a keyboard 923, a pointing device 924, and the like.

[0493] FIG. 32(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 93. He holds the third prize.

[0494] FIG. 32(E) shows a video camera, which includes a first housing 941, a second housing 942, a display unit 943, The operation key 944, the lens 945, the connection part 946, etc. 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 94 at the connection unit 946. 2.

[0495] FIG. 32(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, and a rear view mirror. It has Ito 954 etc.

[0496] <Electronic device with curved display or light-emitting area> Hereinafter, an electronic device having a curved surface in a display area or a light-emitting area will be described as an example of an electronic device according to one aspect of the present invention. The electronic device having the same will be described with reference to FIG. As an example, an information device, particularly a portable information device (portable device) will be described. Examples of information devices with mobility include mobile phones (phablets, smartphones ( This also includes smartphones, tablet devices (slate PCs), etc.

[0497] FIG. 33(A-1) is a perspective view illustrating the external shape of the mobile device 1300A. 33(A-2) is a top view of the portable device 1300A. FIG.

[0498] 33(B-1) and 33(B-2) are perspective views illustrating the external shape of the portable device 1300B. Figure.

[0499] 33(C-1) and 33(C-2) are perspective views illustrating the external shape of the portable device 1300C. Figure.

[0500] <Mobile devices> The portable device 1300A is a device for carrying out functions such as making a phone call, creating and viewing e-mails, and browsing a notebook or other information. It has one or more functions selected from the following:

[0501] The mobile device 1300A has display units provided along multiple surfaces of the housing. The display unit can be provided by arranging a flexible display device along the inside of the housing. This allows text information, image information, etc. to be stored in the first area 1311 and / or the second area 1312. It can be displayed on 1312.

[0502] For example, images for three operations can be displayed in the first area 1311 (see FIG. 33(A-1).) In addition, as shown in the dashed rectangle in the figure, text information etc. is stored in the second area. It can be displayed in area 1312 (see FIG. 33(A-2)).

[0503] When the second region 1312 is placed on the top of the portable device 1300A, the portable device 1300A In the state where the portable device 1300A is stored in the breast pocket of the clothes, the second area 1312 of the portable device 1300A is The user can easily check the displayed text and image information (Figure 33 (A-3) For example, the mobile device 130 may receive the caller's phone number or name. It can be observed from above 0A.

[0504] The portable device 1300A may have an input device between the display device and the housing, in the display device, or on the housing. The input device may include, for example, a touch sensor, a light sensor, an ultrasonic sensor, etc. When the input device is placed between the display device and the housing or on the housing, , matrix switch type, resistive film type, ultrasonic surface acoustic wave type, infrared type, electromagnetic induction type A touch panel of the type using a touch sensor or a capacitance type may be used. When placing the sensor, use an in-cell type sensor or an on-cell type sensor. That's fine.

[0505] The mobile device 1300A includes a vibration sensor and a vibration signal detected by the vibration sensor. It is equipped with a storage device that stores a program that switches to a mode that rejects incoming calls based on vibration. This allows the user to tap and shake the portable device 1300A lightly over the clothes. By applying a signal, the device can be switched to a mode in which incoming calls are rejected.

[0506] The mobile device 1300B has a display unit having a first area 1311 and a second area 1312. The display device 1300 includes a housing 1310 that supports the display unit.

[0507] The housing 1310 has a plurality of bent portions, and the longest bent portion of the housing 1310 is the first region. It is sandwiched between a first region 1311 and a second region 1312 .

[0508] The portable device 1300B has a second region 1312 on the side, which is provided along the longest bend. It can be used towards.

[0509] The mobile device 1300C has a display unit having a first area 1311 and a second area 1312. The display device 1300 includes a housing 1310 that supports the display unit.

[0510] The housing 1310 has a plurality of bends, and the second longest bend of the housing 1310 is The first region 1311 and the second region 1312 are sandwiched between them.

[0511] The portable device 1300C can be used with the second area 1312 facing upward.

[0512] The contents described in the embodiments may be applied or combined with one another. Furthermore, the contents described in the embodiments may be changed in various ways. The content is described using drawings or written statements in the specification. .

[0513] Also, it is possible to combine a part of a figure with another part of that figure and another part of another figure as appropriate. can be used to construct even more diagrams.

[0514] In addition, the content not specified in the figures or text is excluded from the publication. Alternatively, a certain value may be expressed as an upper limit value and a lower limit value. When a range of values is stated, it is not permitted to narrow that range arbitrarily or to By excluding one point in the range, it is possible to define an embodiment of the invention that excludes part of that range. These, for example, can be used to define that prior art does not fall within the technical scope of one aspect of the present invention. It can be determined.

[0515] As a specific example, a circuit diagram using first to fifth transistors in a circuit is shown below. In that case, the circuit does not have a sixth transistor. Alternatively, the circuit may be defined as an invention that does not have a capacitance element. Furthermore, it is possible to specify that the circuit has a specific connection structure. The invention can be configured by specifying that the semiconductor device does not have a sixth transistor. Alternatively, it is specified that the circuit does not have a capacitive element having a specific connection structure. For example, the gate of the first transistor is connected to the gate of the second transistor. It is possible to define the invention as not having a sixth transistor. Alternatively, for example, a capacitor element having a first electrode connected to the gate of the third transistor may be provided. It is possible to define the invention as not having

[0516] As another specific example, for a certain value, for example, "a certain voltage is 3V or more and 10V or less" In that case, for example, if a certain voltage is -2V or more, It is possible to define one aspect of the invention as "excluding cases where the content is V or less." Or, for example, , except when the voltage is 13 V or higher. It is also possible to define the invention as a voltage between 5V and 8V. It is also possible to define the invention so that the voltage is approximately 9V. For example, the voltage is between 3V and 10V, but not including 9V. It is also possible to state that a certain value is "preferably within a certain range." Even if a value is stated as "preferred," it is not limited to that stated value. Even if the document contains a description such as "the document is not limited to such a description," the document is not limited to such a description.

[0517] As another example, regarding a certain value, for example, "it is preferable that a certain voltage is 10V" In that case, for example, if a certain voltage is between -2V and 1V, It is possible to define an aspect of the invention as "except when, for example, a certain voltage is One aspect of the invention can be defined as excluding cases where the voltage is 13V or higher.

[0518] As another example, when describing the properties of a certain substance, for example, "a certain film is an insulating film," In this case, the insulating film is an organic insulating film. It is possible to define one aspect of the invention. Alternatively, for example, the insulating film may be an inorganic insulating film. It is possible to define an aspect of the invention as "except in certain cases." It is possible to define one aspect of the invention as excluding the case where the conductive film is a conductive film. For example, one embodiment of the invention can be defined as excluding the case where the film is a semiconductor film.

[0519] As another example, regarding a certain laminated structure, for example, "a certain film is present between film A and film B" In that case, for example, if the film is a stack of four or more layers, Or, for example, it is possible to define the invention as excluding the case of a film A and its It is possible to define the invention as excluding cases where a conductive film is provided between the film and the .

[0520] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of elements such as capacitors and resistors, the connection destination must be specified. However, a person skilled in the art may be able to compose an aspect of the invention. Even if the destination is not specified, one aspect of the invention can be said to be clear. When the content is described in this specification, etc., one aspect of the invention that does not specify the connection destination is In particular, if the terminal is connected to multiple If multiple locations are expected, the connection destination of the terminal does not need to be limited to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements) By specifying the connection destinations of only some of the terminals possessed by devices such as It may be possible to configure a different embodiment.

[0521] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art. It may be possible for a person skilled in the art to identify an invention. A person skilled in the art may be able to identify an invention by at least specifying the function. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, specifying the connection destination can be considered an aspect of an invention. and can constitute one aspect of the invention. Even if the connection destination of a certain circuit is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an aspect of the invention.

[0522] In this specification, etc., in the drawings or text described in a certain item of the embodiment, It is possible to extract a part of it and use it to form an aspect of the invention. If there is a figure or sentence describing a part of the product, The contents are also disclosed as one aspect of the invention and may constitute one aspect of the invention. Therefore, one aspect of the invention is clear. For example, in a figure or text that describes an active element (such as a transistor or a diode), a wiring, a passive element (such as a capacitor or a resistor), a conductor, an insulator, a semiconductor, an organic substance, an inorganic substance, a component, a device, an operation method, a manufacturing method, etc., it is assumed that a part thereof can be extracted to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is a natural number) circuit elements (such as transistors and capacitor elements), it is possible to extract M (M is a natural number and M < N) circuit elements (such as transistors and capacitor elements) to constitute an aspect of the invention. In another example, from a cross-sectional view composed of N (N is a natural number) layers, it is possible to extract M (M is a natural number and M < N) layers to constitute an aspect of the invention. As yet another example, from a flowchart composed of N (N is a natural number) elements, it is possible to extract M (M is a natural number and M < N) elements to constitute an aspect of the invention. Furthermore, as yet another example, from a sentence that describes "A has B, C, D, E or F", by arbitrarily extracting some elements, inventions such as "A has B and E", "A has E and F", "A has C, E and F", or "A has B, C, D and E" can be constituted as aspects of the invention. Note that in this specification, etc., when at least one specific example is described in the figure or text described in the embodiment, those skilled in the art can easily understand deriving the upper concept of the specific example. Therefore, when at least one specific example is described in the figure or text described in the embodiment, the upper concept of the specific example is also regarded as an aspect of the invention.

[0523] ​​​​​​​​​​​The disclosed invention can be an embodiment of the invention. One aspect of clarity is clarity.

[0524] In this specification, at least the contents shown in the drawings are disclosed as one embodiment of the invention. This can constitute one aspect of the invention. If the content of the invention is described in the drawings, it is considered to be indicative of the invention even if it is not stated in words. This is disclosed as one embodiment and can constitute one embodiment of the invention. Similarly, even a partial view of the drawings is disclosed as one embodiment of the invention. This can constitute one aspect of the invention. And, this aspect of the invention is clear. It can be said that. [Example]

[0525] In this example, a cross-sectional shape of a semiconductor device according to one embodiment of the present invention was measured using a cross-sectional TEM image. I rated it as follows.

[0526] The method for preparing the sample will be described below with reference to FIG. 37. ), and Fig. 37(C) and Fig. 37(D) show cross-sectional TEM images of the sample. ) shows a flowchart of the sample preparation method.

[0527] First, a glass substrate was prepared. Then, a 1000-membrane thin film was deposited on the glass substrate by PECVD. Next, a thick silicon nitride film was formed on the silicon nitride film by the PECVD method. A silicon oxynitride film having a thickness of 400 nm was then formed. A 50 nm thick oxide semiconductor (also referred to as OS) film was formed by the ring method. Then, a silicon oxynitride (S) film with a thickness of 100 nm was deposited on the oxide semiconductor by the PECVD method. Next, a silicon oxynitride film was formed on the silicon oxynitride film by a sputtering method. A tantalum nitride film having a thickness of 30 nm was then formed on the tantalum nitride by sputtering. A tungsten film with a thickness of 150 nm was formed by the etching method.

[0528] The oxide semiconductor film was formed using a target with an atomic ratio of In:Ga:Zn=5:5:6. This was carried out using

[0529] Next, a resist mask was formed on the tungsten (see step S101 in FIG. 37(E)). (Refer to Fig. 37(A) for a cross-sectional TEM image of the sample extracted here.

[0530] Next, a resist mask was used to etch a portion of the tungsten and tantalum nitride. (See step S102 in FIG. 37(E)). The cross-sectional TEM image of the sample extracted here is shown in FIG. 7(B).

[0531] The etching was carried out in three stages. First, the etching was carried out at a flow rate of 160 sccm. Chlorine gas, 320 sccm of sulfur hexafluoride gas, and 80 sccm of oxygen gas were used. The pressure was set to 0.6 Pa, and 250 W (13.56 MHz) was applied to the sample side. By applying 9000W (13.56MHz) to the mating coil-type electrodes, tungsten At this time, the tungsten was not completely etched away, and the tantalum nitride remained. I adjusted the time so that it wouldn't be too exposed.

[0532] Next, in the second step, 320 sccm of chlorine gas and 160 sccm of sulfur hexafluoride gas were added. and 240 sccm oxygen gas, the pressure was set to 0.6 Pa, and 1000 W was connected to the sample side. (13.56MHz) was applied to the coil-type electrode facing the sample. The remaining tungsten was etched by applying a frequency of 0.56 MHz. The etching rate of tantalum nitride is slower than that of tungsten. Therefore, the second stage reduces the variation in the amount of etching within the sample surface. It is possible.

[0533] Next, in the third step, 540 sccm of chlorine gas and 540 sccm of sulfur hexafluoride were added. Using gas, the pressure was set to 3.0 Pa and a 3000 W (1 The tantalum nitride was etched by applying a 3.56 MHz frequency. The etching rate of silicon oxynitride is slower than that of tantalum. This reduces the variation in the amount of etching within the sample surface. The step etching was carried out with the temperature of the sample-side electrode set to 80°C.

[0534] In this manner, the tungsten and part of the tantalum nitride were etched.

[0535] Next, a resist mask, tungsten and tantalum nitride are used as masks, and oxidation is performed. Etching a portion of the silicon nitride and removing the edge of the tungsten and tantalum nitride The groove was machined so that it had a taper angle (see step S103 in FIG. 37(E)). A cross-sectional TEM image of the extracted sample is shown in FIG. 37(C).

[0536] The etching conditions were 240 sccm of carbon tetrafluoride gas and 160 sccm of Using oxygen gas, the pressure was set to 0.8 Pa, and 1000 W (13.56 MHz) was applied to the sample side. A voltage of 7000 W (13.56 MHz) was applied to the coil-type electrode facing the sample. The silicon oxynitride was etched by this etching. The etching rate of the oxide semiconductor is slower than the etching rate. The etching can reduce variations in the amount of etching. The temperature at the pole was set at 10°C.

[0537] From Figure 37(C), the taper angle between the top surface of the tantalum nitride and the side surface of the tungsten is The angle was about 40°. Also, because of the top surface of the silicon oxynitride and the side surface of the tantalum nitride, The taper angle was approximately 31°. The taper angle between the side of and was approximately 84°.

[0538] The cross-sectional shape shown in FIG. 37(C) corresponds to the cross-sectional shape shown in FIG. The silicon oxynitride shown in 37(C) corresponds to the insulator 112 shown in FIG. The tantalum nitride shown in FIG. 7(C) corresponds to the conductor 114a shown in FIG. 16. The tungsten shown in C) corresponds to the conductor 114b shown in FIG.

[0539] The sample in FIG. 37(C) was further treated with 240 sccm of carbon tetrafluoride gas and Using 160 sccm of oxygen gas, the pressure was set to 0.8 Pa, and a 1000 W (13 A power of 7000 W (13.56 MHz) was applied to the coil-type electrode facing the sample. The silicon oxynitride was etched by applying a voltage of 1000 MHz. The etching rate of the oxide semiconductor must be slower than the etching rate of silicon. Therefore, it is possible to reduce variations in the amount of etching within the sample surface. The temperature of the electrode on the sample side was set to 10°C.

[0540] From the relationship between the etching rates of silicon oxynitride, tantalum nitride, and tungsten, The edge of the silicon oxynitride becomes arc-shaped, and the tantalum nitride protrudes from the tungsten. The shape becomes as shown in FIG. 37(E), step S104.

[0541] Then, silicon nitride with a thickness of 100 nm and silicon oxynitride with a thickness of 300 nm were formed. A cross-sectional TEM image of the coated sample is shown in Figure 37(D).

[0542] From Figure 37(D), the taper angle between the top surface of the tantalum nitride and the side surface of the tungsten is The angle was approximately 82°. Also, due to the top surface of the silicon oxynitride and the side surface of the tantalum nitride, The taper angle was approximately 23°. The taper angle between the side of and was approximately 55°. [Explanation of symbols]

[0543] 100 boards 101 Insulator 102 Insulator 102a Insulator 102b Insulator 104 Conductors 104a Electric conductor 104a1 Conductors 104a2 conductor 104b Conductor 104b1 Electric conductor 104b2 Conductor 104c conductor 104d Conductors 104e Conductor 104f Conductor 106 Semiconductors 106a Semiconductors 106b Semiconductors 106c Semiconductor 107a area 107a1 area 107a2 area 107a3 area 107b area 107b1 area 107b2 area 107b3 area 107c area 107d area 107e area 107f area 108 Insulator 112 Insulator 113 Protective film 114 Conductors 114a Conductor 114b Conductor 115a Conductor 115b Conductor 116a Conductor 116a1 Electric conductor 116a2 conductor 116b Conductor 116b1 Electric conductor 116b2 Electric conductor 116c Conductor 116c1 Electric conductor 116c2 conductor 116d conductor 116e Conductor 116f conductor 118 Insulator 128 Insulator 132 Insulator 138 Insulator 148 Insulators 150 transistors 160 Capacitor 200 pellets 200a pellets 200b pellets 201 Aeon 220 board 230 Target 500 transistors 501 PCB 502 board 504B Light-emitting element 504G Light-emitting element 504R Light-emitting element 504W light emitting element 506 Conductors 507 Conductors 508 Bulkhead 509 Spacer 510 Light-emitting layer 512 Conductors 514B Colored layer 514G colored layer 514R colored layer 514W colored layer 516 PCB 518 Sealing film 520 areas 800 RF tags 801 Communication Device 802 antenna 803 wireless signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 chassis 912 Case 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 Case 942 Case 943 Display section 944 Operation Key 945 lens 946 Connection 951 body 952 wheels 953 Dashboard 954 Light 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Elements 1207 Capacitor element 1208 Capacitor 1209 Transistor 1210 transistor 1213 Transistor 1214 transistor 1220 circuits 1300A Portable Device 1300B Portable Devices 1300C Portable Devices 1310 Case 1311 area 1312 area 2100 transistors 2200 transistors 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitor 4000 RF tags 5000 boards 5001 Pixel unit 5002 Scanning line driver circuit 5003 Scanning line driver circuit 5004 Signal line driver circuit 5010 Capacitor wiring 5012 Gate wiring 5013 Gate wiring 5014 Source electrode or drain electrode 5016 Transistor 5017 Transistor 5018 Liquid crystal element 5019 Liquid crystal element 5020 pixels 5021 Switching transistor 5022 Drive transistor 5023 Capacitor element 5023A Capacitive Element 5023B Capacitive Element 5024 Light-emitting element 5025 signal line 5026 scan lines 5027 Power line 5028 Common electrode 5100 pellets 5111 pixels 5120 board 5154 Light-emitting element 5155 Transistor 5156 Transistor 5157 Transistor 5158 Capacitor element 5161 area 5211 pixels 5214 Light-emitting element 5215 Transistor 5216 Transistor 5217 Transistor 5218 Capacitor element 5219 Transistor 5311 pixels 5314 Light-emitting elements 5315 Transistor 5316 Transistor 5317 Transistor 5318 Capacitor element 5319 Transistor 5320 Transistor 5411 pixels 5414 Light-emitting element 5415 Transistor 5416 Transistor 5417 Transistor 5418 Capacitor element 5440 transistor 5441 Transistor 5442 transistor 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 cells 8007 Backlight Unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery< / cpu>

Claims

[Claim 1] A semiconductor device including a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, and an oxide semiconductor, the first insulator has a region in contact with an upper surface of the first conductor and a region in contact with an upper surface of the second conductor; the second insulator has a region in contact with an upper surface of the first insulator, the oxide semiconductor has a region in contact with an upper surface of the second insulator, the third insulator has a region in contact with an upper surface of the oxide semiconductor; the third conductor has a region in contact with an upper surface of the third insulator, the fourth insulator has a region in contact with an upper surface of the third conductor, a region in contact with a side surface of the third insulator, a region in contact with an upper surface of the oxide semiconductor, and a region in contact with an upper surface of the first insulator; the fifth insulator has a region in contact with an upper surface of the fourth insulator, the fourth conductor has a region in contact with an upper surface of the oxide semiconductor; the fifth conductor has a region in contact with an upper surface of the oxide semiconductor, the sixth conductor has a region in contact with an upper surface of the fourth insulator, the first conductor has a region where the first conductor and the oxide semiconductor overlap with each other via the first insulator and the second insulator; the third conductor has a region where the third conductor and the oxide semiconductor overlap with each other via the third insulator; a sixth conductor having a region where the second conductor and the sixth conductor overlap each other via the first insulator and the fourth insulator;

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